1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #ifndef SI_H 25 #define SI_H 26 27 #define TAHITI_RB_BITMAP_WIDTH_PER_SH 2 28 29 #define SI_MAX_SH_GPRS 256 30 #define SI_MAX_TEMP_GPRS 16 31 #define SI_MAX_SH_THREADS 256 32 #define SI_MAX_SH_STACK_ENTRIES 4096 33 #define SI_MAX_FRC_EOV_CNT 16384 34 #define SI_MAX_BACKENDS 8 35 #define SI_MAX_BACKENDS_MASK 0xFF 36 #define SI_MAX_BACKENDS_PER_SE_MASK 0x0F 37 #define SI_MAX_SIMDS 12 38 #define SI_MAX_SIMDS_MASK 0x0FFF 39 #define SI_MAX_SIMDS_PER_SE_MASK 0x00FF 40 #define SI_MAX_PIPES 8 41 #define SI_MAX_PIPES_MASK 0xFF 42 #define SI_MAX_PIPES_PER_SIMD_MASK 0x3F 43 #define SI_MAX_LDS_NUM 0xFFFF 44 #define SI_MAX_TCC 16 45 #define SI_MAX_TCC_MASK 0xFFFF 46 #define SI_MAX_CTLACKS_ASSERTION_WAIT 100 47 48 /* SMC IND accessor regs */ 49 #define SMC_IND_INDEX_0 0x80 50 #define SMC_IND_DATA_0 0x81 51 52 #define SMC_IND_ACCESS_CNTL 0x8A 53 # define AUTO_INCREMENT_IND_0 (1 << 0) 54 #define SMC_MESSAGE_0 0x8B 55 #define SMC_RESP_0 0x8C 56 57 /* CG IND registers are accessed via SMC indirect space + SMC_CG_IND_START */ 58 #define SMC_CG_IND_START 0xc0030000 59 #define SMC_CG_IND_END 0xc0040000 60 61 #define CG_CGTT_LOCAL_0 0x400 62 #define CG_CGTT_LOCAL_1 0x401 63 64 /* SMC IND registers */ 65 #define SMC_SYSCON_RESET_CNTL 0x80000000 66 # define RST_REG (1 << 0) 67 #define SMC_SYSCON_CLOCK_CNTL_0 0x80000004 68 # define CK_DISABLE (1 << 0) 69 # define CKEN (1 << 24) 70 71 #define VGA_HDP_CONTROL 0xCA 72 #define VGA_MEMORY_DISABLE (1 << 4) 73 74 #define DCCG_DISP_SLOW_SELECT_REG 0x13F 75 #define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0) 76 #define DCCG_DISP1_SLOW_SELECT_MASK (7 << 0) 77 #define DCCG_DISP1_SLOW_SELECT_SHIFT 0 78 #define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4) 79 #define DCCG_DISP2_SLOW_SELECT_MASK (7 << 4) 80 #define DCCG_DISP2_SLOW_SELECT_SHIFT 4 81 82 #define CG_SPLL_FUNC_CNTL 0x180 83 #define SPLL_RESET (1 << 0) 84 #define SPLL_SLEEP (1 << 1) 85 #define SPLL_BYPASS_EN (1 << 3) 86 #define SPLL_REF_DIV(x) ((x) << 4) 87 #define SPLL_REF_DIV_MASK (0x3f << 4) 88 #define SPLL_PDIV_A(x) ((x) << 20) 89 #define SPLL_PDIV_A_MASK (0x7f << 20) 90 #define SPLL_PDIV_A_SHIFT 20 91 #define CG_SPLL_FUNC_CNTL_2 0x181 92 #define SCLK_MUX_SEL(x) ((x) << 0) 93 #define SCLK_MUX_SEL_MASK (0x1ff << 0) 94 #define SPLL_CTLREQ_CHG (1 << 23) 95 #define SCLK_MUX_UPDATE (1 << 26) 96 #define CG_SPLL_FUNC_CNTL_3 0x182 97 #define SPLL_FB_DIV(x) ((x) << 0) 98 #define SPLL_FB_DIV_MASK (0x3ffffff << 0) 99 #define SPLL_FB_DIV_SHIFT 0 100 #define SPLL_DITHEN (1 << 28) 101 #define CG_SPLL_FUNC_CNTL_4 0x183 102 103 #define SPLL_STATUS 0x185 104 #define SPLL_CHG_STATUS (1 << 1) 105 #define SPLL_CNTL_MODE 0x186 106 #define SPLL_SW_DIR_CONTROL (1 << 0) 107 # define SPLL_REFCLK_SEL(x) ((x) << 26) 108 # define SPLL_REFCLK_SEL_MASK (3 << 26) 109 110 #define CG_SPLL_SPREAD_SPECTRUM 0x188 111 #define SSEN (1 << 0) 112 #define CLK_S(x) ((x) << 4) 113 #define CLK_S_MASK (0xfff << 4) 114 #define CLK_S_SHIFT 4 115 #define CG_SPLL_SPREAD_SPECTRUM_2 0x189 116 #define CLK_V(x) ((x) << 0) 117 #define CLK_V_MASK (0x3ffffff << 0) 118 #define CLK_V_SHIFT 0 119 120 #define CG_SPLL_AUTOSCALE_CNTL 0x18b 121 # define AUTOSCALE_ON_SS_CLEAR (1 << 9) 122 123 /* discrete uvd clocks */ 124 #define CG_UPLL_FUNC_CNTL 0x18d 125 # define UPLL_RESET_MASK 0x00000001 126 # define UPLL_SLEEP_MASK 0x00000002 127 # define UPLL_BYPASS_EN_MASK 0x00000004 128 # define UPLL_CTLREQ_MASK 0x00000008 129 # define UPLL_VCO_MODE_MASK 0x00000600 130 # define UPLL_REF_DIV_MASK 0x003F0000 131 # define UPLL_CTLACK_MASK 0x40000000 132 # define UPLL_CTLACK2_MASK 0x80000000 133 #define CG_UPLL_FUNC_CNTL_2 0x18e 134 # define UPLL_PDIV_A(x) ((x) << 0) 135 # define UPLL_PDIV_A_MASK 0x0000007F 136 # define UPLL_PDIV_B(x) ((x) << 8) 137 # define UPLL_PDIV_B_MASK 0x00007F00 138 # define VCLK_SRC_SEL(x) ((x) << 20) 139 # define VCLK_SRC_SEL_MASK 0x01F00000 140 # define DCLK_SRC_SEL(x) ((x) << 25) 141 # define DCLK_SRC_SEL_MASK 0x3E000000 142 #define CG_UPLL_FUNC_CNTL_3 0x18f 143 # define UPLL_FB_DIV(x) ((x) << 0) 144 # define UPLL_FB_DIV_MASK 0x01FFFFFF 145 #define CG_UPLL_FUNC_CNTL_4 0x191 146 # define UPLL_SPARE_ISPARE9 0x00020000 147 #define CG_UPLL_FUNC_CNTL_5 0x192 148 # define RESET_ANTI_MUX_MASK 0x00000200 149 #define CG_UPLL_SPREAD_SPECTRUM 0x194 150 # define SSEN_MASK 0x00000001 151 152 #define MPLL_BYPASSCLK_SEL 0x197 153 # define MPLL_CLKOUT_SEL(x) ((x) << 8) 154 # define MPLL_CLKOUT_SEL_MASK 0xFF00 155 156 #define CG_CLKPIN_CNTL 0x198 157 # define XTALIN_DIVIDE (1 << 1) 158 # define BCLK_AS_XCLK (1 << 2) 159 #define CG_CLKPIN_CNTL_2 0x199 160 # define FORCE_BIF_REFCLK_EN (1 << 3) 161 # define MUX_TCLK_TO_XCLK (1 << 8) 162 163 #define THM_CLK_CNTL 0x19b 164 # define CMON_CLK_SEL(x) ((x) << 0) 165 # define CMON_CLK_SEL_MASK 0xFF 166 # define TMON_CLK_SEL(x) ((x) << 8) 167 # define TMON_CLK_SEL_MASK 0xFF00 168 #define MISC_CLK_CNTL 0x19c 169 # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0) 170 # define DEEP_SLEEP_CLK_SEL_MASK 0xFF 171 # define ZCLK_SEL(x) ((x) << 8) 172 # define ZCLK_SEL_MASK 0xFF00 173 174 #define CG_THERMAL_CTRL 0x1c0 175 #define DPM_EVENT_SRC(x) ((x) << 0) 176 #define DPM_EVENT_SRC_MASK (7 << 0) 177 #define DIG_THERM_DPM(x) ((x) << 14) 178 #define DIG_THERM_DPM_MASK 0x003FC000 179 #define DIG_THERM_DPM_SHIFT 14 180 #define CG_THERMAL_STATUS 0x1c1 181 #define FDO_PWM_DUTY(x) ((x) << 9) 182 #define FDO_PWM_DUTY_MASK (0xff << 9) 183 #define FDO_PWM_DUTY_SHIFT 9 184 #define CG_THERMAL_INT 0x1c2 185 #define DIG_THERM_INTH(x) ((x) << 8) 186 #define DIG_THERM_INTH_MASK 0x0000FF00 187 #define DIG_THERM_INTH_SHIFT 8 188 #define DIG_THERM_INTL(x) ((x) << 16) 189 #define DIG_THERM_INTL_MASK 0x00FF0000 190 #define DIG_THERM_INTL_SHIFT 16 191 #define THERM_INT_MASK_HIGH (1 << 24) 192 #define THERM_INT_MASK_LOW (1 << 25) 193 194 #define CG_MULT_THERMAL_CTRL 0x1c4 195 #define TEMP_SEL(x) ((x) << 20) 196 #define TEMP_SEL_MASK (0xff << 20) 197 #define TEMP_SEL_SHIFT 20 198 #define CG_MULT_THERMAL_STATUS 0x1c5 199 #define ASIC_MAX_TEMP(x) ((x) << 0) 200 #define ASIC_MAX_TEMP_MASK 0x000001ff 201 #define ASIC_MAX_TEMP_SHIFT 0 202 #define CTF_TEMP(x) ((x) << 9) 203 #define CTF_TEMP_MASK 0x0003fe00 204 #define CTF_TEMP_SHIFT 9 205 206 #define CG_FDO_CTRL0 0x1d5 207 #define FDO_STATIC_DUTY(x) ((x) << 0) 208 #define FDO_STATIC_DUTY_MASK 0x000000FF 209 #define FDO_STATIC_DUTY_SHIFT 0 210 #define CG_FDO_CTRL1 0x1d6 211 #define FMAX_DUTY100(x) ((x) << 0) 212 #define FMAX_DUTY100_MASK 0x000000FF 213 #define FMAX_DUTY100_SHIFT 0 214 #define CG_FDO_CTRL2 0x1d7 215 #define TMIN(x) ((x) << 0) 216 #define TMIN_MASK 0x000000FF 217 #define TMIN_SHIFT 0 218 #define FDO_PWM_MODE(x) ((x) << 11) 219 #define FDO_PWM_MODE_MASK (7 << 11) 220 #define FDO_PWM_MODE_SHIFT 11 221 #define TACH_PWM_RESP_RATE(x) ((x) << 25) 222 #define TACH_PWM_RESP_RATE_MASK (0x7f << 25) 223 #define TACH_PWM_RESP_RATE_SHIFT 25 224 225 #define CG_TACH_CTRL 0x1dc 226 # define EDGE_PER_REV(x) ((x) << 0) 227 # define EDGE_PER_REV_MASK (0x7 << 0) 228 # define EDGE_PER_REV_SHIFT 0 229 # define TARGET_PERIOD(x) ((x) << 3) 230 # define TARGET_PERIOD_MASK 0xfffffff8 231 # define TARGET_PERIOD_SHIFT 3 232 #define CG_TACH_STATUS 0x1dd 233 # define TACH_PERIOD(x) ((x) << 0) 234 # define TACH_PERIOD_MASK 0xffffffff 235 # define TACH_PERIOD_SHIFT 0 236 237 #define GENERAL_PWRMGT 0x1e0 238 # define GLOBAL_PWRMGT_EN (1 << 0) 239 # define STATIC_PM_EN (1 << 1) 240 # define THERMAL_PROTECTION_DIS (1 << 2) 241 # define THERMAL_PROTECTION_TYPE (1 << 3) 242 # define SW_SMIO_INDEX(x) ((x) << 6) 243 # define SW_SMIO_INDEX_MASK (1 << 6) 244 # define SW_SMIO_INDEX_SHIFT 6 245 # define VOLT_PWRMGT_EN (1 << 10) 246 # define DYN_SPREAD_SPECTRUM_EN (1 << 23) 247 #define CG_TPC 0x1e1 248 #define SCLK_PWRMGT_CNTL 0x1e2 249 # define SCLK_PWRMGT_OFF (1 << 0) 250 # define SCLK_LOW_D1 (1 << 1) 251 # define FIR_RESET (1 << 4) 252 # define FIR_FORCE_TREND_SEL (1 << 5) 253 # define FIR_TREND_MODE (1 << 6) 254 # define DYN_GFX_CLK_OFF_EN (1 << 7) 255 # define GFX_CLK_FORCE_ON (1 << 8) 256 # define GFX_CLK_REQUEST_OFF (1 << 9) 257 # define GFX_CLK_FORCE_OFF (1 << 10) 258 # define GFX_CLK_OFF_ACPI_D1 (1 << 11) 259 # define GFX_CLK_OFF_ACPI_D2 (1 << 12) 260 # define GFX_CLK_OFF_ACPI_D3 (1 << 13) 261 # define DYN_LIGHT_SLEEP_EN (1 << 14) 262 263 #define TARGET_AND_CURRENT_PROFILE_INDEX 0x1e6 264 # define CURRENT_STATE_INDEX_MASK (0xf << 4) 265 # define CURRENT_STATE_INDEX_SHIFT 4 266 267 #define CG_FTV 0x1ef 268 269 #define CG_FFCT_0 0x1f0 270 # define UTC_0(x) ((x) << 0) 271 # define UTC_0_MASK (0x3ff << 0) 272 # define DTC_0(x) ((x) << 10) 273 # define DTC_0_MASK (0x3ff << 10) 274 275 #define CG_BSP 0x1ff 276 # define BSP(x) ((x) << 0) 277 # define BSP_MASK (0xffff << 0) 278 # define BSU(x) ((x) << 16) 279 # define BSU_MASK (0xf << 16) 280 #define CG_AT 0x200 281 # define CG_R(x) ((x) << 0) 282 # define CG_R_MASK (0xffff << 0) 283 # define CG_L(x) ((x) << 16) 284 # define CG_L_MASK (0xffff << 16) 285 286 #define CG_GIT 0x201 287 # define CG_GICST(x) ((x) << 0) 288 # define CG_GICST_MASK (0xffff << 0) 289 # define CG_GIPOT(x) ((x) << 16) 290 # define CG_GIPOT_MASK (0xffff << 16) 291 292 #define CG_SSP 0x203 293 # define SST(x) ((x) << 0) 294 # define SST_MASK (0xffff << 0) 295 # define SSTU(x) ((x) << 16) 296 # define SSTU_MASK (0xf << 16) 297 298 #define CG_DISPLAY_GAP_CNTL 0x20a 299 # define DISP1_GAP(x) ((x) << 0) 300 # define DISP1_GAP_MASK (3 << 0) 301 # define DISP2_GAP(x) ((x) << 2) 302 # define DISP2_GAP_MASK (3 << 2) 303 # define VBI_TIMER_COUNT(x) ((x) << 4) 304 # define VBI_TIMER_COUNT_MASK (0x3fff << 4) 305 # define VBI_TIMER_UNIT(x) ((x) << 20) 306 # define VBI_TIMER_UNIT_MASK (7 << 20) 307 # define DISP1_GAP_MCHG(x) ((x) << 24) 308 # define DISP1_GAP_MCHG_MASK (3 << 24) 309 # define DISP2_GAP_MCHG(x) ((x) << 26) 310 # define DISP2_GAP_MCHG_MASK (3 << 26) 311 312 #define CG_ULV_CONTROL 0x21e 313 #define CG_ULV_PARAMETER 0x21f 314 315 #define SMC_SCRATCH0 0x221 316 317 #define CG_CAC_CTRL 0x22e 318 # define CAC_WINDOW(x) ((x) << 0) 319 # define CAC_WINDOW_MASK 0x00ffffff 320 321 #define DMIF_ADDR_CONFIG 0x2F5 322 323 #define DMIF_ADDR_CALC 0x300 324 325 #define PIPE0_DMIF_BUFFER_CONTROL 0x0328 326 # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0) 327 # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4) 328 329 #define SRBM_STATUS 0x394 330 #define GRBM_RQ_PENDING (1 << 5) 331 #define VMC_BUSY (1 << 8) 332 #define MCB_BUSY (1 << 9) 333 #define MCB_NON_DISPLAY_BUSY (1 << 10) 334 #define MCC_BUSY (1 << 11) 335 #define MCD_BUSY (1 << 12) 336 #define SEM_BUSY (1 << 14) 337 #define IH_BUSY (1 << 17) 338 339 #define SRBM_SOFT_RESET 0x398 340 #define SOFT_RESET_BIF (1 << 1) 341 #define SOFT_RESET_DC (1 << 5) 342 #define SOFT_RESET_DMA1 (1 << 6) 343 #define SOFT_RESET_GRBM (1 << 8) 344 #define SOFT_RESET_HDP (1 << 9) 345 #define SOFT_RESET_IH (1 << 10) 346 #define SOFT_RESET_MC (1 << 11) 347 #define SOFT_RESET_ROM (1 << 14) 348 #define SOFT_RESET_SEM (1 << 15) 349 #define SOFT_RESET_VMC (1 << 17) 350 #define SOFT_RESET_DMA (1 << 20) 351 #define SOFT_RESET_TST (1 << 21) 352 #define SOFT_RESET_REGBB (1 << 22) 353 #define SOFT_RESET_ORB (1 << 23) 354 355 #define CC_SYS_RB_BACKEND_DISABLE 0x3A0 356 #define GC_USER_SYS_RB_BACKEND_DISABLE 0x3A1 357 358 #define SRBM_READ_ERROR 0x3A6 359 #define SRBM_INT_CNTL 0x3A8 360 #define SRBM_INT_ACK 0x3AA 361 362 #define SRBM_STATUS2 0x3B1 363 #define DMA_BUSY (1 << 5) 364 #define DMA1_BUSY (1 << 6) 365 366 #define VM_L2_CNTL 0x500 367 #define ENABLE_L2_CACHE (1 << 0) 368 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 369 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) 370 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) 371 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 372 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 373 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) 374 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) 375 #define VM_L2_CNTL2 0x501 376 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 377 #define INVALIDATE_L2_CACHE (1 << 1) 378 #define INVALIDATE_CACHE_MODE(x) ((x) << 26) 379 #define INVALIDATE_PTE_AND_PDE_CACHES 0 380 #define INVALIDATE_ONLY_PTE_CACHES 1 381 #define INVALIDATE_ONLY_PDE_CACHES 2 382 #define VM_L2_CNTL3 0x502 383 #define BANK_SELECT(x) ((x) << 0) 384 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) 385 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 386 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 387 #define VM_L2_STATUS 0x503 388 #define L2_BUSY (1 << 0) 389 #define VM_CONTEXT0_CNTL 0x504 390 #define ENABLE_CONTEXT (1 << 0) 391 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 392 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 393 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 394 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 395 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 396 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 397 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 398 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 399 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 400 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 401 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 402 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 403 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 404 #define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24) 405 #define VM_CONTEXT1_CNTL 0x505 406 #define VM_CONTEXT0_CNTL2 0x50C 407 #define VM_CONTEXT1_CNTL2 0x50D 408 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x50E 409 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x50F 410 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x510 411 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x511 412 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x512 413 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x513 414 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x514 415 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x515 416 417 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x53f 418 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x537 419 #define PROTECTIONS_MASK (0xf << 0) 420 #define PROTECTIONS_SHIFT 0 421 /* bit 0: range 422 * bit 1: pde0 423 * bit 2: valid 424 * bit 3: read 425 * bit 4: write 426 */ 427 #define MEMORY_CLIENT_ID_MASK (0xff << 12) 428 #define MEMORY_CLIENT_ID_SHIFT 12 429 #define MEMORY_CLIENT_RW_MASK (1 << 24) 430 #define MEMORY_CLIENT_RW_SHIFT 24 431 #define FAULT_VMID_MASK (0xf << 25) 432 #define FAULT_VMID_SHIFT 25 433 434 #define VM_INVALIDATE_REQUEST 0x51E 435 #define VM_INVALIDATE_RESPONSE 0x51F 436 437 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x546 438 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x547 439 440 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54F 441 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x550 442 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x551 443 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x552 444 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x553 445 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x554 446 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x555 447 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x556 448 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x557 449 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x558 450 451 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x55F 452 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x560 453 454 #define VM_L2_CG 0x570 455 #define MC_CG_ENABLE (1 << 18) 456 #define MC_LS_ENABLE (1 << 19) 457 458 #define MC_SHARED_CHMAP 0x801 459 #define NOOFCHAN_SHIFT 12 460 #define NOOFCHAN_MASK 0x0000f000 461 #define MC_SHARED_CHREMAP 0x802 462 463 #define MC_VM_FB_LOCATION 0x809 464 #define MC_VM_AGP_TOP 0x80A 465 #define MC_VM_AGP_BOT 0x80B 466 #define MC_VM_AGP_BASE 0x80C 467 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x80D 468 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x80E 469 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x80F 470 471 #define MC_VM_MX_L1_TLB_CNTL 0x819 472 #define ENABLE_L1_TLB (1 << 0) 473 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 474 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 475 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 476 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 477 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 478 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 479 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 480 481 #define MC_SHARED_BLACKOUT_CNTL 0x82B 482 483 #define MC_HUB_MISC_HUB_CG 0x82E 484 #define MC_HUB_MISC_VM_CG 0x82F 485 486 #define MC_HUB_MISC_SIP_CG 0x830 487 488 #define MC_XPB_CLK_GAT 0x91E 489 490 #define MC_CITF_MISC_RD_CG 0x992 491 #define MC_CITF_MISC_WR_CG 0x993 492 #define MC_CITF_MISC_VM_CG 0x994 493 494 #define MC_ARB_RAMCFG 0x9D8 495 #define NOOFBANK_SHIFT 0 496 #define NOOFBANK_MASK 0x00000003 497 #define NOOFRANK_SHIFT 2 498 #define NOOFRANK_MASK 0x00000004 499 #define NOOFROWS_SHIFT 3 500 #define NOOFROWS_MASK 0x00000038 501 #define NOOFCOLS_SHIFT 6 502 #define NOOFCOLS_MASK 0x000000C0 503 #define CHANSIZE_SHIFT 8 504 #define CHANSIZE_MASK 0x00000100 505 #define CHANSIZE_OVERRIDE (1 << 11) 506 #define NOOFGROUPS_SHIFT 12 507 #define NOOFGROUPS_MASK 0x00001000 508 509 #define MC_ARB_DRAM_TIMING 0x9DD 510 #define MC_ARB_DRAM_TIMING2 0x9DE 511 512 #define MC_ARB_BURST_TIME 0xA02 513 #define STATE0(x) ((x) << 0) 514 #define STATE0_MASK (0x1f << 0) 515 #define STATE0_SHIFT 0 516 #define STATE1(x) ((x) << 5) 517 #define STATE1_MASK (0x1f << 5) 518 #define STATE1_SHIFT 5 519 #define STATE2(x) ((x) << 10) 520 #define STATE2_MASK (0x1f << 10) 521 #define STATE2_SHIFT 10 522 #define STATE3(x) ((x) << 15) 523 #define STATE3_MASK (0x1f << 15) 524 #define STATE3_SHIFT 15 525 526 #define MC_SEQ_TRAIN_WAKEUP_CNTL 0xA3A 527 #define TRAIN_DONE_D0 (1 << 30) 528 #define TRAIN_DONE_D1 (1 << 31) 529 530 #define MC_SEQ_SUP_CNTL 0xA32 531 #define RUN_MASK (1 << 0) 532 #define MC_SEQ_SUP_PGM 0xA33 533 #define MC_PMG_AUTO_CMD 0xA34 534 535 #define MC_IO_PAD_CNTL_D0 0xA74 536 #define MEM_FALL_OUT_CMD (1 << 8) 537 538 #define MC_SEQ_RAS_TIMING 0xA28 539 #define MC_SEQ_CAS_TIMING 0xA29 540 #define MC_SEQ_MISC_TIMING 0xA2A 541 #define MC_SEQ_MISC_TIMING2 0xA2B 542 #define MC_SEQ_PMG_TIMING 0xA2C 543 #define MC_SEQ_RD_CTL_D0 0xA2D 544 #define MC_SEQ_RD_CTL_D1 0xA2E 545 #define MC_SEQ_WR_CTL_D0 0xA2F 546 #define MC_SEQ_WR_CTL_D1 0xA30 547 548 #define MC_SEQ_MISC0 0xA80 549 #define MC_SEQ_MISC0_VEN_ID_SHIFT 8 550 #define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00 551 #define MC_SEQ_MISC0_VEN_ID_VALUE 3 552 #define MC_SEQ_MISC0_REV_ID_SHIFT 12 553 #define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000 554 #define MC_SEQ_MISC0_REV_ID_VALUE 1 555 #define MC_SEQ_MISC0_GDDR5_SHIFT 28 556 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 557 #define MC_SEQ_MISC0_GDDR5_VALUE 5 558 #define MC_SEQ_MISC1 0xA81 559 #define MC_SEQ_RESERVE_M 0xA82 560 #define MC_PMG_CMD_EMRS 0xA83 561 562 #define MC_SEQ_IO_DEBUG_INDEX 0xA91 563 #define MC_SEQ_IO_DEBUG_DATA 0xA92 564 565 #define MC_SEQ_MISC5 0xA95 566 #define MC_SEQ_MISC6 0xA96 567 568 #define MC_SEQ_MISC7 0xA99 569 570 #define MC_SEQ_RAS_TIMING_LP 0xA9B 571 #define MC_SEQ_CAS_TIMING_LP 0xA9C 572 #define MC_SEQ_MISC_TIMING_LP 0xA9D 573 #define MC_SEQ_MISC_TIMING2_LP 0xA9E 574 #define MC_SEQ_WR_CTL_D0_LP 0xA9F 575 #define MC_SEQ_WR_CTL_D1_LP 0xAA0 576 #define MC_SEQ_PMG_CMD_EMRS_LP 0xAA1 577 #define MC_SEQ_PMG_CMD_MRS_LP 0xAA2 578 579 #define MC_PMG_CMD_MRS 0xAAB 580 581 #define MC_SEQ_RD_CTL_D0_LP 0xAC7 582 #define MC_SEQ_RD_CTL_D1_LP 0xAC8 583 584 #define MC_PMG_CMD_MRS1 0xAD1 585 #define MC_SEQ_PMG_CMD_MRS1_LP 0xAD2 586 #define MC_SEQ_PMG_TIMING_LP 0xAD3 587 588 #define MC_SEQ_WR_CTL_2 0xAD5 589 #define MC_SEQ_WR_CTL_2_LP 0xAD6 590 #define MC_PMG_CMD_MRS2 0xAD7 591 #define MC_SEQ_PMG_CMD_MRS2_LP 0xAD8 592 593 #define MCLK_PWRMGT_CNTL 0xAE8 594 # define DLL_SPEED(x) ((x) << 0) 595 # define DLL_SPEED_MASK (0x1f << 0) 596 # define DLL_READY (1 << 6) 597 # define MC_INT_CNTL (1 << 7) 598 # define MRDCK0_PDNB (1 << 8) 599 # define MRDCK1_PDNB (1 << 9) 600 # define MRDCK0_RESET (1 << 16) 601 # define MRDCK1_RESET (1 << 17) 602 # define DLL_READY_READ (1 << 24) 603 #define DLL_CNTL 0xAE9 604 # define MRDCK0_BYPASS (1 << 24) 605 # define MRDCK1_BYPASS (1 << 25) 606 607 #define MPLL_CNTL_MODE 0xAEC 608 # define MPLL_MCLK_SEL (1 << 11) 609 #define MPLL_FUNC_CNTL 0xAED 610 #define BWCTRL(x) ((x) << 20) 611 #define BWCTRL_MASK (0xff << 20) 612 #define MPLL_FUNC_CNTL_1 0xAEE 613 #define VCO_MODE(x) ((x) << 0) 614 #define VCO_MODE_MASK (3 << 0) 615 #define CLKFRAC(x) ((x) << 4) 616 #define CLKFRAC_MASK (0xfff << 4) 617 #define CLKF(x) ((x) << 16) 618 #define CLKF_MASK (0xfff << 16) 619 #define MPLL_FUNC_CNTL_2 0xAEF 620 #define MPLL_AD_FUNC_CNTL 0xAF0 621 #define YCLK_POST_DIV(x) ((x) << 0) 622 #define YCLK_POST_DIV_MASK (7 << 0) 623 #define MPLL_DQ_FUNC_CNTL 0xAF1 624 #define YCLK_SEL(x) ((x) << 4) 625 #define YCLK_SEL_MASK (1 << 4) 626 627 #define MPLL_SS1 0xAF3 628 #define CLKV(x) ((x) << 0) 629 #define CLKV_MASK (0x3ffffff << 0) 630 #define MPLL_SS2 0xAF4 631 #define CLKS(x) ((x) << 0) 632 #define CLKS_MASK (0xfff << 0) 633 634 #define HDP_HOST_PATH_CNTL 0xB00 635 #define CLOCK_GATING_DIS (1 << 23) 636 #define HDP_NONSURFACE_BASE 0xB01 637 #define HDP_NONSURFACE_INFO 0xB02 638 #define HDP_NONSURFACE_SIZE 0xB03 639 640 #define HDP_DEBUG0 0xBCC 641 642 #define HDP_ADDR_CONFIG 0xBD2 643 #define HDP_MISC_CNTL 0xBD3 644 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 645 #define HDP_MEM_POWER_LS 0xBD4 646 #define HDP_LS_ENABLE (1 << 0) 647 648 #define ATC_MISC_CG 0xCD4 649 650 #define IH_RB_CNTL 0xF80 651 # define IH_RB_ENABLE (1 << 0) 652 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 653 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 654 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 655 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 656 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 657 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 658 #define IH_RB_BASE 0xF81 659 #define IH_RB_RPTR 0xF82 660 #define IH_RB_WPTR 0xF83 661 # define RB_OVERFLOW (1 << 0) 662 # define WPTR_OFFSET_MASK 0x3fffc 663 #define IH_RB_WPTR_ADDR_HI 0xF84 664 #define IH_RB_WPTR_ADDR_LO 0xF85 665 #define IH_CNTL 0xF86 666 # define ENABLE_INTR (1 << 0) 667 # define IH_MC_SWAP(x) ((x) << 1) 668 # define IH_MC_SWAP_NONE 0 669 # define IH_MC_SWAP_16BIT 1 670 # define IH_MC_SWAP_32BIT 2 671 # define IH_MC_SWAP_64BIT 3 672 # define RPTR_REARM (1 << 4) 673 # define MC_WRREQ_CREDIT(x) ((x) << 15) 674 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 675 # define MC_VMID(x) ((x) << 25) 676 677 #define CONFIG_MEMSIZE 0x150A 678 679 #define INTERRUPT_CNTL 0x151A 680 # define IH_DUMMY_RD_OVERRIDE (1 << 0) 681 # define IH_DUMMY_RD_EN (1 << 1) 682 # define IH_REQ_NONSNOOP_EN (1 << 3) 683 # define GEN_IH_INT_EN (1 << 8) 684 #define INTERRUPT_CNTL2 0x151B 685 686 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x1520 687 688 #define BIF_FB_EN 0x1524 689 #define FB_READ_EN (1 << 0) 690 #define FB_WRITE_EN (1 << 1) 691 692 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x1528 693 694 /* DCE6 ELD audio interface */ 695 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 /* LPCM */ 696 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 /* AC3 */ 697 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2A /* MPEG1 */ 698 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2B /* MP3 */ 699 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2C /* MPEG2 */ 700 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2D /* AAC */ 701 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2E /* DTS */ 702 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2F /* ATRAC */ 703 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 /* one bit audio - leave at 0 (default) */ 704 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31 /* Dolby Digital */ 705 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 /* DTS-HD */ 706 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 /* MAT-MLP */ 707 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34 /* DTS */ 708 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35 /* WMA Pro */ 709 # define MAX_CHANNELS(x) (((x) & 0x7) << 0) 710 /* max channels minus one. 7 = 8 channels */ 711 # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8) 712 # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16) 713 # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */ 714 /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO 715 * bit0 = 32 kHz 716 * bit1 = 44.1 kHz 717 * bit2 = 48 kHz 718 * bit3 = 88.2 kHz 719 * bit4 = 96 kHz 720 * bit5 = 176.4 kHz 721 * bit6 = 192 kHz 722 */ 723 724 #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37 725 # define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0) 726 # define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8) 727 /* VIDEO_LIPSYNC, AUDIO_LIPSYNC 728 * 0 = invalid 729 * x = legal delay value 730 * 255 = sync not supported 731 */ 732 #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38 733 # define HBR_CAPABLE (1 << 0) /* enabled by default */ 734 735 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a 736 # define MANUFACTURER_ID(x) (((x) & 0xffff) << 0) 737 # define PRODUCT_ID(x) (((x) & 0xffff) << 16) 738 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b 739 # define SINK_DESCRIPTION_LEN(x) (((x) & 0xff) << 0) 740 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c 741 # define PORT_ID0(x) (((x) & 0xffffffff) << 0) 742 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d 743 # define PORT_ID1(x) (((x) & 0xffffffff) << 0) 744 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e 745 # define DESCRIPTION0(x) (((x) & 0xff) << 0) 746 # define DESCRIPTION1(x) (((x) & 0xff) << 8) 747 # define DESCRIPTION2(x) (((x) & 0xff) << 16) 748 # define DESCRIPTION3(x) (((x) & 0xff) << 24) 749 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f 750 # define DESCRIPTION4(x) (((x) & 0xff) << 0) 751 # define DESCRIPTION5(x) (((x) & 0xff) << 8) 752 # define DESCRIPTION6(x) (((x) & 0xff) << 16) 753 # define DESCRIPTION7(x) (((x) & 0xff) << 24) 754 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40 755 # define DESCRIPTION8(x) (((x) & 0xff) << 0) 756 # define DESCRIPTION9(x) (((x) & 0xff) << 8) 757 # define DESCRIPTION10(x) (((x) & 0xff) << 16) 758 # define DESCRIPTION11(x) (((x) & 0xff) << 24) 759 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41 760 # define DESCRIPTION12(x) (((x) & 0xff) << 0) 761 # define DESCRIPTION13(x) (((x) & 0xff) << 8) 762 # define DESCRIPTION14(x) (((x) & 0xff) << 16) 763 # define DESCRIPTION15(x) (((x) & 0xff) << 24) 764 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42 765 # define DESCRIPTION16(x) (((x) & 0xff) << 0) 766 # define DESCRIPTION17(x) (((x) & 0xff) << 8) 767 768 #define AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 769 # define AUDIO_ENABLED (1 << 31) 770 771 #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 772 #define PORT_CONNECTIVITY_MASK (3 << 30) 773 #define PORT_CONNECTIVITY_SHIFT 30 774 775 #define PRIORITY_A_CNT 0x1AC6 776 #define PRIORITY_MARK_MASK 0x7fff 777 #define PRIORITY_OFF (1 << 16) 778 #define PRIORITY_ALWAYS_ON (1 << 20) 779 #define PRIORITY_B_CNT 0x1AC7 780 781 #define DPG_PIPE_LATENCY_CONTROL 0x1B33 782 # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 783 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 784 785 #define DISP_INTERRUPT_STATUS 0x183D 786 # define LB_D1_VLINE_INTERRUPT (1 << 2) 787 # define LB_D1_VBLANK_INTERRUPT (1 << 3) 788 # define DC_HPD1_INTERRUPT (1 << 17) 789 # define DC_HPD1_RX_INTERRUPT (1 << 18) 790 # define DACA_AUTODETECT_INTERRUPT (1 << 22) 791 # define DACB_AUTODETECT_INTERRUPT (1 << 23) 792 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 793 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 794 #define DISP_INTERRUPT_STATUS_CONTINUE 0x183E 795 # define LB_D2_VLINE_INTERRUPT (1 << 2) 796 # define LB_D2_VBLANK_INTERRUPT (1 << 3) 797 # define DC_HPD2_INTERRUPT (1 << 17) 798 # define DC_HPD2_RX_INTERRUPT (1 << 18) 799 # define DISP_TIMER_INTERRUPT (1 << 24) 800 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x183F 801 # define LB_D3_VLINE_INTERRUPT (1 << 2) 802 # define LB_D3_VBLANK_INTERRUPT (1 << 3) 803 # define DC_HPD3_INTERRUPT (1 << 17) 804 # define DC_HPD3_RX_INTERRUPT (1 << 18) 805 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x1840 806 # define LB_D4_VLINE_INTERRUPT (1 << 2) 807 # define LB_D4_VBLANK_INTERRUPT (1 << 3) 808 # define DC_HPD4_INTERRUPT (1 << 17) 809 # define DC_HPD4_RX_INTERRUPT (1 << 18) 810 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x1853 811 # define LB_D5_VLINE_INTERRUPT (1 << 2) 812 # define LB_D5_VBLANK_INTERRUPT (1 << 3) 813 # define DC_HPD5_INTERRUPT (1 << 17) 814 # define DC_HPD5_RX_INTERRUPT (1 << 18) 815 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x1854 816 # define LB_D6_VLINE_INTERRUPT (1 << 2) 817 # define LB_D6_VBLANK_INTERRUPT (1 << 3) 818 # define DC_HPD6_INTERRUPT (1 << 17) 819 # define DC_HPD6_RX_INTERRUPT (1 << 18) 820 821 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 822 #define GRPH_INT_STATUS 0x1A16 823 # define GRPH_PFLIP_INT_OCCURRED (1 << 0) 824 # define GRPH_PFLIP_INT_CLEAR (1 << 8) 825 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 826 #define GRPH_INT_CONTROL 0x1A17 827 # define GRPH_PFLIP_INT_MASK (1 << 0) 828 # define GRPH_PFLIP_INT_TYPE (1 << 8) 829 830 #define DAC_AUTODETECT_INT_CONTROL 0x19F2 831 832 #define DC_HPD1_INT_STATUS 0x1807 833 #define DC_HPD2_INT_STATUS 0x180A 834 #define DC_HPD3_INT_STATUS 0x180D 835 #define DC_HPD4_INT_STATUS 0x1810 836 #define DC_HPD5_INT_STATUS 0x1813 837 #define DC_HPD6_INT_STATUS 0x1816 838 # define DC_HPDx_INT_STATUS (1 << 0) 839 # define DC_HPDx_SENSE (1 << 1) 840 # define DC_HPDx_RX_INT_STATUS (1 << 8) 841 842 #define DC_HPD1_INT_CONTROL 0x1808 843 #define DC_HPD2_INT_CONTROL 0x180B 844 #define DC_HPD3_INT_CONTROL 0x180E 845 #define DC_HPD4_INT_CONTROL 0x1811 846 #define DC_HPD5_INT_CONTROL 0x1814 847 #define DC_HPD6_INT_CONTROL 0x1817 848 # define DC_HPDx_INT_ACK (1 << 0) 849 # define DC_HPDx_INT_POLARITY (1 << 8) 850 # define DC_HPDx_INT_EN (1 << 16) 851 # define DC_HPDx_RX_INT_ACK (1 << 20) 852 # define DC_HPDx_RX_INT_EN (1 << 24) 853 854 #define DC_HPD1_CONTROL 0x1809 855 #define DC_HPD2_CONTROL 0x180C 856 #define DC_HPD3_CONTROL 0x180F 857 #define DC_HPD4_CONTROL 0x1812 858 #define DC_HPD5_CONTROL 0x1815 859 #define DC_HPD6_CONTROL 0x1818 860 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 861 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 862 # define DC_HPDx_EN (1 << 28) 863 864 #define DPG_PIPE_STUTTER_CONTROL 0x1B35 865 # define STUTTER_ENABLE (1 << 0) 866 867 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ 868 #define CRTC_STATUS_FRAME_COUNT 0x1BA6 869 870 /* Audio clocks */ 871 #define DCCG_AUDIO_DTO0_PHASE 0x05b0 872 #define DCCG_AUDIO_DTO0_MODULE 0x05b4 873 #define DCCG_AUDIO_DTO1_PHASE 0x05c0 874 #define DCCG_AUDIO_DTO1_MODULE 0x05c4 875 876 #define GRBM_CNTL 0x2000 877 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 878 879 #define GRBM_STATUS2 0x2002 880 #define RLC_RQ_PENDING (1 << 0) 881 #define RLC_BUSY (1 << 8) 882 #define TC_BUSY (1 << 9) 883 884 #define GRBM_STATUS 0x2004 885 #define CMDFIFO_AVAIL_MASK 0x0000000F 886 #define RING2_RQ_PENDING (1 << 4) 887 #define SRBM_RQ_PENDING (1 << 5) 888 #define RING1_RQ_PENDING (1 << 6) 889 #define CF_RQ_PENDING (1 << 7) 890 #define PF_RQ_PENDING (1 << 8) 891 #define GDS_DMA_RQ_PENDING (1 << 9) 892 #define GRBM_EE_BUSY (1 << 10) 893 #define DB_CLEAN (1 << 12) 894 #define CB_CLEAN (1 << 13) 895 #define TA_BUSY (1 << 14) 896 #define GDS_BUSY (1 << 15) 897 #define VGT_BUSY (1 << 17) 898 #define IA_BUSY_NO_DMA (1 << 18) 899 #define IA_BUSY (1 << 19) 900 #define SX_BUSY (1 << 20) 901 #define SPI_BUSY (1 << 22) 902 #define BCI_BUSY (1 << 23) 903 #define SC_BUSY (1 << 24) 904 #define PA_BUSY (1 << 25) 905 #define DB_BUSY (1 << 26) 906 #define CP_COHERENCY_BUSY (1 << 28) 907 #define CP_BUSY (1 << 29) 908 #define CB_BUSY (1 << 30) 909 #define GUI_ACTIVE (1 << 31) 910 #define GRBM_STATUS_SE0 0x2005 911 #define GRBM_STATUS_SE1 0x2006 912 #define SE_DB_CLEAN (1 << 1) 913 #define SE_CB_CLEAN (1 << 2) 914 #define SE_BCI_BUSY (1 << 22) 915 #define SE_VGT_BUSY (1 << 23) 916 #define SE_PA_BUSY (1 << 24) 917 #define SE_TA_BUSY (1 << 25) 918 #define SE_SX_BUSY (1 << 26) 919 #define SE_SPI_BUSY (1 << 27) 920 #define SE_SC_BUSY (1 << 29) 921 #define SE_DB_BUSY (1 << 30) 922 #define SE_CB_BUSY (1 << 31) 923 924 #define GRBM_INT_CNTL 0x2018 925 # define RDERR_INT_ENABLE (1 << 0) 926 # define GUI_IDLE_INT_ENABLE (1 << 19) 927 928 #define CP_STRMOUT_CNTL 0x213F 929 #define SCRATCH_REG0 0x2140 930 #define SCRATCH_REG1 0x2141 931 #define SCRATCH_REG2 0x2142 932 #define SCRATCH_REG3 0x2143 933 #define SCRATCH_REG4 0x2144 934 #define SCRATCH_REG5 0x2145 935 #define SCRATCH_REG6 0x2146 936 #define SCRATCH_REG7 0x2147 937 938 #define SCRATCH_UMSK 0x2150 939 #define SCRATCH_ADDR 0x2151 940 941 #define CP_SEM_WAIT_TIMER 0x216F 942 943 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x2172 944 945 #define CP_ME_CNTL 0x21B6 946 #define CP_CE_HALT (1 << 24) 947 #define CP_PFP_HALT (1 << 26) 948 #define CP_ME_HALT (1 << 28) 949 950 #define CP_COHER_CNTL2 0x217A 951 952 #define CP_RB2_RPTR 0x21BE 953 #define CP_RB1_RPTR 0x21BF 954 #define CP_RB0_RPTR 0x21C0 955 #define CP_RB_WPTR_DELAY 0x21C1 956 957 #define CP_QUEUE_THRESHOLDS 0x21D8 958 #define ROQ_IB1_START(x) ((x) << 0) 959 #define ROQ_IB2_START(x) ((x) << 8) 960 #define CP_MEQ_THRESHOLDS 0x21D9 961 #define MEQ1_START(x) ((x) << 0) 962 #define MEQ2_START(x) ((x) << 8) 963 964 #define CP_PERFMON_CNTL 0x21FF 965 966 #define VGT_VTX_VECT_EJECT_REG 0x222C 967 968 #define VGT_ESGS_RING_SIZE 0x2232 969 #define VGT_GSVS_RING_SIZE 0x2233 970 971 #define VGT_GS_VERTEX_REUSE 0x2235 972 973 #define VGT_PRIMITIVE_TYPE 0x2256 974 #define VGT_INDEX_TYPE 0x2257 975 976 #define VGT_NUM_INDICES 0x225C 977 #define VGT_NUM_INSTANCES 0x225D 978 979 #define VGT_TF_RING_SIZE 0x2262 980 981 #define VGT_HS_OFFCHIP_PARAM 0x226C 982 983 #define VGT_TF_MEMORY_BASE 0x226E 984 985 #define PA_CL_ENHANCE 0x2285 986 #define CLIP_VTX_REORDER_ENA (1 << 0) 987 #define NUM_CLIP_SEQ(x) ((x) << 1) 988 989 #define PA_SU_LINE_STIPPLE_VALUE 0x2298 990 991 #define PA_SC_LINE_STIPPLE_STATE 0x22C4 992 993 #define PA_SC_FORCE_EOV_MAX_CNTS 0x22C9 994 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 995 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 996 997 #define PA_SC_FIFO_SIZE 0x22F3 998 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) 999 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) 1000 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) 1001 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) 1002 1003 #define PA_SC_ENHANCE 0x22FC 1004 1005 #define SQ_CONFIG 0x2300 1006 1007 #define SQC_CACHES 0x2302 1008 1009 #define SQ_POWER_THROTTLE 0x2396 1010 #define MIN_POWER(x) ((x) << 0) 1011 #define MIN_POWER_MASK (0x3fff << 0) 1012 #define MIN_POWER_SHIFT 0 1013 #define MAX_POWER(x) ((x) << 16) 1014 #define MAX_POWER_MASK (0x3fff << 16) 1015 #define MAX_POWER_SHIFT 0 1016 #define SQ_POWER_THROTTLE2 0x2397 1017 #define MAX_POWER_DELTA(x) ((x) << 0) 1018 #define MAX_POWER_DELTA_MASK (0x3fff << 0) 1019 #define MAX_POWER_DELTA_SHIFT 0 1020 #define STI_SIZE(x) ((x) << 16) 1021 #define STI_SIZE_MASK (0x3ff << 16) 1022 #define STI_SIZE_SHIFT 16 1023 #define LTI_RATIO(x) ((x) << 27) 1024 #define LTI_RATIO_MASK (0xf << 27) 1025 #define LTI_RATIO_SHIFT 27 1026 1027 #define SX_DEBUG_1 0x2418 1028 1029 #define SPI_STATIC_THREAD_MGMT_1 0x2438 1030 #define SPI_STATIC_THREAD_MGMT_2 0x2439 1031 #define SPI_STATIC_THREAD_MGMT_3 0x243A 1032 #define SPI_PS_MAX_WAVE_ID 0x243B 1033 1034 #define SPI_CONFIG_CNTL 0x2440 1035 1036 #define SPI_CONFIG_CNTL_1 0x244F 1037 #define VTX_DONE_DELAY(x) ((x) << 0) 1038 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 1039 1040 #define CGTS_TCC_DISABLE 0x2452 1041 #define CGTS_USER_TCC_DISABLE 0x2453 1042 #define TCC_DISABLE_MASK 0xFFFF0000 1043 #define TCC_DISABLE_SHIFT 16 1044 #define CGTS_SM_CTRL_REG 0x2454 1045 #define OVERRIDE (1 << 21) 1046 #define LS_OVERRIDE (1 << 22) 1047 1048 #define SPI_LB_CU_MASK 0x24D5 1049 1050 #define TA_CNTL_AUX 0x2542 1051 1052 #define CC_RB_BACKEND_DISABLE 0x263D 1053 #define BACKEND_DISABLE(x) ((x) << 16) 1054 #define GB_ADDR_CONFIG 0x263E 1055 #define NUM_PIPES(x) ((x) << 0) 1056 #define NUM_PIPES_MASK 0x00000007 1057 #define NUM_PIPES_SHIFT 0 1058 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 1059 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 1060 #define PIPE_INTERLEAVE_SIZE_SHIFT 4 1061 #define NUM_SHADER_ENGINES(x) ((x) << 12) 1062 #define NUM_SHADER_ENGINES_MASK 0x00003000 1063 #define NUM_SHADER_ENGINES_SHIFT 12 1064 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 1065 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 1066 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 1067 #define NUM_GPUS(x) ((x) << 20) 1068 #define NUM_GPUS_MASK 0x00700000 1069 #define NUM_GPUS_SHIFT 20 1070 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 1071 #define MULTI_GPU_TILE_SIZE_MASK 0x03000000 1072 #define MULTI_GPU_TILE_SIZE_SHIFT 24 1073 #define ROW_SIZE(x) ((x) << 28) 1074 #define ROW_SIZE_MASK 0x30000000 1075 #define ROW_SIZE_SHIFT 28 1076 1077 #define CB_PERFCOUNTER0_SELECT0 0x2688 1078 #define CB_PERFCOUNTER0_SELECT1 0x2689 1079 #define CB_PERFCOUNTER1_SELECT0 0x268A 1080 #define CB_PERFCOUNTER1_SELECT1 0x268B 1081 #define CB_PERFCOUNTER2_SELECT0 0x268C 1082 #define CB_PERFCOUNTER2_SELECT1 0x268D 1083 #define CB_PERFCOUNTER3_SELECT0 0x268E 1084 #define CB_PERFCOUNTER3_SELECT1 0x268F 1085 1086 #define CB_CGTT_SCLK_CTRL 0x2698 1087 1088 #define TCP_CHAN_STEER_LO 0x2B03 1089 #define TCP_CHAN_STEER_HI 0x2B94 1090 1091 #define CP_RB0_BASE 0x3040 1092 #define CP_RB0_CNTL 0x3041 1093 #define RB_BUFSZ(x) ((x) << 0) 1094 #define RB_BLKSZ(x) ((x) << 8) 1095 #define BUF_SWAP_32BIT (2 << 16) 1096 #define RB_NO_UPDATE (1 << 27) 1097 #define RB_RPTR_WR_ENA (1 << 31) 1098 1099 #define CP_RB0_RPTR_ADDR 0x3043 1100 #define CP_RB0_RPTR_ADDR_HI 0x3044 1101 #define CP_RB0_WPTR 0x3045 1102 1103 #define CP_PFP_UCODE_ADDR 0x3054 1104 #define CP_PFP_UCODE_DATA 0x3055 1105 #define CP_ME_RAM_RADDR 0x3056 1106 #define CP_ME_RAM_WADDR 0x3057 1107 #define CP_ME_RAM_DATA 0x3058 1108 1109 #define CP_CE_UCODE_ADDR 0x305A 1110 #define CP_CE_UCODE_DATA 0x305B 1111 1112 #define CP_RB1_BASE 0x3060 1113 #define CP_RB1_CNTL 0x3061 1114 #define CP_RB1_RPTR_ADDR 0x3062 1115 #define CP_RB1_RPTR_ADDR_HI 0x3063 1116 #define CP_RB1_WPTR 0x3064 1117 #define CP_RB2_BASE 0x3065 1118 #define CP_RB2_CNTL 0x3066 1119 #define CP_RB2_RPTR_ADDR 0x3067 1120 #define CP_RB2_RPTR_ADDR_HI 0x3068 1121 #define CP_RB2_WPTR 0x3069 1122 #define CP_INT_CNTL_RING0 0x306A 1123 #define CP_INT_CNTL_RING1 0x306B 1124 #define CP_INT_CNTL_RING2 0x306C 1125 # define CNTX_BUSY_INT_ENABLE (1 << 19) 1126 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 1127 # define WAIT_MEM_SEM_INT_ENABLE (1 << 21) 1128 # define TIME_STAMP_INT_ENABLE (1 << 26) 1129 # define CP_RINGID2_INT_ENABLE (1 << 29) 1130 # define CP_RINGID1_INT_ENABLE (1 << 30) 1131 # define CP_RINGID0_INT_ENABLE (1 << 31) 1132 #define CP_INT_STATUS_RING0 0x306D 1133 #define CP_INT_STATUS_RING1 0x306E 1134 #define CP_INT_STATUS_RING2 0x306F 1135 # define WAIT_MEM_SEM_INT_STAT (1 << 21) 1136 # define TIME_STAMP_INT_STAT (1 << 26) 1137 # define CP_RINGID2_INT_STAT (1 << 29) 1138 # define CP_RINGID1_INT_STAT (1 << 30) 1139 # define CP_RINGID0_INT_STAT (1 << 31) 1140 1141 // #define PA_SC_RASTER_CONFIG 0xA0D4 1142 # define RB_XSEL2(x) ((x) << 4) 1143 # define RB_XSEL2_MASK (0x3 << 4) 1144 # define RB_XSEL (1 << 6) 1145 # define RB_YSEL (1 << 7) 1146 # define PKR_MAP(x) ((x) << 8) 1147 # define PKR_XSEL(x) ((x) << 10) 1148 # define PKR_XSEL_MASK (0x3 << 10) 1149 # define PKR_YSEL(x) ((x) << 12) 1150 # define PKR_YSEL_MASK (0x3 << 12) 1151 # define SC_MAP(x) ((x) << 16) 1152 # define SC_MAP_MASK (0x3 << 16) 1153 # define SC_XSEL(x) ((x) << 18) 1154 # define SC_XSEL_MASK (0x3 << 18) 1155 # define SC_YSEL(x) ((x) << 20) 1156 # define SC_YSEL_MASK (0x3 << 20) 1157 # define SE_MAP(x) ((x) << 24) 1158 # define SE_XSEL(x) ((x) << 26) 1159 # define SE_XSEL_MASK (0x3 << 26) 1160 # define SE_YSEL(x) ((x) << 28) 1161 # define SE_YSEL_MASK (0x3 << 28) 1162 1163 /* PIF PHY0 registers idx/data 0x8/0xc */ 1164 #define PB0_PIF_CNTL 0x10 1165 # define LS2_EXIT_TIME(x) ((x) << 17) 1166 # define LS2_EXIT_TIME_MASK (0x7 << 17) 1167 # define LS2_EXIT_TIME_SHIFT 17 1168 #define PB0_PIF_PAIRING 0x11 1169 # define MULTI_PIF (1 << 25) 1170 #define PB0_PIF_PWRDOWN_0 0x12 1171 # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7) 1172 # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7) 1173 # define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7 1174 # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10) 1175 # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10) 1176 # define PLL_POWER_STATE_IN_OFF_0_SHIFT 10 1177 # define PLL_RAMP_UP_TIME_0(x) ((x) << 24) 1178 # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24) 1179 # define PLL_RAMP_UP_TIME_0_SHIFT 24 1180 #define PB0_PIF_PWRDOWN_1 0x13 1181 # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7) 1182 # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7) 1183 # define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7 1184 # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10) 1185 # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10) 1186 # define PLL_POWER_STATE_IN_OFF_1_SHIFT 10 1187 # define PLL_RAMP_UP_TIME_1(x) ((x) << 24) 1188 # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24) 1189 # define PLL_RAMP_UP_TIME_1_SHIFT 24 1190 1191 #define PB0_PIF_PWRDOWN_2 0x17 1192 # define PLL_POWER_STATE_IN_TXS2_2(x) ((x) << 7) 1193 # define PLL_POWER_STATE_IN_TXS2_2_MASK (0x7 << 7) 1194 # define PLL_POWER_STATE_IN_TXS2_2_SHIFT 7 1195 # define PLL_POWER_STATE_IN_OFF_2(x) ((x) << 10) 1196 # define PLL_POWER_STATE_IN_OFF_2_MASK (0x7 << 10) 1197 # define PLL_POWER_STATE_IN_OFF_2_SHIFT 10 1198 # define PLL_RAMP_UP_TIME_2(x) ((x) << 24) 1199 # define PLL_RAMP_UP_TIME_2_MASK (0x7 << 24) 1200 # define PLL_RAMP_UP_TIME_2_SHIFT 24 1201 #define PB0_PIF_PWRDOWN_3 0x18 1202 # define PLL_POWER_STATE_IN_TXS2_3(x) ((x) << 7) 1203 # define PLL_POWER_STATE_IN_TXS2_3_MASK (0x7 << 7) 1204 # define PLL_POWER_STATE_IN_TXS2_3_SHIFT 7 1205 # define PLL_POWER_STATE_IN_OFF_3(x) ((x) << 10) 1206 # define PLL_POWER_STATE_IN_OFF_3_MASK (0x7 << 10) 1207 # define PLL_POWER_STATE_IN_OFF_3_SHIFT 10 1208 # define PLL_RAMP_UP_TIME_3(x) ((x) << 24) 1209 # define PLL_RAMP_UP_TIME_3_MASK (0x7 << 24) 1210 # define PLL_RAMP_UP_TIME_3_SHIFT 24 1211 /* PIF PHY1 registers idx/data 0x10/0x14 */ 1212 #define PB1_PIF_CNTL 0x10 1213 #define PB1_PIF_PAIRING 0x11 1214 #define PB1_PIF_PWRDOWN_0 0x12 1215 #define PB1_PIF_PWRDOWN_1 0x13 1216 1217 #define PB1_PIF_PWRDOWN_2 0x17 1218 #define PB1_PIF_PWRDOWN_3 0x18 1219 /* PCIE registers idx/data 0x30/0x34 */ 1220 #define PCIE_CNTL2 0x1c /* PCIE */ 1221 # define SLV_MEM_LS_EN (1 << 16) 1222 # define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17) 1223 # define MST_MEM_LS_EN (1 << 18) 1224 # define REPLAY_MEM_LS_EN (1 << 19) 1225 #define PCIE_LC_STATUS1 0x28 /* PCIE */ 1226 # define LC_REVERSE_RCVR (1 << 0) 1227 # define LC_REVERSE_XMIT (1 << 1) 1228 # define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2) 1229 # define LC_OPERATING_LINK_WIDTH_SHIFT 2 1230 # define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5) 1231 # define LC_DETECTED_LINK_WIDTH_SHIFT 5 1232 1233 #define PCIE_P_CNTL 0x40 /* PCIE */ 1234 # define P_IGNORE_EDB_ERR (1 << 6) 1235 1236 /* PCIE PORT registers idx/data 0x38/0x3c */ 1237 #define PCIE_LC_CNTL 0xa0 1238 # define LC_L0S_INACTIVITY(x) ((x) << 8) 1239 # define LC_L0S_INACTIVITY_MASK (0xf << 8) 1240 # define LC_L0S_INACTIVITY_SHIFT 8 1241 # define LC_L1_INACTIVITY(x) ((x) << 12) 1242 # define LC_L1_INACTIVITY_MASK (0xf << 12) 1243 # define LC_L1_INACTIVITY_SHIFT 12 1244 # define LC_PMI_TO_L1_DIS (1 << 16) 1245 # define LC_ASPM_TO_L1_DIS (1 << 24) 1246 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 1247 # define LC_LINK_WIDTH_SHIFT 0 1248 # define LC_LINK_WIDTH_MASK 0x7 1249 # define LC_LINK_WIDTH_X0 0 1250 # define LC_LINK_WIDTH_X1 1 1251 # define LC_LINK_WIDTH_X2 2 1252 # define LC_LINK_WIDTH_X4 3 1253 # define LC_LINK_WIDTH_X8 4 1254 # define LC_LINK_WIDTH_X16 6 1255 # define LC_LINK_WIDTH_RD_SHIFT 4 1256 # define LC_LINK_WIDTH_RD_MASK 0x70 1257 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 1258 # define LC_RECONFIG_NOW (1 << 8) 1259 # define LC_RENEGOTIATION_SUPPORT (1 << 9) 1260 # define LC_RENEGOTIATE_EN (1 << 10) 1261 # define LC_SHORT_RECONFIG_EN (1 << 11) 1262 # define LC_UPCONFIGURE_SUPPORT (1 << 12) 1263 # define LC_UPCONFIGURE_DIS (1 << 13) 1264 # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21) 1265 # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21) 1266 # define LC_DYN_LANES_PWR_STATE_SHIFT 21 1267 #define PCIE_LC_N_FTS_CNTL 0xa3 /* PCIE_P */ 1268 # define LC_XMIT_N_FTS(x) ((x) << 0) 1269 # define LC_XMIT_N_FTS_MASK (0xff << 0) 1270 # define LC_XMIT_N_FTS_SHIFT 0 1271 # define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8) 1272 # define LC_N_FTS_MASK (0xff << 24) 1273 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 1274 # define LC_GEN2_EN_STRAP (1 << 0) 1275 # define LC_GEN3_EN_STRAP (1 << 1) 1276 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2) 1277 # define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3) 1278 # define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3 1279 # define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5) 1280 # define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6) 1281 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7) 1282 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8) 1283 # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9) 1284 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10) 1285 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10 1286 # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */ 1287 # define LC_CURRENT_DATA_RATE_SHIFT 13 1288 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16) 1289 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18) 1290 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19) 1291 # define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20) 1292 # define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21) 1293 1294 #define PCIE_LC_CNTL2 0xb1 1295 # define LC_ALLOW_PDWN_IN_L1 (1 << 17) 1296 # define LC_ALLOW_PDWN_IN_L23 (1 << 18) 1297 1298 #define PCIE_LC_CNTL3 0xb5 /* PCIE_P */ 1299 # define LC_GO_TO_RECOVERY (1 << 30) 1300 #define PCIE_LC_CNTL4 0xb6 /* PCIE_P */ 1301 # define LC_REDO_EQ (1 << 5) 1302 # define LC_SET_QUIESCE (1 << 13) 1303 1304 /* 1305 * UVD 1306 */ 1307 #define UVD_UDEC_ADDR_CONFIG 0x3bd3 1308 #define UVD_UDEC_DB_ADDR_CONFIG 0x3bd4 1309 #define UVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 1310 #define UVD_RBC_RB_RPTR 0x3da4 1311 #define UVD_RBC_RB_WPTR 0x3da5 1312 #define UVD_STATUS 0x3daf 1313 1314 #define UVD_CGC_CTRL 0x3dc2 1315 # define DCM (1 << 0) 1316 # define CG_DT(x) ((x) << 2) 1317 # define CG_DT_MASK (0xf << 2) 1318 # define CLK_OD(x) ((x) << 6) 1319 # define CLK_OD_MASK (0x1f << 6) 1320 1321 /* UVD CTX indirect */ 1322 #define UVD_CGC_MEM_CTRL 0xC0 1323 #define UVD_CGC_CTRL2 0xC1 1324 # define DYN_OR_EN (1 << 0) 1325 # define DYN_RR_EN (1 << 1) 1326 # define G_DIV_ID(x) ((x) << 2) 1327 # define G_DIV_ID_MASK (0x7 << 2) 1328 1329 /* 1330 * PM4 1331 */ 1332 #define PACKET_TYPE0 0 1333 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 1334 ((reg) & 0xFFFF) | \ 1335 ((n) & 0x3FFF) << 16) 1336 #define CP_PACKET2 0x80000000 1337 #define PACKET2_PAD_SHIFT 0 1338 #define PACKET2_PAD_MASK (0x3fffffff << 0) 1339 1340 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 1341 #define RADEON_PACKET_TYPE3 3 1342 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 1343 (((op) & 0xFF) << 8) | \ 1344 ((n) & 0x3FFF) << 16) 1345 1346 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 1347 1348 /* Packet 3 types */ 1349 #define PACKET3_NOP 0x10 1350 #define PACKET3_SET_BASE 0x11 1351 #define PACKET3_BASE_INDEX(x) ((x) << 0) 1352 #define GDS_PARTITION_BASE 2 1353 #define CE_PARTITION_BASE 3 1354 #define PACKET3_CLEAR_STATE 0x12 1355 #define PACKET3_INDEX_BUFFER_SIZE 0x13 1356 #define PACKET3_DISPATCH_DIRECT 0x15 1357 #define PACKET3_DISPATCH_INDIRECT 0x16 1358 #define PACKET3_ALLOC_GDS 0x1B 1359 #define PACKET3_WRITE_GDS_RAM 0x1C 1360 #define PACKET3_ATOMIC_GDS 0x1D 1361 #define PACKET3_ATOMIC 0x1E 1362 #define PACKET3_OCCLUSION_QUERY 0x1F 1363 #define PACKET3_SET_PREDICATION 0x20 1364 #define PACKET3_REG_RMW 0x21 1365 #define PACKET3_COND_EXEC 0x22 1366 #define PACKET3_PRED_EXEC 0x23 1367 #define PACKET3_DRAW_INDIRECT 0x24 1368 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 1369 #define PACKET3_INDEX_BASE 0x26 1370 #define PACKET3_DRAW_INDEX_2 0x27 1371 #define PACKET3_CONTEXT_CONTROL 0x28 1372 #define PACKET3_INDEX_TYPE 0x2A 1373 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 1374 #define PACKET3_DRAW_INDEX_AUTO 0x2D 1375 #define PACKET3_DRAW_INDEX_IMMD 0x2E 1376 #define PACKET3_NUM_INSTANCES 0x2F 1377 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 1378 #define PACKET3_INDIRECT_BUFFER_CONST 0x31 1379 #define PACKET3_INDIRECT_BUFFER 0x3F 1380 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 1381 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 1382 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 1383 #define PACKET3_WRITE_DATA 0x37 1384 #define WRITE_DATA_DST_SEL(x) ((x) << 8) 1385 /* 0 - register 1386 * 1 - memory (sync - via GRBM) 1387 * 2 - tc/l2 1388 * 3 - gds 1389 * 4 - reserved 1390 * 5 - memory (async - direct) 1391 */ 1392 #define WR_ONE_ADDR (1 << 16) 1393 #define WR_CONFIRM (1 << 20) 1394 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 1395 /* 0 - me 1396 * 1 - pfp 1397 * 2 - ce 1398 */ 1399 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 1400 #define PACKET3_MEM_SEMAPHORE 0x39 1401 #define PACKET3_MPEG_INDEX 0x3A 1402 #define PACKET3_COPY_DW 0x3B 1403 #define PACKET3_WAIT_REG_MEM 0x3C 1404 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 1405 /* 0 - always 1406 * 1 - < 1407 * 2 - <= 1408 * 3 - == 1409 * 4 - != 1410 * 5 - >= 1411 * 6 - > 1412 */ 1413 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 1414 /* 0 - reg 1415 * 1 - mem 1416 */ 1417 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 1418 /* 0 - me 1419 * 1 - pfp 1420 */ 1421 #define PACKET3_MEM_WRITE 0x3D 1422 #define PACKET3_COPY_DATA 0x40 1423 #define PACKET3_CP_DMA 0x41 1424 /* 1. header 1425 * 2. SRC_ADDR_LO or DATA [31:0] 1426 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | 1427 * SRC_ADDR_HI [7:0] 1428 * 4. DST_ADDR_LO [31:0] 1429 * 5. DST_ADDR_HI [7:0] 1430 * 6. COMMAND [30:21] | BYTE_COUNT [20:0] 1431 */ 1432 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) 1433 /* 0 - DST_ADDR 1434 * 1 - GDS 1435 */ 1436 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) 1437 /* 0 - ME 1438 * 1 - PFP 1439 */ 1440 # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) 1441 /* 0 - SRC_ADDR 1442 * 1 - GDS 1443 * 2 - DATA 1444 */ 1445 # define PACKET3_CP_DMA_CP_SYNC (1 << 31) 1446 /* COMMAND */ 1447 # define PACKET3_CP_DMA_DIS_WC (1 << 21) 1448 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) 1449 /* 0 - none 1450 * 1 - 8 in 16 1451 * 2 - 8 in 32 1452 * 3 - 8 in 64 1453 */ 1454 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) 1455 /* 0 - none 1456 * 1 - 8 in 16 1457 * 2 - 8 in 32 1458 * 3 - 8 in 64 1459 */ 1460 # define PACKET3_CP_DMA_CMD_SAS (1 << 26) 1461 /* 0 - memory 1462 * 1 - register 1463 */ 1464 # define PACKET3_CP_DMA_CMD_DAS (1 << 27) 1465 /* 0 - memory 1466 * 1 - register 1467 */ 1468 # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) 1469 # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 1470 # define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30) 1471 #define PACKET3_PFP_SYNC_ME 0x42 1472 #define PACKET3_SURFACE_SYNC 0x43 1473 # define PACKET3_DEST_BASE_0_ENA (1 << 0) 1474 # define PACKET3_DEST_BASE_1_ENA (1 << 1) 1475 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 1476 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 1477 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 1478 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 1479 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 1480 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 1481 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 1482 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 1483 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 1484 # define PACKET3_DEST_BASE_2_ENA (1 << 19) 1485 # define PACKET3_DEST_BASE_3_ENA (1 << 21) 1486 # define PACKET3_TCL1_ACTION_ENA (1 << 22) 1487 # define PACKET3_TC_ACTION_ENA (1 << 23) 1488 # define PACKET3_CB_ACTION_ENA (1 << 25) 1489 # define PACKET3_DB_ACTION_ENA (1 << 26) 1490 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 1491 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 1492 #define PACKET3_ME_INITIALIZE 0x44 1493 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1494 #define PACKET3_COND_WRITE 0x45 1495 #define PACKET3_EVENT_WRITE 0x46 1496 #define EVENT_TYPE(x) ((x) << 0) 1497 #define EVENT_INDEX(x) ((x) << 8) 1498 /* 0 - any non-TS event 1499 * 1 - ZPASS_DONE 1500 * 2 - SAMPLE_PIPELINESTAT 1501 * 3 - SAMPLE_STREAMOUTSTAT* 1502 * 4 - *S_PARTIAL_FLUSH 1503 * 5 - EOP events 1504 * 6 - EOS events 1505 * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT 1506 */ 1507 #define INV_L2 (1 << 20) 1508 /* INV TC L2 cache when EVENT_INDEX = 7 */ 1509 #define PACKET3_EVENT_WRITE_EOP 0x47 1510 #define DATA_SEL(x) ((x) << 29) 1511 /* 0 - discard 1512 * 1 - send low 32bit data 1513 * 2 - send 64bit data 1514 * 3 - send 64bit counter value 1515 */ 1516 #define INT_SEL(x) ((x) << 24) 1517 /* 0 - none 1518 * 1 - interrupt only (DATA_SEL = 0) 1519 * 2 - interrupt when data write is confirmed 1520 */ 1521 #define PACKET3_EVENT_WRITE_EOS 0x48 1522 #define PACKET3_PREAMBLE_CNTL 0x4A 1523 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 1524 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 1525 #define PACKET3_ONE_REG_WRITE 0x57 1526 #define PACKET3_LOAD_CONFIG_REG 0x5F 1527 #define PACKET3_LOAD_CONTEXT_REG 0x60 1528 #define PACKET3_LOAD_SH_REG 0x61 1529 #define PACKET3_SET_CONFIG_REG 0x68 1530 #define PACKET3_SET_CONFIG_REG_START 0x00002000 1531 #define PACKET3_SET_CONFIG_REG_END 0x00002c00 1532 #define PACKET3_SET_CONTEXT_REG 0x69 1533 #define PACKET3_SET_CONTEXT_REG_START 0x000a000 1534 #define PACKET3_SET_CONTEXT_REG_END 0x000a400 1535 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 1536 #define PACKET3_SET_RESOURCE_INDIRECT 0x74 1537 #define PACKET3_SET_SH_REG 0x76 1538 #define PACKET3_SET_SH_REG_START 0x00002c00 1539 #define PACKET3_SET_SH_REG_END 0x00003000 1540 #define PACKET3_SET_SH_REG_OFFSET 0x77 1541 #define PACKET3_ME_WRITE 0x7A 1542 #define PACKET3_SCRATCH_RAM_WRITE 0x7D 1543 #define PACKET3_SCRATCH_RAM_READ 0x7E 1544 #define PACKET3_CE_WRITE 0x7F 1545 #define PACKET3_LOAD_CONST_RAM 0x80 1546 #define PACKET3_WRITE_CONST_RAM 0x81 1547 #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82 1548 #define PACKET3_DUMP_CONST_RAM 0x83 1549 #define PACKET3_INCREMENT_CE_COUNTER 0x84 1550 #define PACKET3_INCREMENT_DE_COUNTER 0x85 1551 #define PACKET3_WAIT_ON_CE_COUNTER 0x86 1552 #define PACKET3_WAIT_ON_DE_COUNTER 0x87 1553 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 1554 #define PACKET3_SET_CE_DE_COUNTERS 0x89 1555 #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A 1556 #define PACKET3_SWITCH_BUFFER 0x8B 1557 1558 /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */ 1559 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ 1560 #define DMA1_REGISTER_OFFSET 0x200 /* not a register */ 1561 1562 #define DMA_IB_RPTR 0x340a 1563 #define DMA_TILING_CONFIG 0x342e 1564 1565 #define DMA_PG 0x3435 1566 # define PG_CNTL_ENABLE (1 << 0) 1567 1568 #define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \ 1569 (((b) & 0x1) << 26) | \ 1570 (((t) & 0x1) << 23) | \ 1571 (((s) & 0x1) << 22) | \ 1572 (((n) & 0xFFFFF) << 0)) 1573 1574 #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \ 1575 (((vmid) & 0xF) << 20) | \ 1576 (((n) & 0xFFFFF) << 0)) 1577 1578 #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \ 1579 (1 << 26) | \ 1580 (1 << 21) | \ 1581 (((n) & 0xFFFFF) << 0)) 1582 1583 /* async DMA Packet types */ 1584 #define DMA_PACKET_WRITE 0x2 1585 #define DMA_PACKET_COPY 0x3 1586 #define DMA_PACKET_INDIRECT_BUFFER 0x4 1587 #define DMA_PACKET_SEMAPHORE 0x5 1588 #define DMA_PACKET_FENCE 0x6 1589 #define DMA_PACKET_TRAP 0x7 1590 #define DMA_PACKET_SRBM_WRITE 0x9 1591 #define DMA_PACKET_CONSTANT_FILL 0xd 1592 #define DMA_PACKET_POLL_REG_MEM 0xe 1593 #define DMA_PACKET_NOP 0xf 1594 1595 /* VCE */ 1596 #define VCE_STATUS 0x20004 1597 #define VCE_VCPU_CNTL 0x20014 1598 #define VCE_CLK_EN (1 << 0) 1599 #define VCE_VCPU_CACHE_OFFSET0 0x20024 1600 #define VCE_VCPU_CACHE_SIZE0 0x20028 1601 #define VCE_VCPU_CACHE_OFFSET1 0x2002c 1602 #define VCE_VCPU_CACHE_SIZE1 0x20030 1603 #define VCE_VCPU_CACHE_OFFSET2 0x20034 1604 #define VCE_VCPU_CACHE_SIZE2 0x20038 1605 #define VCE_SOFT_RESET 0x20120 1606 #define VCE_ECPU_SOFT_RESET (1 << 0) 1607 #define VCE_FME_SOFT_RESET (1 << 2) 1608 #define VCE_RB_BASE_LO2 0x2016c 1609 #define VCE_RB_BASE_HI2 0x20170 1610 #define VCE_RB_SIZE2 0x20174 1611 #define VCE_RB_RPTR2 0x20178 1612 #define VCE_RB_WPTR2 0x2017c 1613 #define VCE_RB_BASE_LO 0x20180 1614 #define VCE_RB_BASE_HI 0x20184 1615 #define VCE_RB_SIZE 0x20188 1616 #define VCE_RB_RPTR 0x2018c 1617 #define VCE_RB_WPTR 0x20190 1618 #define VCE_CLOCK_GATING_A 0x202f8 1619 #define VCE_CLOCK_GATING_B 0x202fc 1620 #define VCE_UENC_CLOCK_GATING 0x205bc 1621 #define VCE_UENC_REG_CLOCK_GATING 0x205c0 1622 #define VCE_FW_REG_STATUS 0x20e10 1623 # define VCE_FW_REG_STATUS_BUSY (1 << 0) 1624 # define VCE_FW_REG_STATUS_PASS (1 << 3) 1625 # define VCE_FW_REG_STATUS_DONE (1 << 11) 1626 #define VCE_LMI_FW_START_KEYSEL 0x20e18 1627 #define VCE_LMI_FW_PERIODIC_CTRL 0x20e20 1628 #define VCE_LMI_CTRL2 0x20e74 1629 #define VCE_LMI_CTRL 0x20e98 1630 #define VCE_LMI_VM_CTRL 0x20ea0 1631 #define VCE_LMI_SWAP_CNTL 0x20eb4 1632 #define VCE_LMI_SWAP_CNTL1 0x20eb8 1633 #define VCE_LMI_CACHE_CTRL 0x20ef4 1634 1635 #define VCE_CMD_NO_OP 0x00000000 1636 #define VCE_CMD_END 0x00000001 1637 #define VCE_CMD_IB 0x00000002 1638 #define VCE_CMD_FENCE 0x00000003 1639 #define VCE_CMD_TRAP 0x00000004 1640 #define VCE_CMD_IB_AUTO 0x00000005 1641 #define VCE_CMD_SEMAPHORE 0x00000006 1642 1643 1644 //#dce stupp 1645 /* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */ 1646 #define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c) //(0x6df0 - 0x6df0)/4 1647 #define CRTC1_REGISTER_OFFSET (0x1e7c - 0x1b7c) //(0x79f0 - 0x6df0)/4 1648 #define CRTC2_REGISTER_OFFSET (0x417c - 0x1b7c) //(0x105f0 - 0x6df0)/4 1649 #define CRTC3_REGISTER_OFFSET (0x447c - 0x1b7c) //(0x111f0 - 0x6df0)/4 1650 #define CRTC4_REGISTER_OFFSET (0x477c - 0x1b7c) //(0x11df0 - 0x6df0)/4 1651 #define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c) //(0x129f0 - 0x6df0)/4 1652 1653 /* hpd instance offsets */ 1654 #define HPD0_REGISTER_OFFSET (0x1807 - 0x1807) 1655 #define HPD1_REGISTER_OFFSET (0x180a - 0x1807) 1656 #define HPD2_REGISTER_OFFSET (0x180d - 0x1807) 1657 #define HPD3_REGISTER_OFFSET (0x1810 - 0x1807) 1658 #define HPD4_REGISTER_OFFSET (0x1813 - 0x1807) 1659 #define HPD5_REGISTER_OFFSET (0x1816 - 0x1807) 1660 1661 /* audio endpt instance offsets */ 1662 #define AUD0_REGISTER_OFFSET (0x1780 - 0x1780) 1663 #define AUD1_REGISTER_OFFSET (0x1786 - 0x1780) 1664 #define AUD2_REGISTER_OFFSET (0x178c - 0x1780) 1665 #define AUD3_REGISTER_OFFSET (0x1792 - 0x1780) 1666 #define AUD4_REGISTER_OFFSET (0x1798 - 0x1780) 1667 #define AUD5_REGISTER_OFFSET (0x179d - 0x1780) 1668 #define AUD6_REGISTER_OFFSET (0x17a4 - 0x1780) 1669 1670 #define CURSOR_WIDTH 64 1671 #define CURSOR_HEIGHT 64 1672 #define AMDGPU_MM_INDEX 0x0000 1673 #define AMDGPU_MM_DATA 0x0001 1674 1675 #define VERDE_NUM_CRTC 6 1676 #define BLACKOUT_MODE_MASK 0x00000007 1677 #define VGA_RENDER_CONTROL 0xC0 1678 #define R_000300_VGA_RENDER_CONTROL 0xC0 1679 #define C_000300_VGA_VSTATUS_CNTL 0xFFFCFFFF 1680 #define EVERGREEN_CRTC_STATUS 0x1BA3 1681 #define EVERGREEN_CRTC_V_BLANK (1 << 0) 1682 #define EVERGREEN_CRTC_STATUS_POSITION 0x1BA4 1683 /* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */ 1684 #define EVERGREEN_CRTC_V_BLANK_START_END 0x1b8d 1685 #define EVERGREEN_CRTC_CONTROL 0x1b9c 1686 #define EVERGREEN_CRTC_MASTER_EN (1 << 0) 1687 #define EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24) 1688 #define EVERGREEN_CRTC_BLANK_CONTROL 0x1b9d 1689 #define EVERGREEN_CRTC_BLANK_DATA_EN (1 << 8) 1690 #define EVERGREEN_CRTC_V_BLANK (1 << 0) 1691 #define EVERGREEN_CRTC_STATUS_HV_COUNT 0x1ba8 1692 #define EVERGREEN_CRTC_UPDATE_LOCK 0x1bb5 1693 #define EVERGREEN_MASTER_UPDATE_LOCK 0x1bbd 1694 #define EVERGREEN_MASTER_UPDATE_MODE 0x1bbe 1695 #define EVERGREEN_GRPH_UPDATE_LOCK (1 << 16) 1696 #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 1697 #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 1698 #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 1699 #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 1700 #define EVERGREEN_GRPH_UPDATE 0x1a11 1701 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0xc4 1702 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0xc9 1703 #define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING (1 << 2) 1704 1705 #define EVERGREEN_DATA_FORMAT 0x1ac0 1706 # define EVERGREEN_INTERLEAVE_EN (1 << 0) 1707 1708 #define R600_D1GRPH_ARRAY_MODE_LINEAR_GENERAL (0 << 20) 1709 #define R600_D1GRPH_ARRAY_MODE_LINEAR_ALIGNED (1 << 20) 1710 #define R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1 (2 << 20) 1711 #define R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1 (4 << 20) 1712 1713 #define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a45 1714 #define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1845 1715 1716 #define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1847 1717 #define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a47 1718 1719 #define R600_D1GRPH_SWAP_CONTROL 0x1843 1720 #define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0) 1721 #define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0) 1722 #define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0) 1723 #define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0) 1724 1725 #define AVIVO_D1VGA_CONTROL 0x00cc 1726 # define AVIVO_DVGA_CONTROL_MODE_ENABLE (1 << 0) 1727 # define AVIVO_DVGA_CONTROL_TIMING_SELECT (1 << 8) 1728 # define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1 << 9) 1729 # define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1 << 10) 1730 # define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1 << 16) 1731 # define AVIVO_DVGA_CONTROL_ROTATE (1 << 24) 1732 #define AVIVO_D2VGA_CONTROL 0x00ce 1733 1734 #define R600_BUS_CNTL 0x1508 1735 # define R600_BIOS_ROM_DIS (1 << 1) 1736 1737 #define R600_ROM_CNTL 0x580 1738 # define R600_SCK_OVERWRITE (1 << 1) 1739 # define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28 1740 # define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28) 1741 1742 #define FMT_BIT_DEPTH_CONTROL 0x1bf2 1743 #define FMT_TRUNCATE_EN (1 << 0) 1744 #define FMT_TRUNCATE_DEPTH (1 << 4) 1745 #define FMT_SPATIAL_DITHER_EN (1 << 8) 1746 #define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9) 1747 #define FMT_SPATIAL_DITHER_DEPTH (1 << 12) 1748 #define FMT_FRAME_RANDOM_ENABLE (1 << 13) 1749 #define FMT_RGB_RANDOM_ENABLE (1 << 14) 1750 #define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15) 1751 #define FMT_TEMPORAL_DITHER_EN (1 << 16) 1752 #define FMT_TEMPORAL_DITHER_DEPTH (1 << 20) 1753 #define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21) 1754 #define FMT_TEMPORAL_LEVEL (1 << 24) 1755 #define FMT_TEMPORAL_DITHER_RESET (1 << 25) 1756 #define FMT_25FRC_SEL(x) ((x) << 26) 1757 #define FMT_50FRC_SEL(x) ((x) << 28) 1758 #define FMT_75FRC_SEL(x) ((x) << 30) 1759 1760 #define EVERGREEN_D3VGA_CONTROL 0xf8 1761 #define EVERGREEN_D4VGA_CONTROL 0xf9 1762 #define EVERGREEN_D5VGA_CONTROL 0xfa 1763 #define EVERGREEN_D6VGA_CONTROL 0xfb 1764 1765 #define EVERGREEN_GRPH_SURFACE_ADDRESS_MASK 0xffffff00 1766 1767 #define EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL 0x1a02 1768 #define EVERGREEN_LUT_10BIT_BYPASS_EN (1 << 8) 1769 1770 #define EVERGREEN_GRPH_PITCH 0x1a06 1771 #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 1772 #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 1773 #define EVERGREEN_GRPH_SURFACE_OFFSET_X 0x1a09 1774 #define EVERGREEN_GRPH_SURFACE_OFFSET_Y 0x1a0a 1775 #define EVERGREEN_GRPH_X_START 0x1a0b 1776 #define EVERGREEN_GRPH_Y_START 0x1a0c 1777 #define EVERGREEN_GRPH_X_END 0x1a0d 1778 #define EVERGREEN_GRPH_Y_END 0x1a0e 1779 #define EVERGREEN_GRPH_UPDATE 0x1a11 1780 #define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING (1 << 2) 1781 #define EVERGREEN_GRPH_UPDATE_LOCK (1 << 16) 1782 #define EVERGREEN_GRPH_FLIP_CONTROL 0x1a12 1783 #define EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN (1 << 0) 1784 1785 #define EVERGREEN_VIEWPORT_START 0x1b5c 1786 #define EVERGREEN_VIEWPORT_SIZE 0x1b5d 1787 #define EVERGREEN_DESKTOP_HEIGHT 0x1ac1 1788 1789 #define GRPH_ARRAY_LINEAR_GENERAL 0 1790 #define GRPH_ARRAY_LINEAR_ALIGNED 1 1791 #define GRPH_ARRAY_1D_TILED_THIN1 2 1792 #define GRPH_ARRAY_2D_TILED_THIN1 4 1793 1794 #define ES_AND_GS_AUTO 3 1795 #define BUF_SWAP_32BIT (2 << 16) 1796 1797 /* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */ 1798 #define EVERGREEN_CUR_CONTROL 0x1a66 1799 # define EVERGREEN_CURSOR_EN (1 << 0) 1800 # define EVERGREEN_CURSOR_MODE(x) (((x) & 0x3) << 8) 1801 # define EVERGREEN_CURSOR_MONO 0 1802 # define EVERGREEN_CURSOR_24_1 1 1803 # define EVERGREEN_CURSOR_24_8_PRE_MULT 2 1804 # define EVERGREEN_CURSOR_24_8_UNPRE_MULT 3 1805 # define EVERGREEN_CURSOR_2X_MAGNIFY (1 << 16) 1806 # define EVERGREEN_CURSOR_FORCE_MC_ON (1 << 20) 1807 # define EVERGREEN_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24) 1808 # define EVERGREEN_CURSOR_URGENT_ALWAYS 0 1809 # define EVERGREEN_CURSOR_URGENT_1_8 1 1810 # define EVERGREEN_CURSOR_URGENT_1_4 2 1811 # define EVERGREEN_CURSOR_URGENT_3_8 3 1812 # define EVERGREEN_CURSOR_URGENT_1_2 4 1813 #define EVERGREEN_CUR_SURFACE_ADDRESS 0x1a67 1814 # define EVERGREEN_CUR_SURFACE_ADDRESS_MASK 0xfffff000 1815 #define EVERGREEN_CUR_SIZE 0x1a68 1816 #define EVERGREEN_CUR_SURFACE_ADDRESS_HIGH 0x1a69 1817 #define EVERGREEN_CUR_POSITION 0x1a6a 1818 #define EVERGREEN_CUR_HOT_SPOT 0x1a6b 1819 #define EVERGREEN_CUR_COLOR1 0x1a6c 1820 #define EVERGREEN_CUR_COLOR2 0x1a6d 1821 #define EVERGREEN_CUR_UPDATE 0x1a6e 1822 # define EVERGREEN_CURSOR_UPDATE_PENDING (1 << 0) 1823 # define EVERGREEN_CURSOR_UPDATE_TAKEN (1 << 1) 1824 # define EVERGREEN_CURSOR_UPDATE_LOCK (1 << 16) 1825 # define EVERGREEN_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24) 1826 1827 #define BLACKOUT_MODE_MASK 0x00000007 1828 #define VGA_RENDER_CONTROL 0xC0 1829 #define R_000300_VGA_RENDER_CONTROL 0xC0 1830 #define C_000300_VGA_VSTATUS_CNTL 0xFFFCFFFF 1831 #define EVERGREEN_CRTC_STATUS 0x1BA3 1832 #define EVERGREEN_CRTC_V_BLANK (1 << 0) 1833 #define EVERGREEN_CRTC_STATUS_POSITION 0x1BA4 1834 /* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */ 1835 #define EVERGREEN_CRTC_V_BLANK_START_END 0x1b8d 1836 #define EVERGREEN_CRTC_CONTROL 0x1b9c 1837 # define EVERGREEN_CRTC_MASTER_EN (1 << 0) 1838 # define EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24) 1839 #define EVERGREEN_CRTC_BLANK_CONTROL 0x1b9d 1840 # define EVERGREEN_CRTC_BLANK_DATA_EN (1 << 8) 1841 # define EVERGREEN_CRTC_V_BLANK (1 << 0) 1842 #define EVERGREEN_CRTC_STATUS_HV_COUNT 0x1ba8 1843 #define EVERGREEN_CRTC_UPDATE_LOCK 0x1bb5 1844 #define EVERGREEN_MASTER_UPDATE_LOCK 0x1bbd 1845 #define EVERGREEN_MASTER_UPDATE_MODE 0x1bbe 1846 #define EVERGREEN_GRPH_UPDATE_LOCK (1 << 16) 1847 #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 1848 #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 1849 #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 1850 #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 1851 #define EVERGREEN_GRPH_UPDATE 0x1a11 1852 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0xc4 1853 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0xc9 1854 #define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING (1 << 2) 1855 1856 #define mmVM_CONTEXT1_CNTL__xxRANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10 1857 #define mmVM_CONTEXT1_CNTL__xxRANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 1858 #define mmVM_CONTEXT1_CNTL__xxDUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80 1859 #define mmVM_CONTEXT1_CNTL__xxDUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 1860 #define mmVM_CONTEXT1_CNTL__xxPDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400 1861 #define mmVM_CONTEXT1_CNTL__xxPDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 1862 #define mmVM_CONTEXT1_CNTL__xxVALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000 1863 #define mmVM_CONTEXT1_CNTL__xxVALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd 1864 #define mmVM_CONTEXT1_CNTL__xxREAD_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000 1865 #define mmVM_CONTEXT1_CNTL__xxREAD_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 1866 #define mmVM_CONTEXT1_CNTL__xxWRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000 1867 #define mmVM_CONTEXT1_CNTL__xxWRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 1868 1869 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxVMID_MASK 0x1e000000 1870 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxVMID__SHIFT 0x19 1871 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxPROTECTIONS_MASK 0xff 1872 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxPROTECTIONS__SHIFT 0x0 1873 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_ID_MASK 0xff000 1874 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_ID__SHIFT 0xc 1875 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_RW_MASK 0x1000000 1876 #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS__xxMEMORY_CLIENT_RW__SHIFT 0x18 1877 1878 #define mmMC_SHARED_BLACKOUT_CNTL__xxBLACKOUT_MODE_MASK 0x7 1879 #define mmMC_SHARED_BLACKOUT_CNTL__xxBLACKOUT_MODE__SHIFT 0x0 1880 1881 #define mmBIF_FB_EN__xxFB_READ_EN_MASK 0x1 1882 #define mmBIF_FB_EN__xxFB_READ_EN__SHIFT 0x0 1883 #define mmBIF_FB_EN__xxFB_WRITE_EN_MASK 0x2 1884 #define mmBIF_FB_EN__xxFB_WRITE_EN__SHIFT 0x1 1885 1886 #define GRPH_DEPTH_8BPP 0 1887 #define GRPH_DEPTH_16BPP 1 1888 #define GRPH_DEPTH_32BPP 2 1889 1890 /* 8 BPP */ 1891 #define GRPH_FORMAT_INDEXED 0 1892 1893 /* 16 BPP */ 1894 #define GRPH_FORMAT_ARGB1555 0 1895 #define GRPH_FORMAT_ARGB565 1 1896 #define GRPH_FORMAT_ARGB4444 2 1897 #define GRPH_FORMAT_AI88 3 1898 #define GRPH_FORMAT_MONO16 4 1899 #define GRPH_FORMAT_BGRA5551 5 1900 1901 /* 32 BPP */ 1902 #define GRPH_FORMAT_ARGB8888 0 1903 #define GRPH_FORMAT_ARGB2101010 1 1904 #define GRPH_FORMAT_32BPP_DIG 2 1905 #define GRPH_FORMAT_8B_ARGB2101010 3 1906 #define GRPH_FORMAT_BGRA1010102 4 1907 #define GRPH_FORMAT_8B_BGRA1010102 5 1908 #define GRPH_FORMAT_RGB111110 6 1909 #define GRPH_FORMAT_BGR101111 7 1910 1911 #define GRPH_ENDIAN_NONE 0 1912 #define GRPH_ENDIAN_8IN16 1 1913 #define GRPH_ENDIAN_8IN32 2 1914 #define GRPH_ENDIAN_8IN64 3 1915 #define GRPH_RED_SEL_R 0 1916 #define GRPH_RED_SEL_G 1 1917 #define GRPH_RED_SEL_B 2 1918 #define GRPH_RED_SEL_A 3 1919 1920 #define GRPH_GREEN_SEL_G 0 1921 #define GRPH_GREEN_SEL_B 1 1922 #define GRPH_GREEN_SEL_A 2 1923 #define GRPH_GREEN_SEL_R 3 1924 1925 #define GRPH_BLUE_SEL_B 0 1926 #define GRPH_BLUE_SEL_A 1 1927 #define GRPH_BLUE_SEL_R 2 1928 #define GRPH_BLUE_SEL_G 3 1929 1930 #define GRPH_ALPHA_SEL_A 0 1931 #define GRPH_ALPHA_SEL_R 1 1932 #define GRPH_ALPHA_SEL_G 2 1933 #define GRPH_ALPHA_SEL_B 3 1934 1935 /* CUR_CONTROL */ 1936 #define CURSOR_MONO 0 1937 #define CURSOR_24_1 1 1938 #define CURSOR_24_8_PRE_MULT 2 1939 #define CURSOR_24_8_UNPRE_MULT 3 1940 #define CURSOR_URGENT_ALWAYS 0 1941 #define CURSOR_URGENT_1_8 1 1942 #define CURSOR_URGENT_1_4 2 1943 #define CURSOR_URGENT_3_8 3 1944 #define CURSOR_URGENT_1_2 4 1945 1946 /* INPUT_CSC_CONTROL */ 1947 # define INPUT_CSC_BYPASS 0 1948 # define INPUT_CSC_PROG_COEFF 1 1949 # define INPUT_CSC_PROG_SHARED_MATRIXA 2 1950 1951 /* OUTPUT_CSC_CONTROL */ 1952 # define OUTPUT_CSC_BYPASS 0 1953 # define OUTPUT_CSC_TV_RGB 1 1954 # define OUTPUT_CSC_YCBCR_601 2 1955 # define OUTPUT_CSC_YCBCR_709 3 1956 # define OUTPUT_CSC_PROG_COEFF 4 1957 # define OUTPUT_CSC_PROG_SHARED_MATRIXB 5 1958 1959 /* DEGAMMA_CONTROL */ 1960 # define DEGAMMA_BYPASS 0 1961 # define DEGAMMA_SRGB_24 1 1962 # define DEGAMMA_XVYCC_222 2 1963 1964 /* GAMUT_REMAP_CONTROL */ 1965 # define GAMUT_REMAP_BYPASS 0 1966 # define GAMUT_REMAP_PROG_COEFF 1 1967 # define GAMUT_REMAP_PROG_SHARED_MATRIXA 2 1968 # define GAMUT_REMAP_PROG_SHARED_MATRIXB 3 1969 1970 /* REGAMMA_CONTROL */ 1971 # define REGAMMA_BYPASS 0 1972 # define REGAMMA_SRGB_24 1 1973 # define REGAMMA_XVYCC_222 2 1974 # define REGAMMA_PROG_A 3 1975 # define REGAMMA_PROG_B 4 1976 1977 1978 /* INPUT_GAMMA_CONTROL */ 1979 # define INPUT_GAMMA_USE_LUT 0 1980 # define INPUT_GAMMA_BYPASS 1 1981 # define INPUT_GAMMA_SRGB_24 2 1982 # define INPUT_GAMMA_XVYCC_222 3 1983 1984 #define mmSRBM_SOFT_RESET__xxSOFT_RESET_VMC_MASK 0x20000 1985 #define mmSRBM_SOFT_RESET__xxSOFT_RESET_VMC__SHIFT 0x11 1986 #define mmSRBM_SOFT_RESET__xxSOFT_RESET_MC_MASK 0x800 1987 #define mmSRBM_SOFT_RESET__xxSOFT_RESET_MC__SHIFT 0xb 1988 1989 #define MC_SEQ_MISC0__MT__MASK 0xf0000000 1990 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000 1991 #define MC_SEQ_MISC0__MT__DDR2 0x20000000 1992 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000 1993 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000 1994 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000 1995 #define MC_SEQ_MISC0__MT__HBM 0x60000000 1996 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000 1997 1998 #define CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK 0x4000000 1999 #define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12) 2000 #define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 2001 #define PACKET3_SEM_SEL_WAIT (0x7 << 29) 2002 2003 #define CONFIG_CNTL 0x1509 2004 #define CC_DRM_ID_STRAPS 0X1559 2005 #define AMDGPU_PCIE_INDEX 0xc 2006 #define AMDGPU_PCIE_DATA 0xd 2007 2008 #define DMA_MODE 0x342f 2009 #define DMA_BUSY_MASK 0x20 2010 #define SDMA_MAX_INSTANCE 2 2011 2012 #define PCIE_BUS_CLK 10000 2013 #define TCLK (PCIE_BUS_CLK / 10) 2014 #define PCIE_PORT_INDEX 0xe 2015 #define PCIE_PORT_DATA 0xf 2016 #define EVERGREEN_PIF_PHY0_INDEX 0x8 2017 #define EVERGREEN_PIF_PHY0_DATA 0xc 2018 #define EVERGREEN_PIF_PHY1_INDEX 0x10 2019 #define EVERGREEN_PIF_PHY1_DATA 0x14 2020 2021 #define MC_VM_FB_OFFSET 0x81a 2022 2023 /* Discrete VCE clocks */ 2024 #define CG_VCEPLL_FUNC_CNTL 0xc0030600 2025 #define VCEPLL_RESET_MASK 0x00000001 2026 #define VCEPLL_SLEEP_MASK 0x00000002 2027 #define VCEPLL_BYPASS_EN_MASK 0x00000004 2028 #define VCEPLL_CTLREQ_MASK 0x00000008 2029 #define VCEPLL_VCO_MODE_MASK 0x00000600 2030 #define VCEPLL_REF_DIV_MASK 0x003F0000 2031 #define VCEPLL_CTLACK_MASK 0x40000000 2032 #define VCEPLL_CTLACK2_MASK 0x80000000 2033 2034 #define CG_VCEPLL_FUNC_CNTL_2 0xc0030601 2035 #define VCEPLL_PDIV_A(x) ((x) << 0) 2036 #define VCEPLL_PDIV_A_MASK 0x0000007F 2037 #define VCEPLL_PDIV_B(x) ((x) << 8) 2038 #define VCEPLL_PDIV_B_MASK 0x00007F00 2039 #define EVCLK_SRC_SEL(x) ((x) << 20) 2040 #define EVCLK_SRC_SEL_MASK 0x01F00000 2041 #define ECCLK_SRC_SEL(x) ((x) << 25) 2042 #define ECCLK_SRC_SEL_MASK 0x3E000000 2043 2044 #define CG_VCEPLL_FUNC_CNTL_3 0xc0030602 2045 #define VCEPLL_FB_DIV(x) ((x) << 0) 2046 #define VCEPLL_FB_DIV_MASK 0x01FFFFFF 2047 2048 #define CG_VCEPLL_FUNC_CNTL_4 0xc0030603 2049 2050 #define CG_VCEPLL_FUNC_CNTL_5 0xc0030604 2051 #define CG_VCEPLL_SPREAD_SPECTRUM 0xc0030606 2052 #define VCEPLL_SSEN_MASK 0x00000001 2053 2054 2055 #endif 2056