1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #ifndef SI_H 25 #define SI_H 26 27 #define SI_MAX_CTLACKS_ASSERTION_WAIT 100 28 29 /* CG IND registers are accessed via SMC indirect space + SMC_CG_IND_START */ 30 #define SMC_CG_IND_START 0xc0030000 31 #define SMC_CG_IND_END 0xc0040000 32 33 /* SMC IND registers */ 34 #define SMC_SYSCON_RESET_CNTL 0x80000000 35 # define RST_REG (1 << 0) 36 #define SMC_SYSCON_CLOCK_CNTL_0 0x80000004 37 # define CK_DISABLE (1 << 0) 38 # define CKEN (1 << 24) 39 40 #define DCCG_DISP_SLOW_SELECT_REG 0x13F 41 #define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0) 42 #define DCCG_DISP1_SLOW_SELECT_MASK (7 << 0) 43 #define DCCG_DISP1_SLOW_SELECT_SHIFT 0 44 #define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4) 45 #define DCCG_DISP2_SLOW_SELECT_MASK (7 << 4) 46 #define DCCG_DISP2_SLOW_SELECT_SHIFT 4 47 48 /* discrete uvd clocks */ 49 #define CG_UPLL_FUNC_CNTL 0x18d 50 # define UPLL_RESET_MASK 0x00000001 51 # define UPLL_SLEEP_MASK 0x00000002 52 # define UPLL_BYPASS_EN_MASK 0x00000004 53 # define UPLL_CTLREQ_MASK 0x00000008 54 # define UPLL_VCO_MODE_MASK 0x00000600 55 # define UPLL_REF_DIV_MASK 0x003F0000 56 # define UPLL_CTLACK_MASK 0x40000000 57 # define UPLL_CTLACK2_MASK 0x80000000 58 #define CG_UPLL_FUNC_CNTL_2 0x18e 59 # define UPLL_PDIV_A(x) ((x) << 0) 60 # define UPLL_PDIV_A_MASK 0x0000007F 61 # define UPLL_PDIV_B(x) ((x) << 8) 62 # define UPLL_PDIV_B_MASK 0x00007F00 63 # define VCLK_SRC_SEL(x) ((x) << 20) 64 # define VCLK_SRC_SEL_MASK 0x01F00000 65 # define DCLK_SRC_SEL(x) ((x) << 25) 66 # define DCLK_SRC_SEL_MASK 0x3E000000 67 #define CG_UPLL_FUNC_CNTL_3 0x18f 68 # define UPLL_FB_DIV(x) ((x) << 0) 69 # define UPLL_FB_DIV_MASK 0x01FFFFFF 70 #define CG_UPLL_FUNC_CNTL_4 0x191 71 # define UPLL_SPARE_ISPARE9 0x00020000 72 #define CG_UPLL_FUNC_CNTL_5 0x192 73 # define RESET_ANTI_MUX_MASK 0x00000200 74 #define CG_UPLL_SPREAD_SPECTRUM 0x194 75 # define SSEN_MASK 0x00000001 76 77 #define VM_INVALIDATE_REQUEST 0x51E 78 #define VM_INVALIDATE_RESPONSE 0x51F 79 80 #define VM_L2_CG 0x570 81 #define MC_CG_ENABLE (1 << 18) 82 #define MC_LS_ENABLE (1 << 19) 83 84 #define MC_SHARED_CHMAP 0x801 85 #define NOOFCHAN_SHIFT 12 86 #define NOOFCHAN_MASK 0x0000f000 87 #define MC_SHARED_CHREMAP 0x802 88 89 #define MC_VM_FB_LOCATION 0x809 90 #define MC_VM_AGP_TOP 0x80A 91 #define MC_VM_AGP_BOT 0x80B 92 #define MC_VM_AGP_BASE 0x80C 93 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x80D 94 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x80E 95 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x80F 96 97 #define MC_VM_MX_L1_TLB_CNTL 0x819 98 #define ENABLE_L1_TLB (1 << 0) 99 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 100 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 101 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 102 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 103 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 104 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 105 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 106 107 #define MC_SHARED_BLACKOUT_CNTL 0x82B 108 109 #define MC_HUB_MISC_HUB_CG 0x82E 110 #define MC_HUB_MISC_VM_CG 0x82F 111 112 #define MC_HUB_MISC_SIP_CG 0x830 113 114 #define MC_XPB_CLK_GAT 0x91E 115 116 #define MC_CITF_MISC_RD_CG 0x992 117 #define MC_CITF_MISC_WR_CG 0x993 118 #define MC_CITF_MISC_VM_CG 0x994 119 120 #define MC_ARB_DRAM_TIMING 0x9DD 121 #define MC_ARB_DRAM_TIMING2 0x9DE 122 123 #define MC_ARB_BURST_TIME 0xA02 124 #define STATE0(x) ((x) << 0) 125 #define STATE0_MASK (0x1f << 0) 126 #define STATE0_SHIFT 0 127 #define STATE1(x) ((x) << 5) 128 #define STATE1_MASK (0x1f << 5) 129 #define STATE1_SHIFT 5 130 #define STATE2(x) ((x) << 10) 131 #define STATE2_MASK (0x1f << 10) 132 #define STATE2_SHIFT 10 133 #define STATE3(x) ((x) << 15) 134 #define STATE3_MASK (0x1f << 15) 135 #define STATE3_SHIFT 15 136 137 #define MC_SEQ_TRAIN_WAKEUP_CNTL 0xA3A 138 #define TRAIN_DONE_D0 (1 << 30) 139 #define TRAIN_DONE_D1 (1 << 31) 140 141 #define MC_SEQ_SUP_CNTL 0xA32 142 #define RUN_MASK (1 << 0) 143 #define MC_SEQ_SUP_PGM 0xA33 144 #define MC_PMG_AUTO_CMD 0xA34 145 146 #define MC_IO_PAD_CNTL_D0 0xA74 147 #define MEM_FALL_OUT_CMD (1 << 8) 148 149 #define MC_SEQ_RAS_TIMING 0xA28 150 #define MC_SEQ_CAS_TIMING 0xA29 151 #define MC_SEQ_MISC_TIMING 0xA2A 152 #define MC_SEQ_MISC_TIMING2 0xA2B 153 #define MC_SEQ_PMG_TIMING 0xA2C 154 #define MC_SEQ_RD_CTL_D0 0xA2D 155 #define MC_SEQ_RD_CTL_D1 0xA2E 156 #define MC_SEQ_WR_CTL_D0 0xA2F 157 #define MC_SEQ_WR_CTL_D1 0xA30 158 159 #define MC_SEQ_MISC0 0xA80 160 #define MC_SEQ_MISC0_VEN_ID_SHIFT 8 161 #define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00 162 #define MC_SEQ_MISC0_VEN_ID_VALUE 3 163 #define MC_SEQ_MISC0_REV_ID_SHIFT 12 164 #define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000 165 #define MC_SEQ_MISC0_REV_ID_VALUE 1 166 #define MC_SEQ_MISC0_GDDR5_SHIFT 28 167 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 168 #define MC_SEQ_MISC0_GDDR5_VALUE 5 169 #define MC_SEQ_MISC1 0xA81 170 #define MC_SEQ_RESERVE_M 0xA82 171 #define MC_PMG_CMD_EMRS 0xA83 172 173 #define MC_SEQ_IO_DEBUG_INDEX 0xA91 174 #define MC_SEQ_IO_DEBUG_DATA 0xA92 175 176 #define MC_SEQ_MISC5 0xA95 177 #define MC_SEQ_MISC6 0xA96 178 179 #define MC_SEQ_MISC7 0xA99 180 181 #define MC_SEQ_RAS_TIMING_LP 0xA9B 182 #define MC_SEQ_CAS_TIMING_LP 0xA9C 183 #define MC_SEQ_MISC_TIMING_LP 0xA9D 184 #define MC_SEQ_MISC_TIMING2_LP 0xA9E 185 #define MC_SEQ_WR_CTL_D0_LP 0xA9F 186 #define MC_SEQ_WR_CTL_D1_LP 0xAA0 187 #define MC_SEQ_PMG_CMD_EMRS_LP 0xAA1 188 #define MC_SEQ_PMG_CMD_MRS_LP 0xAA2 189 190 #define MC_PMG_CMD_MRS 0xAAB 191 192 #define MC_SEQ_RD_CTL_D0_LP 0xAC7 193 #define MC_SEQ_RD_CTL_D1_LP 0xAC8 194 195 #define MC_PMG_CMD_MRS1 0xAD1 196 #define MC_SEQ_PMG_CMD_MRS1_LP 0xAD2 197 #define MC_SEQ_PMG_TIMING_LP 0xAD3 198 199 #define MC_SEQ_WR_CTL_2 0xAD5 200 #define MC_SEQ_WR_CTL_2_LP 0xAD6 201 #define MC_PMG_CMD_MRS2 0xAD7 202 #define MC_SEQ_PMG_CMD_MRS2_LP 0xAD8 203 204 #define MCLK_PWRMGT_CNTL 0xAE8 205 # define DLL_SPEED(x) ((x) << 0) 206 # define DLL_SPEED_MASK (0x1f << 0) 207 # define DLL_READY (1 << 6) 208 # define MC_INT_CNTL (1 << 7) 209 # define MRDCK0_PDNB (1 << 8) 210 # define MRDCK1_PDNB (1 << 9) 211 # define MRDCK0_RESET (1 << 16) 212 # define MRDCK1_RESET (1 << 17) 213 # define DLL_READY_READ (1 << 24) 214 #define DLL_CNTL 0xAE9 215 # define MRDCK0_BYPASS (1 << 24) 216 # define MRDCK1_BYPASS (1 << 25) 217 218 #define MPLL_CNTL_MODE 0xAEC 219 # define MPLL_MCLK_SEL (1 << 11) 220 #define MPLL_FUNC_CNTL 0xAED 221 #define BWCTRL(x) ((x) << 20) 222 #define BWCTRL_MASK (0xff << 20) 223 #define MPLL_FUNC_CNTL_1 0xAEE 224 #define VCO_MODE(x) ((x) << 0) 225 #define VCO_MODE_MASK (3 << 0) 226 #define CLKFRAC(x) ((x) << 4) 227 #define CLKFRAC_MASK (0xfff << 4) 228 #define CLKF(x) ((x) << 16) 229 #define CLKF_MASK (0xfff << 16) 230 #define MPLL_FUNC_CNTL_2 0xAEF 231 #define MPLL_AD_FUNC_CNTL 0xAF0 232 #define YCLK_POST_DIV(x) ((x) << 0) 233 #define YCLK_POST_DIV_MASK (7 << 0) 234 #define MPLL_DQ_FUNC_CNTL 0xAF1 235 #define YCLK_SEL(x) ((x) << 4) 236 #define YCLK_SEL_MASK (1 << 4) 237 238 #define MPLL_SS1 0xAF3 239 #define CLKV(x) ((x) << 0) 240 #define CLKV_MASK (0x3ffffff << 0) 241 #define MPLL_SS2 0xAF4 242 #define CLKS(x) ((x) << 0) 243 #define CLKS_MASK (0xfff << 0) 244 245 #define ATC_MISC_CG 0xCD4 246 247 #define IH_RB_CNTL 0xF80 248 # define IH_RB_ENABLE (1 << 0) 249 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 250 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 251 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 252 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 253 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 254 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 255 #define IH_RB_BASE 0xF81 256 #define IH_RB_RPTR 0xF82 257 #define IH_RB_WPTR 0xF83 258 # define RB_OVERFLOW (1 << 0) 259 # define WPTR_OFFSET_MASK 0x3fffc 260 #define IH_RB_WPTR_ADDR_HI 0xF84 261 #define IH_RB_WPTR_ADDR_LO 0xF85 262 #define IH_CNTL 0xF86 263 # define ENABLE_INTR (1 << 0) 264 # define IH_MC_SWAP(x) ((x) << 1) 265 # define IH_MC_SWAP_NONE 0 266 # define IH_MC_SWAP_16BIT 1 267 # define IH_MC_SWAP_32BIT 2 268 # define IH_MC_SWAP_64BIT 3 269 # define RPTR_REARM (1 << 4) 270 # define MC_WRREQ_CREDIT(x) ((x) << 15) 271 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 272 # define MC_VMID(x) ((x) << 25) 273 274 #define INTERRUPT_CNTL 0x151A 275 # define IH_DUMMY_RD_OVERRIDE (1 << 0) 276 # define IH_DUMMY_RD_EN (1 << 1) 277 # define IH_REQ_NONSNOOP_EN (1 << 3) 278 # define GEN_IH_INT_EN (1 << 8) 279 #define INTERRUPT_CNTL2 0x151B 280 281 #define VGT_VTX_VECT_EJECT_REG 0x222C 282 #define VGT_ESGS_RING_SIZE 0x2232 283 #define VGT_GSVS_RING_SIZE 0x2233 284 #define VGT_GS_VERTEX_REUSE 0x2235 285 #define VGT_PRIMITIVE_TYPE 0x2256 286 #define VGT_INDEX_TYPE 0x2257 287 #define VGT_NUM_INDICES 0x225C 288 #define VGT_NUM_INSTANCES 0x225D 289 #define VGT_TF_RING_SIZE 0x2262 290 #define VGT_HS_OFFCHIP_PARAM 0x226C 291 #define VGT_TF_MEMORY_BASE 0x226E 292 293 #define PA_SC_ENHANCE 0x22FC 294 295 #define TA_CNTL_AUX 0x2542 296 297 // #define PA_SC_RASTER_CONFIG 0xA0D4 298 # define RB_XSEL2(x) ((x) << 4) 299 # define RB_XSEL2_MASK (0x3 << 4) 300 # define RB_XSEL (1 << 6) 301 # define RB_YSEL (1 << 7) 302 # define PKR_MAP(x) ((x) << 8) 303 # define PKR_XSEL(x) ((x) << 10) 304 # define PKR_XSEL_MASK (0x3 << 10) 305 # define PKR_YSEL(x) ((x) << 12) 306 # define PKR_YSEL_MASK (0x3 << 12) 307 # define SC_MAP(x) ((x) << 16) 308 # define SC_MAP_MASK (0x3 << 16) 309 # define SC_XSEL(x) ((x) << 18) 310 # define SC_XSEL_MASK (0x3 << 18) 311 # define SC_YSEL(x) ((x) << 20) 312 # define SC_YSEL_MASK (0x3 << 20) 313 # define SE_MAP(x) ((x) << 24) 314 # define SE_XSEL(x) ((x) << 26) 315 # define SE_XSEL_MASK (0x3 << 26) 316 # define SE_YSEL(x) ((x) << 28) 317 # define SE_YSEL_MASK (0x3 << 28) 318 319 /* PCIE PORT registers idx/data 0x38/0x3c */ 320 // #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 321 # define LC_LINK_WIDTH_X0 0 322 # define LC_LINK_WIDTH_X1 1 323 # define LC_LINK_WIDTH_X2 2 324 # define LC_LINK_WIDTH_X4 3 325 # define LC_LINK_WIDTH_X8 4 326 # define LC_LINK_WIDTH_X16 6 327 328 /* 329 * PM4 330 */ 331 #define PACKET_TYPE0 0 332 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 333 ((reg) & 0xFFFF) | \ 334 ((n) & 0x3FFF) << 16) 335 #define CP_PACKET2 0x80000000 336 #define PACKET2_PAD_SHIFT 0 337 #define PACKET2_PAD_MASK (0x3fffffff << 0) 338 339 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 340 #define RADEON_PACKET_TYPE3 3 341 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 342 (((op) & 0xFF) << 8) | \ 343 ((n) & 0x3FFF) << 16) 344 345 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 346 347 /* Packet 3 types */ 348 #define PACKET3_NOP 0x10 349 #define PACKET3_SET_BASE 0x11 350 #define PACKET3_BASE_INDEX(x) ((x) << 0) 351 #define GDS_PARTITION_BASE 2 352 #define CE_PARTITION_BASE 3 353 #define PACKET3_CLEAR_STATE 0x12 354 #define PACKET3_INDEX_BUFFER_SIZE 0x13 355 #define PACKET3_DISPATCH_DIRECT 0x15 356 #define PACKET3_DISPATCH_INDIRECT 0x16 357 #define PACKET3_ALLOC_GDS 0x1B 358 #define PACKET3_WRITE_GDS_RAM 0x1C 359 #define PACKET3_ATOMIC_GDS 0x1D 360 #define PACKET3_ATOMIC 0x1E 361 #define PACKET3_OCCLUSION_QUERY 0x1F 362 #define PACKET3_SET_PREDICATION 0x20 363 #define PACKET3_REG_RMW 0x21 364 #define PACKET3_COND_EXEC 0x22 365 #define PACKET3_PRED_EXEC 0x23 366 #define PACKET3_DRAW_INDIRECT 0x24 367 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 368 #define PACKET3_INDEX_BASE 0x26 369 #define PACKET3_DRAW_INDEX_2 0x27 370 #define PACKET3_CONTEXT_CONTROL 0x28 371 #define PACKET3_INDEX_TYPE 0x2A 372 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 373 #define PACKET3_DRAW_INDEX_AUTO 0x2D 374 #define PACKET3_DRAW_INDEX_IMMD 0x2E 375 #define PACKET3_NUM_INSTANCES 0x2F 376 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 377 #define PACKET3_INDIRECT_BUFFER_CONST 0x31 378 #define PACKET3_INDIRECT_BUFFER 0x3F 379 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 380 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 381 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 382 #define PACKET3_WRITE_DATA 0x37 383 #define WRITE_DATA_DST_SEL(x) ((x) << 8) 384 /* 0 - register 385 * 1 - memory (sync - via GRBM) 386 * 2 - tc/l2 387 * 3 - gds 388 * 4 - reserved 389 * 5 - memory (async - direct) 390 */ 391 #define WR_ONE_ADDR (1 << 16) 392 #define WR_CONFIRM (1 << 20) 393 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 394 /* 0 - me 395 * 1 - pfp 396 * 2 - ce 397 */ 398 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 399 #define PACKET3_MEM_SEMAPHORE 0x39 400 #define PACKET3_MPEG_INDEX 0x3A 401 #define PACKET3_COPY_DW 0x3B 402 #define PACKET3_WAIT_REG_MEM 0x3C 403 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 404 /* 0 - always 405 * 1 - < 406 * 2 - <= 407 * 3 - == 408 * 4 - != 409 * 5 - >= 410 * 6 - > 411 */ 412 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 413 /* 0 - reg 414 * 1 - mem 415 */ 416 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 417 /* 0 - me 418 * 1 - pfp 419 */ 420 #define PACKET3_MEM_WRITE 0x3D 421 #define PACKET3_COPY_DATA 0x40 422 #define PACKET3_CP_DMA 0x41 423 /* 1. header 424 * 2. SRC_ADDR_LO or DATA [31:0] 425 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | 426 * SRC_ADDR_HI [7:0] 427 * 4. DST_ADDR_LO [31:0] 428 * 5. DST_ADDR_HI [7:0] 429 * 6. COMMAND [30:21] | BYTE_COUNT [20:0] 430 */ 431 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) 432 /* 0 - DST_ADDR 433 * 1 - GDS 434 */ 435 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) 436 /* 0 - ME 437 * 1 - PFP 438 */ 439 # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) 440 /* 0 - SRC_ADDR 441 * 1 - GDS 442 * 2 - DATA 443 */ 444 # define PACKET3_CP_DMA_CP_SYNC (1 << 31) 445 /* COMMAND */ 446 # define PACKET3_CP_DMA_DIS_WC (1 << 21) 447 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) 448 /* 0 - none 449 * 1 - 8 in 16 450 * 2 - 8 in 32 451 * 3 - 8 in 64 452 */ 453 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) 454 /* 0 - none 455 * 1 - 8 in 16 456 * 2 - 8 in 32 457 * 3 - 8 in 64 458 */ 459 # define PACKET3_CP_DMA_CMD_SAS (1 << 26) 460 /* 0 - memory 461 * 1 - register 462 */ 463 # define PACKET3_CP_DMA_CMD_DAS (1 << 27) 464 /* 0 - memory 465 * 1 - register 466 */ 467 # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) 468 # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 469 # define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30) 470 #define PACKET3_PFP_SYNC_ME 0x42 471 #define PACKET3_SURFACE_SYNC 0x43 472 # define PACKET3_DEST_BASE_0_ENA (1 << 0) 473 # define PACKET3_DEST_BASE_1_ENA (1 << 1) 474 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 475 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 476 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 477 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 478 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 479 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 480 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 481 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 482 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 483 # define PACKET3_DEST_BASE_2_ENA (1 << 19) 484 # define PACKET3_DEST_BASE_3_ENA (1 << 21) 485 # define PACKET3_TCL1_ACTION_ENA (1 << 22) 486 # define PACKET3_TC_ACTION_ENA (1 << 23) 487 # define PACKET3_CB_ACTION_ENA (1 << 25) 488 # define PACKET3_DB_ACTION_ENA (1 << 26) 489 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 490 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 491 #define PACKET3_ME_INITIALIZE 0x44 492 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 493 #define PACKET3_COND_WRITE 0x45 494 #define PACKET3_EVENT_WRITE 0x46 495 #define EVENT_TYPE(x) ((x) << 0) 496 #define EVENT_INDEX(x) ((x) << 8) 497 /* 0 - any non-TS event 498 * 1 - ZPASS_DONE 499 * 2 - SAMPLE_PIPELINESTAT 500 * 3 - SAMPLE_STREAMOUTSTAT* 501 * 4 - *S_PARTIAL_FLUSH 502 * 5 - EOP events 503 * 6 - EOS events 504 * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT 505 */ 506 #define INV_L2 (1 << 20) 507 /* INV TC L2 cache when EVENT_INDEX = 7 */ 508 #define PACKET3_EVENT_WRITE_EOP 0x47 509 #define DATA_SEL(x) ((x) << 29) 510 /* 0 - discard 511 * 1 - send low 32bit data 512 * 2 - send 64bit data 513 * 3 - send 64bit counter value 514 */ 515 #define INT_SEL(x) ((x) << 24) 516 /* 0 - none 517 * 1 - interrupt only (DATA_SEL = 0) 518 * 2 - interrupt when data write is confirmed 519 */ 520 #define PACKET3_EVENT_WRITE_EOS 0x48 521 #define PACKET3_PREAMBLE_CNTL 0x4A 522 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 523 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 524 #define PACKET3_ONE_REG_WRITE 0x57 525 #define PACKET3_LOAD_CONFIG_REG 0x5F 526 #define PACKET3_LOAD_CONTEXT_REG 0x60 527 #define PACKET3_LOAD_SH_REG 0x61 528 #define PACKET3_SET_CONFIG_REG 0x68 529 #define PACKET3_SET_CONFIG_REG_START 0x00002000 530 #define PACKET3_SET_CONFIG_REG_END 0x00002c00 531 #define PACKET3_SET_CONTEXT_REG 0x69 532 #define PACKET3_SET_CONTEXT_REG_START 0x000a000 533 #define PACKET3_SET_CONTEXT_REG_END 0x000a400 534 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 535 #define PACKET3_SET_RESOURCE_INDIRECT 0x74 536 #define PACKET3_SET_SH_REG 0x76 537 #define PACKET3_SET_SH_REG_START 0x00002c00 538 #define PACKET3_SET_SH_REG_END 0x00003000 539 #define PACKET3_SET_SH_REG_OFFSET 0x77 540 #define PACKET3_ME_WRITE 0x7A 541 #define PACKET3_SCRATCH_RAM_WRITE 0x7D 542 #define PACKET3_SCRATCH_RAM_READ 0x7E 543 #define PACKET3_CE_WRITE 0x7F 544 #define PACKET3_LOAD_CONST_RAM 0x80 545 #define PACKET3_WRITE_CONST_RAM 0x81 546 #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82 547 #define PACKET3_DUMP_CONST_RAM 0x83 548 #define PACKET3_INCREMENT_CE_COUNTER 0x84 549 #define PACKET3_INCREMENT_DE_COUNTER 0x85 550 #define PACKET3_WAIT_ON_CE_COUNTER 0x86 551 #define PACKET3_WAIT_ON_DE_COUNTER 0x87 552 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 553 #define PACKET3_SET_CE_DE_COUNTERS 0x89 554 #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A 555 #define PACKET3_SWITCH_BUFFER 0x8B 556 557 /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */ 558 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ 559 #define DMA1_REGISTER_OFFSET 0x200 /* not a register */ 560 #define SDMA_MAX_INSTANCE 2 561 562 #define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \ 563 (((b) & 0x1) << 26) | \ 564 (((t) & 0x1) << 23) | \ 565 (((s) & 0x1) << 22) | \ 566 (((n) & 0xFFFFF) << 0)) 567 568 #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \ 569 (((vmid) & 0xF) << 20) | \ 570 (((n) & 0xFFFFF) << 0)) 571 572 #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \ 573 (1 << 26) | \ 574 (1 << 21) | \ 575 (((n) & 0xFFFFF) << 0)) 576 577 /* async DMA Packet types */ 578 #define DMA_PACKET_WRITE 0x2 579 #define DMA_PACKET_COPY 0x3 580 #define DMA_PACKET_INDIRECT_BUFFER 0x4 581 #define DMA_PACKET_SEMAPHORE 0x5 582 #define DMA_PACKET_FENCE 0x6 583 #define DMA_PACKET_TRAP 0x7 584 #define DMA_PACKET_SRBM_WRITE 0x9 585 #define DMA_PACKET_CONSTANT_FILL 0xd 586 #define DMA_PACKET_POLL_REG_MEM 0xe 587 #define DMA_PACKET_NOP 0xf 588 589 /* VCE */ 590 #define VCE_STATUS 0x20004 591 #define VCE_VCPU_CNTL 0x20014 592 #define VCE_CLK_EN (1 << 0) 593 #define VCE_VCPU_CACHE_OFFSET0 0x20024 594 #define VCE_VCPU_CACHE_SIZE0 0x20028 595 #define VCE_VCPU_CACHE_OFFSET1 0x2002c 596 #define VCE_VCPU_CACHE_SIZE1 0x20030 597 #define VCE_VCPU_CACHE_OFFSET2 0x20034 598 #define VCE_VCPU_CACHE_SIZE2 0x20038 599 #define VCE_SOFT_RESET 0x20120 600 #define VCE_ECPU_SOFT_RESET (1 << 0) 601 #define VCE_FME_SOFT_RESET (1 << 2) 602 #define VCE_RB_BASE_LO2 0x2016c 603 #define VCE_RB_BASE_HI2 0x20170 604 #define VCE_RB_SIZE2 0x20174 605 #define VCE_RB_RPTR2 0x20178 606 #define VCE_RB_WPTR2 0x2017c 607 #define VCE_RB_BASE_LO 0x20180 608 #define VCE_RB_BASE_HI 0x20184 609 #define VCE_RB_SIZE 0x20188 610 #define VCE_RB_RPTR 0x2018c 611 #define VCE_RB_WPTR 0x20190 612 #define VCE_CLOCK_GATING_A 0x202f8 613 #define VCE_CLOCK_GATING_B 0x202fc 614 #define VCE_UENC_CLOCK_GATING 0x205bc 615 #define VCE_UENC_REG_CLOCK_GATING 0x205c0 616 #define VCE_FW_REG_STATUS 0x20e10 617 # define VCE_FW_REG_STATUS_BUSY (1 << 0) 618 # define VCE_FW_REG_STATUS_PASS (1 << 3) 619 # define VCE_FW_REG_STATUS_DONE (1 << 11) 620 #define VCE_LMI_FW_START_KEYSEL 0x20e18 621 #define VCE_LMI_FW_PERIODIC_CTRL 0x20e20 622 #define VCE_LMI_CTRL2 0x20e74 623 #define VCE_LMI_CTRL 0x20e98 624 #define VCE_LMI_VM_CTRL 0x20ea0 625 #define VCE_LMI_SWAP_CNTL 0x20eb4 626 #define VCE_LMI_SWAP_CNTL1 0x20eb8 627 #define VCE_LMI_CACHE_CTRL 0x20ef4 628 629 #define VCE_CMD_NO_OP 0x00000000 630 #define VCE_CMD_END 0x00000001 631 #define VCE_CMD_IB 0x00000002 632 #define VCE_CMD_FENCE 0x00000003 633 #define VCE_CMD_TRAP 0x00000004 634 #define VCE_CMD_IB_AUTO 0x00000005 635 #define VCE_CMD_SEMAPHORE 0x00000006 636 637 638 //#dce stupp 639 /* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */ 640 #define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c) //(0x6df0 - 0x6df0)/4 641 #define CRTC1_REGISTER_OFFSET (0x1e7c - 0x1b7c) //(0x79f0 - 0x6df0)/4 642 #define CRTC2_REGISTER_OFFSET (0x417c - 0x1b7c) //(0x105f0 - 0x6df0)/4 643 #define CRTC3_REGISTER_OFFSET (0x447c - 0x1b7c) //(0x111f0 - 0x6df0)/4 644 #define CRTC4_REGISTER_OFFSET (0x477c - 0x1b7c) //(0x11df0 - 0x6df0)/4 645 #define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c) //(0x129f0 - 0x6df0)/4 646 647 /* hpd instance offsets */ 648 #define HPD0_REGISTER_OFFSET (0x1807 - 0x1807) 649 #define HPD1_REGISTER_OFFSET (0x180a - 0x1807) 650 #define HPD2_REGISTER_OFFSET (0x180d - 0x1807) 651 #define HPD3_REGISTER_OFFSET (0x1810 - 0x1807) 652 #define HPD4_REGISTER_OFFSET (0x1813 - 0x1807) 653 #define HPD5_REGISTER_OFFSET (0x1816 - 0x1807) 654 655 /* audio endpt instance offsets */ 656 #define AUD0_REGISTER_OFFSET (0x1780 - 0x1780) 657 #define AUD1_REGISTER_OFFSET (0x1786 - 0x1780) 658 #define AUD2_REGISTER_OFFSET (0x178c - 0x1780) 659 #define AUD3_REGISTER_OFFSET (0x1792 - 0x1780) 660 #define AUD4_REGISTER_OFFSET (0x1798 - 0x1780) 661 #define AUD5_REGISTER_OFFSET (0x179d - 0x1780) 662 #define AUD6_REGISTER_OFFSET (0x17a4 - 0x1780) 663 664 #define CURSOR_WIDTH 64 665 #define CURSOR_HEIGHT 64 666 667 #define AVIVO_D1VGA_CONTROL 0x00cc 668 # define AVIVO_DVGA_CONTROL_MODE_ENABLE (1 << 0) 669 # define AVIVO_DVGA_CONTROL_TIMING_SELECT (1 << 8) 670 # define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1 << 9) 671 # define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1 << 10) 672 # define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1 << 16) 673 # define AVIVO_DVGA_CONTROL_ROTATE (1 << 24) 674 #define AVIVO_D2VGA_CONTROL 0x00ce 675 676 #define R600_BUS_CNTL 0x1508 677 # define R600_BIOS_ROM_DIS (1 << 1) 678 679 #define R600_ROM_CNTL 0x580 680 # define R600_SCK_OVERWRITE (1 << 1) 681 # define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28 682 # define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28) 683 684 #define GRPH_ARRAY_LINEAR_GENERAL 0 685 #define GRPH_ARRAY_LINEAR_ALIGNED 1 686 #define GRPH_ARRAY_1D_TILED_THIN1 2 687 #define GRPH_ARRAY_2D_TILED_THIN1 4 688 689 #define ES_AND_GS_AUTO 3 690 #define BUF_SWAP_32BIT (2 << 16) 691 692 #define GRPH_DEPTH_8BPP 0 693 #define GRPH_DEPTH_16BPP 1 694 #define GRPH_DEPTH_32BPP 2 695 696 /* 8 BPP */ 697 #define GRPH_FORMAT_INDEXED 0 698 699 /* 16 BPP */ 700 #define GRPH_FORMAT_ARGB1555 0 701 #define GRPH_FORMAT_ARGB565 1 702 #define GRPH_FORMAT_ARGB4444 2 703 #define GRPH_FORMAT_AI88 3 704 #define GRPH_FORMAT_MONO16 4 705 #define GRPH_FORMAT_BGRA5551 5 706 707 /* 32 BPP */ 708 #define GRPH_FORMAT_ARGB8888 0 709 #define GRPH_FORMAT_ARGB2101010 1 710 #define GRPH_FORMAT_32BPP_DIG 2 711 #define GRPH_FORMAT_8B_ARGB2101010 3 712 #define GRPH_FORMAT_BGRA1010102 4 713 #define GRPH_FORMAT_8B_BGRA1010102 5 714 #define GRPH_FORMAT_RGB111110 6 715 #define GRPH_FORMAT_BGR101111 7 716 717 #define GRPH_ENDIAN_NONE 0 718 #define GRPH_ENDIAN_8IN16 1 719 #define GRPH_ENDIAN_8IN32 2 720 #define GRPH_ENDIAN_8IN64 3 721 #define GRPH_RED_SEL_R 0 722 #define GRPH_RED_SEL_G 1 723 #define GRPH_RED_SEL_B 2 724 #define GRPH_RED_SEL_A 3 725 726 #define GRPH_GREEN_SEL_G 0 727 #define GRPH_GREEN_SEL_B 1 728 #define GRPH_GREEN_SEL_A 2 729 #define GRPH_GREEN_SEL_R 3 730 731 #define GRPH_BLUE_SEL_B 0 732 #define GRPH_BLUE_SEL_A 1 733 #define GRPH_BLUE_SEL_R 2 734 #define GRPH_BLUE_SEL_G 3 735 736 #define GRPH_ALPHA_SEL_A 0 737 #define GRPH_ALPHA_SEL_R 1 738 #define GRPH_ALPHA_SEL_G 2 739 #define GRPH_ALPHA_SEL_B 3 740 741 /* CUR_CONTROL */ 742 #define CURSOR_MONO 0 743 #define CURSOR_24_1 1 744 #define CURSOR_24_8_PRE_MULT 2 745 #define CURSOR_24_8_UNPRE_MULT 3 746 #define CURSOR_URGENT_ALWAYS 0 747 #define CURSOR_URGENT_1_8 1 748 #define CURSOR_URGENT_1_4 2 749 #define CURSOR_URGENT_3_8 3 750 #define CURSOR_URGENT_1_2 4 751 752 /* INPUT_CSC_CONTROL */ 753 # define INPUT_CSC_BYPASS 0 754 # define INPUT_CSC_PROG_COEFF 1 755 # define INPUT_CSC_PROG_SHARED_MATRIXA 2 756 757 /* OUTPUT_CSC_CONTROL */ 758 # define OUTPUT_CSC_BYPASS 0 759 # define OUTPUT_CSC_TV_RGB 1 760 # define OUTPUT_CSC_YCBCR_601 2 761 # define OUTPUT_CSC_YCBCR_709 3 762 # define OUTPUT_CSC_PROG_COEFF 4 763 # define OUTPUT_CSC_PROG_SHARED_MATRIXB 5 764 765 /* DEGAMMA_CONTROL */ 766 # define DEGAMMA_BYPASS 0 767 # define DEGAMMA_SRGB_24 1 768 # define DEGAMMA_XVYCC_222 2 769 770 /* GAMUT_REMAP_CONTROL */ 771 # define GAMUT_REMAP_BYPASS 0 772 # define GAMUT_REMAP_PROG_COEFF 1 773 # define GAMUT_REMAP_PROG_SHARED_MATRIXA 2 774 # define GAMUT_REMAP_PROG_SHARED_MATRIXB 3 775 776 /* REGAMMA_CONTROL */ 777 # define REGAMMA_BYPASS 0 778 # define REGAMMA_SRGB_24 1 779 # define REGAMMA_XVYCC_222 2 780 # define REGAMMA_PROG_A 3 781 # define REGAMMA_PROG_B 4 782 783 784 /* INPUT_GAMMA_CONTROL */ 785 # define INPUT_GAMMA_USE_LUT 0 786 # define INPUT_GAMMA_BYPASS 1 787 # define INPUT_GAMMA_SRGB_24 2 788 # define INPUT_GAMMA_XVYCC_222 3 789 790 #define MC_SEQ_MISC0__MT__MASK 0xf0000000 791 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000 792 #define MC_SEQ_MISC0__MT__DDR2 0x20000000 793 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000 794 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000 795 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000 796 #define MC_SEQ_MISC0__MT__HBM 0x60000000 797 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000 798 799 #define CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK 0x4000000 800 #define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12) 801 #define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 802 #define PACKET3_SEM_SEL_WAIT (0x7 << 29) 803 804 #define AMDGPU_PCIE_INDEX 0xc 805 #define AMDGPU_PCIE_DATA 0xd 806 807 #define PCIE_BUS_CLK 10000 808 #define TCLK (PCIE_BUS_CLK / 10) 809 #define PCIE_PORT_INDEX 0xe 810 #define PCIE_PORT_DATA 0xf 811 #define EVERGREEN_PIF_PHY0_INDEX 0x8 812 #define EVERGREEN_PIF_PHY0_DATA 0xc 813 #define EVERGREEN_PIF_PHY1_INDEX 0x10 814 #define EVERGREEN_PIF_PHY1_DATA 0x14 815 816 /* Discrete VCE clocks */ 817 #define CG_VCEPLL_FUNC_CNTL 0xc0030600 818 #define VCEPLL_RESET_MASK 0x00000001 819 #define VCEPLL_SLEEP_MASK 0x00000002 820 #define VCEPLL_BYPASS_EN_MASK 0x00000004 821 #define VCEPLL_CTLREQ_MASK 0x00000008 822 #define VCEPLL_VCO_MODE_MASK 0x00000600 823 #define VCEPLL_REF_DIV_MASK 0x003F0000 824 #define VCEPLL_CTLACK_MASK 0x40000000 825 #define VCEPLL_CTLACK2_MASK 0x80000000 826 827 #define CG_VCEPLL_FUNC_CNTL_2 0xc0030601 828 #define VCEPLL_PDIV_A(x) ((x) << 0) 829 #define VCEPLL_PDIV_A_MASK 0x0000007F 830 #define VCEPLL_PDIV_B(x) ((x) << 8) 831 #define VCEPLL_PDIV_B_MASK 0x00007F00 832 #define EVCLK_SRC_SEL(x) ((x) << 20) 833 #define EVCLK_SRC_SEL_MASK 0x01F00000 834 #define ECCLK_SRC_SEL(x) ((x) << 25) 835 #define ECCLK_SRC_SEL_MASK 0x3E000000 836 837 #define CG_VCEPLL_FUNC_CNTL_3 0xc0030602 838 #define VCEPLL_FB_DIV(x) ((x) << 0) 839 #define VCEPLL_FB_DIV_MASK 0x01FFFFFF 840 841 #define CG_VCEPLL_FUNC_CNTL_4 0xc0030603 842 843 #define CG_VCEPLL_FUNC_CNTL_5 0xc0030604 844 #define CG_VCEPLL_SPREAD_SPECTRUM 0xc0030606 845 #define VCEPLL_SSEN_MASK 0x00000001 846 847 848 #endif 849