1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #ifndef SI_H 25 #define SI_H 26 27 #define SI_MAX_CTLACKS_ASSERTION_WAIT 100 28 29 /* CG IND registers are accessed via SMC indirect space + SMC_CG_IND_START */ 30 #define SMC_CG_IND_START 0xc0030000 31 #define SMC_CG_IND_END 0xc0040000 32 33 /* SMC IND registers */ 34 #define SMC_SYSCON_RESET_CNTL 0x80000000 35 # define RST_REG (1 << 0) 36 #define SMC_SYSCON_CLOCK_CNTL_0 0x80000004 37 # define CK_DISABLE (1 << 0) 38 # define CKEN (1 << 24) 39 40 #define DCCG_DISP_SLOW_SELECT_REG 0x13F 41 #define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0) 42 #define DCCG_DISP1_SLOW_SELECT_MASK (7 << 0) 43 #define DCCG_DISP1_SLOW_SELECT_SHIFT 0 44 #define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4) 45 #define DCCG_DISP2_SLOW_SELECT_MASK (7 << 4) 46 #define DCCG_DISP2_SLOW_SELECT_SHIFT 4 47 48 /* discrete uvd clocks */ 49 #define CG_UPLL_FUNC_CNTL 0x18d 50 # define UPLL_RESET_MASK 0x00000001 51 # define UPLL_SLEEP_MASK 0x00000002 52 # define UPLL_BYPASS_EN_MASK 0x00000004 53 # define UPLL_CTLREQ_MASK 0x00000008 54 # define UPLL_VCO_MODE_MASK 0x00000600 55 # define UPLL_REF_DIV_MASK 0x003F0000 56 # define UPLL_CTLACK_MASK 0x40000000 57 # define UPLL_CTLACK2_MASK 0x80000000 58 #define CG_UPLL_FUNC_CNTL_2 0x18e 59 # define UPLL_PDIV_A(x) ((x) << 0) 60 # define UPLL_PDIV_A_MASK 0x0000007F 61 # define UPLL_PDIV_B(x) ((x) << 8) 62 # define UPLL_PDIV_B_MASK 0x00007F00 63 # define VCLK_SRC_SEL(x) ((x) << 20) 64 # define VCLK_SRC_SEL_MASK 0x01F00000 65 # define DCLK_SRC_SEL(x) ((x) << 25) 66 # define DCLK_SRC_SEL_MASK 0x3E000000 67 #define CG_UPLL_FUNC_CNTL_3 0x18f 68 # define UPLL_FB_DIV(x) ((x) << 0) 69 # define UPLL_FB_DIV_MASK 0x01FFFFFF 70 #define CG_UPLL_FUNC_CNTL_4 0x191 71 # define UPLL_SPARE_ISPARE9 0x00020000 72 #define CG_UPLL_FUNC_CNTL_5 0x192 73 # define RESET_ANTI_MUX_MASK 0x00000200 74 #define CG_UPLL_SPREAD_SPECTRUM 0x194 75 # define SSEN_MASK 0x00000001 76 77 #define VM_INVALIDATE_REQUEST 0x51E 78 #define VM_INVALIDATE_RESPONSE 0x51F 79 80 #define VM_L2_CG 0x570 81 #define MC_CG_ENABLE (1 << 18) 82 #define MC_LS_ENABLE (1 << 19) 83 84 #define MC_VM_FB_LOCATION 0x809 85 #define MC_VM_AGP_TOP 0x80A 86 #define MC_VM_AGP_BOT 0x80B 87 #define MC_VM_AGP_BASE 0x80C 88 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x80D 89 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x80E 90 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x80F 91 92 #define MC_VM_MX_L1_TLB_CNTL 0x819 93 #define ENABLE_L1_TLB (1 << 0) 94 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 95 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 96 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 97 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 98 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 99 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 100 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 101 102 #define MC_SHARED_BLACKOUT_CNTL 0x82B 103 104 #define MC_HUB_MISC_HUB_CG 0x82E 105 #define MC_HUB_MISC_VM_CG 0x82F 106 107 #define MC_HUB_MISC_SIP_CG 0x830 108 109 #define MC_XPB_CLK_GAT 0x91E 110 111 #define MC_CITF_MISC_RD_CG 0x992 112 #define MC_CITF_MISC_WR_CG 0x993 113 #define MC_CITF_MISC_VM_CG 0x994 114 115 #define MC_ARB_DRAM_TIMING 0x9DD 116 #define MC_ARB_DRAM_TIMING2 0x9DE 117 118 #define MC_ARB_BURST_TIME 0xA02 119 #define STATE0(x) ((x) << 0) 120 #define STATE0_MASK (0x1f << 0) 121 #define STATE0_SHIFT 0 122 #define STATE1(x) ((x) << 5) 123 #define STATE1_MASK (0x1f << 5) 124 #define STATE1_SHIFT 5 125 #define STATE2(x) ((x) << 10) 126 #define STATE2_MASK (0x1f << 10) 127 #define STATE2_SHIFT 10 128 #define STATE3(x) ((x) << 15) 129 #define STATE3_MASK (0x1f << 15) 130 #define STATE3_SHIFT 15 131 132 #define MC_SEQ_TRAIN_WAKEUP_CNTL 0xA3A 133 #define TRAIN_DONE_D0 (1 << 30) 134 #define TRAIN_DONE_D1 (1 << 31) 135 136 #define MC_SEQ_SUP_CNTL 0xA32 137 #define RUN_MASK (1 << 0) 138 #define MC_SEQ_SUP_PGM 0xA33 139 #define MC_PMG_AUTO_CMD 0xA34 140 141 #define MC_IO_PAD_CNTL_D0 0xA74 142 #define MEM_FALL_OUT_CMD (1 << 8) 143 144 #define MC_SEQ_RAS_TIMING 0xA28 145 #define MC_SEQ_CAS_TIMING 0xA29 146 #define MC_SEQ_MISC_TIMING 0xA2A 147 #define MC_SEQ_MISC_TIMING2 0xA2B 148 #define MC_SEQ_PMG_TIMING 0xA2C 149 #define MC_SEQ_RD_CTL_D0 0xA2D 150 #define MC_SEQ_RD_CTL_D1 0xA2E 151 #define MC_SEQ_WR_CTL_D0 0xA2F 152 #define MC_SEQ_WR_CTL_D1 0xA30 153 154 #define MC_SEQ_MISC0 0xA80 155 #define MC_SEQ_MISC0_VEN_ID_SHIFT 8 156 #define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00 157 #define MC_SEQ_MISC0_VEN_ID_VALUE 3 158 #define MC_SEQ_MISC0_REV_ID_SHIFT 12 159 #define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000 160 #define MC_SEQ_MISC0_REV_ID_VALUE 1 161 #define MC_SEQ_MISC0_GDDR5_SHIFT 28 162 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 163 #define MC_SEQ_MISC0_GDDR5_VALUE 5 164 #define MC_SEQ_MISC1 0xA81 165 #define MC_SEQ_RESERVE_M 0xA82 166 #define MC_PMG_CMD_EMRS 0xA83 167 168 #define MC_SEQ_IO_DEBUG_INDEX 0xA91 169 #define MC_SEQ_IO_DEBUG_DATA 0xA92 170 171 #define MC_SEQ_MISC5 0xA95 172 #define MC_SEQ_MISC6 0xA96 173 174 #define MC_SEQ_MISC7 0xA99 175 176 #define MC_SEQ_RAS_TIMING_LP 0xA9B 177 #define MC_SEQ_CAS_TIMING_LP 0xA9C 178 #define MC_SEQ_MISC_TIMING_LP 0xA9D 179 #define MC_SEQ_MISC_TIMING2_LP 0xA9E 180 #define MC_SEQ_WR_CTL_D0_LP 0xA9F 181 #define MC_SEQ_WR_CTL_D1_LP 0xAA0 182 #define MC_SEQ_PMG_CMD_EMRS_LP 0xAA1 183 #define MC_SEQ_PMG_CMD_MRS_LP 0xAA2 184 185 #define MC_PMG_CMD_MRS 0xAAB 186 187 #define MC_SEQ_RD_CTL_D0_LP 0xAC7 188 #define MC_SEQ_RD_CTL_D1_LP 0xAC8 189 190 #define MC_PMG_CMD_MRS1 0xAD1 191 #define MC_SEQ_PMG_CMD_MRS1_LP 0xAD2 192 #define MC_SEQ_PMG_TIMING_LP 0xAD3 193 194 #define MC_SEQ_WR_CTL_2 0xAD5 195 #define MC_SEQ_WR_CTL_2_LP 0xAD6 196 #define MC_PMG_CMD_MRS2 0xAD7 197 #define MC_SEQ_PMG_CMD_MRS2_LP 0xAD8 198 199 #define MCLK_PWRMGT_CNTL 0xAE8 200 # define DLL_SPEED(x) ((x) << 0) 201 # define DLL_SPEED_MASK (0x1f << 0) 202 # define DLL_READY (1 << 6) 203 # define MC_INT_CNTL (1 << 7) 204 # define MRDCK0_PDNB (1 << 8) 205 # define MRDCK1_PDNB (1 << 9) 206 # define MRDCK0_RESET (1 << 16) 207 # define MRDCK1_RESET (1 << 17) 208 # define DLL_READY_READ (1 << 24) 209 #define DLL_CNTL 0xAE9 210 # define MRDCK0_BYPASS (1 << 24) 211 # define MRDCK1_BYPASS (1 << 25) 212 213 #define MPLL_CNTL_MODE 0xAEC 214 # define MPLL_MCLK_SEL (1 << 11) 215 #define MPLL_FUNC_CNTL 0xAED 216 #define BWCTRL(x) ((x) << 20) 217 #define BWCTRL_MASK (0xff << 20) 218 #define MPLL_FUNC_CNTL_1 0xAEE 219 #define VCO_MODE(x) ((x) << 0) 220 #define VCO_MODE_MASK (3 << 0) 221 #define CLKFRAC(x) ((x) << 4) 222 #define CLKFRAC_MASK (0xfff << 4) 223 #define CLKF(x) ((x) << 16) 224 #define CLKF_MASK (0xfff << 16) 225 #define MPLL_FUNC_CNTL_2 0xAEF 226 #define MPLL_AD_FUNC_CNTL 0xAF0 227 #define YCLK_POST_DIV(x) ((x) << 0) 228 #define YCLK_POST_DIV_MASK (7 << 0) 229 #define MPLL_DQ_FUNC_CNTL 0xAF1 230 #define YCLK_SEL(x) ((x) << 4) 231 #define YCLK_SEL_MASK (1 << 4) 232 233 #define MPLL_SS1 0xAF3 234 #define CLKV(x) ((x) << 0) 235 #define CLKV_MASK (0x3ffffff << 0) 236 #define MPLL_SS2 0xAF4 237 #define CLKS(x) ((x) << 0) 238 #define CLKS_MASK (0xfff << 0) 239 240 #define ATC_MISC_CG 0xCD4 241 242 #define IH_RB_CNTL 0xF80 243 # define IH_RB_ENABLE (1 << 0) 244 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 245 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 246 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 247 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 248 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 249 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 250 #define IH_RB_BASE 0xF81 251 #define IH_RB_RPTR 0xF82 252 #define IH_RB_WPTR 0xF83 253 # define RB_OVERFLOW (1 << 0) 254 # define WPTR_OFFSET_MASK 0x3fffc 255 #define IH_RB_WPTR_ADDR_HI 0xF84 256 #define IH_RB_WPTR_ADDR_LO 0xF85 257 #define IH_CNTL 0xF86 258 # define ENABLE_INTR (1 << 0) 259 # define IH_MC_SWAP(x) ((x) << 1) 260 # define IH_MC_SWAP_NONE 0 261 # define IH_MC_SWAP_16BIT 1 262 # define IH_MC_SWAP_32BIT 2 263 # define IH_MC_SWAP_64BIT 3 264 # define RPTR_REARM (1 << 4) 265 # define MC_WRREQ_CREDIT(x) ((x) << 15) 266 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 267 # define MC_VMID(x) ((x) << 25) 268 269 #define INTERRUPT_CNTL 0x151A 270 # define IH_DUMMY_RD_OVERRIDE (1 << 0) 271 # define IH_DUMMY_RD_EN (1 << 1) 272 # define IH_REQ_NONSNOOP_EN (1 << 3) 273 # define GEN_IH_INT_EN (1 << 8) 274 #define INTERRUPT_CNTL2 0x151B 275 276 #define VGT_VTX_VECT_EJECT_REG 0x222C 277 #define VGT_ESGS_RING_SIZE 0x2232 278 #define VGT_GSVS_RING_SIZE 0x2233 279 #define VGT_GS_VERTEX_REUSE 0x2235 280 #define VGT_PRIMITIVE_TYPE 0x2256 281 #define VGT_INDEX_TYPE 0x2257 282 #define VGT_NUM_INDICES 0x225C 283 #define VGT_NUM_INSTANCES 0x225D 284 #define VGT_TF_RING_SIZE 0x2262 285 #define VGT_HS_OFFCHIP_PARAM 0x226C 286 #define VGT_TF_MEMORY_BASE 0x226E 287 288 #define PA_SC_ENHANCE 0x22FC 289 290 #define TA_CNTL_AUX 0x2542 291 292 // #define PA_SC_RASTER_CONFIG 0xA0D4 293 # define RB_XSEL2(x) ((x) << 4) 294 # define RB_XSEL2_MASK (0x3 << 4) 295 # define RB_XSEL (1 << 6) 296 # define RB_YSEL (1 << 7) 297 # define PKR_MAP(x) ((x) << 8) 298 # define PKR_XSEL(x) ((x) << 10) 299 # define PKR_XSEL_MASK (0x3 << 10) 300 # define PKR_YSEL(x) ((x) << 12) 301 # define PKR_YSEL_MASK (0x3 << 12) 302 # define SC_MAP(x) ((x) << 16) 303 # define SC_MAP_MASK (0x3 << 16) 304 # define SC_XSEL(x) ((x) << 18) 305 # define SC_XSEL_MASK (0x3 << 18) 306 # define SC_YSEL(x) ((x) << 20) 307 # define SC_YSEL_MASK (0x3 << 20) 308 # define SE_MAP(x) ((x) << 24) 309 # define SE_XSEL(x) ((x) << 26) 310 # define SE_XSEL_MASK (0x3 << 26) 311 # define SE_YSEL(x) ((x) << 28) 312 # define SE_YSEL_MASK (0x3 << 28) 313 314 /* PCIE PORT registers idx/data 0x38/0x3c */ 315 // #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 316 # define LC_LINK_WIDTH_X0 0 317 # define LC_LINK_WIDTH_X1 1 318 # define LC_LINK_WIDTH_X2 2 319 # define LC_LINK_WIDTH_X4 3 320 # define LC_LINK_WIDTH_X8 4 321 # define LC_LINK_WIDTH_X16 6 322 323 /* 324 * PM4 325 */ 326 #define PACKET_TYPE0 0 327 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 328 ((reg) & 0xFFFF) | \ 329 ((n) & 0x3FFF) << 16) 330 #define CP_PACKET2 0x80000000 331 #define PACKET2_PAD_SHIFT 0 332 #define PACKET2_PAD_MASK (0x3fffffff << 0) 333 334 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 335 #define RADEON_PACKET_TYPE3 3 336 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 337 (((op) & 0xFF) << 8) | \ 338 ((n) & 0x3FFF) << 16) 339 340 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 341 342 /* Packet 3 types */ 343 #define PACKET3_NOP 0x10 344 #define PACKET3_SET_BASE 0x11 345 #define PACKET3_BASE_INDEX(x) ((x) << 0) 346 #define GDS_PARTITION_BASE 2 347 #define CE_PARTITION_BASE 3 348 #define PACKET3_CLEAR_STATE 0x12 349 #define PACKET3_INDEX_BUFFER_SIZE 0x13 350 #define PACKET3_DISPATCH_DIRECT 0x15 351 #define PACKET3_DISPATCH_INDIRECT 0x16 352 #define PACKET3_ALLOC_GDS 0x1B 353 #define PACKET3_WRITE_GDS_RAM 0x1C 354 #define PACKET3_ATOMIC_GDS 0x1D 355 #define PACKET3_ATOMIC 0x1E 356 #define PACKET3_OCCLUSION_QUERY 0x1F 357 #define PACKET3_SET_PREDICATION 0x20 358 #define PACKET3_REG_RMW 0x21 359 #define PACKET3_COND_EXEC 0x22 360 #define PACKET3_PRED_EXEC 0x23 361 #define PACKET3_DRAW_INDIRECT 0x24 362 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 363 #define PACKET3_INDEX_BASE 0x26 364 #define PACKET3_DRAW_INDEX_2 0x27 365 #define PACKET3_CONTEXT_CONTROL 0x28 366 #define PACKET3_INDEX_TYPE 0x2A 367 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 368 #define PACKET3_DRAW_INDEX_AUTO 0x2D 369 #define PACKET3_DRAW_INDEX_IMMD 0x2E 370 #define PACKET3_NUM_INSTANCES 0x2F 371 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 372 #define PACKET3_INDIRECT_BUFFER_CONST 0x31 373 #define PACKET3_INDIRECT_BUFFER 0x3F 374 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 375 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 376 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 377 #define PACKET3_WRITE_DATA 0x37 378 #define WRITE_DATA_DST_SEL(x) ((x) << 8) 379 /* 0 - register 380 * 1 - memory (sync - via GRBM) 381 * 2 - tc/l2 382 * 3 - gds 383 * 4 - reserved 384 * 5 - memory (async - direct) 385 */ 386 #define WR_ONE_ADDR (1 << 16) 387 #define WR_CONFIRM (1 << 20) 388 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 389 /* 0 - me 390 * 1 - pfp 391 * 2 - ce 392 */ 393 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 394 #define PACKET3_MEM_SEMAPHORE 0x39 395 #define PACKET3_MPEG_INDEX 0x3A 396 #define PACKET3_COPY_DW 0x3B 397 #define PACKET3_WAIT_REG_MEM 0x3C 398 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 399 /* 0 - always 400 * 1 - < 401 * 2 - <= 402 * 3 - == 403 * 4 - != 404 * 5 - >= 405 * 6 - > 406 */ 407 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 408 /* 0 - reg 409 * 1 - mem 410 */ 411 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 412 /* 0 - me 413 * 1 - pfp 414 */ 415 #define PACKET3_MEM_WRITE 0x3D 416 #define PACKET3_COPY_DATA 0x40 417 #define PACKET3_CP_DMA 0x41 418 /* 1. header 419 * 2. SRC_ADDR_LO or DATA [31:0] 420 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | 421 * SRC_ADDR_HI [7:0] 422 * 4. DST_ADDR_LO [31:0] 423 * 5. DST_ADDR_HI [7:0] 424 * 6. COMMAND [30:21] | BYTE_COUNT [20:0] 425 */ 426 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) 427 /* 0 - DST_ADDR 428 * 1 - GDS 429 */ 430 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) 431 /* 0 - ME 432 * 1 - PFP 433 */ 434 # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) 435 /* 0 - SRC_ADDR 436 * 1 - GDS 437 * 2 - DATA 438 */ 439 # define PACKET3_CP_DMA_CP_SYNC (1 << 31) 440 /* COMMAND */ 441 # define PACKET3_CP_DMA_DIS_WC (1 << 21) 442 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) 443 /* 0 - none 444 * 1 - 8 in 16 445 * 2 - 8 in 32 446 * 3 - 8 in 64 447 */ 448 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) 449 /* 0 - none 450 * 1 - 8 in 16 451 * 2 - 8 in 32 452 * 3 - 8 in 64 453 */ 454 # define PACKET3_CP_DMA_CMD_SAS (1 << 26) 455 /* 0 - memory 456 * 1 - register 457 */ 458 # define PACKET3_CP_DMA_CMD_DAS (1 << 27) 459 /* 0 - memory 460 * 1 - register 461 */ 462 # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) 463 # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 464 # define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30) 465 #define PACKET3_PFP_SYNC_ME 0x42 466 #define PACKET3_SURFACE_SYNC 0x43 467 # define PACKET3_DEST_BASE_0_ENA (1 << 0) 468 # define PACKET3_DEST_BASE_1_ENA (1 << 1) 469 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 470 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 471 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 472 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 473 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 474 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 475 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 476 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 477 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 478 # define PACKET3_DEST_BASE_2_ENA (1 << 19) 479 # define PACKET3_DEST_BASE_3_ENA (1 << 21) 480 # define PACKET3_TCL1_ACTION_ENA (1 << 22) 481 # define PACKET3_TC_ACTION_ENA (1 << 23) 482 # define PACKET3_CB_ACTION_ENA (1 << 25) 483 # define PACKET3_DB_ACTION_ENA (1 << 26) 484 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 485 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 486 #define PACKET3_ME_INITIALIZE 0x44 487 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 488 #define PACKET3_COND_WRITE 0x45 489 #define PACKET3_EVENT_WRITE 0x46 490 #define EVENT_TYPE(x) ((x) << 0) 491 #define EVENT_INDEX(x) ((x) << 8) 492 /* 0 - any non-TS event 493 * 1 - ZPASS_DONE 494 * 2 - SAMPLE_PIPELINESTAT 495 * 3 - SAMPLE_STREAMOUTSTAT* 496 * 4 - *S_PARTIAL_FLUSH 497 * 5 - EOP events 498 * 6 - EOS events 499 * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT 500 */ 501 #define INV_L2 (1 << 20) 502 /* INV TC L2 cache when EVENT_INDEX = 7 */ 503 #define PACKET3_EVENT_WRITE_EOP 0x47 504 #define DATA_SEL(x) ((x) << 29) 505 /* 0 - discard 506 * 1 - send low 32bit data 507 * 2 - send 64bit data 508 * 3 - send 64bit counter value 509 */ 510 #define INT_SEL(x) ((x) << 24) 511 /* 0 - none 512 * 1 - interrupt only (DATA_SEL = 0) 513 * 2 - interrupt when data write is confirmed 514 */ 515 #define PACKET3_EVENT_WRITE_EOS 0x48 516 #define PACKET3_PREAMBLE_CNTL 0x4A 517 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 518 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 519 #define PACKET3_ONE_REG_WRITE 0x57 520 #define PACKET3_LOAD_CONFIG_REG 0x5F 521 #define PACKET3_LOAD_CONTEXT_REG 0x60 522 #define PACKET3_LOAD_SH_REG 0x61 523 #define PACKET3_SET_CONFIG_REG 0x68 524 #define PACKET3_SET_CONFIG_REG_START 0x00002000 525 #define PACKET3_SET_CONFIG_REG_END 0x00002c00 526 #define PACKET3_SET_CONTEXT_REG 0x69 527 #define PACKET3_SET_CONTEXT_REG_START 0x000a000 528 #define PACKET3_SET_CONTEXT_REG_END 0x000a400 529 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 530 #define PACKET3_SET_RESOURCE_INDIRECT 0x74 531 #define PACKET3_SET_SH_REG 0x76 532 #define PACKET3_SET_SH_REG_START 0x00002c00 533 #define PACKET3_SET_SH_REG_END 0x00003000 534 #define PACKET3_SET_SH_REG_OFFSET 0x77 535 #define PACKET3_ME_WRITE 0x7A 536 #define PACKET3_SCRATCH_RAM_WRITE 0x7D 537 #define PACKET3_SCRATCH_RAM_READ 0x7E 538 #define PACKET3_CE_WRITE 0x7F 539 #define PACKET3_LOAD_CONST_RAM 0x80 540 #define PACKET3_WRITE_CONST_RAM 0x81 541 #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82 542 #define PACKET3_DUMP_CONST_RAM 0x83 543 #define PACKET3_INCREMENT_CE_COUNTER 0x84 544 #define PACKET3_INCREMENT_DE_COUNTER 0x85 545 #define PACKET3_WAIT_ON_CE_COUNTER 0x86 546 #define PACKET3_WAIT_ON_DE_COUNTER 0x87 547 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 548 #define PACKET3_SET_CE_DE_COUNTERS 0x89 549 #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A 550 #define PACKET3_SWITCH_BUFFER 0x8B 551 552 /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */ 553 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ 554 #define DMA1_REGISTER_OFFSET 0x200 /* not a register */ 555 #define SDMA_MAX_INSTANCE 2 556 557 #define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \ 558 (((b) & 0x1) << 26) | \ 559 (((t) & 0x1) << 23) | \ 560 (((s) & 0x1) << 22) | \ 561 (((n) & 0xFFFFF) << 0)) 562 563 #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \ 564 (((vmid) & 0xF) << 20) | \ 565 (((n) & 0xFFFFF) << 0)) 566 567 #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \ 568 (1 << 26) | \ 569 (1 << 21) | \ 570 (((n) & 0xFFFFF) << 0)) 571 572 /* async DMA Packet types */ 573 #define DMA_PACKET_WRITE 0x2 574 #define DMA_PACKET_COPY 0x3 575 #define DMA_PACKET_INDIRECT_BUFFER 0x4 576 #define DMA_PACKET_SEMAPHORE 0x5 577 #define DMA_PACKET_FENCE 0x6 578 #define DMA_PACKET_TRAP 0x7 579 #define DMA_PACKET_SRBM_WRITE 0x9 580 #define DMA_PACKET_CONSTANT_FILL 0xd 581 #define DMA_PACKET_POLL_REG_MEM 0xe 582 #define DMA_PACKET_NOP 0xf 583 584 /* VCE */ 585 #define VCE_STATUS 0x20004 586 #define VCE_VCPU_CNTL 0x20014 587 #define VCE_CLK_EN (1 << 0) 588 #define VCE_VCPU_CACHE_OFFSET0 0x20024 589 #define VCE_VCPU_CACHE_SIZE0 0x20028 590 #define VCE_VCPU_CACHE_OFFSET1 0x2002c 591 #define VCE_VCPU_CACHE_SIZE1 0x20030 592 #define VCE_VCPU_CACHE_OFFSET2 0x20034 593 #define VCE_VCPU_CACHE_SIZE2 0x20038 594 #define VCE_SOFT_RESET 0x20120 595 #define VCE_ECPU_SOFT_RESET (1 << 0) 596 #define VCE_FME_SOFT_RESET (1 << 2) 597 #define VCE_RB_BASE_LO2 0x2016c 598 #define VCE_RB_BASE_HI2 0x20170 599 #define VCE_RB_SIZE2 0x20174 600 #define VCE_RB_RPTR2 0x20178 601 #define VCE_RB_WPTR2 0x2017c 602 #define VCE_RB_BASE_LO 0x20180 603 #define VCE_RB_BASE_HI 0x20184 604 #define VCE_RB_SIZE 0x20188 605 #define VCE_RB_RPTR 0x2018c 606 #define VCE_RB_WPTR 0x20190 607 #define VCE_CLOCK_GATING_A 0x202f8 608 #define VCE_CLOCK_GATING_B 0x202fc 609 #define VCE_UENC_CLOCK_GATING 0x205bc 610 #define VCE_UENC_REG_CLOCK_GATING 0x205c0 611 #define VCE_FW_REG_STATUS 0x20e10 612 # define VCE_FW_REG_STATUS_BUSY (1 << 0) 613 # define VCE_FW_REG_STATUS_PASS (1 << 3) 614 # define VCE_FW_REG_STATUS_DONE (1 << 11) 615 #define VCE_LMI_FW_START_KEYSEL 0x20e18 616 #define VCE_LMI_FW_PERIODIC_CTRL 0x20e20 617 #define VCE_LMI_CTRL2 0x20e74 618 #define VCE_LMI_CTRL 0x20e98 619 #define VCE_LMI_VM_CTRL 0x20ea0 620 #define VCE_LMI_SWAP_CNTL 0x20eb4 621 #define VCE_LMI_SWAP_CNTL1 0x20eb8 622 #define VCE_LMI_CACHE_CTRL 0x20ef4 623 624 #define VCE_CMD_NO_OP 0x00000000 625 #define VCE_CMD_END 0x00000001 626 #define VCE_CMD_IB 0x00000002 627 #define VCE_CMD_FENCE 0x00000003 628 #define VCE_CMD_TRAP 0x00000004 629 #define VCE_CMD_IB_AUTO 0x00000005 630 #define VCE_CMD_SEMAPHORE 0x00000006 631 632 633 //#dce stupp 634 /* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */ 635 #define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c) //(0x6df0 - 0x6df0)/4 636 #define CRTC1_REGISTER_OFFSET (0x1e7c - 0x1b7c) //(0x79f0 - 0x6df0)/4 637 #define CRTC2_REGISTER_OFFSET (0x417c - 0x1b7c) //(0x105f0 - 0x6df0)/4 638 #define CRTC3_REGISTER_OFFSET (0x447c - 0x1b7c) //(0x111f0 - 0x6df0)/4 639 #define CRTC4_REGISTER_OFFSET (0x477c - 0x1b7c) //(0x11df0 - 0x6df0)/4 640 #define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c) //(0x129f0 - 0x6df0)/4 641 642 /* hpd instance offsets */ 643 #define HPD0_REGISTER_OFFSET (0x1807 - 0x1807) 644 #define HPD1_REGISTER_OFFSET (0x180a - 0x1807) 645 #define HPD2_REGISTER_OFFSET (0x180d - 0x1807) 646 #define HPD3_REGISTER_OFFSET (0x1810 - 0x1807) 647 #define HPD4_REGISTER_OFFSET (0x1813 - 0x1807) 648 #define HPD5_REGISTER_OFFSET (0x1816 - 0x1807) 649 650 /* audio endpt instance offsets */ 651 #define AUD0_REGISTER_OFFSET (0x1780 - 0x1780) 652 #define AUD1_REGISTER_OFFSET (0x1786 - 0x1780) 653 #define AUD2_REGISTER_OFFSET (0x178c - 0x1780) 654 #define AUD3_REGISTER_OFFSET (0x1792 - 0x1780) 655 #define AUD4_REGISTER_OFFSET (0x1798 - 0x1780) 656 #define AUD5_REGISTER_OFFSET (0x179d - 0x1780) 657 #define AUD6_REGISTER_OFFSET (0x17a4 - 0x1780) 658 659 #define CURSOR_WIDTH 64 660 #define CURSOR_HEIGHT 64 661 662 663 #define R600_ROM_CNTL 0x580 664 # define R600_SCK_OVERWRITE (1 << 1) 665 # define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28 666 # define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28) 667 668 #define GRPH_ARRAY_LINEAR_GENERAL 0 669 #define GRPH_ARRAY_LINEAR_ALIGNED 1 670 #define GRPH_ARRAY_1D_TILED_THIN1 2 671 #define GRPH_ARRAY_2D_TILED_THIN1 4 672 673 #define ES_AND_GS_AUTO 3 674 #define BUF_SWAP_32BIT (2 << 16) 675 676 #define GRPH_DEPTH_8BPP 0 677 #define GRPH_DEPTH_16BPP 1 678 #define GRPH_DEPTH_32BPP 2 679 680 /* 8 BPP */ 681 #define GRPH_FORMAT_INDEXED 0 682 683 /* 16 BPP */ 684 #define GRPH_FORMAT_ARGB1555 0 685 #define GRPH_FORMAT_ARGB565 1 686 #define GRPH_FORMAT_ARGB4444 2 687 #define GRPH_FORMAT_AI88 3 688 #define GRPH_FORMAT_MONO16 4 689 #define GRPH_FORMAT_BGRA5551 5 690 691 /* 32 BPP */ 692 #define GRPH_FORMAT_ARGB8888 0 693 #define GRPH_FORMAT_ARGB2101010 1 694 #define GRPH_FORMAT_32BPP_DIG 2 695 #define GRPH_FORMAT_8B_ARGB2101010 3 696 #define GRPH_FORMAT_BGRA1010102 4 697 #define GRPH_FORMAT_8B_BGRA1010102 5 698 #define GRPH_FORMAT_RGB111110 6 699 #define GRPH_FORMAT_BGR101111 7 700 701 #define GRPH_ENDIAN_NONE 0 702 #define GRPH_ENDIAN_8IN16 1 703 #define GRPH_ENDIAN_8IN32 2 704 #define GRPH_ENDIAN_8IN64 3 705 #define GRPH_RED_SEL_R 0 706 #define GRPH_RED_SEL_G 1 707 #define GRPH_RED_SEL_B 2 708 #define GRPH_RED_SEL_A 3 709 710 #define GRPH_GREEN_SEL_G 0 711 #define GRPH_GREEN_SEL_B 1 712 #define GRPH_GREEN_SEL_A 2 713 #define GRPH_GREEN_SEL_R 3 714 715 #define GRPH_BLUE_SEL_B 0 716 #define GRPH_BLUE_SEL_A 1 717 #define GRPH_BLUE_SEL_R 2 718 #define GRPH_BLUE_SEL_G 3 719 720 #define GRPH_ALPHA_SEL_A 0 721 #define GRPH_ALPHA_SEL_R 1 722 #define GRPH_ALPHA_SEL_G 2 723 #define GRPH_ALPHA_SEL_B 3 724 725 /* CUR_CONTROL */ 726 #define CURSOR_MONO 0 727 #define CURSOR_24_1 1 728 #define CURSOR_24_8_PRE_MULT 2 729 #define CURSOR_24_8_UNPRE_MULT 3 730 #define CURSOR_URGENT_ALWAYS 0 731 #define CURSOR_URGENT_1_8 1 732 #define CURSOR_URGENT_1_4 2 733 #define CURSOR_URGENT_3_8 3 734 #define CURSOR_URGENT_1_2 4 735 736 /* INPUT_CSC_CONTROL */ 737 # define INPUT_CSC_BYPASS 0 738 # define INPUT_CSC_PROG_COEFF 1 739 # define INPUT_CSC_PROG_SHARED_MATRIXA 2 740 741 /* OUTPUT_CSC_CONTROL */ 742 # define OUTPUT_CSC_BYPASS 0 743 # define OUTPUT_CSC_TV_RGB 1 744 # define OUTPUT_CSC_YCBCR_601 2 745 # define OUTPUT_CSC_YCBCR_709 3 746 # define OUTPUT_CSC_PROG_COEFF 4 747 # define OUTPUT_CSC_PROG_SHARED_MATRIXB 5 748 749 /* DEGAMMA_CONTROL */ 750 # define DEGAMMA_BYPASS 0 751 # define DEGAMMA_SRGB_24 1 752 # define DEGAMMA_XVYCC_222 2 753 754 /* GAMUT_REMAP_CONTROL */ 755 # define GAMUT_REMAP_BYPASS 0 756 # define GAMUT_REMAP_PROG_COEFF 1 757 # define GAMUT_REMAP_PROG_SHARED_MATRIXA 2 758 # define GAMUT_REMAP_PROG_SHARED_MATRIXB 3 759 760 /* REGAMMA_CONTROL */ 761 # define REGAMMA_BYPASS 0 762 # define REGAMMA_SRGB_24 1 763 # define REGAMMA_XVYCC_222 2 764 # define REGAMMA_PROG_A 3 765 # define REGAMMA_PROG_B 4 766 767 768 /* INPUT_GAMMA_CONTROL */ 769 # define INPUT_GAMMA_USE_LUT 0 770 # define INPUT_GAMMA_BYPASS 1 771 # define INPUT_GAMMA_SRGB_24 2 772 # define INPUT_GAMMA_XVYCC_222 3 773 774 #define MC_SEQ_MISC0__MT__MASK 0xf0000000 775 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000 776 #define MC_SEQ_MISC0__MT__DDR2 0x20000000 777 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000 778 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000 779 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000 780 #define MC_SEQ_MISC0__MT__HBM 0x60000000 781 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000 782 783 #define CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK 0x4000000 784 #define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12) 785 #define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 786 #define PACKET3_SEM_SEL_WAIT (0x7 << 29) 787 788 #define AMDGPU_PCIE_INDEX 0xc 789 #define AMDGPU_PCIE_DATA 0xd 790 791 #define PCIE_BUS_CLK 10000 792 #define TCLK (PCIE_BUS_CLK / 10) 793 #define PCIE_PORT_INDEX 0xe 794 #define PCIE_PORT_DATA 0xf 795 #define EVERGREEN_PIF_PHY0_INDEX 0x8 796 #define EVERGREEN_PIF_PHY0_DATA 0xc 797 #define EVERGREEN_PIF_PHY1_INDEX 0x10 798 #define EVERGREEN_PIF_PHY1_DATA 0x14 799 800 /* Discrete VCE clocks */ 801 #define CG_VCEPLL_FUNC_CNTL 0xc0030600 802 #define VCEPLL_RESET_MASK 0x00000001 803 #define VCEPLL_SLEEP_MASK 0x00000002 804 #define VCEPLL_BYPASS_EN_MASK 0x00000004 805 #define VCEPLL_CTLREQ_MASK 0x00000008 806 #define VCEPLL_VCO_MODE_MASK 0x00000600 807 #define VCEPLL_REF_DIV_MASK 0x003F0000 808 #define VCEPLL_CTLACK_MASK 0x40000000 809 #define VCEPLL_CTLACK2_MASK 0x80000000 810 811 #define CG_VCEPLL_FUNC_CNTL_2 0xc0030601 812 #define VCEPLL_PDIV_A(x) ((x) << 0) 813 #define VCEPLL_PDIV_A_MASK 0x0000007F 814 #define VCEPLL_PDIV_B(x) ((x) << 8) 815 #define VCEPLL_PDIV_B_MASK 0x00007F00 816 #define EVCLK_SRC_SEL(x) ((x) << 20) 817 #define EVCLK_SRC_SEL_MASK 0x01F00000 818 #define ECCLK_SRC_SEL(x) ((x) << 25) 819 #define ECCLK_SRC_SEL_MASK 0x3E000000 820 821 #define CG_VCEPLL_FUNC_CNTL_3 0xc0030602 822 #define VCEPLL_FB_DIV(x) ((x) << 0) 823 #define VCEPLL_FB_DIV_MASK 0x01FFFFFF 824 825 #define CG_VCEPLL_FUNC_CNTL_4 0xc0030603 826 827 #define CG_VCEPLL_FUNC_CNTL_5 0xc0030604 828 #define CG_VCEPLL_SPREAD_SPECTRUM 0xc0030606 829 #define VCEPLL_SSEN_MASK 0x00000001 830 831 832 #endif 833