1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 #include "sid.h" 29 #include "si_ih.h" 30 31 #include "oss/oss_1_0_d.h" 32 #include "oss/oss_1_0_sh_mask.h" 33 34 static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev); 35 36 static void si_ih_enable_interrupts(struct amdgpu_device *adev) 37 { 38 u32 ih_cntl = RREG32(IH_CNTL); 39 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 40 41 ih_cntl |= ENABLE_INTR; 42 ih_rb_cntl |= IH_RB_ENABLE; 43 WREG32(IH_CNTL, ih_cntl); 44 WREG32(IH_RB_CNTL, ih_rb_cntl); 45 adev->irq.ih.enabled = true; 46 } 47 48 static void si_ih_disable_interrupts(struct amdgpu_device *adev) 49 { 50 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 51 u32 ih_cntl = RREG32(IH_CNTL); 52 53 ih_rb_cntl &= ~IH_RB_ENABLE; 54 ih_cntl &= ~ENABLE_INTR; 55 WREG32(IH_RB_CNTL, ih_rb_cntl); 56 WREG32(IH_CNTL, ih_cntl); 57 WREG32(IH_RB_RPTR, 0); 58 WREG32(IH_RB_WPTR, 0); 59 adev->irq.ih.enabled = false; 60 adev->irq.ih.rptr = 0; 61 } 62 63 static int si_ih_irq_init(struct amdgpu_device *adev) 64 { 65 struct amdgpu_ih_ring *ih = &adev->irq.ih; 66 int rb_bufsz; 67 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 68 69 si_ih_disable_interrupts(adev); 70 /* set dummy read address to dummy page address */ 71 WREG32(INTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 72 interrupt_cntl = RREG32(INTERRUPT_CNTL); 73 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; 74 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; 75 WREG32(INTERRUPT_CNTL, interrupt_cntl); 76 77 WREG32(IH_RB_BASE, adev->irq.ih.gpu_addr >> 8); 78 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); 79 80 ih_rb_cntl = IH_WPTR_OVERFLOW_ENABLE | 81 IH_WPTR_OVERFLOW_CLEAR | 82 (rb_bufsz << 1) | 83 IH_WPTR_WRITEBACK_ENABLE; 84 85 WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); 86 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); 87 WREG32(IH_RB_CNTL, ih_rb_cntl); 88 WREG32(IH_RB_RPTR, 0); 89 WREG32(IH_RB_WPTR, 0); 90 91 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0); 92 if (adev->irq.msi_enabled) 93 ih_cntl |= RPTR_REARM; 94 WREG32(IH_CNTL, ih_cntl); 95 96 pci_set_master(adev->pdev); 97 si_ih_enable_interrupts(adev); 98 99 return 0; 100 } 101 102 static void si_ih_irq_disable(struct amdgpu_device *adev) 103 { 104 si_ih_disable_interrupts(adev); 105 mdelay(1); 106 } 107 108 static u32 si_ih_get_wptr(struct amdgpu_device *adev, 109 struct amdgpu_ih_ring *ih) 110 { 111 u32 wptr, tmp; 112 113 wptr = le32_to_cpu(*ih->wptr_cpu); 114 115 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) { 116 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; 117 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", 118 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); 119 ih->rptr = (wptr + 16) & ih->ptr_mask; 120 tmp = RREG32(IH_RB_CNTL); 121 tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK; 122 WREG32(IH_RB_CNTL, tmp); 123 124 /* Unset the CLEAR_OVERFLOW bit immediately so new overflows 125 * can be detected. 126 */ 127 tmp &= ~IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK; 128 WREG32(IH_RB_CNTL, tmp); 129 } 130 return (wptr & ih->ptr_mask); 131 } 132 133 static void si_ih_decode_iv(struct amdgpu_device *adev, 134 struct amdgpu_ih_ring *ih, 135 struct amdgpu_iv_entry *entry) 136 { 137 u32 ring_index = ih->rptr >> 2; 138 uint32_t dw[4]; 139 140 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 141 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 142 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 143 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 144 145 entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 146 entry->src_id = dw[0] & 0xff; 147 entry->src_data[0] = dw[1] & 0xfffffff; 148 entry->ring_id = dw[2] & 0xff; 149 entry->vmid = (dw[2] >> 8) & 0xff; 150 151 ih->rptr += 16; 152 } 153 154 static void si_ih_set_rptr(struct amdgpu_device *adev, 155 struct amdgpu_ih_ring *ih) 156 { 157 WREG32(IH_RB_RPTR, ih->rptr); 158 } 159 160 static int si_ih_early_init(struct amdgpu_ip_block *ip_block) 161 { 162 struct amdgpu_device *adev = ip_block->adev; 163 164 si_ih_set_interrupt_funcs(adev); 165 166 return 0; 167 } 168 169 static int si_ih_sw_init(struct amdgpu_ip_block *ip_block) 170 { 171 int r; 172 struct amdgpu_device *adev = ip_block->adev; 173 174 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false); 175 if (r) 176 return r; 177 178 return amdgpu_irq_init(adev); 179 } 180 181 static int si_ih_sw_fini(struct amdgpu_ip_block *ip_block) 182 { 183 struct amdgpu_device *adev = ip_block->adev; 184 185 amdgpu_irq_fini_sw(adev); 186 187 return 0; 188 } 189 190 static int si_ih_hw_init(struct amdgpu_ip_block *ip_block) 191 { 192 struct amdgpu_device *adev = ip_block->adev; 193 194 return si_ih_irq_init(adev); 195 } 196 197 static int si_ih_hw_fini(struct amdgpu_ip_block *ip_block) 198 { 199 si_ih_irq_disable(ip_block->adev); 200 201 return 0; 202 } 203 204 static int si_ih_suspend(struct amdgpu_ip_block *ip_block) 205 { 206 return si_ih_hw_fini(ip_block); 207 } 208 209 static int si_ih_resume(struct amdgpu_ip_block *ip_block) 210 { 211 return si_ih_hw_init(ip_block); 212 } 213 214 static bool si_ih_is_idle(struct amdgpu_ip_block *ip_block) 215 { 216 struct amdgpu_device *adev = ip_block->adev; 217 u32 tmp = RREG32(mmSRBM_STATUS); 218 219 if (tmp & SRBM_STATUS__IH_BUSY_MASK) 220 return false; 221 222 return true; 223 } 224 225 static int si_ih_wait_for_idle(struct amdgpu_ip_block *ip_block) 226 { 227 unsigned i; 228 struct amdgpu_device *adev = ip_block->adev; 229 230 for (i = 0; i < adev->usec_timeout; i++) { 231 if (si_ih_is_idle(ip_block)) 232 return 0; 233 udelay(1); 234 } 235 return -ETIMEDOUT; 236 } 237 238 static int si_ih_soft_reset(struct amdgpu_ip_block *ip_block) 239 { 240 struct amdgpu_device *adev = ip_block->adev; 241 242 u32 srbm_soft_reset = 0; 243 u32 tmp = RREG32(mmSRBM_STATUS); 244 245 if (tmp & SRBM_STATUS__IH_BUSY_MASK) 246 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK; 247 248 if (srbm_soft_reset) { 249 tmp = RREG32(mmSRBM_SOFT_RESET); 250 tmp |= srbm_soft_reset; 251 dev_info(adev->dev, "mmSRBM_SOFT_RESET=0x%08X\n", tmp); 252 WREG32(mmSRBM_SOFT_RESET, tmp); 253 tmp = RREG32(mmSRBM_SOFT_RESET); 254 255 udelay(50); 256 257 tmp &= ~srbm_soft_reset; 258 WREG32(mmSRBM_SOFT_RESET, tmp); 259 tmp = RREG32(mmSRBM_SOFT_RESET); 260 261 udelay(50); 262 } 263 264 return 0; 265 } 266 267 static int si_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block, 268 enum amd_clockgating_state state) 269 { 270 return 0; 271 } 272 273 static int si_ih_set_powergating_state(struct amdgpu_ip_block *ip_block, 274 enum amd_powergating_state state) 275 { 276 return 0; 277 } 278 279 static const struct amd_ip_funcs si_ih_ip_funcs = { 280 .name = "si_ih", 281 .early_init = si_ih_early_init, 282 .sw_init = si_ih_sw_init, 283 .sw_fini = si_ih_sw_fini, 284 .hw_init = si_ih_hw_init, 285 .hw_fini = si_ih_hw_fini, 286 .suspend = si_ih_suspend, 287 .resume = si_ih_resume, 288 .is_idle = si_ih_is_idle, 289 .wait_for_idle = si_ih_wait_for_idle, 290 .soft_reset = si_ih_soft_reset, 291 .set_clockgating_state = si_ih_set_clockgating_state, 292 .set_powergating_state = si_ih_set_powergating_state, 293 }; 294 295 static const struct amdgpu_ih_funcs si_ih_funcs = { 296 .get_wptr = si_ih_get_wptr, 297 .decode_iv = si_ih_decode_iv, 298 .set_rptr = si_ih_set_rptr 299 }; 300 301 static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev) 302 { 303 adev->irq.ih_funcs = &si_ih_funcs; 304 } 305 306 const struct amdgpu_ip_block_version si_ih_ip_block = 307 { 308 .type = AMD_IP_BLOCK_TYPE_IH, 309 .major = 1, 310 .minor = 0, 311 .rev = 0, 312 .funcs = &si_ih_ip_funcs, 313 }; 314