1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/slab.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include <drm/amdgpu_drm.h> 30 31 #include "amdgpu.h" 32 #include "amdgpu_atombios.h" 33 #include "amdgpu_ih.h" 34 #include "amdgpu_uvd.h" 35 #include "amdgpu_vce.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "si_dpm.h" 40 #include "sid.h" 41 #include "si_ih.h" 42 #include "gfx_v6_0.h" 43 #include "gmc_v6_0.h" 44 #include "si_dma.h" 45 #include "dce_v6_0.h" 46 #include "si.h" 47 #include "uvd_v3_1.h" 48 49 #include "uvd/uvd_4_0_d.h" 50 51 #include "smu/smu_6_0_d.h" 52 #include "smu/smu_6_0_sh_mask.h" 53 54 #include "gca/gfx_6_0_d.h" 55 #include "gca/gfx_6_0_sh_mask.h" 56 57 #include "oss/oss_1_0_d.h" 58 #include "oss/oss_1_0_sh_mask.h" 59 60 #include "gmc/gmc_6_0_d.h" 61 #include"gmc/gmc_6_0_sh_mask.h" 62 63 #include "dce/dce_6_0_d.h" 64 #include "dce/dce_6_0_sh_mask.h" 65 66 #include "bif/bif_3_0_d.h" 67 #include "bif/bif_3_0_sh_mask.h" 68 #include "si_enums.h" 69 70 #include "amdgpu_dm.h" 71 #include "amdgpu_vkms.h" 72 73 static const u32 tahiti_golden_registers[] = 74 { 75 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011, 76 mmCB_HW_CONTROL, 0x00010000, 0x00018208, 77 mmDB_DEBUG, 0xffffffff, 0x00000000, 78 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 79 mmDB_DEBUG3, 0x0002021c, 0x00020200, 80 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 81 0x340c, 0x000000c0, 0x00800040, 82 0x360c, 0x000000c0, 0x00800040, 83 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 84 mmFBC_MISC, 0x00200000, 0x50100000, 85 mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011, 86 mmMC_ARB_WTM_CNTL_RD, 0x00000003, 0x000007ff, 87 mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000, 88 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007, 89 mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff, 90 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 91 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000, 92 mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x2a00126a, 93 0x000c, 0xffffffff, 0x0040, 94 0x000d, 0x00000040, 0x00004040, 95 mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000, 96 mmSQ_DED_CNT, 0x01ff1f3f, 0x00000000, 97 mmSQ_SEC_CNT, 0x01ff1f3f, 0x00000000, 98 mmSX_DEBUG_1, 0x0000007f, 0x00000020, 99 mmTA_CNTL_AUX, 0x00010000, 0x00010000, 100 mmTCP_ADDR_CONFIG, 0x00000200, 0x000002fb, 101 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b, 102 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876, 103 mmVGT_FIFO_DEPTHS, 0xffffffff, 0x000fff40, 104 mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010, 105 mmVM_CONTEXT0_CNTL, 0x20000000, 0x20fffed8, 106 mmVM_L2_CG, 0x000c0fc0, 0x000c0400, 107 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff, 108 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 109 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 110 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 111 }; 112 113 static const u32 tahiti_golden_registers2[] = 114 { 115 mmMCIF_MEM_CONTROL, 0x00000001, 0x00000001, 116 }; 117 118 static const u32 tahiti_golden_rlc_registers[] = 119 { 120 mmGB_ADDR_CONFIG, 0xffffffff, 0x12011003, 121 mmRLC_LB_PARAMS, 0xffffffff, 0x00601005, 122 0x311f, 0xffffffff, 0x10104040, 123 0x3122, 0xffffffff, 0x0100000a, 124 mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800, 125 mmRLC_LB_CNTL, 0xffffffff, 0x800000f4, 126 mmUVD_CGC_GATE, 0x00000008, 0x00000000, 127 }; 128 129 static const u32 pitcairn_golden_registers[] = 130 { 131 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011, 132 mmCB_HW_CONTROL, 0x00010000, 0x00018208, 133 mmDB_DEBUG, 0xffffffff, 0x00000000, 134 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 135 mmDB_DEBUG3, 0x0002021c, 0x00020200, 136 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 137 0x340c, 0x000300c0, 0x00800040, 138 0x360c, 0x000300c0, 0x00800040, 139 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 140 mmFBC_MISC, 0x00200000, 0x50100000, 141 mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011, 142 mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2, 143 mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000, 144 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007, 145 mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff, 146 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 147 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000, 148 mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x2a00126a, 149 0x000c, 0xffffffff, 0x0040, 150 0x000d, 0x00000040, 0x00004040, 151 mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000, 152 mmSX_DEBUG_1, 0x0000007f, 0x00000020, 153 mmTA_CNTL_AUX, 0x00010000, 0x00010000, 154 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7, 155 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 156 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x32761054, 157 mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010, 158 mmVM_L2_CG, 0x000c0fc0, 0x000c0400, 159 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff, 160 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 161 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 162 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 163 }; 164 165 static const u32 pitcairn_golden_rlc_registers[] = 166 { 167 mmGB_ADDR_CONFIG, 0xffffffff, 0x12011003, 168 mmRLC_LB_PARAMS, 0xffffffff, 0x00601004, 169 0x311f, 0xffffffff, 0x10102020, 170 0x3122, 0xffffffff, 0x01000020, 171 mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800, 172 mmRLC_LB_CNTL, 0xffffffff, 0x800000a4, 173 }; 174 175 static const u32 verde_pg_init[] = 176 { 177 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x40000, 178 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x200010ff, 179 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 180 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 181 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 182 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 183 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 184 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x7007, 185 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x300010ff, 186 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 187 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 188 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 189 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 190 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 191 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x400000, 192 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x100010ff, 193 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 194 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 195 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 196 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 197 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 198 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x120200, 199 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x500010ff, 200 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 201 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 202 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 203 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 204 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 205 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x1e1e16, 206 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x600010ff, 207 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 208 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 209 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 210 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 211 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 212 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x171f1e, 213 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x700010ff, 214 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 215 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 216 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 217 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 218 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 219 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 220 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x9ff, 221 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x0, 222 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10000800, 223 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xf, 224 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xf, 225 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x4, 226 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1000051e, 227 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xffff, 228 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xffff, 229 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x8, 230 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x80500, 231 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x12, 232 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x9050c, 233 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1d, 234 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xb052c, 235 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x2a, 236 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1053e, 237 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x2d, 238 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10546, 239 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x30, 240 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xa054e, 241 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x3c, 242 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1055f, 243 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x3f, 244 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10567, 245 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x42, 246 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1056f, 247 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x45, 248 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10572, 249 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x48, 250 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x20575, 251 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x4c, 252 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x190801, 253 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x67, 254 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1082a, 255 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x6a, 256 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1b082d, 257 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x87, 258 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x310851, 259 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xba, 260 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x891, 261 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xbc, 262 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x893, 263 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xbe, 264 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x20895, 265 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xc2, 266 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x20899, 267 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xc6, 268 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x2089d, 269 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xca, 270 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x8a1, 271 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xcc, 272 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x8a3, 273 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xce, 274 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x308a5, 275 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xd3, 276 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x6d08cd, 277 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x142, 278 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x2000095a, 279 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1, 280 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x144, 281 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x301f095b, 282 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x165, 283 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xc094d, 284 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x173, 285 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xf096d, 286 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x184, 287 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x15097f, 288 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x19b, 289 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xc0998, 290 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1a9, 291 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x409a7, 292 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1af, 293 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xcdc, 294 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1b1, 295 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x800, 296 mmGMCON_RENG_EXECUTE, 0xffffffff, 0x6c9b2000, 297 mmGMCON_MISC2, 0xfc00, 0x2000, 298 mmGMCON_MISC3, 0xffffffff, 0xfc0, 299 mmMC_PMG_AUTO_CFG, 0x00000100, 0x100, 300 }; 301 302 static const u32 verde_golden_rlc_registers[] = 303 { 304 mmGB_ADDR_CONFIG, 0xffffffff, 0x02010002, 305 mmRLC_LB_PARAMS, 0xffffffff, 0x033f1005, 306 0x311f, 0xffffffff, 0x10808020, 307 0x3122, 0xffffffff, 0x00800008, 308 mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00001000, 309 mmRLC_LB_CNTL, 0xffffffff, 0x80010014, 310 }; 311 312 static const u32 verde_golden_registers[] = 313 { 314 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011, 315 mmCB_HW_CONTROL, 0x00010000, 0x00018208, 316 mmDB_DEBUG, 0xffffffff, 0x00000000, 317 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 318 mmDB_DEBUG3, 0x0002021c, 0x00020200, 319 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 320 0x340c, 0x000300c0, 0x00800040, 321 0x360c, 0x000300c0, 0x00800040, 322 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 323 mmFBC_MISC, 0x00200000, 0x50100000, 324 mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011, 325 mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2, 326 mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000, 327 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007, 328 mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff, 329 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 330 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000, 331 mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x0000124a, 332 0x000c, 0xffffffff, 0x0040, 333 0x000d, 0x00000040, 0x00004040, 334 mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000, 335 mmSQ_DED_CNT, 0x01ff1f3f, 0x00000000, 336 mmSQ_SEC_CNT, 0x01ff1f3f, 0x00000000, 337 mmSX_DEBUG_1, 0x0000007f, 0x00000020, 338 mmTA_CNTL_AUX, 0x00010000, 0x00010000, 339 mmTCP_ADDR_CONFIG, 0x000003ff, 0x00000003, 340 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 341 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001032, 342 mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010, 343 mmVM_L2_CG, 0x000c0fc0, 0x000c0400, 344 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff, 345 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 346 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 347 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 348 }; 349 350 static const u32 oland_golden_registers[] = 351 { 352 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011, 353 mmCB_HW_CONTROL, 0x00010000, 0x00018208, 354 mmDB_DEBUG, 0xffffffff, 0x00000000, 355 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 356 mmDB_DEBUG3, 0x0002021c, 0x00020200, 357 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 358 0x340c, 0x000300c0, 0x00800040, 359 0x360c, 0x000300c0, 0x00800040, 360 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 361 mmFBC_MISC, 0x00200000, 0x50100000, 362 mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011, 363 mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2, 364 mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000, 365 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007, 366 mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff, 367 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 368 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000, 369 mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x00000082, 370 0x000c, 0xffffffff, 0x0040, 371 0x000d, 0x00000040, 0x00004040, 372 mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000, 373 mmSX_DEBUG_1, 0x0000007f, 0x00000020, 374 mmTA_CNTL_AUX, 0x00010000, 0x00010000, 375 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3, 376 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 377 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210, 378 mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010, 379 mmVM_L2_CG, 0x000c0fc0, 0x000c0400, 380 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff, 381 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 382 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 383 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 384 385 }; 386 387 static const u32 oland_golden_rlc_registers[] = 388 { 389 mmGB_ADDR_CONFIG, 0xffffffff, 0x02010002, 390 mmRLC_LB_PARAMS, 0xffffffff, 0x00601005, 391 0x311f, 0xffffffff, 0x10104040, 392 0x3122, 0xffffffff, 0x0100000a, 393 mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800, 394 mmRLC_LB_CNTL, 0xffffffff, 0x800000f4, 395 }; 396 397 static const u32 hainan_golden_registers[] = 398 { 399 0x17bc, 0x00000030, 0x00000011, 400 mmCB_HW_CONTROL, 0x00010000, 0x00018208, 401 mmDB_DEBUG, 0xffffffff, 0x00000000, 402 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 403 mmDB_DEBUG3, 0x0002021c, 0x00020200, 404 0x031e, 0x00000080, 0x00000000, 405 0x3430, 0xff000fff, 0x00000100, 406 0x340c, 0x000300c0, 0x00800040, 407 0x3630, 0xff000fff, 0x00000100, 408 0x360c, 0x000300c0, 0x00800040, 409 0x16ec, 0x000000f0, 0x00000070, 410 0x16f0, 0x00200000, 0x50100000, 411 0x1c0c, 0x31000311, 0x00000011, 412 mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2, 413 mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000, 414 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007, 415 mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff, 416 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 417 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000, 418 mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x00000000, 419 0x000c, 0xffffffff, 0x0040, 420 0x000d, 0x00000040, 0x00004040, 421 mmSPI_CONFIG_CNTL, 0x03e00000, 0x03600000, 422 mmSX_DEBUG_1, 0x0000007f, 0x00000020, 423 mmTA_CNTL_AUX, 0x00010000, 0x00010000, 424 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1, 425 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 426 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210, 427 mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010, 428 mmVM_L2_CG, 0x000c0fc0, 0x000c0400, 429 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff, 430 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 431 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 432 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 433 }; 434 435 static const u32 hainan_golden_registers2[] = 436 { 437 mmGB_ADDR_CONFIG, 0xffffffff, 0x2011003, 438 }; 439 440 static const u32 tahiti_mgcg_cgcg_init[] = 441 { 442 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc, 443 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 444 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 445 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 446 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 447 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 448 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 449 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 450 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 451 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 452 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 453 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 454 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 455 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 456 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 457 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 458 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 459 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 460 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 461 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 462 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 463 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 464 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 465 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 466 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 467 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 468 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 469 0x2458, 0xffffffff, 0x00010000, 470 0x2459, 0xffffffff, 0x00030002, 471 0x245a, 0xffffffff, 0x00040007, 472 0x245b, 0xffffffff, 0x00060005, 473 0x245c, 0xffffffff, 0x00090008, 474 0x245d, 0xffffffff, 0x00020001, 475 0x245e, 0xffffffff, 0x00040003, 476 0x245f, 0xffffffff, 0x00000007, 477 0x2460, 0xffffffff, 0x00060005, 478 0x2461, 0xffffffff, 0x00090008, 479 0x2462, 0xffffffff, 0x00030002, 480 0x2463, 0xffffffff, 0x00050004, 481 0x2464, 0xffffffff, 0x00000008, 482 0x2465, 0xffffffff, 0x00070006, 483 0x2466, 0xffffffff, 0x000a0009, 484 0x2467, 0xffffffff, 0x00040003, 485 0x2468, 0xffffffff, 0x00060005, 486 0x2469, 0xffffffff, 0x00000009, 487 0x246a, 0xffffffff, 0x00080007, 488 0x246b, 0xffffffff, 0x000b000a, 489 0x246c, 0xffffffff, 0x00050004, 490 0x246d, 0xffffffff, 0x00070006, 491 0x246e, 0xffffffff, 0x0008000b, 492 0x246f, 0xffffffff, 0x000a0009, 493 0x2470, 0xffffffff, 0x000d000c, 494 0x2471, 0xffffffff, 0x00060005, 495 0x2472, 0xffffffff, 0x00080007, 496 0x2473, 0xffffffff, 0x0000000b, 497 0x2474, 0xffffffff, 0x000a0009, 498 0x2475, 0xffffffff, 0x000d000c, 499 0x2476, 0xffffffff, 0x00070006, 500 0x2477, 0xffffffff, 0x00090008, 501 0x2478, 0xffffffff, 0x0000000c, 502 0x2479, 0xffffffff, 0x000b000a, 503 0x247a, 0xffffffff, 0x000e000d, 504 0x247b, 0xffffffff, 0x00080007, 505 0x247c, 0xffffffff, 0x000a0009, 506 0x247d, 0xffffffff, 0x0000000d, 507 0x247e, 0xffffffff, 0x000c000b, 508 0x247f, 0xffffffff, 0x000f000e, 509 0x2480, 0xffffffff, 0x00090008, 510 0x2481, 0xffffffff, 0x000b000a, 511 0x2482, 0xffffffff, 0x000c000f, 512 0x2483, 0xffffffff, 0x000e000d, 513 0x2484, 0xffffffff, 0x00110010, 514 0x2485, 0xffffffff, 0x000a0009, 515 0x2486, 0xffffffff, 0x000c000b, 516 0x2487, 0xffffffff, 0x0000000f, 517 0x2488, 0xffffffff, 0x000e000d, 518 0x2489, 0xffffffff, 0x00110010, 519 0x248a, 0xffffffff, 0x000b000a, 520 0x248b, 0xffffffff, 0x000d000c, 521 0x248c, 0xffffffff, 0x00000010, 522 0x248d, 0xffffffff, 0x000f000e, 523 0x248e, 0xffffffff, 0x00120011, 524 0x248f, 0xffffffff, 0x000c000b, 525 0x2490, 0xffffffff, 0x000e000d, 526 0x2491, 0xffffffff, 0x00000011, 527 0x2492, 0xffffffff, 0x0010000f, 528 0x2493, 0xffffffff, 0x00130012, 529 0x2494, 0xffffffff, 0x000d000c, 530 0x2495, 0xffffffff, 0x000f000e, 531 0x2496, 0xffffffff, 0x00100013, 532 0x2497, 0xffffffff, 0x00120011, 533 0x2498, 0xffffffff, 0x00150014, 534 0x2499, 0xffffffff, 0x000e000d, 535 0x249a, 0xffffffff, 0x0010000f, 536 0x249b, 0xffffffff, 0x00000013, 537 0x249c, 0xffffffff, 0x00120011, 538 0x249d, 0xffffffff, 0x00150014, 539 0x249e, 0xffffffff, 0x000f000e, 540 0x249f, 0xffffffff, 0x00110010, 541 0x24a0, 0xffffffff, 0x00000014, 542 0x24a1, 0xffffffff, 0x00130012, 543 0x24a2, 0xffffffff, 0x00160015, 544 0x24a3, 0xffffffff, 0x0010000f, 545 0x24a4, 0xffffffff, 0x00120011, 546 0x24a5, 0xffffffff, 0x00000015, 547 0x24a6, 0xffffffff, 0x00140013, 548 0x24a7, 0xffffffff, 0x00170016, 549 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 550 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 551 mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080, 552 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 553 0x000c, 0xffffffff, 0x0000001c, 554 0x000d, 0x000f0000, 0x000f0000, 555 0x0583, 0xffffffff, 0x00000100, 556 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 557 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 558 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104, 559 mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000, 560 mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000, 561 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 562 0x157a, 0x00000001, 0x00000001, 563 mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001, 564 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 565 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 566 0x3430, 0xfffffff0, 0x00000100, 567 0x3630, 0xfffffff0, 0x00000100, 568 }; 569 static const u32 pitcairn_mgcg_cgcg_init[] = 570 { 571 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc, 572 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 573 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 574 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 575 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 576 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 577 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 578 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 579 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 580 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 581 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 582 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 583 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 584 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 585 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 586 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 587 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 588 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 589 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 590 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 591 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 592 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 593 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 594 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 595 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 596 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 597 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 598 0x2458, 0xffffffff, 0x00010000, 599 0x2459, 0xffffffff, 0x00030002, 600 0x245a, 0xffffffff, 0x00040007, 601 0x245b, 0xffffffff, 0x00060005, 602 0x245c, 0xffffffff, 0x00090008, 603 0x245d, 0xffffffff, 0x00020001, 604 0x245e, 0xffffffff, 0x00040003, 605 0x245f, 0xffffffff, 0x00000007, 606 0x2460, 0xffffffff, 0x00060005, 607 0x2461, 0xffffffff, 0x00090008, 608 0x2462, 0xffffffff, 0x00030002, 609 0x2463, 0xffffffff, 0x00050004, 610 0x2464, 0xffffffff, 0x00000008, 611 0x2465, 0xffffffff, 0x00070006, 612 0x2466, 0xffffffff, 0x000a0009, 613 0x2467, 0xffffffff, 0x00040003, 614 0x2468, 0xffffffff, 0x00060005, 615 0x2469, 0xffffffff, 0x00000009, 616 0x246a, 0xffffffff, 0x00080007, 617 0x246b, 0xffffffff, 0x000b000a, 618 0x246c, 0xffffffff, 0x00050004, 619 0x246d, 0xffffffff, 0x00070006, 620 0x246e, 0xffffffff, 0x0008000b, 621 0x246f, 0xffffffff, 0x000a0009, 622 0x2470, 0xffffffff, 0x000d000c, 623 0x2480, 0xffffffff, 0x00090008, 624 0x2481, 0xffffffff, 0x000b000a, 625 0x2482, 0xffffffff, 0x000c000f, 626 0x2483, 0xffffffff, 0x000e000d, 627 0x2484, 0xffffffff, 0x00110010, 628 0x2485, 0xffffffff, 0x000a0009, 629 0x2486, 0xffffffff, 0x000c000b, 630 0x2487, 0xffffffff, 0x0000000f, 631 0x2488, 0xffffffff, 0x000e000d, 632 0x2489, 0xffffffff, 0x00110010, 633 0x248a, 0xffffffff, 0x000b000a, 634 0x248b, 0xffffffff, 0x000d000c, 635 0x248c, 0xffffffff, 0x00000010, 636 0x248d, 0xffffffff, 0x000f000e, 637 0x248e, 0xffffffff, 0x00120011, 638 0x248f, 0xffffffff, 0x000c000b, 639 0x2490, 0xffffffff, 0x000e000d, 640 0x2491, 0xffffffff, 0x00000011, 641 0x2492, 0xffffffff, 0x0010000f, 642 0x2493, 0xffffffff, 0x00130012, 643 0x2494, 0xffffffff, 0x000d000c, 644 0x2495, 0xffffffff, 0x000f000e, 645 0x2496, 0xffffffff, 0x00100013, 646 0x2497, 0xffffffff, 0x00120011, 647 0x2498, 0xffffffff, 0x00150014, 648 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 649 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 650 mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080, 651 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 652 0x000c, 0xffffffff, 0x0000001c, 653 0x000d, 0x000f0000, 0x000f0000, 654 0x0583, 0xffffffff, 0x00000100, 655 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 656 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 657 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104, 658 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 659 0x157a, 0x00000001, 0x00000001, 660 mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001, 661 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 662 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 663 0x3430, 0xfffffff0, 0x00000100, 664 0x3630, 0xfffffff0, 0x00000100, 665 }; 666 667 static const u32 verde_mgcg_cgcg_init[] = 668 { 669 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc, 670 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 671 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 672 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 673 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 674 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 675 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 676 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 677 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 678 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 679 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 680 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 681 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 682 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 683 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 684 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 685 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 686 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 687 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 688 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 689 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 690 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 691 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 692 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 693 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 694 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 695 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 696 0x2458, 0xffffffff, 0x00010000, 697 0x2459, 0xffffffff, 0x00030002, 698 0x245a, 0xffffffff, 0x00040007, 699 0x245b, 0xffffffff, 0x00060005, 700 0x245c, 0xffffffff, 0x00090008, 701 0x245d, 0xffffffff, 0x00020001, 702 0x245e, 0xffffffff, 0x00040003, 703 0x245f, 0xffffffff, 0x00000007, 704 0x2460, 0xffffffff, 0x00060005, 705 0x2461, 0xffffffff, 0x00090008, 706 0x2462, 0xffffffff, 0x00030002, 707 0x2463, 0xffffffff, 0x00050004, 708 0x2464, 0xffffffff, 0x00000008, 709 0x2465, 0xffffffff, 0x00070006, 710 0x2466, 0xffffffff, 0x000a0009, 711 0x2467, 0xffffffff, 0x00040003, 712 0x2468, 0xffffffff, 0x00060005, 713 0x2469, 0xffffffff, 0x00000009, 714 0x246a, 0xffffffff, 0x00080007, 715 0x246b, 0xffffffff, 0x000b000a, 716 0x246c, 0xffffffff, 0x00050004, 717 0x246d, 0xffffffff, 0x00070006, 718 0x246e, 0xffffffff, 0x0008000b, 719 0x246f, 0xffffffff, 0x000a0009, 720 0x2470, 0xffffffff, 0x000d000c, 721 0x2480, 0xffffffff, 0x00090008, 722 0x2481, 0xffffffff, 0x000b000a, 723 0x2482, 0xffffffff, 0x000c000f, 724 0x2483, 0xffffffff, 0x000e000d, 725 0x2484, 0xffffffff, 0x00110010, 726 0x2485, 0xffffffff, 0x000a0009, 727 0x2486, 0xffffffff, 0x000c000b, 728 0x2487, 0xffffffff, 0x0000000f, 729 0x2488, 0xffffffff, 0x000e000d, 730 0x2489, 0xffffffff, 0x00110010, 731 0x248a, 0xffffffff, 0x000b000a, 732 0x248b, 0xffffffff, 0x000d000c, 733 0x248c, 0xffffffff, 0x00000010, 734 0x248d, 0xffffffff, 0x000f000e, 735 0x248e, 0xffffffff, 0x00120011, 736 0x248f, 0xffffffff, 0x000c000b, 737 0x2490, 0xffffffff, 0x000e000d, 738 0x2491, 0xffffffff, 0x00000011, 739 0x2492, 0xffffffff, 0x0010000f, 740 0x2493, 0xffffffff, 0x00130012, 741 0x2494, 0xffffffff, 0x000d000c, 742 0x2495, 0xffffffff, 0x000f000e, 743 0x2496, 0xffffffff, 0x00100013, 744 0x2497, 0xffffffff, 0x00120011, 745 0x2498, 0xffffffff, 0x00150014, 746 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 747 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 748 mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080, 749 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 750 0x000c, 0xffffffff, 0x0000001c, 751 0x000d, 0x000f0000, 0x000f0000, 752 0x0583, 0xffffffff, 0x00000100, 753 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 754 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 755 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104, 756 mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000, 757 mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000, 758 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 759 0x157a, 0x00000001, 0x00000001, 760 mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001, 761 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 762 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 763 0x3430, 0xfffffff0, 0x00000100, 764 0x3630, 0xfffffff0, 0x00000100, 765 }; 766 767 static const u32 oland_mgcg_cgcg_init[] = 768 { 769 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc, 770 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 771 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 772 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 773 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 774 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 775 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 776 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 777 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 778 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 779 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 780 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 781 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 782 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 783 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 784 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 785 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 786 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 787 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 788 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 789 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 790 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 791 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 792 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 793 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 794 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 795 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 796 0x2458, 0xffffffff, 0x00010000, 797 0x2459, 0xffffffff, 0x00030002, 798 0x245a, 0xffffffff, 0x00040007, 799 0x245b, 0xffffffff, 0x00060005, 800 0x245c, 0xffffffff, 0x00090008, 801 0x245d, 0xffffffff, 0x00020001, 802 0x245e, 0xffffffff, 0x00040003, 803 0x245f, 0xffffffff, 0x00000007, 804 0x2460, 0xffffffff, 0x00060005, 805 0x2461, 0xffffffff, 0x00090008, 806 0x2462, 0xffffffff, 0x00030002, 807 0x2463, 0xffffffff, 0x00050004, 808 0x2464, 0xffffffff, 0x00000008, 809 0x2465, 0xffffffff, 0x00070006, 810 0x2466, 0xffffffff, 0x000a0009, 811 0x2467, 0xffffffff, 0x00040003, 812 0x2468, 0xffffffff, 0x00060005, 813 0x2469, 0xffffffff, 0x00000009, 814 0x246a, 0xffffffff, 0x00080007, 815 0x246b, 0xffffffff, 0x000b000a, 816 0x246c, 0xffffffff, 0x00050004, 817 0x246d, 0xffffffff, 0x00070006, 818 0x246e, 0xffffffff, 0x0008000b, 819 0x246f, 0xffffffff, 0x000a0009, 820 0x2470, 0xffffffff, 0x000d000c, 821 0x2471, 0xffffffff, 0x00060005, 822 0x2472, 0xffffffff, 0x00080007, 823 0x2473, 0xffffffff, 0x0000000b, 824 0x2474, 0xffffffff, 0x000a0009, 825 0x2475, 0xffffffff, 0x000d000c, 826 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 827 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 828 mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080, 829 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 830 0x000c, 0xffffffff, 0x0000001c, 831 0x000d, 0x000f0000, 0x000f0000, 832 0x0583, 0xffffffff, 0x00000100, 833 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 834 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 835 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104, 836 mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000, 837 mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000, 838 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 839 0x157a, 0x00000001, 0x00000001, 840 mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001, 841 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 842 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 843 0x3430, 0xfffffff0, 0x00000100, 844 0x3630, 0xfffffff0, 0x00000100, 845 }; 846 847 static const u32 hainan_mgcg_cgcg_init[] = 848 { 849 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc, 850 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 851 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 852 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 853 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 854 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 855 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 856 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 857 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 858 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 859 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 860 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 861 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 862 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 863 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 864 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 865 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 866 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 867 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 868 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 869 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 870 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 871 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 872 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 873 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 874 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 875 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 876 0x2458, 0xffffffff, 0x00010000, 877 0x2459, 0xffffffff, 0x00030002, 878 0x245a, 0xffffffff, 0x00040007, 879 0x245b, 0xffffffff, 0x00060005, 880 0x245c, 0xffffffff, 0x00090008, 881 0x245d, 0xffffffff, 0x00020001, 882 0x245e, 0xffffffff, 0x00040003, 883 0x245f, 0xffffffff, 0x00000007, 884 0x2460, 0xffffffff, 0x00060005, 885 0x2461, 0xffffffff, 0x00090008, 886 0x2462, 0xffffffff, 0x00030002, 887 0x2463, 0xffffffff, 0x00050004, 888 0x2464, 0xffffffff, 0x00000008, 889 0x2465, 0xffffffff, 0x00070006, 890 0x2466, 0xffffffff, 0x000a0009, 891 0x2467, 0xffffffff, 0x00040003, 892 0x2468, 0xffffffff, 0x00060005, 893 0x2469, 0xffffffff, 0x00000009, 894 0x246a, 0xffffffff, 0x00080007, 895 0x246b, 0xffffffff, 0x000b000a, 896 0x246c, 0xffffffff, 0x00050004, 897 0x246d, 0xffffffff, 0x00070006, 898 0x246e, 0xffffffff, 0x0008000b, 899 0x246f, 0xffffffff, 0x000a0009, 900 0x2470, 0xffffffff, 0x000d000c, 901 0x2471, 0xffffffff, 0x00060005, 902 0x2472, 0xffffffff, 0x00080007, 903 0x2473, 0xffffffff, 0x0000000b, 904 0x2474, 0xffffffff, 0x000a0009, 905 0x2475, 0xffffffff, 0x000d000c, 906 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 907 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 908 mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080, 909 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 910 0x000c, 0xffffffff, 0x0000001c, 911 0x000d, 0x000f0000, 0x000f0000, 912 0x0583, 0xffffffff, 0x00000100, 913 0x0409, 0xffffffff, 0x00000100, 914 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104, 915 mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000, 916 mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000, 917 mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001, 918 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 919 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 920 0x3430, 0xfffffff0, 0x00000100, 921 0x3630, 0xfffffff0, 0x00000100, 922 }; 923 924 /* XXX: update when we support VCE */ 925 #if 0 926 /* tahiti, pitcairn, verde */ 927 static const struct amdgpu_video_codec_info tahiti_video_codecs_encode_array[] = 928 { 929 { 930 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 931 .max_width = 2048, 932 .max_height = 1152, 933 .max_pixels_per_frame = 2048 * 1152, 934 .max_level = 0, 935 }, 936 }; 937 938 static const struct amdgpu_video_codecs tahiti_video_codecs_encode = 939 { 940 .codec_count = ARRAY_SIZE(tahiti_video_codecs_encode_array), 941 .codec_array = tahiti_video_codecs_encode_array, 942 }; 943 #else 944 static const struct amdgpu_video_codecs tahiti_video_codecs_encode = 945 { 946 .codec_count = 0, 947 .codec_array = NULL, 948 }; 949 #endif 950 /* oland and hainan don't support encode */ 951 static const struct amdgpu_video_codecs hainan_video_codecs_encode = 952 { 953 .codec_count = 0, 954 .codec_array = NULL, 955 }; 956 957 /* tahiti, pitcairn, verde, oland */ 958 static const struct amdgpu_video_codec_info tahiti_video_codecs_decode_array[] = 959 { 960 { 961 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 962 .max_width = 2048, 963 .max_height = 1152, 964 .max_pixels_per_frame = 2048 * 1152, 965 .max_level = 3, 966 }, 967 { 968 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 969 .max_width = 2048, 970 .max_height = 1152, 971 .max_pixels_per_frame = 2048 * 1152, 972 .max_level = 5, 973 }, 974 { 975 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 976 .max_width = 2048, 977 .max_height = 1152, 978 .max_pixels_per_frame = 2048 * 1152, 979 .max_level = 41, 980 }, 981 { 982 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 983 .max_width = 2048, 984 .max_height = 1152, 985 .max_pixels_per_frame = 2048 * 1152, 986 .max_level = 4, 987 }, 988 }; 989 990 static const struct amdgpu_video_codecs tahiti_video_codecs_decode = 991 { 992 .codec_count = ARRAY_SIZE(tahiti_video_codecs_decode_array), 993 .codec_array = tahiti_video_codecs_decode_array, 994 }; 995 996 /* hainan doesn't support decode */ 997 static const struct amdgpu_video_codecs hainan_video_codecs_decode = 998 { 999 .codec_count = 0, 1000 .codec_array = NULL, 1001 }; 1002 1003 static int si_query_video_codecs(struct amdgpu_device *adev, bool encode, 1004 const struct amdgpu_video_codecs **codecs) 1005 { 1006 switch (adev->asic_type) { 1007 case CHIP_VERDE: 1008 case CHIP_TAHITI: 1009 case CHIP_PITCAIRN: 1010 if (encode) 1011 *codecs = &tahiti_video_codecs_encode; 1012 else 1013 *codecs = &tahiti_video_codecs_decode; 1014 return 0; 1015 case CHIP_OLAND: 1016 if (encode) 1017 *codecs = &hainan_video_codecs_encode; 1018 else 1019 *codecs = &tahiti_video_codecs_decode; 1020 return 0; 1021 case CHIP_HAINAN: 1022 if (encode) 1023 *codecs = &hainan_video_codecs_encode; 1024 else 1025 *codecs = &hainan_video_codecs_decode; 1026 return 0; 1027 default: 1028 return -EINVAL; 1029 } 1030 } 1031 1032 static u32 si_pcie_rreg(struct amdgpu_device *adev, u32 reg) 1033 { 1034 unsigned long flags; 1035 u32 r; 1036 1037 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 1038 WREG32(AMDGPU_PCIE_INDEX, reg); 1039 (void)RREG32(AMDGPU_PCIE_INDEX); 1040 r = RREG32(AMDGPU_PCIE_DATA); 1041 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 1042 return r; 1043 } 1044 1045 static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 1046 { 1047 unsigned long flags; 1048 1049 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 1050 WREG32(AMDGPU_PCIE_INDEX, reg); 1051 (void)RREG32(AMDGPU_PCIE_INDEX); 1052 WREG32(AMDGPU_PCIE_DATA, v); 1053 (void)RREG32(AMDGPU_PCIE_DATA); 1054 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 1055 } 1056 1057 static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg) 1058 { 1059 unsigned long flags; 1060 u32 r; 1061 1062 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 1063 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 1064 (void)RREG32(PCIE_PORT_INDEX); 1065 r = RREG32(PCIE_PORT_DATA); 1066 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 1067 return r; 1068 } 1069 1070 static void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 1071 { 1072 unsigned long flags; 1073 1074 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 1075 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 1076 (void)RREG32(PCIE_PORT_INDEX); 1077 WREG32(PCIE_PORT_DATA, (v)); 1078 (void)RREG32(PCIE_PORT_DATA); 1079 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 1080 } 1081 1082 static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg) 1083 { 1084 unsigned long flags; 1085 u32 r; 1086 1087 spin_lock_irqsave(&adev->smc_idx_lock, flags); 1088 WREG32(SMC_IND_INDEX_0, (reg)); 1089 r = RREG32(SMC_IND_DATA_0); 1090 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 1091 return r; 1092 } 1093 1094 static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 1095 { 1096 unsigned long flags; 1097 1098 spin_lock_irqsave(&adev->smc_idx_lock, flags); 1099 WREG32(SMC_IND_INDEX_0, (reg)); 1100 WREG32(SMC_IND_DATA_0, (v)); 1101 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 1102 } 1103 1104 static u32 si_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 1105 { 1106 unsigned long flags; 1107 u32 r; 1108 1109 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 1110 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 1111 r = RREG32(mmUVD_CTX_DATA); 1112 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 1113 return r; 1114 } 1115 1116 static void si_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 1117 { 1118 unsigned long flags; 1119 1120 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 1121 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 1122 WREG32(mmUVD_CTX_DATA, (v)); 1123 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 1124 } 1125 1126 static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = { 1127 {GRBM_STATUS}, 1128 {mmGRBM_STATUS2}, 1129 {mmGRBM_STATUS_SE0}, 1130 {mmGRBM_STATUS_SE1}, 1131 {mmSRBM_STATUS}, 1132 {mmSRBM_STATUS2}, 1133 {mmDMA_STATUS_REG + DMA0_REGISTER_OFFSET}, 1134 {mmDMA_STATUS_REG + DMA1_REGISTER_OFFSET}, 1135 {mmCP_STAT}, 1136 {mmCP_STALLED_STAT1}, 1137 {mmCP_STALLED_STAT2}, 1138 {mmCP_STALLED_STAT3}, 1139 {GB_ADDR_CONFIG}, 1140 {MC_ARB_RAMCFG}, 1141 {mmGB_TILE_MODE0}, 1142 {mmGB_TILE_MODE1}, 1143 {mmGB_TILE_MODE2}, 1144 {mmGB_TILE_MODE3}, 1145 {mmGB_TILE_MODE4}, 1146 {mmGB_TILE_MODE5}, 1147 {mmGB_TILE_MODE6}, 1148 {mmGB_TILE_MODE7}, 1149 {mmGB_TILE_MODE8}, 1150 {mmGB_TILE_MODE9}, 1151 {mmGB_TILE_MODE10}, 1152 {mmGB_TILE_MODE11}, 1153 {mmGB_TILE_MODE12}, 1154 {mmGB_TILE_MODE13}, 1155 {mmGB_TILE_MODE14}, 1156 {mmGB_TILE_MODE15}, 1157 {mmGB_TILE_MODE16}, 1158 {mmGB_TILE_MODE17}, 1159 {mmGB_TILE_MODE18}, 1160 {mmGB_TILE_MODE19}, 1161 {mmGB_TILE_MODE20}, 1162 {mmGB_TILE_MODE21}, 1163 {mmGB_TILE_MODE22}, 1164 {mmGB_TILE_MODE23}, 1165 {mmGB_TILE_MODE24}, 1166 {mmGB_TILE_MODE25}, 1167 {mmGB_TILE_MODE26}, 1168 {mmGB_TILE_MODE27}, 1169 {mmGB_TILE_MODE28}, 1170 {mmGB_TILE_MODE29}, 1171 {mmGB_TILE_MODE30}, 1172 {mmGB_TILE_MODE31}, 1173 {CC_RB_BACKEND_DISABLE, true}, 1174 {mmGC_USER_RB_BACKEND_DISABLE, true}, 1175 {mmPA_SC_RASTER_CONFIG, true}, 1176 }; 1177 1178 static uint32_t si_get_register_value(struct amdgpu_device *adev, 1179 bool indexed, u32 se_num, 1180 u32 sh_num, u32 reg_offset) 1181 { 1182 if (indexed) { 1183 uint32_t val; 1184 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num; 1185 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; 1186 1187 switch (reg_offset) { 1188 case mmCC_RB_BACKEND_DISABLE: 1189 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable; 1190 case mmGC_USER_RB_BACKEND_DISABLE: 1191 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable; 1192 case mmPA_SC_RASTER_CONFIG: 1193 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config; 1194 } 1195 1196 mutex_lock(&adev->grbm_idx_mutex); 1197 if (se_num != 0xffffffff || sh_num != 0xffffffff) 1198 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); 1199 1200 val = RREG32(reg_offset); 1201 1202 if (se_num != 0xffffffff || sh_num != 0xffffffff) 1203 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1204 mutex_unlock(&adev->grbm_idx_mutex); 1205 return val; 1206 } else { 1207 unsigned idx; 1208 1209 switch (reg_offset) { 1210 case mmGB_ADDR_CONFIG: 1211 return adev->gfx.config.gb_addr_config; 1212 case mmMC_ARB_RAMCFG: 1213 return adev->gfx.config.mc_arb_ramcfg; 1214 case mmGB_TILE_MODE0: 1215 case mmGB_TILE_MODE1: 1216 case mmGB_TILE_MODE2: 1217 case mmGB_TILE_MODE3: 1218 case mmGB_TILE_MODE4: 1219 case mmGB_TILE_MODE5: 1220 case mmGB_TILE_MODE6: 1221 case mmGB_TILE_MODE7: 1222 case mmGB_TILE_MODE8: 1223 case mmGB_TILE_MODE9: 1224 case mmGB_TILE_MODE10: 1225 case mmGB_TILE_MODE11: 1226 case mmGB_TILE_MODE12: 1227 case mmGB_TILE_MODE13: 1228 case mmGB_TILE_MODE14: 1229 case mmGB_TILE_MODE15: 1230 case mmGB_TILE_MODE16: 1231 case mmGB_TILE_MODE17: 1232 case mmGB_TILE_MODE18: 1233 case mmGB_TILE_MODE19: 1234 case mmGB_TILE_MODE20: 1235 case mmGB_TILE_MODE21: 1236 case mmGB_TILE_MODE22: 1237 case mmGB_TILE_MODE23: 1238 case mmGB_TILE_MODE24: 1239 case mmGB_TILE_MODE25: 1240 case mmGB_TILE_MODE26: 1241 case mmGB_TILE_MODE27: 1242 case mmGB_TILE_MODE28: 1243 case mmGB_TILE_MODE29: 1244 case mmGB_TILE_MODE30: 1245 case mmGB_TILE_MODE31: 1246 idx = (reg_offset - mmGB_TILE_MODE0); 1247 return adev->gfx.config.tile_mode_array[idx]; 1248 default: 1249 return RREG32(reg_offset); 1250 } 1251 } 1252 } 1253 static int si_read_register(struct amdgpu_device *adev, u32 se_num, 1254 u32 sh_num, u32 reg_offset, u32 *value) 1255 { 1256 uint32_t i; 1257 1258 *value = 0; 1259 for (i = 0; i < ARRAY_SIZE(si_allowed_read_registers); i++) { 1260 bool indexed = si_allowed_read_registers[i].grbm_indexed; 1261 1262 if (reg_offset != si_allowed_read_registers[i].reg_offset) 1263 continue; 1264 1265 *value = si_get_register_value(adev, indexed, se_num, sh_num, 1266 reg_offset); 1267 return 0; 1268 } 1269 return -EINVAL; 1270 } 1271 1272 static bool si_read_disabled_bios(struct amdgpu_device *adev) 1273 { 1274 u32 bus_cntl; 1275 u32 d1vga_control = 0; 1276 u32 d2vga_control = 0; 1277 u32 vga_render_control = 0; 1278 u32 rom_cntl; 1279 bool r; 1280 1281 bus_cntl = RREG32(R600_BUS_CNTL); 1282 if (adev->mode_info.num_crtc) { 1283 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 1284 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 1285 vga_render_control = RREG32(VGA_RENDER_CONTROL); 1286 } 1287 rom_cntl = RREG32(R600_ROM_CNTL); 1288 1289 /* enable the rom */ 1290 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 1291 if (adev->mode_info.num_crtc) { 1292 /* Disable VGA mode */ 1293 WREG32(AVIVO_D1VGA_CONTROL, 1294 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 1295 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 1296 WREG32(AVIVO_D2VGA_CONTROL, 1297 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 1298 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 1299 WREG32(VGA_RENDER_CONTROL, 1300 (vga_render_control & C_000300_VGA_VSTATUS_CNTL)); 1301 } 1302 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 1303 1304 r = amdgpu_read_bios(adev); 1305 1306 /* restore regs */ 1307 WREG32(R600_BUS_CNTL, bus_cntl); 1308 if (adev->mode_info.num_crtc) { 1309 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 1310 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 1311 WREG32(VGA_RENDER_CONTROL, vga_render_control); 1312 } 1313 WREG32(R600_ROM_CNTL, rom_cntl); 1314 return r; 1315 } 1316 1317 #define mmROM_INDEX 0x2A 1318 #define mmROM_DATA 0x2B 1319 1320 static bool si_read_bios_from_rom(struct amdgpu_device *adev, 1321 u8 *bios, u32 length_bytes) 1322 { 1323 u32 *dw_ptr; 1324 u32 i, length_dw; 1325 1326 if (bios == NULL) 1327 return false; 1328 if (length_bytes == 0) 1329 return false; 1330 /* APU vbios image is part of sbios image */ 1331 if (adev->flags & AMD_IS_APU) 1332 return false; 1333 1334 dw_ptr = (u32 *)bios; 1335 length_dw = ALIGN(length_bytes, 4) / 4; 1336 /* set rom index to 0 */ 1337 WREG32(mmROM_INDEX, 0); 1338 for (i = 0; i < length_dw; i++) 1339 dw_ptr[i] = RREG32(mmROM_DATA); 1340 1341 return true; 1342 } 1343 1344 static void si_set_clk_bypass_mode(struct amdgpu_device *adev) 1345 { 1346 u32 tmp, i; 1347 1348 tmp = RREG32(CG_SPLL_FUNC_CNTL); 1349 tmp |= SPLL_BYPASS_EN; 1350 WREG32(CG_SPLL_FUNC_CNTL, tmp); 1351 1352 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); 1353 tmp |= SPLL_CTLREQ_CHG; 1354 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); 1355 1356 for (i = 0; i < adev->usec_timeout; i++) { 1357 if (RREG32(SPLL_STATUS) & SPLL_CHG_STATUS) 1358 break; 1359 udelay(1); 1360 } 1361 1362 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); 1363 tmp &= ~(SPLL_CTLREQ_CHG | SCLK_MUX_UPDATE); 1364 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); 1365 1366 tmp = RREG32(MPLL_CNTL_MODE); 1367 tmp &= ~MPLL_MCLK_SEL; 1368 WREG32(MPLL_CNTL_MODE, tmp); 1369 } 1370 1371 static void si_spll_powerdown(struct amdgpu_device *adev) 1372 { 1373 u32 tmp; 1374 1375 tmp = RREG32(SPLL_CNTL_MODE); 1376 tmp |= SPLL_SW_DIR_CONTROL; 1377 WREG32(SPLL_CNTL_MODE, tmp); 1378 1379 tmp = RREG32(CG_SPLL_FUNC_CNTL); 1380 tmp |= SPLL_RESET; 1381 WREG32(CG_SPLL_FUNC_CNTL, tmp); 1382 1383 tmp = RREG32(CG_SPLL_FUNC_CNTL); 1384 tmp |= SPLL_SLEEP; 1385 WREG32(CG_SPLL_FUNC_CNTL, tmp); 1386 1387 tmp = RREG32(SPLL_CNTL_MODE); 1388 tmp &= ~SPLL_SW_DIR_CONTROL; 1389 WREG32(SPLL_CNTL_MODE, tmp); 1390 } 1391 1392 static int si_gpu_pci_config_reset(struct amdgpu_device *adev) 1393 { 1394 u32 i; 1395 int r = -EINVAL; 1396 1397 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 1398 1399 /* set mclk/sclk to bypass */ 1400 si_set_clk_bypass_mode(adev); 1401 /* powerdown spll */ 1402 si_spll_powerdown(adev); 1403 /* disable BM */ 1404 pci_clear_master(adev->pdev); 1405 /* reset */ 1406 amdgpu_device_pci_config_reset(adev); 1407 1408 udelay(100); 1409 1410 /* wait for asic to come out of reset */ 1411 for (i = 0; i < adev->usec_timeout; i++) { 1412 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) { 1413 /* enable BM */ 1414 pci_set_master(adev->pdev); 1415 adev->has_hw_reset = true; 1416 r = 0; 1417 break; 1418 } 1419 udelay(1); 1420 } 1421 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 1422 1423 return r; 1424 } 1425 1426 static int si_asic_supports_baco(struct amdgpu_device *adev) 1427 { 1428 return 0; 1429 } 1430 1431 static enum amd_reset_method 1432 si_asic_reset_method(struct amdgpu_device *adev) 1433 { 1434 if (amdgpu_reset_method == AMD_RESET_METHOD_PCI) 1435 return amdgpu_reset_method; 1436 else if (amdgpu_reset_method != AMD_RESET_METHOD_LEGACY && 1437 amdgpu_reset_method != -1) 1438 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 1439 amdgpu_reset_method); 1440 1441 return AMD_RESET_METHOD_LEGACY; 1442 } 1443 1444 static int si_asic_reset(struct amdgpu_device *adev) 1445 { 1446 int r; 1447 1448 switch (si_asic_reset_method(adev)) { 1449 case AMD_RESET_METHOD_PCI: 1450 dev_info(adev->dev, "PCI reset\n"); 1451 r = amdgpu_device_pci_reset(adev); 1452 break; 1453 default: 1454 dev_info(adev->dev, "PCI CONFIG reset\n"); 1455 r = si_gpu_pci_config_reset(adev); 1456 break; 1457 } 1458 1459 return r; 1460 } 1461 1462 static u32 si_get_config_memsize(struct amdgpu_device *adev) 1463 { 1464 return RREG32(mmCONFIG_MEMSIZE); 1465 } 1466 1467 static void si_vga_set_state(struct amdgpu_device *adev, bool state) 1468 { 1469 uint32_t temp; 1470 1471 temp = RREG32(CONFIG_CNTL); 1472 if (!state) { 1473 temp &= ~(1<<0); 1474 temp |= (1<<1); 1475 } else { 1476 temp &= ~(1<<1); 1477 } 1478 WREG32(CONFIG_CNTL, temp); 1479 } 1480 1481 static u32 si_get_xclk(struct amdgpu_device *adev) 1482 { 1483 u32 reference_clock = adev->clock.spll.reference_freq; 1484 u32 tmp; 1485 1486 tmp = RREG32(CG_CLKPIN_CNTL_2); 1487 if (tmp & MUX_TCLK_TO_XCLK) 1488 return TCLK; 1489 1490 tmp = RREG32(CG_CLKPIN_CNTL); 1491 if (tmp & XTALIN_DIVIDE) 1492 return reference_clock / 4; 1493 1494 return reference_clock; 1495 } 1496 1497 static void si_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 1498 { 1499 if (!ring || !ring->funcs->emit_wreg) { 1500 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); 1501 RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL); 1502 } else { 1503 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); 1504 } 1505 } 1506 1507 static void si_invalidate_hdp(struct amdgpu_device *adev, 1508 struct amdgpu_ring *ring) 1509 { 1510 if (!ring || !ring->funcs->emit_wreg) { 1511 WREG32(mmHDP_DEBUG0, 1); 1512 RREG32(mmHDP_DEBUG0); 1513 } else { 1514 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1); 1515 } 1516 } 1517 1518 static bool si_need_full_reset(struct amdgpu_device *adev) 1519 { 1520 /* change this when we support soft reset */ 1521 return true; 1522 } 1523 1524 static bool si_need_reset_on_init(struct amdgpu_device *adev) 1525 { 1526 return false; 1527 } 1528 1529 static int si_get_pcie_lanes(struct amdgpu_device *adev) 1530 { 1531 u32 link_width_cntl; 1532 1533 if (adev->flags & AMD_IS_APU) 1534 return 0; 1535 1536 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 1537 1538 switch ((link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT) { 1539 case LC_LINK_WIDTH_X1: 1540 return 1; 1541 case LC_LINK_WIDTH_X2: 1542 return 2; 1543 case LC_LINK_WIDTH_X4: 1544 return 4; 1545 case LC_LINK_WIDTH_X8: 1546 return 8; 1547 case LC_LINK_WIDTH_X0: 1548 case LC_LINK_WIDTH_X16: 1549 default: 1550 return 16; 1551 } 1552 } 1553 1554 static void si_set_pcie_lanes(struct amdgpu_device *adev, int lanes) 1555 { 1556 u32 link_width_cntl, mask; 1557 1558 if (adev->flags & AMD_IS_APU) 1559 return; 1560 1561 switch (lanes) { 1562 case 0: 1563 mask = LC_LINK_WIDTH_X0; 1564 break; 1565 case 1: 1566 mask = LC_LINK_WIDTH_X1; 1567 break; 1568 case 2: 1569 mask = LC_LINK_WIDTH_X2; 1570 break; 1571 case 4: 1572 mask = LC_LINK_WIDTH_X4; 1573 break; 1574 case 8: 1575 mask = LC_LINK_WIDTH_X8; 1576 break; 1577 case 16: 1578 mask = LC_LINK_WIDTH_X16; 1579 break; 1580 default: 1581 DRM_ERROR("invalid pcie lane request: %d\n", lanes); 1582 return; 1583 } 1584 1585 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 1586 link_width_cntl &= ~LC_LINK_WIDTH_MASK; 1587 link_width_cntl |= mask << LC_LINK_WIDTH_SHIFT; 1588 link_width_cntl |= (LC_RECONFIG_NOW | 1589 LC_RECONFIG_ARC_MISSING_ESCAPE); 1590 1591 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 1592 } 1593 1594 static void si_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 1595 uint64_t *count1) 1596 { 1597 uint32_t perfctr = 0; 1598 uint64_t cnt0_of, cnt1_of; 1599 int tmp; 1600 1601 /* This reports 0 on APUs, so return to avoid writing/reading registers 1602 * that may or may not be different from their GPU counterparts 1603 */ 1604 if (adev->flags & AMD_IS_APU) 1605 return; 1606 1607 /* Set the 2 events that we wish to watch, defined above */ 1608 /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */ 1609 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); 1610 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); 1611 1612 /* Write to enable desired perf counters */ 1613 WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr); 1614 /* Zero out and enable the perf counters 1615 * Write 0x5: 1616 * Bit 0 = Start all counters(1) 1617 * Bit 2 = Global counter reset enable(1) 1618 */ 1619 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005); 1620 1621 msleep(1000); 1622 1623 /* Load the shadow and disable the perf counters 1624 * Write 0x2: 1625 * Bit 0 = Stop counters(0) 1626 * Bit 1 = Load the shadow counters(1) 1627 */ 1628 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002); 1629 1630 /* Read register values to get any >32bit overflow */ 1631 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK); 1632 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); 1633 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); 1634 1635 /* Get the values and add the overflow */ 1636 *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); 1637 *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); 1638 } 1639 1640 static uint64_t si_get_pcie_replay_count(struct amdgpu_device *adev) 1641 { 1642 uint64_t nak_r, nak_g; 1643 1644 /* Get the number of NAKs received and generated */ 1645 nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK); 1646 nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED); 1647 1648 /* Add the total number of NAKs, i.e the number of replays */ 1649 return (nak_r + nak_g); 1650 } 1651 1652 static int si_uvd_send_upll_ctlreq(struct amdgpu_device *adev, 1653 unsigned cg_upll_func_cntl) 1654 { 1655 unsigned i; 1656 1657 /* Make sure UPLL_CTLREQ is deasserted */ 1658 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); 1659 1660 mdelay(10); 1661 1662 /* Assert UPLL_CTLREQ */ 1663 WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); 1664 1665 /* Wait for CTLACK and CTLACK2 to get asserted */ 1666 for (i = 0; i < SI_MAX_CTLACKS_ASSERTION_WAIT; ++i) { 1667 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; 1668 1669 if ((RREG32(cg_upll_func_cntl) & mask) == mask) 1670 break; 1671 mdelay(10); 1672 } 1673 1674 /* Deassert UPLL_CTLREQ */ 1675 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); 1676 1677 if (i == SI_MAX_CTLACKS_ASSERTION_WAIT) { 1678 DRM_ERROR("Timeout setting UVD clocks!\n"); 1679 return -ETIMEDOUT; 1680 } 1681 1682 return 0; 1683 } 1684 1685 static unsigned si_uvd_calc_upll_post_div(unsigned vco_freq, 1686 unsigned target_freq, 1687 unsigned pd_min, 1688 unsigned pd_even) 1689 { 1690 unsigned post_div = vco_freq / target_freq; 1691 1692 /* Adjust to post divider minimum value */ 1693 if (post_div < pd_min) 1694 post_div = pd_min; 1695 1696 /* We alway need a frequency less than or equal the target */ 1697 if ((vco_freq / post_div) > target_freq) 1698 post_div += 1; 1699 1700 /* Post dividers above a certain value must be even */ 1701 if (post_div > pd_even && post_div % 2) 1702 post_div += 1; 1703 1704 return post_div; 1705 } 1706 1707 /** 1708 * si_calc_upll_dividers - calc UPLL clock dividers 1709 * 1710 * @adev: amdgpu_device pointer 1711 * @vclk: wanted VCLK 1712 * @dclk: wanted DCLK 1713 * @vco_min: minimum VCO frequency 1714 * @vco_max: maximum VCO frequency 1715 * @fb_factor: factor to multiply vco freq with 1716 * @fb_mask: limit and bitmask for feedback divider 1717 * @pd_min: post divider minimum 1718 * @pd_max: post divider maximum 1719 * @pd_even: post divider must be even above this value 1720 * @optimal_fb_div: resulting feedback divider 1721 * @optimal_vclk_div: resulting vclk post divider 1722 * @optimal_dclk_div: resulting dclk post divider 1723 * 1724 * Calculate dividers for UVDs UPLL (except APUs). 1725 * Returns zero on success; -EINVAL on error. 1726 */ 1727 static int si_calc_upll_dividers(struct amdgpu_device *adev, 1728 unsigned vclk, unsigned dclk, 1729 unsigned vco_min, unsigned vco_max, 1730 unsigned fb_factor, unsigned fb_mask, 1731 unsigned pd_min, unsigned pd_max, 1732 unsigned pd_even, 1733 unsigned *optimal_fb_div, 1734 unsigned *optimal_vclk_div, 1735 unsigned *optimal_dclk_div) 1736 { 1737 unsigned vco_freq, ref_freq = adev->clock.spll.reference_freq; 1738 1739 /* Start off with something large */ 1740 unsigned optimal_score = ~0; 1741 1742 /* Loop through vco from low to high */ 1743 vco_min = max(max(vco_min, vclk), dclk); 1744 for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) { 1745 uint64_t fb_div = (uint64_t)vco_freq * fb_factor; 1746 unsigned vclk_div, dclk_div, score; 1747 1748 do_div(fb_div, ref_freq); 1749 1750 /* fb div out of range ? */ 1751 if (fb_div > fb_mask) 1752 break; /* It can oly get worse */ 1753 1754 fb_div &= fb_mask; 1755 1756 /* Calc vclk divider with current vco freq */ 1757 vclk_div = si_uvd_calc_upll_post_div(vco_freq, vclk, 1758 pd_min, pd_even); 1759 if (vclk_div > pd_max) 1760 break; /* vco is too big, it has to stop */ 1761 1762 /* Calc dclk divider with current vco freq */ 1763 dclk_div = si_uvd_calc_upll_post_div(vco_freq, dclk, 1764 pd_min, pd_even); 1765 if (dclk_div > pd_max) 1766 break; /* vco is too big, it has to stop */ 1767 1768 /* Calc score with current vco freq */ 1769 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); 1770 1771 /* Determine if this vco setting is better than current optimal settings */ 1772 if (score < optimal_score) { 1773 *optimal_fb_div = fb_div; 1774 *optimal_vclk_div = vclk_div; 1775 *optimal_dclk_div = dclk_div; 1776 optimal_score = score; 1777 if (optimal_score == 0) 1778 break; /* It can't get better than this */ 1779 } 1780 } 1781 1782 /* Did we found a valid setup ? */ 1783 if (optimal_score == ~0) 1784 return -EINVAL; 1785 1786 return 0; 1787 } 1788 1789 static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 1790 { 1791 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; 1792 int r; 1793 1794 /* Bypass vclk and dclk with bclk */ 1795 WREG32_P(CG_UPLL_FUNC_CNTL_2, 1796 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1), 1797 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); 1798 1799 /* Put PLL in bypass mode */ 1800 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); 1801 1802 if (!vclk || !dclk) { 1803 /* Keep the Bypass mode */ 1804 return 0; 1805 } 1806 1807 r = si_calc_upll_dividers(adev, vclk, dclk, 125000, 250000, 1808 16384, 0x03FFFFFF, 0, 128, 5, 1809 &fb_div, &vclk_div, &dclk_div); 1810 if (r) 1811 return r; 1812 1813 /* Set RESET_ANTI_MUX to 0 */ 1814 WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK); 1815 1816 /* Set VCO_MODE to 1 */ 1817 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK); 1818 1819 /* Disable sleep mode */ 1820 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK); 1821 1822 /* Deassert UPLL_RESET */ 1823 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); 1824 1825 mdelay(1); 1826 1827 r = si_uvd_send_upll_ctlreq(adev, CG_UPLL_FUNC_CNTL); 1828 if (r) 1829 return r; 1830 1831 /* Assert UPLL_RESET again */ 1832 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); 1833 1834 /* Disable spread spectrum. */ 1835 WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK); 1836 1837 /* Set feedback divider */ 1838 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK); 1839 1840 /* Set ref divider to 0 */ 1841 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK); 1842 1843 if (fb_div < 307200) 1844 WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9); 1845 else 1846 WREG32_P(CG_UPLL_FUNC_CNTL_4, 1847 UPLL_SPARE_ISPARE9, 1848 ~UPLL_SPARE_ISPARE9); 1849 1850 /* Set PDIV_A and PDIV_B */ 1851 WREG32_P(CG_UPLL_FUNC_CNTL_2, 1852 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div), 1853 ~(UPLL_PDIV_A_MASK | UPLL_PDIV_B_MASK)); 1854 1855 /* Give the PLL some time to settle */ 1856 mdelay(15); 1857 1858 /* Deassert PLL_RESET */ 1859 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); 1860 1861 mdelay(15); 1862 1863 /* Switch from bypass mode to normal mode */ 1864 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); 1865 1866 r = si_uvd_send_upll_ctlreq(adev, CG_UPLL_FUNC_CNTL); 1867 if (r) 1868 return r; 1869 1870 /* Switch VCLK and DCLK selection */ 1871 WREG32_P(CG_UPLL_FUNC_CNTL_2, 1872 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2), 1873 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); 1874 1875 mdelay(100); 1876 1877 return 0; 1878 } 1879 1880 static int si_vce_send_vcepll_ctlreq(struct amdgpu_device *adev) 1881 { 1882 unsigned i; 1883 1884 /* Make sure VCEPLL_CTLREQ is deasserted */ 1885 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); 1886 1887 mdelay(10); 1888 1889 /* Assert UPLL_CTLREQ */ 1890 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); 1891 1892 /* Wait for CTLACK and CTLACK2 to get asserted */ 1893 for (i = 0; i < SI_MAX_CTLACKS_ASSERTION_WAIT; ++i) { 1894 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; 1895 1896 if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask) 1897 break; 1898 mdelay(10); 1899 } 1900 1901 /* Deassert UPLL_CTLREQ */ 1902 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); 1903 1904 if (i == SI_MAX_CTLACKS_ASSERTION_WAIT) { 1905 DRM_ERROR("Timeout setting VCE clocks!\n"); 1906 return -ETIMEDOUT; 1907 } 1908 1909 return 0; 1910 } 1911 1912 static int si_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 1913 { 1914 unsigned fb_div = 0, evclk_div = 0, ecclk_div = 0; 1915 int r; 1916 1917 /* Bypass evclk and ecclk with bclk */ 1918 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2, 1919 EVCLK_SRC_SEL(1) | ECCLK_SRC_SEL(1), 1920 ~(EVCLK_SRC_SEL_MASK | ECCLK_SRC_SEL_MASK)); 1921 1922 /* Put PLL in bypass mode */ 1923 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_BYPASS_EN_MASK, 1924 ~VCEPLL_BYPASS_EN_MASK); 1925 1926 if (!evclk || !ecclk) { 1927 /* Keep the Bypass mode, put PLL to sleep */ 1928 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK, 1929 ~VCEPLL_SLEEP_MASK); 1930 return 0; 1931 } 1932 1933 r = si_calc_upll_dividers(adev, evclk, ecclk, 125000, 250000, 1934 16384, 0x03FFFFFF, 0, 128, 5, 1935 &fb_div, &evclk_div, &ecclk_div); 1936 if (r) 1937 return r; 1938 1939 /* Set RESET_ANTI_MUX to 0 */ 1940 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK); 1941 1942 /* Set VCO_MODE to 1 */ 1943 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_VCO_MODE_MASK, 1944 ~VCEPLL_VCO_MODE_MASK); 1945 1946 /* Toggle VCEPLL_SLEEP to 1 then back to 0 */ 1947 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK, 1948 ~VCEPLL_SLEEP_MASK); 1949 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_SLEEP_MASK); 1950 1951 /* Deassert VCEPLL_RESET */ 1952 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK); 1953 1954 mdelay(1); 1955 1956 r = si_vce_send_vcepll_ctlreq(adev); 1957 if (r) 1958 return r; 1959 1960 /* Assert VCEPLL_RESET again */ 1961 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_RESET_MASK, ~VCEPLL_RESET_MASK); 1962 1963 /* Disable spread spectrum. */ 1964 WREG32_SMC_P(CG_VCEPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK); 1965 1966 /* Set feedback divider */ 1967 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_3, 1968 VCEPLL_FB_DIV(fb_div), 1969 ~VCEPLL_FB_DIV_MASK); 1970 1971 /* Set ref divider to 0 */ 1972 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_REF_DIV_MASK); 1973 1974 /* Set PDIV_A and PDIV_B */ 1975 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2, 1976 VCEPLL_PDIV_A(evclk_div) | VCEPLL_PDIV_B(ecclk_div), 1977 ~(VCEPLL_PDIV_A_MASK | VCEPLL_PDIV_B_MASK)); 1978 1979 /* Give the PLL some time to settle */ 1980 mdelay(15); 1981 1982 /* Deassert PLL_RESET */ 1983 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK); 1984 1985 mdelay(15); 1986 1987 /* Switch from bypass mode to normal mode */ 1988 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_BYPASS_EN_MASK); 1989 1990 r = si_vce_send_vcepll_ctlreq(adev); 1991 if (r) 1992 return r; 1993 1994 /* Switch VCLK and DCLK selection */ 1995 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2, 1996 EVCLK_SRC_SEL(16) | ECCLK_SRC_SEL(16), 1997 ~(EVCLK_SRC_SEL_MASK | ECCLK_SRC_SEL_MASK)); 1998 1999 mdelay(100); 2000 2001 return 0; 2002 } 2003 2004 static void si_pre_asic_init(struct amdgpu_device *adev) 2005 { 2006 } 2007 2008 static const struct amdgpu_asic_funcs si_asic_funcs = 2009 { 2010 .read_disabled_bios = &si_read_disabled_bios, 2011 .read_bios_from_rom = &si_read_bios_from_rom, 2012 .read_register = &si_read_register, 2013 .reset = &si_asic_reset, 2014 .reset_method = &si_asic_reset_method, 2015 .set_vga_state = &si_vga_set_state, 2016 .get_xclk = &si_get_xclk, 2017 .set_uvd_clocks = &si_set_uvd_clocks, 2018 .set_vce_clocks = &si_set_vce_clocks, 2019 .get_pcie_lanes = &si_get_pcie_lanes, 2020 .set_pcie_lanes = &si_set_pcie_lanes, 2021 .get_config_memsize = &si_get_config_memsize, 2022 .flush_hdp = &si_flush_hdp, 2023 .invalidate_hdp = &si_invalidate_hdp, 2024 .need_full_reset = &si_need_full_reset, 2025 .get_pcie_usage = &si_get_pcie_usage, 2026 .need_reset_on_init = &si_need_reset_on_init, 2027 .get_pcie_replay_count = &si_get_pcie_replay_count, 2028 .supports_baco = &si_asic_supports_baco, 2029 .pre_asic_init = &si_pre_asic_init, 2030 .query_video_codecs = &si_query_video_codecs, 2031 }; 2032 2033 static uint32_t si_get_rev_id(struct amdgpu_device *adev) 2034 { 2035 return (RREG32(CC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK) 2036 >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT; 2037 } 2038 2039 static int si_common_early_init(struct amdgpu_ip_block *ip_block) 2040 { 2041 struct amdgpu_device *adev = ip_block->adev; 2042 2043 adev->smc_rreg = &si_smc_rreg; 2044 adev->smc_wreg = &si_smc_wreg; 2045 adev->pcie_rreg = &si_pcie_rreg; 2046 adev->pcie_wreg = &si_pcie_wreg; 2047 adev->pciep_rreg = &si_pciep_rreg; 2048 adev->pciep_wreg = &si_pciep_wreg; 2049 adev->uvd_ctx_rreg = si_uvd_ctx_rreg; 2050 adev->uvd_ctx_wreg = si_uvd_ctx_wreg; 2051 adev->didt_rreg = NULL; 2052 adev->didt_wreg = NULL; 2053 2054 adev->asic_funcs = &si_asic_funcs; 2055 2056 adev->rev_id = si_get_rev_id(adev); 2057 adev->external_rev_id = 0xFF; 2058 switch (adev->asic_type) { 2059 case CHIP_TAHITI: 2060 adev->cg_flags = 2061 AMD_CG_SUPPORT_GFX_MGCG | 2062 AMD_CG_SUPPORT_GFX_MGLS | 2063 /*AMD_CG_SUPPORT_GFX_CGCG |*/ 2064 AMD_CG_SUPPORT_GFX_CGLS | 2065 AMD_CG_SUPPORT_GFX_CGTS | 2066 AMD_CG_SUPPORT_GFX_CP_LS | 2067 AMD_CG_SUPPORT_MC_MGCG | 2068 AMD_CG_SUPPORT_SDMA_MGCG | 2069 AMD_CG_SUPPORT_BIF_LS | 2070 AMD_CG_SUPPORT_VCE_MGCG | 2071 AMD_CG_SUPPORT_UVD_MGCG | 2072 AMD_CG_SUPPORT_HDP_LS | 2073 AMD_CG_SUPPORT_HDP_MGCG; 2074 adev->pg_flags = 0; 2075 adev->external_rev_id = (adev->rev_id == 0) ? 1 : 2076 (adev->rev_id == 1) ? 5 : 6; 2077 break; 2078 case CHIP_PITCAIRN: 2079 adev->cg_flags = 2080 AMD_CG_SUPPORT_GFX_MGCG | 2081 AMD_CG_SUPPORT_GFX_MGLS | 2082 /*AMD_CG_SUPPORT_GFX_CGCG |*/ 2083 AMD_CG_SUPPORT_GFX_CGLS | 2084 AMD_CG_SUPPORT_GFX_CGTS | 2085 AMD_CG_SUPPORT_GFX_CP_LS | 2086 AMD_CG_SUPPORT_GFX_RLC_LS | 2087 AMD_CG_SUPPORT_MC_LS | 2088 AMD_CG_SUPPORT_MC_MGCG | 2089 AMD_CG_SUPPORT_SDMA_MGCG | 2090 AMD_CG_SUPPORT_BIF_LS | 2091 AMD_CG_SUPPORT_VCE_MGCG | 2092 AMD_CG_SUPPORT_UVD_MGCG | 2093 AMD_CG_SUPPORT_HDP_LS | 2094 AMD_CG_SUPPORT_HDP_MGCG; 2095 adev->pg_flags = 0; 2096 adev->external_rev_id = adev->rev_id + 20; 2097 break; 2098 2099 case CHIP_VERDE: 2100 adev->cg_flags = 2101 AMD_CG_SUPPORT_GFX_MGCG | 2102 AMD_CG_SUPPORT_GFX_MGLS | 2103 AMD_CG_SUPPORT_GFX_CGLS | 2104 AMD_CG_SUPPORT_GFX_CGTS | 2105 AMD_CG_SUPPORT_GFX_CGTS_LS | 2106 AMD_CG_SUPPORT_GFX_CP_LS | 2107 AMD_CG_SUPPORT_MC_LS | 2108 AMD_CG_SUPPORT_MC_MGCG | 2109 AMD_CG_SUPPORT_SDMA_MGCG | 2110 AMD_CG_SUPPORT_SDMA_LS | 2111 AMD_CG_SUPPORT_BIF_LS | 2112 AMD_CG_SUPPORT_VCE_MGCG | 2113 AMD_CG_SUPPORT_UVD_MGCG | 2114 AMD_CG_SUPPORT_HDP_LS | 2115 AMD_CG_SUPPORT_HDP_MGCG; 2116 adev->pg_flags = 0; 2117 //??? 2118 adev->external_rev_id = adev->rev_id + 40; 2119 break; 2120 case CHIP_OLAND: 2121 adev->cg_flags = 2122 AMD_CG_SUPPORT_GFX_MGCG | 2123 AMD_CG_SUPPORT_GFX_MGLS | 2124 /*AMD_CG_SUPPORT_GFX_CGCG |*/ 2125 AMD_CG_SUPPORT_GFX_CGLS | 2126 AMD_CG_SUPPORT_GFX_CGTS | 2127 AMD_CG_SUPPORT_GFX_CP_LS | 2128 AMD_CG_SUPPORT_GFX_RLC_LS | 2129 AMD_CG_SUPPORT_MC_LS | 2130 AMD_CG_SUPPORT_MC_MGCG | 2131 AMD_CG_SUPPORT_SDMA_MGCG | 2132 AMD_CG_SUPPORT_BIF_LS | 2133 AMD_CG_SUPPORT_UVD_MGCG | 2134 AMD_CG_SUPPORT_HDP_LS | 2135 AMD_CG_SUPPORT_HDP_MGCG; 2136 adev->pg_flags = 0; 2137 adev->external_rev_id = 60; 2138 break; 2139 case CHIP_HAINAN: 2140 adev->cg_flags = 2141 AMD_CG_SUPPORT_GFX_MGCG | 2142 AMD_CG_SUPPORT_GFX_MGLS | 2143 /*AMD_CG_SUPPORT_GFX_CGCG |*/ 2144 AMD_CG_SUPPORT_GFX_CGLS | 2145 AMD_CG_SUPPORT_GFX_CGTS | 2146 AMD_CG_SUPPORT_GFX_CP_LS | 2147 AMD_CG_SUPPORT_GFX_RLC_LS | 2148 AMD_CG_SUPPORT_MC_LS | 2149 AMD_CG_SUPPORT_MC_MGCG | 2150 AMD_CG_SUPPORT_SDMA_MGCG | 2151 AMD_CG_SUPPORT_BIF_LS | 2152 AMD_CG_SUPPORT_HDP_LS | 2153 AMD_CG_SUPPORT_HDP_MGCG; 2154 adev->pg_flags = 0; 2155 adev->external_rev_id = 70; 2156 break; 2157 2158 default: 2159 return -EINVAL; 2160 } 2161 2162 return 0; 2163 } 2164 2165 static void si_init_golden_registers(struct amdgpu_device *adev) 2166 { 2167 switch (adev->asic_type) { 2168 case CHIP_TAHITI: 2169 amdgpu_device_program_register_sequence(adev, 2170 tahiti_golden_registers, 2171 ARRAY_SIZE(tahiti_golden_registers)); 2172 amdgpu_device_program_register_sequence(adev, 2173 tahiti_golden_rlc_registers, 2174 ARRAY_SIZE(tahiti_golden_rlc_registers)); 2175 amdgpu_device_program_register_sequence(adev, 2176 tahiti_mgcg_cgcg_init, 2177 ARRAY_SIZE(tahiti_mgcg_cgcg_init)); 2178 amdgpu_device_program_register_sequence(adev, 2179 tahiti_golden_registers2, 2180 ARRAY_SIZE(tahiti_golden_registers2)); 2181 break; 2182 case CHIP_PITCAIRN: 2183 amdgpu_device_program_register_sequence(adev, 2184 pitcairn_golden_registers, 2185 ARRAY_SIZE(pitcairn_golden_registers)); 2186 amdgpu_device_program_register_sequence(adev, 2187 pitcairn_golden_rlc_registers, 2188 ARRAY_SIZE(pitcairn_golden_rlc_registers)); 2189 amdgpu_device_program_register_sequence(adev, 2190 pitcairn_mgcg_cgcg_init, 2191 ARRAY_SIZE(pitcairn_mgcg_cgcg_init)); 2192 break; 2193 case CHIP_VERDE: 2194 amdgpu_device_program_register_sequence(adev, 2195 verde_golden_registers, 2196 ARRAY_SIZE(verde_golden_registers)); 2197 amdgpu_device_program_register_sequence(adev, 2198 verde_golden_rlc_registers, 2199 ARRAY_SIZE(verde_golden_rlc_registers)); 2200 amdgpu_device_program_register_sequence(adev, 2201 verde_mgcg_cgcg_init, 2202 ARRAY_SIZE(verde_mgcg_cgcg_init)); 2203 amdgpu_device_program_register_sequence(adev, 2204 verde_pg_init, 2205 ARRAY_SIZE(verde_pg_init)); 2206 break; 2207 case CHIP_OLAND: 2208 amdgpu_device_program_register_sequence(adev, 2209 oland_golden_registers, 2210 ARRAY_SIZE(oland_golden_registers)); 2211 amdgpu_device_program_register_sequence(adev, 2212 oland_golden_rlc_registers, 2213 ARRAY_SIZE(oland_golden_rlc_registers)); 2214 amdgpu_device_program_register_sequence(adev, 2215 oland_mgcg_cgcg_init, 2216 ARRAY_SIZE(oland_mgcg_cgcg_init)); 2217 break; 2218 case CHIP_HAINAN: 2219 amdgpu_device_program_register_sequence(adev, 2220 hainan_golden_registers, 2221 ARRAY_SIZE(hainan_golden_registers)); 2222 amdgpu_device_program_register_sequence(adev, 2223 hainan_golden_registers2, 2224 ARRAY_SIZE(hainan_golden_registers2)); 2225 amdgpu_device_program_register_sequence(adev, 2226 hainan_mgcg_cgcg_init, 2227 ARRAY_SIZE(hainan_mgcg_cgcg_init)); 2228 break; 2229 2230 2231 default: 2232 BUG(); 2233 } 2234 } 2235 2236 static void si_pcie_gen3_enable(struct amdgpu_device *adev) 2237 { 2238 struct pci_dev *root = adev->pdev->bus->self; 2239 u32 speed_cntl, current_data_rate; 2240 int i; 2241 u16 tmp16; 2242 2243 if (pci_is_root_bus(adev->pdev->bus)) 2244 return; 2245 2246 if (amdgpu_pcie_gen2 == 0) 2247 return; 2248 2249 if (adev->flags & AMD_IS_APU) 2250 return; 2251 2252 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 2253 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 2254 return; 2255 2256 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 2257 current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >> 2258 LC_CURRENT_DATA_RATE_SHIFT; 2259 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { 2260 if (current_data_rate == 2) { 2261 DRM_INFO("PCIE gen 3 link speeds already enabled\n"); 2262 return; 2263 } 2264 DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n"); 2265 } else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) { 2266 if (current_data_rate == 1) { 2267 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 2268 return; 2269 } 2270 DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n"); 2271 } 2272 2273 if (!pci_is_pcie(root) || !pci_is_pcie(adev->pdev)) 2274 return; 2275 2276 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { 2277 if (current_data_rate != 2) { 2278 u16 bridge_cfg, gpu_cfg; 2279 u16 bridge_cfg2, gpu_cfg2; 2280 u32 max_lw, current_lw, tmp; 2281 2282 pcie_capability_set_word(root, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD); 2283 pcie_capability_set_word(adev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD); 2284 2285 tmp = RREG32_PCIE(PCIE_LC_STATUS1); 2286 max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT; 2287 current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT; 2288 2289 if (current_lw < max_lw) { 2290 tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 2291 if (tmp & LC_RENEGOTIATION_SUPPORT) { 2292 tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS); 2293 tmp |= (max_lw << LC_LINK_WIDTH_SHIFT); 2294 tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW; 2295 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp); 2296 } 2297 } 2298 2299 for (i = 0; i < 10; i++) { 2300 pcie_capability_read_word(adev->pdev, 2301 PCI_EXP_DEVSTA, 2302 &tmp16); 2303 if (tmp16 & PCI_EXP_DEVSTA_TRPND) 2304 break; 2305 2306 pcie_capability_read_word(root, PCI_EXP_LNKCTL, 2307 &bridge_cfg); 2308 pcie_capability_read_word(adev->pdev, 2309 PCI_EXP_LNKCTL, 2310 &gpu_cfg); 2311 2312 pcie_capability_read_word(root, PCI_EXP_LNKCTL2, 2313 &bridge_cfg2); 2314 pcie_capability_read_word(adev->pdev, 2315 PCI_EXP_LNKCTL2, 2316 &gpu_cfg2); 2317 2318 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); 2319 tmp |= LC_SET_QUIESCE; 2320 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp); 2321 2322 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); 2323 tmp |= LC_REDO_EQ; 2324 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp); 2325 2326 mdelay(100); 2327 2328 pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL, 2329 PCI_EXP_LNKCTL_HAWD, 2330 bridge_cfg & 2331 PCI_EXP_LNKCTL_HAWD); 2332 pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL, 2333 PCI_EXP_LNKCTL_HAWD, 2334 gpu_cfg & 2335 PCI_EXP_LNKCTL_HAWD); 2336 2337 pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL2, 2338 PCI_EXP_LNKCTL2_ENTER_COMP | 2339 PCI_EXP_LNKCTL2_TX_MARGIN, 2340 bridge_cfg2 & 2341 (PCI_EXP_LNKCTL2_ENTER_COMP | 2342 PCI_EXP_LNKCTL2_TX_MARGIN)); 2343 pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL2, 2344 PCI_EXP_LNKCTL2_ENTER_COMP | 2345 PCI_EXP_LNKCTL2_TX_MARGIN, 2346 gpu_cfg2 & 2347 (PCI_EXP_LNKCTL2_ENTER_COMP | 2348 PCI_EXP_LNKCTL2_TX_MARGIN)); 2349 2350 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); 2351 tmp &= ~LC_SET_QUIESCE; 2352 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp); 2353 } 2354 } 2355 } 2356 2357 speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE; 2358 speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE; 2359 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 2360 2361 tmp16 = 0; 2362 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 2363 tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */ 2364 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 2365 tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */ 2366 else 2367 tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */ 2368 pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL2, 2369 PCI_EXP_LNKCTL2_TLS, tmp16); 2370 2371 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 2372 speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE; 2373 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 2374 2375 for (i = 0; i < adev->usec_timeout; i++) { 2376 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 2377 if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0) 2378 break; 2379 udelay(1); 2380 } 2381 } 2382 2383 static inline u32 si_pif_phy0_rreg(struct amdgpu_device *adev, u32 reg) 2384 { 2385 unsigned long flags; 2386 u32 r; 2387 2388 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 2389 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2390 r = RREG32(EVERGREEN_PIF_PHY0_DATA); 2391 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 2392 return r; 2393 } 2394 2395 static inline void si_pif_phy0_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 2396 { 2397 unsigned long flags; 2398 2399 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 2400 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2401 WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); 2402 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 2403 } 2404 2405 static inline u32 si_pif_phy1_rreg(struct amdgpu_device *adev, u32 reg) 2406 { 2407 unsigned long flags; 2408 u32 r; 2409 2410 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 2411 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2412 r = RREG32(EVERGREEN_PIF_PHY1_DATA); 2413 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 2414 return r; 2415 } 2416 2417 static inline void si_pif_phy1_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 2418 { 2419 unsigned long flags; 2420 2421 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 2422 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2423 WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); 2424 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 2425 } 2426 static void si_program_aspm(struct amdgpu_device *adev) 2427 { 2428 u32 data, orig; 2429 bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false; 2430 bool disable_clkreq = false; 2431 2432 if (!amdgpu_device_should_use_aspm(adev)) 2433 return; 2434 2435 orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL); 2436 data &= ~LC_XMIT_N_FTS_MASK; 2437 data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN; 2438 if (orig != data) 2439 WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data); 2440 2441 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3); 2442 data |= LC_GO_TO_RECOVERY; 2443 if (orig != data) 2444 WREG32_PCIE_PORT(PCIE_LC_CNTL3, data); 2445 2446 orig = data = RREG32_PCIE(PCIE_P_CNTL); 2447 data |= P_IGNORE_EDB_ERR; 2448 if (orig != data) 2449 WREG32_PCIE(PCIE_P_CNTL, data); 2450 2451 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL); 2452 data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK); 2453 data |= LC_PMI_TO_L1_DIS; 2454 if (!disable_l0s) 2455 data |= LC_L0S_INACTIVITY(7); 2456 2457 if (!disable_l1) { 2458 data |= LC_L1_INACTIVITY(7); 2459 data &= ~LC_PMI_TO_L1_DIS; 2460 if (orig != data) 2461 WREG32_PCIE_PORT(PCIE_LC_CNTL, data); 2462 2463 if (!disable_plloff_in_l1) { 2464 bool clk_req_support; 2465 2466 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0); 2467 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK); 2468 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7); 2469 if (orig != data) 2470 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data); 2471 2472 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1); 2473 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK); 2474 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7); 2475 if (orig != data) 2476 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data); 2477 2478 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0); 2479 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK); 2480 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7); 2481 if (orig != data) 2482 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data); 2483 2484 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1); 2485 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK); 2486 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7); 2487 if (orig != data) 2488 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data); 2489 2490 if ((adev->asic_type != CHIP_OLAND) && (adev->asic_type != CHIP_HAINAN)) { 2491 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0); 2492 data &= ~PLL_RAMP_UP_TIME_0_MASK; 2493 if (orig != data) 2494 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data); 2495 2496 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1); 2497 data &= ~PLL_RAMP_UP_TIME_1_MASK; 2498 if (orig != data) 2499 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data); 2500 2501 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_2); 2502 data &= ~PLL_RAMP_UP_TIME_2_MASK; 2503 if (orig != data) 2504 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_2, data); 2505 2506 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_3); 2507 data &= ~PLL_RAMP_UP_TIME_3_MASK; 2508 if (orig != data) 2509 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_3, data); 2510 2511 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0); 2512 data &= ~PLL_RAMP_UP_TIME_0_MASK; 2513 if (orig != data) 2514 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data); 2515 2516 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1); 2517 data &= ~PLL_RAMP_UP_TIME_1_MASK; 2518 if (orig != data) 2519 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data); 2520 2521 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_2); 2522 data &= ~PLL_RAMP_UP_TIME_2_MASK; 2523 if (orig != data) 2524 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_2, data); 2525 2526 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_3); 2527 data &= ~PLL_RAMP_UP_TIME_3_MASK; 2528 if (orig != data) 2529 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_3, data); 2530 } 2531 orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 2532 data &= ~LC_DYN_LANES_PWR_STATE_MASK; 2533 data |= LC_DYN_LANES_PWR_STATE(3); 2534 if (orig != data) 2535 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data); 2536 2537 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL); 2538 data &= ~LS2_EXIT_TIME_MASK; 2539 if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type == CHIP_HAINAN)) 2540 data |= LS2_EXIT_TIME(5); 2541 if (orig != data) 2542 si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data); 2543 2544 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL); 2545 data &= ~LS2_EXIT_TIME_MASK; 2546 if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type == CHIP_HAINAN)) 2547 data |= LS2_EXIT_TIME(5); 2548 if (orig != data) 2549 si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data); 2550 2551 if (!disable_clkreq && 2552 !pci_is_root_bus(adev->pdev->bus)) { 2553 struct pci_dev *root = adev->pdev->bus->self; 2554 u32 lnkcap; 2555 2556 clk_req_support = false; 2557 pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap); 2558 if (lnkcap & PCI_EXP_LNKCAP_CLKPM) 2559 clk_req_support = true; 2560 } else { 2561 clk_req_support = false; 2562 } 2563 2564 if (clk_req_support) { 2565 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2); 2566 data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23; 2567 if (orig != data) 2568 WREG32_PCIE_PORT(PCIE_LC_CNTL2, data); 2569 2570 orig = data = RREG32(THM_CLK_CNTL); 2571 data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK); 2572 data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1); 2573 if (orig != data) 2574 WREG32(THM_CLK_CNTL, data); 2575 2576 orig = data = RREG32(MISC_CLK_CNTL); 2577 data &= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK); 2578 data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1); 2579 if (orig != data) 2580 WREG32(MISC_CLK_CNTL, data); 2581 2582 orig = data = RREG32(CG_CLKPIN_CNTL); 2583 data &= ~BCLK_AS_XCLK; 2584 if (orig != data) 2585 WREG32(CG_CLKPIN_CNTL, data); 2586 2587 orig = data = RREG32(CG_CLKPIN_CNTL_2); 2588 data &= ~FORCE_BIF_REFCLK_EN; 2589 if (orig != data) 2590 WREG32(CG_CLKPIN_CNTL_2, data); 2591 2592 orig = data = RREG32(MPLL_BYPASSCLK_SEL); 2593 data &= ~MPLL_CLKOUT_SEL_MASK; 2594 data |= MPLL_CLKOUT_SEL(4); 2595 if (orig != data) 2596 WREG32(MPLL_BYPASSCLK_SEL, data); 2597 2598 orig = data = RREG32(SPLL_CNTL_MODE); 2599 data &= ~SPLL_REFCLK_SEL_MASK; 2600 if (orig != data) 2601 WREG32(SPLL_CNTL_MODE, data); 2602 } 2603 } 2604 } else { 2605 if (orig != data) 2606 WREG32_PCIE_PORT(PCIE_LC_CNTL, data); 2607 } 2608 2609 orig = data = RREG32_PCIE(PCIE_CNTL2); 2610 data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN; 2611 if (orig != data) 2612 WREG32_PCIE(PCIE_CNTL2, data); 2613 2614 if (!disable_l0s) { 2615 data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL); 2616 if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) { 2617 data = RREG32_PCIE(PCIE_LC_STATUS1); 2618 if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) { 2619 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL); 2620 data &= ~LC_L0S_INACTIVITY_MASK; 2621 if (orig != data) 2622 WREG32_PCIE_PORT(PCIE_LC_CNTL, data); 2623 } 2624 } 2625 } 2626 } 2627 2628 static void si_fix_pci_max_read_req_size(struct amdgpu_device *adev) 2629 { 2630 int readrq; 2631 u16 v; 2632 2633 readrq = pcie_get_readrq(adev->pdev); 2634 v = ffs(readrq) - 8; 2635 if ((v == 0) || (v == 6) || (v == 7)) 2636 pcie_set_readrq(adev->pdev, 512); 2637 } 2638 2639 static int si_common_hw_init(struct amdgpu_ip_block *ip_block) 2640 { 2641 struct amdgpu_device *adev = ip_block->adev; 2642 2643 si_fix_pci_max_read_req_size(adev); 2644 si_init_golden_registers(adev); 2645 si_pcie_gen3_enable(adev); 2646 si_program_aspm(adev); 2647 2648 return 0; 2649 } 2650 2651 static int si_common_hw_fini(struct amdgpu_ip_block *ip_block) 2652 { 2653 return 0; 2654 } 2655 2656 static int si_common_resume(struct amdgpu_ip_block *ip_block) 2657 { 2658 return si_common_hw_init(ip_block); 2659 } 2660 2661 static bool si_common_is_idle(struct amdgpu_ip_block *ip_block) 2662 { 2663 return true; 2664 } 2665 2666 static int si_common_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2667 enum amd_clockgating_state state) 2668 { 2669 return 0; 2670 } 2671 2672 static int si_common_set_powergating_state(struct amdgpu_ip_block *ip_block, 2673 enum amd_powergating_state state) 2674 { 2675 return 0; 2676 } 2677 2678 static const struct amd_ip_funcs si_common_ip_funcs = { 2679 .name = "si_common", 2680 .early_init = si_common_early_init, 2681 .hw_init = si_common_hw_init, 2682 .hw_fini = si_common_hw_fini, 2683 .resume = si_common_resume, 2684 .is_idle = si_common_is_idle, 2685 .set_clockgating_state = si_common_set_clockgating_state, 2686 .set_powergating_state = si_common_set_powergating_state, 2687 }; 2688 2689 static const struct amdgpu_ip_block_version si_common_ip_block = 2690 { 2691 .type = AMD_IP_BLOCK_TYPE_COMMON, 2692 .major = 1, 2693 .minor = 0, 2694 .rev = 0, 2695 .funcs = &si_common_ip_funcs, 2696 }; 2697 2698 int si_set_ip_blocks(struct amdgpu_device *adev) 2699 { 2700 switch (adev->asic_type) { 2701 case CHIP_VERDE: 2702 case CHIP_TAHITI: 2703 case CHIP_PITCAIRN: 2704 amdgpu_device_ip_block_add(adev, &si_common_ip_block); 2705 amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block); 2706 amdgpu_device_ip_block_add(adev, &si_ih_ip_block); 2707 amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block); 2708 amdgpu_device_ip_block_add(adev, &si_dma_ip_block); 2709 amdgpu_device_ip_block_add(adev, &si_smu_ip_block); 2710 if (adev->enable_virtual_display) 2711 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2712 #if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_SI) 2713 else if (amdgpu_device_has_dc_support(adev)) 2714 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2715 #endif 2716 else 2717 amdgpu_device_ip_block_add(adev, &dce_v6_0_ip_block); 2718 amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); 2719 /* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */ 2720 break; 2721 case CHIP_OLAND: 2722 amdgpu_device_ip_block_add(adev, &si_common_ip_block); 2723 amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block); 2724 amdgpu_device_ip_block_add(adev, &si_ih_ip_block); 2725 amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block); 2726 amdgpu_device_ip_block_add(adev, &si_dma_ip_block); 2727 amdgpu_device_ip_block_add(adev, &si_smu_ip_block); 2728 if (adev->enable_virtual_display) 2729 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2730 #if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_SI) 2731 else if (amdgpu_device_has_dc_support(adev)) 2732 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2733 #endif 2734 else 2735 amdgpu_device_ip_block_add(adev, &dce_v6_4_ip_block); 2736 amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); 2737 /* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */ 2738 break; 2739 case CHIP_HAINAN: 2740 amdgpu_device_ip_block_add(adev, &si_common_ip_block); 2741 amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block); 2742 amdgpu_device_ip_block_add(adev, &si_ih_ip_block); 2743 amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block); 2744 amdgpu_device_ip_block_add(adev, &si_dma_ip_block); 2745 amdgpu_device_ip_block_add(adev, &si_smu_ip_block); 2746 if (adev->enable_virtual_display) 2747 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2748 break; 2749 default: 2750 BUG(); 2751 } 2752 return 0; 2753 } 2754 2755