1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/slab.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include <drm/amdgpu_drm.h> 30 31 #include "amdgpu.h" 32 #include "amdgpu_atombios.h" 33 #include "amdgpu_ih.h" 34 #include "amdgpu_uvd.h" 35 #include "amdgpu_vce.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "si_dpm.h" 40 #include "sid.h" 41 #include "si_ih.h" 42 #include "gfx_v6_0.h" 43 #include "gmc_v6_0.h" 44 #include "si_dma.h" 45 #include "dce_v6_0.h" 46 #include "si.h" 47 #include "uvd_v3_1.h" 48 #include "vce_v1_0.h" 49 50 #include "uvd/uvd_4_0_d.h" 51 52 #include "smu/smu_6_0_d.h" 53 #include "smu/smu_6_0_sh_mask.h" 54 55 #include "gca/gfx_6_0_d.h" 56 #include "gca/gfx_6_0_sh_mask.h" 57 58 #include "oss/oss_1_0_d.h" 59 #include "oss/oss_1_0_sh_mask.h" 60 61 #include "gmc/gmc_6_0_d.h" 62 #include"gmc/gmc_6_0_sh_mask.h" 63 64 #include "dce/dce_6_0_d.h" 65 #include "dce/dce_6_0_sh_mask.h" 66 67 #include "bif/bif_3_0_d.h" 68 #include "bif/bif_3_0_sh_mask.h" 69 #include "si_enums.h" 70 71 #include "amdgpu_dm.h" 72 #include "amdgpu_vkms.h" 73 74 static const u32 tahiti_golden_registers[] = 75 { 76 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011, 77 mmCB_HW_CONTROL, 0x00010000, 0x00018208, 78 mmDB_DEBUG, 0xffffffff, 0x00000000, 79 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 80 mmDB_DEBUG3, 0x0002021c, 0x00020200, 81 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 82 0x340c, 0x000000c0, 0x00800040, 83 0x360c, 0x000000c0, 0x00800040, 84 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 85 mmFBC_MISC, 0x00200000, 0x50100000, 86 mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011, 87 mmMC_ARB_WTM_CNTL_RD, 0x00000003, 0x000007ff, 88 mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000, 89 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007, 90 mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff, 91 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 92 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000, 93 mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x2a00126a, 94 0x000c, 0xffffffff, 0x0040, 95 0x000d, 0x00000040, 0x00004040, 96 mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000, 97 mmSQ_DED_CNT, 0x01ff1f3f, 0x00000000, 98 mmSQ_SEC_CNT, 0x01ff1f3f, 0x00000000, 99 mmSX_DEBUG_1, 0x0000007f, 0x00000020, 100 mmTA_CNTL_AUX, 0x00010000, 0x00010000, 101 mmTCP_ADDR_CONFIG, 0x00000200, 0x000002fb, 102 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b, 103 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876, 104 mmVGT_FIFO_DEPTHS, 0xffffffff, 0x000fff40, 105 mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010, 106 mmVM_CONTEXT0_CNTL, 0x20000000, 0x20fffed8, 107 mmVM_L2_CG, 0x000c0fc0, 0x000c0400, 108 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff, 109 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 110 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 111 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 112 }; 113 114 static const u32 tahiti_golden_registers2[] = 115 { 116 mmMCIF_MEM_CONTROL, 0x00000001, 0x00000001, 117 }; 118 119 static const u32 tahiti_golden_rlc_registers[] = 120 { 121 mmGB_ADDR_CONFIG, 0xffffffff, 0x12011003, 122 mmRLC_LB_PARAMS, 0xffffffff, 0x00601005, 123 0x311f, 0xffffffff, 0x10104040, 124 0x3122, 0xffffffff, 0x0100000a, 125 mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800, 126 mmRLC_LB_CNTL, 0xffffffff, 0x800000f4, 127 mmUVD_CGC_GATE, 0x00000008, 0x00000000, 128 }; 129 130 static const u32 pitcairn_golden_registers[] = 131 { 132 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011, 133 mmCB_HW_CONTROL, 0x00010000, 0x00018208, 134 mmDB_DEBUG, 0xffffffff, 0x00000000, 135 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 136 mmDB_DEBUG3, 0x0002021c, 0x00020200, 137 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 138 0x340c, 0x000300c0, 0x00800040, 139 0x360c, 0x000300c0, 0x00800040, 140 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 141 mmFBC_MISC, 0x00200000, 0x50100000, 142 mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011, 143 mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2, 144 mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000, 145 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007, 146 mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff, 147 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 148 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000, 149 mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x2a00126a, 150 0x000c, 0xffffffff, 0x0040, 151 0x000d, 0x00000040, 0x00004040, 152 mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000, 153 mmSX_DEBUG_1, 0x0000007f, 0x00000020, 154 mmTA_CNTL_AUX, 0x00010000, 0x00010000, 155 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7, 156 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 157 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x32761054, 158 mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010, 159 mmVM_L2_CG, 0x000c0fc0, 0x000c0400, 160 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff, 161 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 162 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 163 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 164 }; 165 166 static const u32 pitcairn_golden_rlc_registers[] = 167 { 168 mmGB_ADDR_CONFIG, 0xffffffff, 0x12011003, 169 mmRLC_LB_PARAMS, 0xffffffff, 0x00601004, 170 0x311f, 0xffffffff, 0x10102020, 171 0x3122, 0xffffffff, 0x01000020, 172 mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800, 173 mmRLC_LB_CNTL, 0xffffffff, 0x800000a4, 174 }; 175 176 static const u32 verde_pg_init[] = 177 { 178 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x40000, 179 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x200010ff, 180 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 181 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 182 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 183 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 184 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 185 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x7007, 186 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x300010ff, 187 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 188 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 189 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 190 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 191 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 192 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x400000, 193 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x100010ff, 194 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 195 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 196 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 197 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 198 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 199 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x120200, 200 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x500010ff, 201 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 202 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 203 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 204 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 205 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 206 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x1e1e16, 207 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x600010ff, 208 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 209 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 210 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 211 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 212 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 213 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x171f1e, 214 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x700010ff, 215 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 216 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 217 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 218 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 219 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 220 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 221 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x9ff, 222 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x0, 223 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10000800, 224 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xf, 225 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xf, 226 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x4, 227 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1000051e, 228 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xffff, 229 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xffff, 230 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x8, 231 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x80500, 232 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x12, 233 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x9050c, 234 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1d, 235 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xb052c, 236 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x2a, 237 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1053e, 238 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x2d, 239 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10546, 240 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x30, 241 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xa054e, 242 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x3c, 243 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1055f, 244 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x3f, 245 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10567, 246 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x42, 247 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1056f, 248 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x45, 249 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10572, 250 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x48, 251 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x20575, 252 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x4c, 253 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x190801, 254 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x67, 255 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1082a, 256 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x6a, 257 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1b082d, 258 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x87, 259 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x310851, 260 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xba, 261 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x891, 262 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xbc, 263 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x893, 264 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xbe, 265 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x20895, 266 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xc2, 267 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x20899, 268 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xc6, 269 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x2089d, 270 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xca, 271 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x8a1, 272 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xcc, 273 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x8a3, 274 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xce, 275 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x308a5, 276 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xd3, 277 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x6d08cd, 278 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x142, 279 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x2000095a, 280 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1, 281 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x144, 282 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x301f095b, 283 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x165, 284 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xc094d, 285 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x173, 286 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xf096d, 287 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x184, 288 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x15097f, 289 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x19b, 290 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xc0998, 291 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1a9, 292 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x409a7, 293 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1af, 294 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xcdc, 295 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1b1, 296 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x800, 297 mmGMCON_RENG_EXECUTE, 0xffffffff, 0x6c9b2000, 298 mmGMCON_MISC2, 0xfc00, 0x2000, 299 mmGMCON_MISC3, 0xffffffff, 0xfc0, 300 mmMC_PMG_AUTO_CFG, 0x00000100, 0x100, 301 }; 302 303 static const u32 verde_golden_rlc_registers[] = 304 { 305 mmGB_ADDR_CONFIG, 0xffffffff, 0x02010002, 306 mmRLC_LB_PARAMS, 0xffffffff, 0x033f1005, 307 0x311f, 0xffffffff, 0x10808020, 308 0x3122, 0xffffffff, 0x00800008, 309 mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00001000, 310 mmRLC_LB_CNTL, 0xffffffff, 0x80010014, 311 }; 312 313 static const u32 verde_golden_registers[] = 314 { 315 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011, 316 mmCB_HW_CONTROL, 0x00010000, 0x00018208, 317 mmDB_DEBUG, 0xffffffff, 0x00000000, 318 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 319 mmDB_DEBUG3, 0x0002021c, 0x00020200, 320 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 321 0x340c, 0x000300c0, 0x00800040, 322 0x360c, 0x000300c0, 0x00800040, 323 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 324 mmFBC_MISC, 0x00200000, 0x50100000, 325 mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011, 326 mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2, 327 mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000, 328 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007, 329 mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff, 330 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 331 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000, 332 mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x0000124a, 333 0x000c, 0xffffffff, 0x0040, 334 0x000d, 0x00000040, 0x00004040, 335 mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000, 336 mmSQ_DED_CNT, 0x01ff1f3f, 0x00000000, 337 mmSQ_SEC_CNT, 0x01ff1f3f, 0x00000000, 338 mmSX_DEBUG_1, 0x0000007f, 0x00000020, 339 mmTA_CNTL_AUX, 0x00010000, 0x00010000, 340 mmTCP_ADDR_CONFIG, 0x000003ff, 0x00000003, 341 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 342 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001032, 343 mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010, 344 mmVM_L2_CG, 0x000c0fc0, 0x000c0400, 345 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff, 346 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 347 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 348 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 349 }; 350 351 static const u32 oland_golden_registers[] = 352 { 353 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011, 354 mmCB_HW_CONTROL, 0x00010000, 0x00018208, 355 mmDB_DEBUG, 0xffffffff, 0x00000000, 356 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 357 mmDB_DEBUG3, 0x0002021c, 0x00020200, 358 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 359 0x340c, 0x000300c0, 0x00800040, 360 0x360c, 0x000300c0, 0x00800040, 361 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 362 mmFBC_MISC, 0x00200000, 0x50100000, 363 mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011, 364 mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2, 365 mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000, 366 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007, 367 mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff, 368 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 369 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000, 370 mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x00000082, 371 0x000c, 0xffffffff, 0x0040, 372 0x000d, 0x00000040, 0x00004040, 373 mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000, 374 mmSX_DEBUG_1, 0x0000007f, 0x00000020, 375 mmTA_CNTL_AUX, 0x00010000, 0x00010000, 376 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3, 377 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 378 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210, 379 mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010, 380 mmVM_L2_CG, 0x000c0fc0, 0x000c0400, 381 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff, 382 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 383 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 384 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 385 386 }; 387 388 static const u32 oland_golden_rlc_registers[] = 389 { 390 mmGB_ADDR_CONFIG, 0xffffffff, 0x02010002, 391 mmRLC_LB_PARAMS, 0xffffffff, 0x00601005, 392 0x311f, 0xffffffff, 0x10104040, 393 0x3122, 0xffffffff, 0x0100000a, 394 mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800, 395 mmRLC_LB_CNTL, 0xffffffff, 0x800000f4, 396 }; 397 398 static const u32 hainan_golden_registers[] = 399 { 400 0x17bc, 0x00000030, 0x00000011, 401 mmCB_HW_CONTROL, 0x00010000, 0x00018208, 402 mmDB_DEBUG, 0xffffffff, 0x00000000, 403 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 404 mmDB_DEBUG3, 0x0002021c, 0x00020200, 405 0x031e, 0x00000080, 0x00000000, 406 0x3430, 0xff000fff, 0x00000100, 407 0x340c, 0x000300c0, 0x00800040, 408 0x3630, 0xff000fff, 0x00000100, 409 0x360c, 0x000300c0, 0x00800040, 410 0x16ec, 0x000000f0, 0x00000070, 411 0x16f0, 0x00200000, 0x50100000, 412 0x1c0c, 0x31000311, 0x00000011, 413 mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2, 414 mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000, 415 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007, 416 mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff, 417 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 418 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000, 419 mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x00000000, 420 0x000c, 0xffffffff, 0x0040, 421 0x000d, 0x00000040, 0x00004040, 422 mmSPI_CONFIG_CNTL, 0x03e00000, 0x03600000, 423 mmSX_DEBUG_1, 0x0000007f, 0x00000020, 424 mmTA_CNTL_AUX, 0x00010000, 0x00010000, 425 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1, 426 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 427 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210, 428 mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010, 429 mmVM_L2_CG, 0x000c0fc0, 0x000c0400, 430 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff, 431 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 432 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 433 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 434 }; 435 436 static const u32 hainan_golden_registers2[] = 437 { 438 mmGB_ADDR_CONFIG, 0xffffffff, 0x2011003, 439 }; 440 441 static const u32 tahiti_mgcg_cgcg_init[] = 442 { 443 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc, 444 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 445 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 446 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 447 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 448 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 449 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 450 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 451 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 452 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 453 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 454 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 455 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 456 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 457 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 458 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 459 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 460 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 461 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 462 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 463 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 464 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 465 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 466 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 467 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 468 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 469 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 470 0x2458, 0xffffffff, 0x00010000, 471 0x2459, 0xffffffff, 0x00030002, 472 0x245a, 0xffffffff, 0x00040007, 473 0x245b, 0xffffffff, 0x00060005, 474 0x245c, 0xffffffff, 0x00090008, 475 0x245d, 0xffffffff, 0x00020001, 476 0x245e, 0xffffffff, 0x00040003, 477 0x245f, 0xffffffff, 0x00000007, 478 0x2460, 0xffffffff, 0x00060005, 479 0x2461, 0xffffffff, 0x00090008, 480 0x2462, 0xffffffff, 0x00030002, 481 0x2463, 0xffffffff, 0x00050004, 482 0x2464, 0xffffffff, 0x00000008, 483 0x2465, 0xffffffff, 0x00070006, 484 0x2466, 0xffffffff, 0x000a0009, 485 0x2467, 0xffffffff, 0x00040003, 486 0x2468, 0xffffffff, 0x00060005, 487 0x2469, 0xffffffff, 0x00000009, 488 0x246a, 0xffffffff, 0x00080007, 489 0x246b, 0xffffffff, 0x000b000a, 490 0x246c, 0xffffffff, 0x00050004, 491 0x246d, 0xffffffff, 0x00070006, 492 0x246e, 0xffffffff, 0x0008000b, 493 0x246f, 0xffffffff, 0x000a0009, 494 0x2470, 0xffffffff, 0x000d000c, 495 0x2471, 0xffffffff, 0x00060005, 496 0x2472, 0xffffffff, 0x00080007, 497 0x2473, 0xffffffff, 0x0000000b, 498 0x2474, 0xffffffff, 0x000a0009, 499 0x2475, 0xffffffff, 0x000d000c, 500 0x2476, 0xffffffff, 0x00070006, 501 0x2477, 0xffffffff, 0x00090008, 502 0x2478, 0xffffffff, 0x0000000c, 503 0x2479, 0xffffffff, 0x000b000a, 504 0x247a, 0xffffffff, 0x000e000d, 505 0x247b, 0xffffffff, 0x00080007, 506 0x247c, 0xffffffff, 0x000a0009, 507 0x247d, 0xffffffff, 0x0000000d, 508 0x247e, 0xffffffff, 0x000c000b, 509 0x247f, 0xffffffff, 0x000f000e, 510 0x2480, 0xffffffff, 0x00090008, 511 0x2481, 0xffffffff, 0x000b000a, 512 0x2482, 0xffffffff, 0x000c000f, 513 0x2483, 0xffffffff, 0x000e000d, 514 0x2484, 0xffffffff, 0x00110010, 515 0x2485, 0xffffffff, 0x000a0009, 516 0x2486, 0xffffffff, 0x000c000b, 517 0x2487, 0xffffffff, 0x0000000f, 518 0x2488, 0xffffffff, 0x000e000d, 519 0x2489, 0xffffffff, 0x00110010, 520 0x248a, 0xffffffff, 0x000b000a, 521 0x248b, 0xffffffff, 0x000d000c, 522 0x248c, 0xffffffff, 0x00000010, 523 0x248d, 0xffffffff, 0x000f000e, 524 0x248e, 0xffffffff, 0x00120011, 525 0x248f, 0xffffffff, 0x000c000b, 526 0x2490, 0xffffffff, 0x000e000d, 527 0x2491, 0xffffffff, 0x00000011, 528 0x2492, 0xffffffff, 0x0010000f, 529 0x2493, 0xffffffff, 0x00130012, 530 0x2494, 0xffffffff, 0x000d000c, 531 0x2495, 0xffffffff, 0x000f000e, 532 0x2496, 0xffffffff, 0x00100013, 533 0x2497, 0xffffffff, 0x00120011, 534 0x2498, 0xffffffff, 0x00150014, 535 0x2499, 0xffffffff, 0x000e000d, 536 0x249a, 0xffffffff, 0x0010000f, 537 0x249b, 0xffffffff, 0x00000013, 538 0x249c, 0xffffffff, 0x00120011, 539 0x249d, 0xffffffff, 0x00150014, 540 0x249e, 0xffffffff, 0x000f000e, 541 0x249f, 0xffffffff, 0x00110010, 542 0x24a0, 0xffffffff, 0x00000014, 543 0x24a1, 0xffffffff, 0x00130012, 544 0x24a2, 0xffffffff, 0x00160015, 545 0x24a3, 0xffffffff, 0x0010000f, 546 0x24a4, 0xffffffff, 0x00120011, 547 0x24a5, 0xffffffff, 0x00000015, 548 0x24a6, 0xffffffff, 0x00140013, 549 0x24a7, 0xffffffff, 0x00170016, 550 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 551 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 552 mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080, 553 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 554 0x000c, 0xffffffff, 0x0000001c, 555 0x000d, 0x000f0000, 0x000f0000, 556 0x0583, 0xffffffff, 0x00000100, 557 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 558 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 559 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104, 560 mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000, 561 mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000, 562 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 563 0x157a, 0x00000001, 0x00000001, 564 mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001, 565 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 566 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 567 0x3430, 0xfffffff0, 0x00000100, 568 0x3630, 0xfffffff0, 0x00000100, 569 }; 570 static const u32 pitcairn_mgcg_cgcg_init[] = 571 { 572 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc, 573 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 574 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 575 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 576 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 577 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 578 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 579 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 580 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 581 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 582 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 583 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 584 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 585 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 586 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 587 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 588 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 589 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 590 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 591 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 592 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 593 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 594 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 595 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 596 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 597 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 598 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 599 0x2458, 0xffffffff, 0x00010000, 600 0x2459, 0xffffffff, 0x00030002, 601 0x245a, 0xffffffff, 0x00040007, 602 0x245b, 0xffffffff, 0x00060005, 603 0x245c, 0xffffffff, 0x00090008, 604 0x245d, 0xffffffff, 0x00020001, 605 0x245e, 0xffffffff, 0x00040003, 606 0x245f, 0xffffffff, 0x00000007, 607 0x2460, 0xffffffff, 0x00060005, 608 0x2461, 0xffffffff, 0x00090008, 609 0x2462, 0xffffffff, 0x00030002, 610 0x2463, 0xffffffff, 0x00050004, 611 0x2464, 0xffffffff, 0x00000008, 612 0x2465, 0xffffffff, 0x00070006, 613 0x2466, 0xffffffff, 0x000a0009, 614 0x2467, 0xffffffff, 0x00040003, 615 0x2468, 0xffffffff, 0x00060005, 616 0x2469, 0xffffffff, 0x00000009, 617 0x246a, 0xffffffff, 0x00080007, 618 0x246b, 0xffffffff, 0x000b000a, 619 0x246c, 0xffffffff, 0x00050004, 620 0x246d, 0xffffffff, 0x00070006, 621 0x246e, 0xffffffff, 0x0008000b, 622 0x246f, 0xffffffff, 0x000a0009, 623 0x2470, 0xffffffff, 0x000d000c, 624 0x2480, 0xffffffff, 0x00090008, 625 0x2481, 0xffffffff, 0x000b000a, 626 0x2482, 0xffffffff, 0x000c000f, 627 0x2483, 0xffffffff, 0x000e000d, 628 0x2484, 0xffffffff, 0x00110010, 629 0x2485, 0xffffffff, 0x000a0009, 630 0x2486, 0xffffffff, 0x000c000b, 631 0x2487, 0xffffffff, 0x0000000f, 632 0x2488, 0xffffffff, 0x000e000d, 633 0x2489, 0xffffffff, 0x00110010, 634 0x248a, 0xffffffff, 0x000b000a, 635 0x248b, 0xffffffff, 0x000d000c, 636 0x248c, 0xffffffff, 0x00000010, 637 0x248d, 0xffffffff, 0x000f000e, 638 0x248e, 0xffffffff, 0x00120011, 639 0x248f, 0xffffffff, 0x000c000b, 640 0x2490, 0xffffffff, 0x000e000d, 641 0x2491, 0xffffffff, 0x00000011, 642 0x2492, 0xffffffff, 0x0010000f, 643 0x2493, 0xffffffff, 0x00130012, 644 0x2494, 0xffffffff, 0x000d000c, 645 0x2495, 0xffffffff, 0x000f000e, 646 0x2496, 0xffffffff, 0x00100013, 647 0x2497, 0xffffffff, 0x00120011, 648 0x2498, 0xffffffff, 0x00150014, 649 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 650 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 651 mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080, 652 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 653 0x000c, 0xffffffff, 0x0000001c, 654 0x000d, 0x000f0000, 0x000f0000, 655 0x0583, 0xffffffff, 0x00000100, 656 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 657 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 658 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104, 659 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 660 0x157a, 0x00000001, 0x00000001, 661 mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001, 662 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 663 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 664 0x3430, 0xfffffff0, 0x00000100, 665 0x3630, 0xfffffff0, 0x00000100, 666 }; 667 668 static const u32 verde_mgcg_cgcg_init[] = 669 { 670 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc, 671 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 672 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 673 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 674 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 675 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 676 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 677 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 678 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 679 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 680 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 681 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 682 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 683 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 684 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 685 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 686 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 687 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 688 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 689 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 690 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 691 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 692 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 693 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 694 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 695 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 696 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 697 0x2458, 0xffffffff, 0x00010000, 698 0x2459, 0xffffffff, 0x00030002, 699 0x245a, 0xffffffff, 0x00040007, 700 0x245b, 0xffffffff, 0x00060005, 701 0x245c, 0xffffffff, 0x00090008, 702 0x245d, 0xffffffff, 0x00020001, 703 0x245e, 0xffffffff, 0x00040003, 704 0x245f, 0xffffffff, 0x00000007, 705 0x2460, 0xffffffff, 0x00060005, 706 0x2461, 0xffffffff, 0x00090008, 707 0x2462, 0xffffffff, 0x00030002, 708 0x2463, 0xffffffff, 0x00050004, 709 0x2464, 0xffffffff, 0x00000008, 710 0x2465, 0xffffffff, 0x00070006, 711 0x2466, 0xffffffff, 0x000a0009, 712 0x2467, 0xffffffff, 0x00040003, 713 0x2468, 0xffffffff, 0x00060005, 714 0x2469, 0xffffffff, 0x00000009, 715 0x246a, 0xffffffff, 0x00080007, 716 0x246b, 0xffffffff, 0x000b000a, 717 0x246c, 0xffffffff, 0x00050004, 718 0x246d, 0xffffffff, 0x00070006, 719 0x246e, 0xffffffff, 0x0008000b, 720 0x246f, 0xffffffff, 0x000a0009, 721 0x2470, 0xffffffff, 0x000d000c, 722 0x2480, 0xffffffff, 0x00090008, 723 0x2481, 0xffffffff, 0x000b000a, 724 0x2482, 0xffffffff, 0x000c000f, 725 0x2483, 0xffffffff, 0x000e000d, 726 0x2484, 0xffffffff, 0x00110010, 727 0x2485, 0xffffffff, 0x000a0009, 728 0x2486, 0xffffffff, 0x000c000b, 729 0x2487, 0xffffffff, 0x0000000f, 730 0x2488, 0xffffffff, 0x000e000d, 731 0x2489, 0xffffffff, 0x00110010, 732 0x248a, 0xffffffff, 0x000b000a, 733 0x248b, 0xffffffff, 0x000d000c, 734 0x248c, 0xffffffff, 0x00000010, 735 0x248d, 0xffffffff, 0x000f000e, 736 0x248e, 0xffffffff, 0x00120011, 737 0x248f, 0xffffffff, 0x000c000b, 738 0x2490, 0xffffffff, 0x000e000d, 739 0x2491, 0xffffffff, 0x00000011, 740 0x2492, 0xffffffff, 0x0010000f, 741 0x2493, 0xffffffff, 0x00130012, 742 0x2494, 0xffffffff, 0x000d000c, 743 0x2495, 0xffffffff, 0x000f000e, 744 0x2496, 0xffffffff, 0x00100013, 745 0x2497, 0xffffffff, 0x00120011, 746 0x2498, 0xffffffff, 0x00150014, 747 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 748 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 749 mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080, 750 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 751 0x000c, 0xffffffff, 0x0000001c, 752 0x000d, 0x000f0000, 0x000f0000, 753 0x0583, 0xffffffff, 0x00000100, 754 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 755 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 756 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104, 757 mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000, 758 mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000, 759 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 760 0x157a, 0x00000001, 0x00000001, 761 mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001, 762 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 763 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 764 0x3430, 0xfffffff0, 0x00000100, 765 0x3630, 0xfffffff0, 0x00000100, 766 }; 767 768 static const u32 oland_mgcg_cgcg_init[] = 769 { 770 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc, 771 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 772 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 773 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 774 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 775 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 776 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 777 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 778 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 779 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 780 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 781 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 782 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 783 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 784 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 785 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 786 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 787 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 788 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 789 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 790 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 791 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 792 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 793 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 794 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 795 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 796 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 797 0x2458, 0xffffffff, 0x00010000, 798 0x2459, 0xffffffff, 0x00030002, 799 0x245a, 0xffffffff, 0x00040007, 800 0x245b, 0xffffffff, 0x00060005, 801 0x245c, 0xffffffff, 0x00090008, 802 0x245d, 0xffffffff, 0x00020001, 803 0x245e, 0xffffffff, 0x00040003, 804 0x245f, 0xffffffff, 0x00000007, 805 0x2460, 0xffffffff, 0x00060005, 806 0x2461, 0xffffffff, 0x00090008, 807 0x2462, 0xffffffff, 0x00030002, 808 0x2463, 0xffffffff, 0x00050004, 809 0x2464, 0xffffffff, 0x00000008, 810 0x2465, 0xffffffff, 0x00070006, 811 0x2466, 0xffffffff, 0x000a0009, 812 0x2467, 0xffffffff, 0x00040003, 813 0x2468, 0xffffffff, 0x00060005, 814 0x2469, 0xffffffff, 0x00000009, 815 0x246a, 0xffffffff, 0x00080007, 816 0x246b, 0xffffffff, 0x000b000a, 817 0x246c, 0xffffffff, 0x00050004, 818 0x246d, 0xffffffff, 0x00070006, 819 0x246e, 0xffffffff, 0x0008000b, 820 0x246f, 0xffffffff, 0x000a0009, 821 0x2470, 0xffffffff, 0x000d000c, 822 0x2471, 0xffffffff, 0x00060005, 823 0x2472, 0xffffffff, 0x00080007, 824 0x2473, 0xffffffff, 0x0000000b, 825 0x2474, 0xffffffff, 0x000a0009, 826 0x2475, 0xffffffff, 0x000d000c, 827 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 828 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 829 mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080, 830 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 831 0x000c, 0xffffffff, 0x0000001c, 832 0x000d, 0x000f0000, 0x000f0000, 833 0x0583, 0xffffffff, 0x00000100, 834 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 835 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 836 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104, 837 mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000, 838 mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000, 839 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 840 0x157a, 0x00000001, 0x00000001, 841 mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001, 842 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 843 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 844 0x3430, 0xfffffff0, 0x00000100, 845 0x3630, 0xfffffff0, 0x00000100, 846 }; 847 848 static const u32 hainan_mgcg_cgcg_init[] = 849 { 850 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc, 851 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 852 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 853 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 854 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 855 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 856 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 857 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 858 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 859 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 860 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 861 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 862 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 863 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 864 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 865 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 866 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 867 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 868 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 869 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 870 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 871 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 872 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 873 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 874 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 875 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 876 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 877 0x2458, 0xffffffff, 0x00010000, 878 0x2459, 0xffffffff, 0x00030002, 879 0x245a, 0xffffffff, 0x00040007, 880 0x245b, 0xffffffff, 0x00060005, 881 0x245c, 0xffffffff, 0x00090008, 882 0x245d, 0xffffffff, 0x00020001, 883 0x245e, 0xffffffff, 0x00040003, 884 0x245f, 0xffffffff, 0x00000007, 885 0x2460, 0xffffffff, 0x00060005, 886 0x2461, 0xffffffff, 0x00090008, 887 0x2462, 0xffffffff, 0x00030002, 888 0x2463, 0xffffffff, 0x00050004, 889 0x2464, 0xffffffff, 0x00000008, 890 0x2465, 0xffffffff, 0x00070006, 891 0x2466, 0xffffffff, 0x000a0009, 892 0x2467, 0xffffffff, 0x00040003, 893 0x2468, 0xffffffff, 0x00060005, 894 0x2469, 0xffffffff, 0x00000009, 895 0x246a, 0xffffffff, 0x00080007, 896 0x246b, 0xffffffff, 0x000b000a, 897 0x246c, 0xffffffff, 0x00050004, 898 0x246d, 0xffffffff, 0x00070006, 899 0x246e, 0xffffffff, 0x0008000b, 900 0x246f, 0xffffffff, 0x000a0009, 901 0x2470, 0xffffffff, 0x000d000c, 902 0x2471, 0xffffffff, 0x00060005, 903 0x2472, 0xffffffff, 0x00080007, 904 0x2473, 0xffffffff, 0x0000000b, 905 0x2474, 0xffffffff, 0x000a0009, 906 0x2475, 0xffffffff, 0x000d000c, 907 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 908 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 909 mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080, 910 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 911 0x000c, 0xffffffff, 0x0000001c, 912 0x000d, 0x000f0000, 0x000f0000, 913 0x0583, 0xffffffff, 0x00000100, 914 0x0409, 0xffffffff, 0x00000100, 915 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104, 916 mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000, 917 mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000, 918 mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001, 919 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 920 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 921 0x3430, 0xfffffff0, 0x00000100, 922 0x3630, 0xfffffff0, 0x00000100, 923 }; 924 925 /* tahiti, pitcairn, verde */ 926 static const struct amdgpu_video_codec_info tahiti_video_codecs_encode_array[] = 927 { 928 { 929 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 930 .max_width = 2048, 931 .max_height = 1152, 932 .max_pixels_per_frame = 2048 * 1152, 933 .max_level = 0, 934 }, 935 }; 936 937 static const struct amdgpu_video_codecs tahiti_video_codecs_encode = 938 { 939 .codec_count = ARRAY_SIZE(tahiti_video_codecs_encode_array), 940 .codec_array = tahiti_video_codecs_encode_array, 941 }; 942 943 /* oland and hainan don't support encode */ 944 static const struct amdgpu_video_codecs hainan_video_codecs_encode = 945 { 946 .codec_count = 0, 947 .codec_array = NULL, 948 }; 949 950 /* tahiti, pitcairn, verde, oland */ 951 static const struct amdgpu_video_codec_info tahiti_video_codecs_decode_array[] = 952 { 953 { 954 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 955 .max_width = 2048, 956 .max_height = 1152, 957 .max_pixels_per_frame = 2048 * 1152, 958 .max_level = 3, 959 }, 960 { 961 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 962 .max_width = 2048, 963 .max_height = 1152, 964 .max_pixels_per_frame = 2048 * 1152, 965 .max_level = 5, 966 }, 967 { 968 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 969 .max_width = 2048, 970 .max_height = 1152, 971 .max_pixels_per_frame = 2048 * 1152, 972 .max_level = 41, 973 }, 974 { 975 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 976 .max_width = 2048, 977 .max_height = 1152, 978 .max_pixels_per_frame = 2048 * 1152, 979 .max_level = 4, 980 }, 981 }; 982 983 static const struct amdgpu_video_codecs tahiti_video_codecs_decode = 984 { 985 .codec_count = ARRAY_SIZE(tahiti_video_codecs_decode_array), 986 .codec_array = tahiti_video_codecs_decode_array, 987 }; 988 989 /* hainan doesn't support decode */ 990 static const struct amdgpu_video_codecs hainan_video_codecs_decode = 991 { 992 .codec_count = 0, 993 .codec_array = NULL, 994 }; 995 996 static int si_query_video_codecs(struct amdgpu_device *adev, bool encode, 997 const struct amdgpu_video_codecs **codecs) 998 { 999 switch (adev->asic_type) { 1000 case CHIP_VERDE: 1001 case CHIP_TAHITI: 1002 case CHIP_PITCAIRN: 1003 if (encode) 1004 *codecs = &tahiti_video_codecs_encode; 1005 else 1006 *codecs = &tahiti_video_codecs_decode; 1007 return 0; 1008 case CHIP_OLAND: 1009 if (encode) 1010 *codecs = &hainan_video_codecs_encode; 1011 else 1012 *codecs = &tahiti_video_codecs_decode; 1013 return 0; 1014 case CHIP_HAINAN: 1015 if (encode) 1016 *codecs = &hainan_video_codecs_encode; 1017 else 1018 *codecs = &hainan_video_codecs_decode; 1019 return 0; 1020 default: 1021 return -EINVAL; 1022 } 1023 } 1024 1025 static u32 si_pcie_rreg(struct amdgpu_device *adev, u32 reg) 1026 { 1027 unsigned long flags; 1028 u32 r; 1029 1030 spin_lock_irqsave(&adev->reg.pcie.lock, flags); 1031 WREG32(AMDGPU_PCIE_INDEX, reg); 1032 (void)RREG32(AMDGPU_PCIE_INDEX); 1033 r = RREG32(AMDGPU_PCIE_DATA); 1034 spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 1035 return r; 1036 } 1037 1038 static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 1039 { 1040 unsigned long flags; 1041 1042 spin_lock_irqsave(&adev->reg.pcie.lock, flags); 1043 WREG32(AMDGPU_PCIE_INDEX, reg); 1044 (void)RREG32(AMDGPU_PCIE_INDEX); 1045 WREG32(AMDGPU_PCIE_DATA, v); 1046 (void)RREG32(AMDGPU_PCIE_DATA); 1047 spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 1048 } 1049 1050 static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg) 1051 { 1052 unsigned long flags; 1053 u32 r; 1054 1055 spin_lock_irqsave(&adev->reg.pcie.lock, flags); 1056 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 1057 (void)RREG32(PCIE_PORT_INDEX); 1058 r = RREG32(PCIE_PORT_DATA); 1059 spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 1060 return r; 1061 } 1062 1063 static void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 1064 { 1065 unsigned long flags; 1066 1067 spin_lock_irqsave(&adev->reg.pcie.lock, flags); 1068 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 1069 (void)RREG32(PCIE_PORT_INDEX); 1070 WREG32(PCIE_PORT_DATA, (v)); 1071 (void)RREG32(PCIE_PORT_DATA); 1072 spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 1073 } 1074 1075 static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg) 1076 { 1077 unsigned long flags; 1078 u32 r; 1079 1080 spin_lock_irqsave(&adev->reg.smc.lock, flags); 1081 WREG32(mmSMC_IND_INDEX_0, (reg)); 1082 r = RREG32(mmSMC_IND_DATA_0); 1083 spin_unlock_irqrestore(&adev->reg.smc.lock, flags); 1084 return r; 1085 } 1086 1087 static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 1088 { 1089 unsigned long flags; 1090 1091 spin_lock_irqsave(&adev->reg.smc.lock, flags); 1092 WREG32(mmSMC_IND_INDEX_0, (reg)); 1093 WREG32(mmSMC_IND_DATA_0, (v)); 1094 spin_unlock_irqrestore(&adev->reg.smc.lock, flags); 1095 } 1096 1097 static u32 si_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 1098 { 1099 unsigned long flags; 1100 u32 r; 1101 1102 spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); 1103 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 1104 r = RREG32(mmUVD_CTX_DATA); 1105 spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); 1106 return r; 1107 } 1108 1109 static void si_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 1110 { 1111 unsigned long flags; 1112 1113 spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); 1114 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 1115 WREG32(mmUVD_CTX_DATA, (v)); 1116 spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); 1117 } 1118 1119 static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = { 1120 {mmGRBM_STATUS}, 1121 {mmGRBM_STATUS2}, 1122 {mmGRBM_STATUS_SE0}, 1123 {mmGRBM_STATUS_SE1}, 1124 {mmSRBM_STATUS}, 1125 {mmSRBM_STATUS2}, 1126 {mmDMA_STATUS_REG + DMA0_REGISTER_OFFSET}, 1127 {mmDMA_STATUS_REG + DMA1_REGISTER_OFFSET}, 1128 {mmCP_STAT}, 1129 {mmCP_STALLED_STAT1}, 1130 {mmCP_STALLED_STAT2}, 1131 {mmCP_STALLED_STAT3}, 1132 {mmGB_ADDR_CONFIG}, 1133 {mmMC_ARB_RAMCFG}, 1134 {mmGB_TILE_MODE0}, 1135 {mmGB_TILE_MODE1}, 1136 {mmGB_TILE_MODE2}, 1137 {mmGB_TILE_MODE3}, 1138 {mmGB_TILE_MODE4}, 1139 {mmGB_TILE_MODE5}, 1140 {mmGB_TILE_MODE6}, 1141 {mmGB_TILE_MODE7}, 1142 {mmGB_TILE_MODE8}, 1143 {mmGB_TILE_MODE9}, 1144 {mmGB_TILE_MODE10}, 1145 {mmGB_TILE_MODE11}, 1146 {mmGB_TILE_MODE12}, 1147 {mmGB_TILE_MODE13}, 1148 {mmGB_TILE_MODE14}, 1149 {mmGB_TILE_MODE15}, 1150 {mmGB_TILE_MODE16}, 1151 {mmGB_TILE_MODE17}, 1152 {mmGB_TILE_MODE18}, 1153 {mmGB_TILE_MODE19}, 1154 {mmGB_TILE_MODE20}, 1155 {mmGB_TILE_MODE21}, 1156 {mmGB_TILE_MODE22}, 1157 {mmGB_TILE_MODE23}, 1158 {mmGB_TILE_MODE24}, 1159 {mmGB_TILE_MODE25}, 1160 {mmGB_TILE_MODE26}, 1161 {mmGB_TILE_MODE27}, 1162 {mmGB_TILE_MODE28}, 1163 {mmGB_TILE_MODE29}, 1164 {mmGB_TILE_MODE30}, 1165 {mmGB_TILE_MODE31}, 1166 {mmCC_RB_BACKEND_DISABLE, true}, 1167 {mmGC_USER_RB_BACKEND_DISABLE, true}, 1168 {mmPA_SC_RASTER_CONFIG, true}, 1169 }; 1170 1171 static uint32_t si_get_register_value(struct amdgpu_device *adev, 1172 bool indexed, u32 se_num, 1173 u32 sh_num, u32 reg_offset) 1174 { 1175 if (indexed) { 1176 uint32_t val; 1177 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num; 1178 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; 1179 1180 switch (reg_offset) { 1181 case mmCC_RB_BACKEND_DISABLE: 1182 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable; 1183 case mmGC_USER_RB_BACKEND_DISABLE: 1184 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable; 1185 case mmPA_SC_RASTER_CONFIG: 1186 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config; 1187 } 1188 1189 mutex_lock(&adev->grbm_idx_mutex); 1190 if (se_num != 0xffffffff || sh_num != 0xffffffff) 1191 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); 1192 1193 val = RREG32(reg_offset); 1194 1195 if (se_num != 0xffffffff || sh_num != 0xffffffff) 1196 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1197 mutex_unlock(&adev->grbm_idx_mutex); 1198 return val; 1199 } else { 1200 unsigned idx; 1201 1202 switch (reg_offset) { 1203 case mmGB_ADDR_CONFIG: 1204 return adev->gfx.config.gb_addr_config; 1205 case mmMC_ARB_RAMCFG: 1206 return adev->gfx.config.mc_arb_ramcfg; 1207 case mmGB_TILE_MODE0: 1208 case mmGB_TILE_MODE1: 1209 case mmGB_TILE_MODE2: 1210 case mmGB_TILE_MODE3: 1211 case mmGB_TILE_MODE4: 1212 case mmGB_TILE_MODE5: 1213 case mmGB_TILE_MODE6: 1214 case mmGB_TILE_MODE7: 1215 case mmGB_TILE_MODE8: 1216 case mmGB_TILE_MODE9: 1217 case mmGB_TILE_MODE10: 1218 case mmGB_TILE_MODE11: 1219 case mmGB_TILE_MODE12: 1220 case mmGB_TILE_MODE13: 1221 case mmGB_TILE_MODE14: 1222 case mmGB_TILE_MODE15: 1223 case mmGB_TILE_MODE16: 1224 case mmGB_TILE_MODE17: 1225 case mmGB_TILE_MODE18: 1226 case mmGB_TILE_MODE19: 1227 case mmGB_TILE_MODE20: 1228 case mmGB_TILE_MODE21: 1229 case mmGB_TILE_MODE22: 1230 case mmGB_TILE_MODE23: 1231 case mmGB_TILE_MODE24: 1232 case mmGB_TILE_MODE25: 1233 case mmGB_TILE_MODE26: 1234 case mmGB_TILE_MODE27: 1235 case mmGB_TILE_MODE28: 1236 case mmGB_TILE_MODE29: 1237 case mmGB_TILE_MODE30: 1238 case mmGB_TILE_MODE31: 1239 idx = (reg_offset - mmGB_TILE_MODE0); 1240 return adev->gfx.config.tile_mode_array[idx]; 1241 default: 1242 return RREG32(reg_offset); 1243 } 1244 } 1245 } 1246 static int si_read_register(struct amdgpu_device *adev, u32 se_num, 1247 u32 sh_num, u32 reg_offset, u32 *value) 1248 { 1249 uint32_t i; 1250 1251 *value = 0; 1252 for (i = 0; i < ARRAY_SIZE(si_allowed_read_registers); i++) { 1253 bool indexed = si_allowed_read_registers[i].grbm_indexed; 1254 1255 if (reg_offset != si_allowed_read_registers[i].reg_offset) 1256 continue; 1257 1258 *value = si_get_register_value(adev, indexed, se_num, sh_num, 1259 reg_offset); 1260 return 0; 1261 } 1262 return -EINVAL; 1263 } 1264 1265 static bool si_read_disabled_bios(struct amdgpu_device *adev) 1266 { 1267 u32 bus_cntl; 1268 u32 d1vga_control = 0; 1269 u32 d2vga_control = 0; 1270 u32 vga_render_control = 0; 1271 u32 rom_cntl; 1272 bool r; 1273 1274 bus_cntl = RREG32(mmBUS_CNTL); 1275 if (adev->mode_info.num_crtc) { 1276 d1vga_control = RREG32(mmD1VGA_CONTROL); 1277 d2vga_control = RREG32(mmD2VGA_CONTROL); 1278 vga_render_control = RREG32(mmVGA_RENDER_CONTROL); 1279 } 1280 rom_cntl = RREG32(R600_ROM_CNTL); 1281 1282 /* enable the rom */ 1283 WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK)); 1284 if (adev->mode_info.num_crtc) { 1285 /* Disable VGA mode */ 1286 WREG32(mmD1VGA_CONTROL, 1287 (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK | 1288 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK))); 1289 WREG32(mmD2VGA_CONTROL, 1290 (d2vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK | 1291 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK))); 1292 WREG32(mmVGA_RENDER_CONTROL, 1293 (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK)); 1294 } 1295 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 1296 1297 r = amdgpu_read_bios(adev); 1298 1299 /* restore regs */ 1300 WREG32(mmBUS_CNTL, bus_cntl); 1301 if (adev->mode_info.num_crtc) { 1302 WREG32(mmD1VGA_CONTROL, d1vga_control); 1303 WREG32(mmD2VGA_CONTROL, d2vga_control); 1304 WREG32(mmVGA_RENDER_CONTROL, vga_render_control); 1305 } 1306 WREG32(R600_ROM_CNTL, rom_cntl); 1307 return r; 1308 } 1309 1310 #define mmROM_INDEX 0x2A 1311 #define mmROM_DATA 0x2B 1312 1313 static bool si_read_bios_from_rom(struct amdgpu_device *adev, 1314 u8 *bios, u32 length_bytes) 1315 { 1316 u32 *dw_ptr; 1317 u32 i, length_dw; 1318 1319 if (bios == NULL) 1320 return false; 1321 if (length_bytes == 0) 1322 return false; 1323 /* APU vbios image is part of sbios image */ 1324 if (adev->flags & AMD_IS_APU) 1325 return false; 1326 1327 dw_ptr = (u32 *)bios; 1328 length_dw = ALIGN(length_bytes, 4) / 4; 1329 /* set rom index to 0 */ 1330 WREG32(mmROM_INDEX, 0); 1331 for (i = 0; i < length_dw; i++) 1332 dw_ptr[i] = RREG32(mmROM_DATA); 1333 1334 return true; 1335 } 1336 1337 static void si_set_clk_bypass_mode(struct amdgpu_device *adev) 1338 { 1339 u32 tmp, i; 1340 1341 tmp = RREG32(mmCG_SPLL_FUNC_CNTL); 1342 tmp |= CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK; 1343 WREG32(mmCG_SPLL_FUNC_CNTL, tmp); 1344 1345 tmp = RREG32(mmCG_SPLL_FUNC_CNTL_2); 1346 tmp |= CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK; 1347 WREG32(mmCG_SPLL_FUNC_CNTL_2, tmp); 1348 1349 for (i = 0; i < adev->usec_timeout; i++) { 1350 if (RREG32(mmCG_SPLL_STATUS) & CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK) 1351 break; 1352 udelay(1); 1353 } 1354 1355 tmp = RREG32(mmCG_SPLL_FUNC_CNTL_2); 1356 tmp &= ~(CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK | 1357 CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK); 1358 WREG32(mmCG_SPLL_FUNC_CNTL_2, tmp); 1359 1360 tmp = RREG32(MPLL_CNTL_MODE); 1361 tmp &= ~MPLL_MCLK_SEL; 1362 WREG32(MPLL_CNTL_MODE, tmp); 1363 } 1364 1365 static void si_spll_powerdown(struct amdgpu_device *adev) 1366 { 1367 u32 tmp; 1368 1369 tmp = RREG32(mmSPLL_CNTL_MODE); 1370 tmp |= SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK; 1371 WREG32(mmSPLL_CNTL_MODE, tmp); 1372 1373 tmp = RREG32(mmCG_SPLL_FUNC_CNTL); 1374 tmp |= CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK; 1375 WREG32(mmCG_SPLL_FUNC_CNTL, tmp); 1376 1377 tmp = RREG32(mmCG_SPLL_FUNC_CNTL); 1378 tmp |= CG_SPLL_FUNC_CNTL__SPLL_SLEEP_MASK; 1379 WREG32(mmCG_SPLL_FUNC_CNTL, tmp); 1380 1381 tmp = RREG32(mmSPLL_CNTL_MODE); 1382 tmp &= ~SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK; 1383 WREG32(mmSPLL_CNTL_MODE, tmp); 1384 } 1385 1386 static int si_gpu_pci_config_reset(struct amdgpu_device *adev) 1387 { 1388 u32 i; 1389 int r = -EINVAL; 1390 1391 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 1392 1393 /* set mclk/sclk to bypass */ 1394 si_set_clk_bypass_mode(adev); 1395 /* powerdown spll */ 1396 si_spll_powerdown(adev); 1397 /* disable BM */ 1398 pci_clear_master(adev->pdev); 1399 /* reset */ 1400 amdgpu_device_pci_config_reset(adev); 1401 1402 udelay(100); 1403 1404 /* wait for asic to come out of reset */ 1405 for (i = 0; i < adev->usec_timeout; i++) { 1406 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) { 1407 /* enable BM */ 1408 pci_set_master(adev->pdev); 1409 adev->has_hw_reset = true; 1410 r = 0; 1411 break; 1412 } 1413 udelay(1); 1414 } 1415 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 1416 1417 return r; 1418 } 1419 1420 static int si_asic_supports_baco(struct amdgpu_device *adev) 1421 { 1422 return 0; 1423 } 1424 1425 static enum amd_reset_method 1426 si_asic_reset_method(struct amdgpu_device *adev) 1427 { 1428 if (amdgpu_reset_method == AMD_RESET_METHOD_PCI) 1429 return amdgpu_reset_method; 1430 else if (amdgpu_reset_method != AMD_RESET_METHOD_LEGACY && 1431 amdgpu_reset_method != -1) 1432 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 1433 amdgpu_reset_method); 1434 1435 return AMD_RESET_METHOD_LEGACY; 1436 } 1437 1438 static int si_asic_reset(struct amdgpu_device *adev) 1439 { 1440 int r; 1441 1442 switch (si_asic_reset_method(adev)) { 1443 case AMD_RESET_METHOD_PCI: 1444 dev_info(adev->dev, "PCI reset\n"); 1445 r = amdgpu_device_pci_reset(adev); 1446 break; 1447 default: 1448 dev_info(adev->dev, "PCI CONFIG reset\n"); 1449 r = si_gpu_pci_config_reset(adev); 1450 break; 1451 } 1452 1453 return r; 1454 } 1455 1456 static u32 si_get_config_memsize(struct amdgpu_device *adev) 1457 { 1458 return RREG32(mmCONFIG_MEMSIZE); 1459 } 1460 1461 static void si_vga_set_state(struct amdgpu_device *adev, bool state) 1462 { 1463 uint32_t temp; 1464 1465 temp = RREG32(mmCONFIG_CNTL); 1466 if (!state) { 1467 temp &= ~(1<<0); 1468 temp |= (1<<1); 1469 } else { 1470 temp &= ~(1<<1); 1471 } 1472 WREG32(mmCONFIG_CNTL, temp); 1473 } 1474 1475 static u32 si_get_xclk(struct amdgpu_device *adev) 1476 { 1477 u32 reference_clock = adev->clock.spll.reference_freq; 1478 u32 tmp; 1479 1480 tmp = RREG32(mmCG_CLKPIN_CNTL_2); 1481 if (tmp & CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK) 1482 return TCLK; 1483 1484 tmp = RREG32(mmCG_CLKPIN_CNTL); 1485 if (tmp & CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK) 1486 return reference_clock / 4; 1487 1488 return reference_clock; 1489 } 1490 1491 static void si_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 1492 { 1493 if (!ring || !ring->funcs->emit_wreg) { 1494 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); 1495 RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL); 1496 } else { 1497 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); 1498 } 1499 } 1500 1501 static void si_invalidate_hdp(struct amdgpu_device *adev, 1502 struct amdgpu_ring *ring) 1503 { 1504 if (!ring || !ring->funcs->emit_wreg) { 1505 WREG32(mmHDP_DEBUG0, 1); 1506 RREG32(mmHDP_DEBUG0); 1507 } else { 1508 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1); 1509 } 1510 } 1511 1512 static bool si_need_reset_on_init(struct amdgpu_device *adev) 1513 { 1514 return false; 1515 } 1516 1517 static int si_get_pcie_lanes(struct amdgpu_device *adev) 1518 { 1519 u32 link_width_cntl; 1520 1521 if (adev->flags & AMD_IS_APU) 1522 return 0; 1523 1524 link_width_cntl = RREG32_PCIE_PORT(ixPCIE_LC_LINK_WIDTH_CNTL); 1525 1526 switch ((link_width_cntl & PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT) { 1527 case LC_LINK_WIDTH_X1: 1528 return 1; 1529 case LC_LINK_WIDTH_X2: 1530 return 2; 1531 case LC_LINK_WIDTH_X4: 1532 return 4; 1533 case LC_LINK_WIDTH_X8: 1534 return 8; 1535 case LC_LINK_WIDTH_X0: 1536 case LC_LINK_WIDTH_X16: 1537 default: 1538 return 16; 1539 } 1540 } 1541 1542 static void si_set_pcie_lanes(struct amdgpu_device *adev, int lanes) 1543 { 1544 u32 link_width_cntl, mask; 1545 1546 if (adev->flags & AMD_IS_APU) 1547 return; 1548 1549 switch (lanes) { 1550 case 0: 1551 mask = LC_LINK_WIDTH_X0; 1552 break; 1553 case 1: 1554 mask = LC_LINK_WIDTH_X1; 1555 break; 1556 case 2: 1557 mask = LC_LINK_WIDTH_X2; 1558 break; 1559 case 4: 1560 mask = LC_LINK_WIDTH_X4; 1561 break; 1562 case 8: 1563 mask = LC_LINK_WIDTH_X8; 1564 break; 1565 case 16: 1566 mask = LC_LINK_WIDTH_X16; 1567 break; 1568 default: 1569 DRM_ERROR("invalid pcie lane request: %d\n", lanes); 1570 return; 1571 } 1572 1573 link_width_cntl = RREG32_PCIE_PORT(ixPCIE_LC_LINK_WIDTH_CNTL); 1574 link_width_cntl &= ~PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK; 1575 link_width_cntl |= mask << PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT; 1576 link_width_cntl |= (PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK | 1577 PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK); 1578 1579 WREG32_PCIE_PORT(ixPCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 1580 } 1581 1582 static void si_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 1583 uint64_t *count1) 1584 { 1585 uint32_t perfctr = 0; 1586 uint64_t cnt0_of, cnt1_of; 1587 int tmp; 1588 1589 /* This reports 0 on APUs, so return to avoid writing/reading registers 1590 * that may or may not be different from their GPU counterparts 1591 */ 1592 if (adev->flags & AMD_IS_APU) 1593 return; 1594 1595 /* Set the 2 events that we wish to watch, defined above */ 1596 /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */ 1597 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); 1598 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); 1599 1600 /* Write to enable desired perf counters */ 1601 WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr); 1602 /* Zero out and enable the perf counters 1603 * Write 0x5: 1604 * Bit 0 = Start all counters(1) 1605 * Bit 2 = Global counter reset enable(1) 1606 */ 1607 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005); 1608 1609 msleep(1000); 1610 1611 /* Load the shadow and disable the perf counters 1612 * Write 0x2: 1613 * Bit 0 = Stop counters(0) 1614 * Bit 1 = Load the shadow counters(1) 1615 */ 1616 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002); 1617 1618 /* Read register values to get any >32bit overflow */ 1619 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK); 1620 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); 1621 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); 1622 1623 /* Get the values and add the overflow */ 1624 *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); 1625 *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); 1626 } 1627 1628 static uint64_t si_get_pcie_replay_count(struct amdgpu_device *adev) 1629 { 1630 uint64_t nak_r, nak_g; 1631 1632 /* Get the number of NAKs received and generated */ 1633 nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK); 1634 nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED); 1635 1636 /* Add the total number of NAKs, i.e the number of replays */ 1637 return (nak_r + nak_g); 1638 } 1639 1640 static int si_uvd_send_upll_ctlreq(struct amdgpu_device *adev, 1641 unsigned cg_upll_func_cntl) 1642 { 1643 unsigned i; 1644 1645 /* Make sure UPLL_CTLREQ is deasserted */ 1646 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); 1647 1648 mdelay(10); 1649 1650 /* Assert UPLL_CTLREQ */ 1651 WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); 1652 1653 /* Wait for CTLACK and CTLACK2 to get asserted */ 1654 for (i = 0; i < SI_MAX_CTLACKS_ASSERTION_WAIT; ++i) { 1655 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; 1656 1657 if ((RREG32(cg_upll_func_cntl) & mask) == mask) 1658 break; 1659 mdelay(10); 1660 } 1661 1662 /* Deassert UPLL_CTLREQ */ 1663 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); 1664 1665 if (i == SI_MAX_CTLACKS_ASSERTION_WAIT) { 1666 DRM_ERROR("Timeout setting UVD clocks!\n"); 1667 return -ETIMEDOUT; 1668 } 1669 1670 return 0; 1671 } 1672 1673 static unsigned si_uvd_calc_upll_post_div(unsigned vco_freq, 1674 unsigned target_freq, 1675 unsigned pd_min, 1676 unsigned pd_even) 1677 { 1678 unsigned post_div = vco_freq / target_freq; 1679 1680 /* Adjust to post divider minimum value */ 1681 if (post_div < pd_min) 1682 post_div = pd_min; 1683 1684 /* We alway need a frequency less than or equal the target */ 1685 if ((vco_freq / post_div) > target_freq) 1686 post_div += 1; 1687 1688 /* Post dividers above a certain value must be even */ 1689 if (post_div > pd_even && post_div % 2) 1690 post_div += 1; 1691 1692 return post_div; 1693 } 1694 1695 /** 1696 * si_calc_upll_dividers - calc UPLL clock dividers 1697 * 1698 * @adev: amdgpu_device pointer 1699 * @vclk: wanted VCLK 1700 * @dclk: wanted DCLK 1701 * @vco_min: minimum VCO frequency 1702 * @vco_max: maximum VCO frequency 1703 * @fb_factor: factor to multiply vco freq with 1704 * @fb_mask: limit and bitmask for feedback divider 1705 * @pd_min: post divider minimum 1706 * @pd_max: post divider maximum 1707 * @pd_even: post divider must be even above this value 1708 * @optimal_fb_div: resulting feedback divider 1709 * @optimal_vclk_div: resulting vclk post divider 1710 * @optimal_dclk_div: resulting dclk post divider 1711 * 1712 * Calculate dividers for UVDs UPLL (except APUs). 1713 * Returns zero on success; -EINVAL on error. 1714 */ 1715 static int si_calc_upll_dividers(struct amdgpu_device *adev, 1716 unsigned vclk, unsigned dclk, 1717 unsigned vco_min, unsigned vco_max, 1718 unsigned fb_factor, unsigned fb_mask, 1719 unsigned pd_min, unsigned pd_max, 1720 unsigned pd_even, 1721 unsigned *optimal_fb_div, 1722 unsigned *optimal_vclk_div, 1723 unsigned *optimal_dclk_div) 1724 { 1725 unsigned vco_freq, ref_freq = adev->clock.spll.reference_freq; 1726 1727 /* Start off with something large */ 1728 unsigned optimal_score = ~0; 1729 1730 /* Loop through vco from low to high */ 1731 vco_min = max(max(vco_min, vclk), dclk); 1732 for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) { 1733 uint64_t fb_div = (uint64_t)vco_freq * fb_factor; 1734 unsigned vclk_div, dclk_div, score; 1735 1736 do_div(fb_div, ref_freq); 1737 1738 /* fb div out of range ? */ 1739 if (fb_div > fb_mask) 1740 break; /* It can oly get worse */ 1741 1742 fb_div &= fb_mask; 1743 1744 /* Calc vclk divider with current vco freq */ 1745 vclk_div = si_uvd_calc_upll_post_div(vco_freq, vclk, 1746 pd_min, pd_even); 1747 if (vclk_div > pd_max) 1748 break; /* vco is too big, it has to stop */ 1749 1750 /* Calc dclk divider with current vco freq */ 1751 dclk_div = si_uvd_calc_upll_post_div(vco_freq, dclk, 1752 pd_min, pd_even); 1753 if (dclk_div > pd_max) 1754 break; /* vco is too big, it has to stop */ 1755 1756 /* Calc score with current vco freq */ 1757 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); 1758 1759 /* Determine if this vco setting is better than current optimal settings */ 1760 if (score < optimal_score) { 1761 *optimal_fb_div = fb_div; 1762 *optimal_vclk_div = vclk_div; 1763 *optimal_dclk_div = dclk_div; 1764 optimal_score = score; 1765 if (optimal_score == 0) 1766 break; /* It can't get better than this */ 1767 } 1768 } 1769 1770 /* Did we found a valid setup ? */ 1771 if (optimal_score == ~0) 1772 return -EINVAL; 1773 1774 return 0; 1775 } 1776 1777 static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 1778 { 1779 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; 1780 int r; 1781 1782 /* Bypass vclk and dclk with bclk */ 1783 WREG32_P(CG_UPLL_FUNC_CNTL_2, 1784 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1), 1785 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); 1786 1787 /* Put PLL in bypass mode */ 1788 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); 1789 1790 if (!vclk || !dclk) { 1791 /* Keep the Bypass mode */ 1792 return 0; 1793 } 1794 1795 r = si_calc_upll_dividers(adev, vclk, dclk, 125000, 250000, 1796 16384, 0x03FFFFFF, 0, 128, 5, 1797 &fb_div, &vclk_div, &dclk_div); 1798 if (r) 1799 return r; 1800 1801 /* Set RESET_ANTI_MUX to 0 */ 1802 WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK); 1803 1804 /* Set VCO_MODE to 1 */ 1805 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK); 1806 1807 /* Disable sleep mode */ 1808 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK); 1809 1810 /* Deassert UPLL_RESET */ 1811 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); 1812 1813 mdelay(1); 1814 1815 r = si_uvd_send_upll_ctlreq(adev, CG_UPLL_FUNC_CNTL); 1816 if (r) 1817 return r; 1818 1819 /* Assert UPLL_RESET again */ 1820 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); 1821 1822 /* Disable spread spectrum. */ 1823 WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK); 1824 1825 /* Set feedback divider */ 1826 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK); 1827 1828 /* Set ref divider to 0 */ 1829 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK); 1830 1831 if (fb_div < 307200) 1832 WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9); 1833 else 1834 WREG32_P(CG_UPLL_FUNC_CNTL_4, 1835 UPLL_SPARE_ISPARE9, 1836 ~UPLL_SPARE_ISPARE9); 1837 1838 /* Set PDIV_A and PDIV_B */ 1839 WREG32_P(CG_UPLL_FUNC_CNTL_2, 1840 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div), 1841 ~(UPLL_PDIV_A_MASK | UPLL_PDIV_B_MASK)); 1842 1843 /* Give the PLL some time to settle */ 1844 mdelay(15); 1845 1846 /* Deassert PLL_RESET */ 1847 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); 1848 1849 mdelay(15); 1850 1851 /* Switch from bypass mode to normal mode */ 1852 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); 1853 1854 r = si_uvd_send_upll_ctlreq(adev, CG_UPLL_FUNC_CNTL); 1855 if (r) 1856 return r; 1857 1858 /* Switch VCLK and DCLK selection */ 1859 WREG32_P(CG_UPLL_FUNC_CNTL_2, 1860 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2), 1861 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); 1862 1863 mdelay(100); 1864 1865 return 0; 1866 } 1867 1868 static int si_vce_send_vcepll_ctlreq(struct amdgpu_device *adev) 1869 { 1870 unsigned i; 1871 1872 /* Make sure VCEPLL_CTLREQ is deasserted */ 1873 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); 1874 1875 mdelay(10); 1876 1877 /* Assert UPLL_CTLREQ */ 1878 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); 1879 1880 /* Wait for CTLACK and CTLACK2 to get asserted */ 1881 for (i = 0; i < SI_MAX_CTLACKS_ASSERTION_WAIT; ++i) { 1882 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; 1883 1884 if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask) 1885 break; 1886 mdelay(10); 1887 } 1888 1889 /* Deassert UPLL_CTLREQ */ 1890 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); 1891 1892 if (i == SI_MAX_CTLACKS_ASSERTION_WAIT) { 1893 DRM_ERROR("Timeout setting VCE clocks!\n"); 1894 return -ETIMEDOUT; 1895 } 1896 1897 return 0; 1898 } 1899 1900 static int si_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 1901 { 1902 unsigned fb_div = 0, evclk_div = 0, ecclk_div = 0; 1903 int r; 1904 1905 /* Bypass evclk and ecclk with bclk */ 1906 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2, 1907 EVCLK_SRC_SEL(1) | ECCLK_SRC_SEL(1), 1908 ~(EVCLK_SRC_SEL_MASK | ECCLK_SRC_SEL_MASK)); 1909 1910 /* Put PLL in bypass mode */ 1911 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_BYPASS_EN_MASK, 1912 ~VCEPLL_BYPASS_EN_MASK); 1913 1914 if (!evclk || !ecclk) { 1915 /* 1916 * On some chips, the PLL takes way too long to get out of 1917 * sleep mode, causing a timeout waiting on CTLACK/CTLACK2. 1918 * Leave the PLL running in bypass mode. 1919 */ 1920 if (adev->pdev->device == 0x6780) 1921 return 0; 1922 1923 /* Keep the Bypass mode, put PLL to sleep */ 1924 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK, 1925 ~VCEPLL_SLEEP_MASK); 1926 return 0; 1927 } 1928 1929 r = si_calc_upll_dividers(adev, evclk, ecclk, 125000, 250000, 1930 16384, 0x03FFFFFF, 0, 128, 5, 1931 &fb_div, &evclk_div, &ecclk_div); 1932 if (r) 1933 return r; 1934 1935 /* Set RESET_ANTI_MUX to 0 */ 1936 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK); 1937 1938 /* Set VCO_MODE to 1 */ 1939 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_VCO_MODE_MASK, 1940 ~VCEPLL_VCO_MODE_MASK); 1941 1942 /* Toggle VCEPLL_SLEEP to 1 then back to 0 */ 1943 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK, 1944 ~VCEPLL_SLEEP_MASK); 1945 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_SLEEP_MASK); 1946 1947 /* Deassert VCEPLL_RESET */ 1948 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK); 1949 1950 mdelay(1); 1951 1952 r = si_vce_send_vcepll_ctlreq(adev); 1953 if (r) 1954 return r; 1955 1956 /* Assert VCEPLL_RESET again */ 1957 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_RESET_MASK, ~VCEPLL_RESET_MASK); 1958 1959 /* Disable spread spectrum. */ 1960 WREG32_SMC_P(CG_VCEPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK); 1961 1962 /* Set feedback divider */ 1963 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_3, 1964 VCEPLL_FB_DIV(fb_div), 1965 ~VCEPLL_FB_DIV_MASK); 1966 1967 /* Set ref divider to 0 */ 1968 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_REF_DIV_MASK); 1969 1970 /* Set PDIV_A and PDIV_B */ 1971 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2, 1972 VCEPLL_PDIV_A(evclk_div) | VCEPLL_PDIV_B(ecclk_div), 1973 ~(VCEPLL_PDIV_A_MASK | VCEPLL_PDIV_B_MASK)); 1974 1975 /* Give the PLL some time to settle */ 1976 mdelay(15); 1977 1978 /* Deassert PLL_RESET */ 1979 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK); 1980 1981 mdelay(15); 1982 1983 /* Switch from bypass mode to normal mode */ 1984 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_BYPASS_EN_MASK); 1985 1986 r = si_vce_send_vcepll_ctlreq(adev); 1987 if (r) 1988 return r; 1989 1990 /* Switch VCLK and DCLK selection */ 1991 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2, 1992 EVCLK_SRC_SEL(16) | ECCLK_SRC_SEL(16), 1993 ~(EVCLK_SRC_SEL_MASK | ECCLK_SRC_SEL_MASK)); 1994 1995 mdelay(100); 1996 1997 return 0; 1998 } 1999 2000 static const struct amdgpu_asic_funcs si_asic_funcs = 2001 { 2002 .read_disabled_bios = &si_read_disabled_bios, 2003 .read_bios_from_rom = &si_read_bios_from_rom, 2004 .read_register = &si_read_register, 2005 .reset = &si_asic_reset, 2006 .reset_method = &si_asic_reset_method, 2007 .set_vga_state = &si_vga_set_state, 2008 .get_xclk = &si_get_xclk, 2009 .set_uvd_clocks = &si_set_uvd_clocks, 2010 .set_vce_clocks = &si_set_vce_clocks, 2011 .get_pcie_lanes = &si_get_pcie_lanes, 2012 .set_pcie_lanes = &si_set_pcie_lanes, 2013 .get_config_memsize = &si_get_config_memsize, 2014 .flush_hdp = &si_flush_hdp, 2015 .invalidate_hdp = &si_invalidate_hdp, 2016 .get_pcie_usage = &si_get_pcie_usage, 2017 .need_reset_on_init = &si_need_reset_on_init, 2018 .get_pcie_replay_count = &si_get_pcie_replay_count, 2019 .supports_baco = &si_asic_supports_baco, 2020 .query_video_codecs = &si_query_video_codecs, 2021 }; 2022 2023 static uint32_t si_get_rev_id(struct amdgpu_device *adev) 2024 { 2025 return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK) 2026 >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT; 2027 } 2028 2029 static int si_common_early_init(struct amdgpu_ip_block *ip_block) 2030 { 2031 struct amdgpu_device *adev = ip_block->adev; 2032 2033 adev->reg.smc.rreg = si_smc_rreg; 2034 adev->reg.smc.wreg = si_smc_wreg; 2035 adev->reg.pcie.rreg = &si_pcie_rreg; 2036 adev->reg.pcie.wreg = &si_pcie_wreg; 2037 adev->reg.pcie.port_rreg = &si_pciep_rreg; 2038 adev->reg.pcie.port_wreg = &si_pciep_wreg; 2039 adev->reg.uvd_ctx.rreg = &si_uvd_ctx_rreg; 2040 adev->reg.uvd_ctx.wreg = &si_uvd_ctx_wreg; 2041 2042 adev->asic_funcs = &si_asic_funcs; 2043 2044 adev->rev_id = si_get_rev_id(adev); 2045 adev->external_rev_id = 0xFF; 2046 switch (adev->asic_type) { 2047 case CHIP_TAHITI: 2048 adev->cg_flags = 2049 AMD_CG_SUPPORT_GFX_MGCG | 2050 AMD_CG_SUPPORT_GFX_MGLS | 2051 /*AMD_CG_SUPPORT_GFX_CGCG |*/ 2052 AMD_CG_SUPPORT_GFX_CGLS | 2053 AMD_CG_SUPPORT_GFX_CGTS | 2054 AMD_CG_SUPPORT_GFX_CP_LS | 2055 AMD_CG_SUPPORT_MC_MGCG | 2056 AMD_CG_SUPPORT_SDMA_MGCG | 2057 AMD_CG_SUPPORT_BIF_LS | 2058 AMD_CG_SUPPORT_VCE_MGCG | 2059 AMD_CG_SUPPORT_UVD_MGCG | 2060 AMD_CG_SUPPORT_HDP_LS | 2061 AMD_CG_SUPPORT_HDP_MGCG; 2062 adev->pg_flags = 0; 2063 adev->external_rev_id = (adev->rev_id == 0) ? 1 : 2064 (adev->rev_id == 1) ? 5 : 6; 2065 break; 2066 case CHIP_PITCAIRN: 2067 adev->cg_flags = 2068 AMD_CG_SUPPORT_GFX_MGCG | 2069 AMD_CG_SUPPORT_GFX_MGLS | 2070 /*AMD_CG_SUPPORT_GFX_CGCG |*/ 2071 AMD_CG_SUPPORT_GFX_CGLS | 2072 AMD_CG_SUPPORT_GFX_CGTS | 2073 AMD_CG_SUPPORT_GFX_CP_LS | 2074 AMD_CG_SUPPORT_GFX_RLC_LS | 2075 AMD_CG_SUPPORT_MC_LS | 2076 AMD_CG_SUPPORT_MC_MGCG | 2077 AMD_CG_SUPPORT_SDMA_MGCG | 2078 AMD_CG_SUPPORT_BIF_LS | 2079 AMD_CG_SUPPORT_VCE_MGCG | 2080 AMD_CG_SUPPORT_UVD_MGCG | 2081 AMD_CG_SUPPORT_HDP_LS | 2082 AMD_CG_SUPPORT_HDP_MGCG; 2083 adev->pg_flags = 0; 2084 adev->external_rev_id = adev->rev_id + 20; 2085 break; 2086 2087 case CHIP_VERDE: 2088 adev->cg_flags = 2089 AMD_CG_SUPPORT_GFX_MGCG | 2090 AMD_CG_SUPPORT_GFX_MGLS | 2091 AMD_CG_SUPPORT_GFX_CGLS | 2092 AMD_CG_SUPPORT_GFX_CGTS | 2093 AMD_CG_SUPPORT_GFX_CGTS_LS | 2094 AMD_CG_SUPPORT_GFX_CP_LS | 2095 AMD_CG_SUPPORT_MC_LS | 2096 AMD_CG_SUPPORT_MC_MGCG | 2097 AMD_CG_SUPPORT_SDMA_MGCG | 2098 AMD_CG_SUPPORT_SDMA_LS | 2099 AMD_CG_SUPPORT_BIF_LS | 2100 AMD_CG_SUPPORT_VCE_MGCG | 2101 AMD_CG_SUPPORT_UVD_MGCG | 2102 AMD_CG_SUPPORT_HDP_LS | 2103 AMD_CG_SUPPORT_HDP_MGCG; 2104 adev->pg_flags = 0; 2105 //??? 2106 adev->external_rev_id = adev->rev_id + 40; 2107 break; 2108 case CHIP_OLAND: 2109 adev->cg_flags = 2110 AMD_CG_SUPPORT_GFX_MGCG | 2111 AMD_CG_SUPPORT_GFX_MGLS | 2112 /*AMD_CG_SUPPORT_GFX_CGCG |*/ 2113 AMD_CG_SUPPORT_GFX_CGLS | 2114 AMD_CG_SUPPORT_GFX_CGTS | 2115 AMD_CG_SUPPORT_GFX_CP_LS | 2116 AMD_CG_SUPPORT_GFX_RLC_LS | 2117 AMD_CG_SUPPORT_MC_LS | 2118 AMD_CG_SUPPORT_MC_MGCG | 2119 AMD_CG_SUPPORT_SDMA_MGCG | 2120 AMD_CG_SUPPORT_BIF_LS | 2121 AMD_CG_SUPPORT_UVD_MGCG | 2122 AMD_CG_SUPPORT_HDP_LS | 2123 AMD_CG_SUPPORT_HDP_MGCG; 2124 adev->pg_flags = 0; 2125 adev->external_rev_id = 60; 2126 break; 2127 case CHIP_HAINAN: 2128 adev->cg_flags = 2129 AMD_CG_SUPPORT_GFX_MGCG | 2130 AMD_CG_SUPPORT_GFX_MGLS | 2131 /*AMD_CG_SUPPORT_GFX_CGCG |*/ 2132 AMD_CG_SUPPORT_GFX_CGLS | 2133 AMD_CG_SUPPORT_GFX_CGTS | 2134 AMD_CG_SUPPORT_GFX_CP_LS | 2135 AMD_CG_SUPPORT_GFX_RLC_LS | 2136 AMD_CG_SUPPORT_MC_LS | 2137 AMD_CG_SUPPORT_MC_MGCG | 2138 AMD_CG_SUPPORT_SDMA_MGCG | 2139 AMD_CG_SUPPORT_BIF_LS | 2140 AMD_CG_SUPPORT_HDP_LS | 2141 AMD_CG_SUPPORT_HDP_MGCG; 2142 adev->pg_flags = 0; 2143 adev->external_rev_id = 70; 2144 break; 2145 2146 default: 2147 return -EINVAL; 2148 } 2149 2150 return 0; 2151 } 2152 2153 static void si_init_golden_registers(struct amdgpu_device *adev) 2154 { 2155 switch (adev->asic_type) { 2156 case CHIP_TAHITI: 2157 amdgpu_device_program_register_sequence(adev, 2158 tahiti_golden_registers, 2159 ARRAY_SIZE(tahiti_golden_registers)); 2160 amdgpu_device_program_register_sequence(adev, 2161 tahiti_golden_rlc_registers, 2162 ARRAY_SIZE(tahiti_golden_rlc_registers)); 2163 amdgpu_device_program_register_sequence(adev, 2164 tahiti_mgcg_cgcg_init, 2165 ARRAY_SIZE(tahiti_mgcg_cgcg_init)); 2166 amdgpu_device_program_register_sequence(adev, 2167 tahiti_golden_registers2, 2168 ARRAY_SIZE(tahiti_golden_registers2)); 2169 break; 2170 case CHIP_PITCAIRN: 2171 amdgpu_device_program_register_sequence(adev, 2172 pitcairn_golden_registers, 2173 ARRAY_SIZE(pitcairn_golden_registers)); 2174 amdgpu_device_program_register_sequence(adev, 2175 pitcairn_golden_rlc_registers, 2176 ARRAY_SIZE(pitcairn_golden_rlc_registers)); 2177 amdgpu_device_program_register_sequence(adev, 2178 pitcairn_mgcg_cgcg_init, 2179 ARRAY_SIZE(pitcairn_mgcg_cgcg_init)); 2180 break; 2181 case CHIP_VERDE: 2182 amdgpu_device_program_register_sequence(adev, 2183 verde_golden_registers, 2184 ARRAY_SIZE(verde_golden_registers)); 2185 amdgpu_device_program_register_sequence(adev, 2186 verde_golden_rlc_registers, 2187 ARRAY_SIZE(verde_golden_rlc_registers)); 2188 amdgpu_device_program_register_sequence(adev, 2189 verde_mgcg_cgcg_init, 2190 ARRAY_SIZE(verde_mgcg_cgcg_init)); 2191 amdgpu_device_program_register_sequence(adev, 2192 verde_pg_init, 2193 ARRAY_SIZE(verde_pg_init)); 2194 break; 2195 case CHIP_OLAND: 2196 amdgpu_device_program_register_sequence(adev, 2197 oland_golden_registers, 2198 ARRAY_SIZE(oland_golden_registers)); 2199 amdgpu_device_program_register_sequence(adev, 2200 oland_golden_rlc_registers, 2201 ARRAY_SIZE(oland_golden_rlc_registers)); 2202 amdgpu_device_program_register_sequence(adev, 2203 oland_mgcg_cgcg_init, 2204 ARRAY_SIZE(oland_mgcg_cgcg_init)); 2205 break; 2206 case CHIP_HAINAN: 2207 amdgpu_device_program_register_sequence(adev, 2208 hainan_golden_registers, 2209 ARRAY_SIZE(hainan_golden_registers)); 2210 amdgpu_device_program_register_sequence(adev, 2211 hainan_golden_registers2, 2212 ARRAY_SIZE(hainan_golden_registers2)); 2213 amdgpu_device_program_register_sequence(adev, 2214 hainan_mgcg_cgcg_init, 2215 ARRAY_SIZE(hainan_mgcg_cgcg_init)); 2216 break; 2217 2218 2219 default: 2220 BUG(); 2221 } 2222 } 2223 2224 static void si_pcie_gen3_enable(struct amdgpu_device *adev) 2225 { 2226 struct pci_dev *root = adev->pdev->bus->self; 2227 u32 speed_cntl, current_data_rate; 2228 int i; 2229 u16 tmp16; 2230 2231 if (pci_is_root_bus(adev->pdev->bus)) 2232 return; 2233 2234 if (amdgpu_pcie_gen2 == 0) 2235 return; 2236 2237 if (adev->flags & AMD_IS_APU) 2238 return; 2239 2240 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 2241 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 2242 return; 2243 2244 speed_cntl = RREG32_PCIE_PORT(ixPCIE_LC_SPEED_CNTL); 2245 current_data_rate = (speed_cntl & PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) >> 2246 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; 2247 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { 2248 if (current_data_rate == 2) { 2249 drm_info(adev_to_drm(adev), "PCIE gen 3 link speeds already enabled\n"); 2250 return; 2251 } 2252 drm_info(adev_to_drm(adev), "enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n"); 2253 } else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) { 2254 if (current_data_rate == 1) { 2255 drm_info(adev_to_drm(adev), "PCIE gen 2 link speeds already enabled\n"); 2256 return; 2257 } 2258 drm_info(adev_to_drm(adev), "enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n"); 2259 } 2260 2261 if (!pci_is_pcie(root) || !pci_is_pcie(adev->pdev)) 2262 return; 2263 2264 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { 2265 if (current_data_rate != 2) { 2266 u16 bridge_cfg, gpu_cfg; 2267 u16 bridge_cfg2, gpu_cfg2; 2268 u32 max_lw, current_lw, tmp; 2269 2270 pcie_capability_set_word(root, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD); 2271 pcie_capability_set_word(adev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD); 2272 2273 tmp = RREG32_PCIE(ixPCIE_LC_STATUS1); 2274 max_lw = (tmp & PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >> PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT; 2275 current_lw = (tmp & PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK) >> PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT; 2276 2277 if (current_lw < max_lw) { 2278 tmp = RREG32_PCIE_PORT(ixPCIE_LC_LINK_WIDTH_CNTL); 2279 if (tmp & PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK) { 2280 tmp &= ~(PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK | PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK); 2281 tmp |= (max_lw << PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT); 2282 tmp |= PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK | PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK | PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK; 2283 WREG32_PCIE_PORT(ixPCIE_LC_LINK_WIDTH_CNTL, tmp); 2284 } 2285 } 2286 2287 for (i = 0; i < 10; i++) { 2288 pcie_capability_read_word(adev->pdev, 2289 PCI_EXP_DEVSTA, 2290 &tmp16); 2291 if (tmp16 & PCI_EXP_DEVSTA_TRPND) 2292 break; 2293 2294 pcie_capability_read_word(root, PCI_EXP_LNKCTL, 2295 &bridge_cfg); 2296 pcie_capability_read_word(adev->pdev, 2297 PCI_EXP_LNKCTL, 2298 &gpu_cfg); 2299 2300 pcie_capability_read_word(root, PCI_EXP_LNKCTL2, 2301 &bridge_cfg2); 2302 pcie_capability_read_word(adev->pdev, 2303 PCI_EXP_LNKCTL2, 2304 &gpu_cfg2); 2305 2306 tmp = RREG32_PCIE_PORT(ixPCIE_LC_CNTL4); 2307 tmp |= PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK; 2308 WREG32_PCIE_PORT(ixPCIE_LC_CNTL4, tmp); 2309 2310 tmp = RREG32_PCIE_PORT(ixPCIE_LC_CNTL4); 2311 tmp |= PCIE_LC_CNTL4__LC_REDO_EQ_MASK; 2312 WREG32_PCIE_PORT(ixPCIE_LC_CNTL4, tmp); 2313 2314 mdelay(100); 2315 2316 pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL, 2317 PCI_EXP_LNKCTL_HAWD, 2318 bridge_cfg & 2319 PCI_EXP_LNKCTL_HAWD); 2320 pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL, 2321 PCI_EXP_LNKCTL_HAWD, 2322 gpu_cfg & 2323 PCI_EXP_LNKCTL_HAWD); 2324 2325 pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL2, 2326 PCI_EXP_LNKCTL2_ENTER_COMP | 2327 PCI_EXP_LNKCTL2_TX_MARGIN, 2328 bridge_cfg2 & 2329 (PCI_EXP_LNKCTL2_ENTER_COMP | 2330 PCI_EXP_LNKCTL2_TX_MARGIN)); 2331 pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL2, 2332 PCI_EXP_LNKCTL2_ENTER_COMP | 2333 PCI_EXP_LNKCTL2_TX_MARGIN, 2334 gpu_cfg2 & 2335 (PCI_EXP_LNKCTL2_ENTER_COMP | 2336 PCI_EXP_LNKCTL2_TX_MARGIN)); 2337 2338 tmp = RREG32_PCIE_PORT(ixPCIE_LC_CNTL4); 2339 tmp &= ~PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK; 2340 WREG32_PCIE_PORT(ixPCIE_LC_CNTL4, tmp); 2341 } 2342 } 2343 } 2344 2345 speed_cntl |= PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK | PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK; 2346 speed_cntl &= ~PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK; 2347 WREG32_PCIE_PORT(ixPCIE_LC_SPEED_CNTL, speed_cntl); 2348 2349 tmp16 = 0; 2350 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 2351 tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */ 2352 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 2353 tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */ 2354 else 2355 tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */ 2356 pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL2, 2357 PCI_EXP_LNKCTL2_TLS, tmp16); 2358 2359 speed_cntl = RREG32_PCIE_PORT(ixPCIE_LC_SPEED_CNTL); 2360 speed_cntl |= PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK; 2361 WREG32_PCIE_PORT(ixPCIE_LC_SPEED_CNTL, speed_cntl); 2362 2363 for (i = 0; i < adev->usec_timeout; i++) { 2364 speed_cntl = RREG32_PCIE_PORT(ixPCIE_LC_SPEED_CNTL); 2365 if ((speed_cntl & PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK) == 0) 2366 break; 2367 udelay(1); 2368 } 2369 } 2370 2371 static inline u32 si_pif_phy0_rreg(struct amdgpu_device *adev, u32 reg) 2372 { 2373 unsigned long flags; 2374 u32 r; 2375 2376 spin_lock_irqsave(&adev->reg.pcie.lock, flags); 2377 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2378 r = RREG32(EVERGREEN_PIF_PHY0_DATA); 2379 spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 2380 return r; 2381 } 2382 2383 static inline void si_pif_phy0_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 2384 { 2385 unsigned long flags; 2386 2387 spin_lock_irqsave(&adev->reg.pcie.lock, flags); 2388 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2389 WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); 2390 spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 2391 } 2392 2393 static inline u32 si_pif_phy1_rreg(struct amdgpu_device *adev, u32 reg) 2394 { 2395 unsigned long flags; 2396 u32 r; 2397 2398 spin_lock_irqsave(&adev->reg.pcie.lock, flags); 2399 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2400 r = RREG32(EVERGREEN_PIF_PHY1_DATA); 2401 spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 2402 return r; 2403 } 2404 2405 static inline void si_pif_phy1_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 2406 { 2407 unsigned long flags; 2408 2409 spin_lock_irqsave(&adev->reg.pcie.lock, flags); 2410 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2411 WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); 2412 spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 2413 } 2414 static void si_program_aspm(struct amdgpu_device *adev) 2415 { 2416 u32 data, orig; 2417 bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false; 2418 bool disable_clkreq = false; 2419 2420 if (!amdgpu_device_should_use_aspm(adev)) 2421 return; 2422 2423 orig = data = RREG32_PCIE_PORT(ixPCIE_LC_N_FTS_CNTL); 2424 data &= ~PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK; 2425 data |= (0x24 << PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT) | PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK; 2426 if (orig != data) 2427 WREG32_PCIE_PORT(ixPCIE_LC_N_FTS_CNTL, data); 2428 2429 orig = data = RREG32_PCIE_PORT(ixPCIE_LC_CNTL3); 2430 data |= PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK; 2431 if (orig != data) 2432 WREG32_PCIE_PORT(ixPCIE_LC_CNTL3, data); 2433 2434 orig = data = RREG32_PCIE(ixPCIE_P_CNTL); 2435 data |= PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK; 2436 if (orig != data) 2437 WREG32_PCIE(ixPCIE_P_CNTL, data); 2438 2439 orig = data = RREG32_PCIE_PORT(ixPCIE_LC_CNTL); 2440 data &= ~(PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK | PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK); 2441 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 2442 if (!disable_l0s) 2443 data |= (7 << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT); 2444 2445 if (!disable_l1) { 2446 data |= (7 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT); 2447 data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 2448 if (orig != data) 2449 WREG32_PCIE_PORT(ixPCIE_LC_CNTL, data); 2450 2451 if (!disable_plloff_in_l1) { 2452 bool clk_req_support; 2453 2454 orig = data = si_pif_phy0_rreg(adev,ixPB0_PIF_PWRDOWN_0); 2455 data &= ~(PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK | PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK); 2456 data |= (7 << PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT) | (7 << PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT); 2457 if (orig != data) 2458 si_pif_phy0_wreg(adev,ixPB0_PIF_PWRDOWN_0, data); 2459 2460 orig = data = si_pif_phy0_rreg(adev,ixPB0_PIF_PWRDOWN_1); 2461 data &= ~(PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK | PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK); 2462 data |= (7 << PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT) | (7 << PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT); 2463 if (orig != data) 2464 si_pif_phy0_wreg(adev,ixPB0_PIF_PWRDOWN_1, data); 2465 2466 orig = data = si_pif_phy1_rreg(adev,ixPB1_PIF_PWRDOWN_0); 2467 data &= ~(PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK | PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK); 2468 data |= (7 << PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT) | (7 << PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT); 2469 if (orig != data) 2470 si_pif_phy1_wreg(adev,ixPB1_PIF_PWRDOWN_0, data); 2471 2472 orig = data = si_pif_phy1_rreg(adev,ixPB1_PIF_PWRDOWN_1); 2473 data &= ~(PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK | PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK); 2474 data |= (7 << PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT) | (7 << PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT); 2475 if (orig != data) 2476 si_pif_phy1_wreg(adev,ixPB1_PIF_PWRDOWN_1, data); 2477 2478 if ((adev->asic_type != CHIP_OLAND) && (adev->asic_type != CHIP_HAINAN)) { 2479 orig = data = si_pif_phy0_rreg(adev,ixPB0_PIF_PWRDOWN_0); 2480 data &= ~PB0_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0_MASK; 2481 if (orig != data) 2482 si_pif_phy0_wreg(adev,ixPB0_PIF_PWRDOWN_0, data); 2483 2484 orig = data = si_pif_phy0_rreg(adev,ixPB0_PIF_PWRDOWN_1); 2485 data &= ~PB0_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1_MASK; 2486 if (orig != data) 2487 si_pif_phy0_wreg(adev,ixPB0_PIF_PWRDOWN_1, data); 2488 2489 orig = data = si_pif_phy0_rreg(adev,ixPB0_PIF_PWRDOWN_2); 2490 data &= ~PB0_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2_MASK; 2491 if (orig != data) 2492 si_pif_phy0_wreg(adev,ixPB0_PIF_PWRDOWN_2, data); 2493 2494 orig = data = si_pif_phy0_rreg(adev,ixPB0_PIF_PWRDOWN_3); 2495 data &= ~PB0_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3_MASK; 2496 if (orig != data) 2497 si_pif_phy0_wreg(adev,ixPB0_PIF_PWRDOWN_3, data); 2498 2499 orig = data = si_pif_phy1_rreg(adev,ixPB1_PIF_PWRDOWN_0); 2500 data &= ~PB1_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0_MASK; 2501 if (orig != data) 2502 si_pif_phy1_wreg(adev,ixPB1_PIF_PWRDOWN_0, data); 2503 2504 orig = data = si_pif_phy1_rreg(adev,ixPB1_PIF_PWRDOWN_1); 2505 data &= ~PB1_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1_MASK; 2506 if (orig != data) 2507 si_pif_phy1_wreg(adev,ixPB1_PIF_PWRDOWN_1, data); 2508 2509 orig = data = si_pif_phy1_rreg(adev,ixPB1_PIF_PWRDOWN_2); 2510 data &= ~PB1_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2_MASK; 2511 if (orig != data) 2512 si_pif_phy1_wreg(adev,ixPB1_PIF_PWRDOWN_2, data); 2513 2514 orig = data = si_pif_phy1_rreg(adev,ixPB1_PIF_PWRDOWN_3); 2515 data &= ~PB1_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3_MASK; 2516 if (orig != data) 2517 si_pif_phy1_wreg(adev,ixPB1_PIF_PWRDOWN_3, data); 2518 } 2519 orig = data = RREG32_PCIE_PORT(ixPCIE_LC_LINK_WIDTH_CNTL); 2520 data &= ~PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK; 2521 data |= (3 << PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT); 2522 if (orig != data) 2523 WREG32_PCIE_PORT(ixPCIE_LC_LINK_WIDTH_CNTL, data); 2524 2525 orig = data = si_pif_phy0_rreg(adev,ixPB0_PIF_CNTL); 2526 data &= ~PB0_PIF_CNTL__LS2_EXIT_TIME_MASK; 2527 if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type == CHIP_HAINAN)) 2528 data |= (5 << PB0_PIF_CNTL__LS2_EXIT_TIME__SHIFT); 2529 if (orig != data) 2530 si_pif_phy0_wreg(adev,ixPB0_PIF_CNTL, data); 2531 2532 orig = data = si_pif_phy1_rreg(adev,ixPB1_PIF_CNTL); 2533 data &= ~PB1_PIF_CNTL__LS2_EXIT_TIME_MASK; 2534 if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type == CHIP_HAINAN)) 2535 data |= (5 << PB1_PIF_CNTL__LS2_EXIT_TIME__SHIFT); 2536 if (orig != data) 2537 si_pif_phy1_wreg(adev,ixPB1_PIF_CNTL, data); 2538 2539 if (!disable_clkreq && 2540 !pci_is_root_bus(adev->pdev->bus)) { 2541 struct pci_dev *root = adev->pdev->bus->self; 2542 u32 lnkcap; 2543 2544 clk_req_support = false; 2545 pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap); 2546 if (lnkcap & PCI_EXP_LNKCAP_CLKPM) 2547 clk_req_support = true; 2548 } else { 2549 clk_req_support = false; 2550 } 2551 2552 if (clk_req_support) { 2553 orig = data = RREG32_PCIE_PORT(ixPCIE_LC_CNTL2); 2554 data |= PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK | PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK; 2555 if (orig != data) 2556 WREG32_PCIE_PORT(ixPCIE_LC_CNTL2, data); 2557 2558 orig = data = RREG32(mmTHM_CLK_CNTL); 2559 data &= ~(THM_CLK_CNTL__CMON_CLK_SEL_MASK | THM_CLK_CNTL__TMON_CLK_SEL_MASK); 2560 data |= (1 << THM_CLK_CNTL__CMON_CLK_SEL__SHIFT) | (1 << THM_CLK_CNTL__TMON_CLK_SEL__SHIFT); 2561 if (orig != data) 2562 WREG32(mmTHM_CLK_CNTL, data); 2563 2564 orig = data = RREG32(mmMISC_CLK_CNTL); 2565 data &= ~(MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL_MASK | MISC_CLK_CNTL__ZCLK_SEL_MASK); 2566 data |= (1 << MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL__SHIFT) | (1 << MISC_CLK_CNTL__ZCLK_SEL__SHIFT); 2567 if (orig != data) 2568 WREG32(mmMISC_CLK_CNTL, data); 2569 2570 orig = data = RREG32(mmCG_CLKPIN_CNTL); 2571 data &= ~CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK; 2572 if (orig != data) 2573 WREG32(mmCG_CLKPIN_CNTL, data); 2574 2575 orig = data = RREG32(mmCG_CLKPIN_CNTL_2); 2576 data &= ~CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK; 2577 if (orig != data) 2578 WREG32(mmCG_CLKPIN_CNTL_2, data); 2579 2580 orig = data = RREG32(mmMPLL_BYPASSCLK_SEL); 2581 data &= ~MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK; 2582 data |= 4 << MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT; 2583 if (orig != data) 2584 WREG32(mmMPLL_BYPASSCLK_SEL, data); 2585 2586 orig = data = RREG32(mmSPLL_CNTL_MODE); 2587 data &= ~SPLL_CNTL_MODE__SPLL_REFCLK_SEL_MASK; 2588 if (orig != data) 2589 WREG32(mmSPLL_CNTL_MODE, data); 2590 } 2591 } 2592 } else { 2593 if (orig != data) 2594 WREG32_PCIE_PORT(ixPCIE_LC_CNTL, data); 2595 } 2596 2597 orig = data = RREG32_PCIE(ixPCIE_CNTL2); 2598 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK | PCIE_CNTL2__MST_MEM_LS_EN_MASK | PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK; 2599 if (orig != data) 2600 WREG32_PCIE(ixPCIE_CNTL2, data); 2601 2602 if (!disable_l0s) { 2603 data = RREG32_PCIE_PORT(ixPCIE_LC_N_FTS_CNTL); 2604 if((data & PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) == PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) { 2605 data = RREG32_PCIE(ixPCIE_LC_STATUS1); 2606 if ((data & PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK) && (data & PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK)) { 2607 orig = data = RREG32_PCIE_PORT(ixPCIE_LC_CNTL); 2608 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; 2609 if (orig != data) 2610 WREG32_PCIE_PORT(ixPCIE_LC_CNTL, data); 2611 } 2612 } 2613 } 2614 } 2615 2616 static void si_fix_pci_max_read_req_size(struct amdgpu_device *adev) 2617 { 2618 int readrq; 2619 u16 v; 2620 2621 readrq = pcie_get_readrq(adev->pdev); 2622 v = ffs(readrq) - 8; 2623 if ((v == 0) || (v == 6) || (v == 7)) 2624 pcie_set_readrq(adev->pdev, 512); 2625 } 2626 2627 static int si_common_hw_init(struct amdgpu_ip_block *ip_block) 2628 { 2629 struct amdgpu_device *adev = ip_block->adev; 2630 2631 si_fix_pci_max_read_req_size(adev); 2632 si_init_golden_registers(adev); 2633 si_pcie_gen3_enable(adev); 2634 si_program_aspm(adev); 2635 2636 return 0; 2637 } 2638 2639 static int si_common_hw_fini(struct amdgpu_ip_block *ip_block) 2640 { 2641 return 0; 2642 } 2643 2644 static int si_common_resume(struct amdgpu_ip_block *ip_block) 2645 { 2646 return si_common_hw_init(ip_block); 2647 } 2648 2649 static bool si_common_is_idle(struct amdgpu_ip_block *ip_block) 2650 { 2651 return true; 2652 } 2653 2654 static int si_common_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2655 enum amd_clockgating_state state) 2656 { 2657 return 0; 2658 } 2659 2660 static int si_common_set_powergating_state(struct amdgpu_ip_block *ip_block, 2661 enum amd_powergating_state state) 2662 { 2663 return 0; 2664 } 2665 2666 static const struct amd_ip_funcs si_common_ip_funcs = { 2667 .name = "si_common", 2668 .early_init = si_common_early_init, 2669 .hw_init = si_common_hw_init, 2670 .hw_fini = si_common_hw_fini, 2671 .resume = si_common_resume, 2672 .is_idle = si_common_is_idle, 2673 .set_clockgating_state = si_common_set_clockgating_state, 2674 .set_powergating_state = si_common_set_powergating_state, 2675 }; 2676 2677 static const struct amdgpu_ip_block_version si_common_ip_block = 2678 { 2679 .type = AMD_IP_BLOCK_TYPE_COMMON, 2680 .major = 1, 2681 .minor = 0, 2682 .rev = 0, 2683 .funcs = &si_common_ip_funcs, 2684 }; 2685 2686 int si_set_ip_blocks(struct amdgpu_device *adev) 2687 { 2688 switch (adev->asic_type) { 2689 case CHIP_VERDE: 2690 case CHIP_TAHITI: 2691 case CHIP_PITCAIRN: 2692 amdgpu_device_ip_block_add(adev, &si_common_ip_block); 2693 amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block); 2694 amdgpu_device_ip_block_add(adev, &si_ih_ip_block); 2695 amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block); 2696 amdgpu_device_ip_block_add(adev, &si_dma_ip_block); 2697 amdgpu_device_ip_block_add(adev, &si_smu_ip_block); 2698 if (adev->enable_virtual_display) 2699 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2700 #if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_SI) 2701 else if (amdgpu_device_has_dc_support(adev)) 2702 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2703 #endif 2704 else 2705 amdgpu_device_ip_block_add(adev, &dce_v6_0_ip_block); 2706 amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); 2707 amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); 2708 break; 2709 case CHIP_OLAND: 2710 amdgpu_device_ip_block_add(adev, &si_common_ip_block); 2711 amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block); 2712 amdgpu_device_ip_block_add(adev, &si_ih_ip_block); 2713 amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block); 2714 amdgpu_device_ip_block_add(adev, &si_dma_ip_block); 2715 amdgpu_device_ip_block_add(adev, &si_smu_ip_block); 2716 if (adev->enable_virtual_display) 2717 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2718 #if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_SI) 2719 else if (amdgpu_device_has_dc_support(adev)) 2720 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2721 #endif 2722 else 2723 amdgpu_device_ip_block_add(adev, &dce_v6_4_ip_block); 2724 amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); 2725 break; 2726 case CHIP_HAINAN: 2727 amdgpu_device_ip_block_add(adev, &si_common_ip_block); 2728 amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block); 2729 amdgpu_device_ip_block_add(adev, &si_ih_ip_block); 2730 amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block); 2731 amdgpu_device_ip_block_add(adev, &si_dma_ip_block); 2732 amdgpu_device_ip_block_add(adev, &si_smu_ip_block); 2733 if (adev->enable_virtual_display) 2734 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2735 break; 2736 default: 2737 BUG(); 2738 } 2739 return 0; 2740 } 2741 2742