1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_12_0_0_offset.h" 34 #include "gc/gc_12_0_0_sh_mask.h" 35 #include "hdp/hdp_6_0_0_offset.h" 36 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 37 38 #include "soc15_common.h" 39 #include "soc15.h" 40 #include "sdma_v6_0_0_pkt_open.h" 41 #include "nbio_v4_3.h" 42 #include "sdma_common.h" 43 #include "sdma_v7_0.h" 44 #include "v12_structs.h" 45 46 MODULE_FIRMWARE("amdgpu/sdma_7_0_0.bin"); 47 MODULE_FIRMWARE("amdgpu/sdma_7_0_1.bin"); 48 49 #define SDMA1_REG_OFFSET 0x600 50 #define SDMA0_HYP_DEC_REG_START 0x5880 51 #define SDMA0_HYP_DEC_REG_END 0x589a 52 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 53 54 /*define for compression field for sdma7*/ 55 #define SDMA_PKT_CONSTANT_FILL_HEADER_compress_offset 0 56 #define SDMA_PKT_CONSTANT_FILL_HEADER_compress_mask 0x00000001 57 #define SDMA_PKT_CONSTANT_FILL_HEADER_compress_shift 16 58 #define SDMA_PKT_CONSTANT_FILL_HEADER_COMPRESS(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_compress_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_compress_shift) 59 60 static const struct amdgpu_hwip_reg_entry sdma_reg_list_7_0[] = { 61 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS_REG), 62 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS1_REG), 63 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS2_REG), 64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS3_REG), 65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS4_REG), 66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS5_REG), 67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS6_REG), 68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UCODE_REV), 69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH_HI), 70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH), 71 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_STATUS), 72 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_STATUS), 73 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK0), 74 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK1), 75 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK0), 76 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK1), 77 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_CNTL), 78 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR), 79 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR_HI), 80 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR), 81 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR_HI), 82 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_OFFSET), 83 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_LO), 84 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_HI), 85 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_CNTL), 86 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_RPTR), 87 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_SUB_REMAIN), 88 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_DUMMY_REG), 89 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE_STATUS0), 90 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_CNTL), 91 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR), 92 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR_HI), 93 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR), 94 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR_HI), 95 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_OFFSET), 96 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_LO), 97 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_HI), 98 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_RPTR), 99 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_SUB_REMAIN), 100 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_DUMMY_REG), 101 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_CNTL), 102 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR), 103 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR_HI), 104 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR), 105 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR_HI), 106 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_OFFSET), 107 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_LO), 108 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_HI), 109 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_RPTR), 110 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_SUB_REMAIN), 111 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_DUMMY_REG), 112 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_INT_STATUS), 113 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_VM_CNTL), 114 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 115 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_CHICKEN_BITS), 116 }; 117 118 static void sdma_v7_0_set_ring_funcs(struct amdgpu_device *adev); 119 static void sdma_v7_0_set_buffer_funcs(struct amdgpu_device *adev); 120 static void sdma_v7_0_set_vm_pte_funcs(struct amdgpu_device *adev); 121 static void sdma_v7_0_set_irq_funcs(struct amdgpu_device *adev); 122 static int sdma_v7_0_start(struct amdgpu_device *adev); 123 124 static u32 sdma_v7_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 125 { 126 u32 base; 127 128 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 129 internal_offset <= SDMA0_HYP_DEC_REG_END) { 130 base = adev->reg_offset[GC_HWIP][0][1]; 131 if (instance != 0) 132 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance; 133 } else { 134 base = adev->reg_offset[GC_HWIP][0][0]; 135 if (instance == 1) 136 internal_offset += SDMA1_REG_OFFSET; 137 } 138 139 return base + internal_offset; 140 } 141 142 static unsigned sdma_v7_0_ring_init_cond_exec(struct amdgpu_ring *ring, 143 uint64_t addr) 144 { 145 unsigned ret; 146 147 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE)); 148 amdgpu_ring_write(ring, lower_32_bits(addr)); 149 amdgpu_ring_write(ring, upper_32_bits(addr)); 150 amdgpu_ring_write(ring, 1); 151 /* this is the offset we need patch later */ 152 ret = ring->wptr & ring->buf_mask; 153 /* insert dummy here and patch it later */ 154 amdgpu_ring_write(ring, 0); 155 156 return ret; 157 } 158 159 /** 160 * sdma_v7_0_ring_get_rptr - get the current read pointer 161 * 162 * @ring: amdgpu ring pointer 163 * 164 * Get the current rptr from the hardware. 165 */ 166 static uint64_t sdma_v7_0_ring_get_rptr(struct amdgpu_ring *ring) 167 { 168 u64 *rptr; 169 170 /* XXX check if swapping is necessary on BE */ 171 rptr = (u64 *)ring->rptr_cpu_addr; 172 173 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 174 return ((*rptr) >> 2); 175 } 176 177 /** 178 * sdma_v7_0_ring_get_wptr - get the current write pointer 179 * 180 * @ring: amdgpu ring pointer 181 * 182 * Get the current wptr from the hardware. 183 */ 184 static uint64_t sdma_v7_0_ring_get_wptr(struct amdgpu_ring *ring) 185 { 186 u64 wptr = 0; 187 188 if (ring->use_doorbell) { 189 /* XXX check if swapping is necessary on BE */ 190 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 191 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 192 } 193 194 return wptr >> 2; 195 } 196 197 /** 198 * sdma_v7_0_ring_set_wptr - commit the write pointer 199 * 200 * @ring: amdgpu ring pointer 201 * 202 * Write the wptr back to the hardware. 203 */ 204 static void sdma_v7_0_ring_set_wptr(struct amdgpu_ring *ring) 205 { 206 struct amdgpu_device *adev = ring->adev; 207 uint32_t *wptr_saved; 208 uint32_t *is_queue_unmap; 209 uint64_t aggregated_db_index; 210 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_DMA].mqd_size; 211 212 DRM_DEBUG("Setting write pointer\n"); 213 214 if (ring->is_mes_queue) { 215 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 216 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 217 sizeof(uint32_t)); 218 aggregated_db_index = 219 amdgpu_mes_get_aggregated_doorbell_index(adev, 220 ring->hw_prio); 221 222 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 223 ring->wptr << 2); 224 *wptr_saved = ring->wptr << 2; 225 if (*is_queue_unmap) { 226 WDOORBELL64(aggregated_db_index, ring->wptr << 2); 227 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 228 ring->doorbell_index, ring->wptr << 2); 229 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 230 } else { 231 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 232 ring->doorbell_index, ring->wptr << 2); 233 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 234 } 235 } else { 236 if (ring->use_doorbell) { 237 DRM_DEBUG("Using doorbell -- " 238 "wptr_offs == 0x%08x " 239 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 240 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 241 ring->wptr_offs, 242 lower_32_bits(ring->wptr << 2), 243 upper_32_bits(ring->wptr << 2)); 244 /* XXX check if swapping is necessary on BE */ 245 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 246 ring->wptr << 2); 247 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 248 ring->doorbell_index, ring->wptr << 2); 249 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 250 } else { 251 DRM_DEBUG("Not using doorbell -- " 252 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 253 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 254 ring->me, 255 lower_32_bits(ring->wptr << 2), 256 ring->me, 257 upper_32_bits(ring->wptr << 2)); 258 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, 259 ring->me, 260 regSDMA0_QUEUE0_RB_WPTR), 261 lower_32_bits(ring->wptr << 2)); 262 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, 263 ring->me, 264 regSDMA0_QUEUE0_RB_WPTR_HI), 265 upper_32_bits(ring->wptr << 2)); 266 } 267 } 268 } 269 270 static void sdma_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 271 { 272 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 273 int i; 274 275 for (i = 0; i < count; i++) 276 if (sdma && sdma->burst_nop && (i == 0)) 277 amdgpu_ring_write(ring, ring->funcs->nop | 278 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 279 else 280 amdgpu_ring_write(ring, ring->funcs->nop); 281 } 282 283 /** 284 * sdma_v7_0_ring_emit_ib - Schedule an IB on the DMA engine 285 * 286 * @ring: amdgpu ring pointer 287 * @job: job to retrieve vmid from 288 * @ib: IB object to schedule 289 * @flags: unused 290 * 291 * Schedule an IB in the DMA ring. 292 */ 293 static void sdma_v7_0_ring_emit_ib(struct amdgpu_ring *ring, 294 struct amdgpu_job *job, 295 struct amdgpu_ib *ib, 296 uint32_t flags) 297 { 298 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 299 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 300 301 /* An IB packet must end on a 8 DW boundary--the next dword 302 * must be on a 8-dword boundary. Our IB packet below is 6 303 * dwords long, thus add x number of NOPs, such that, in 304 * modular arithmetic, 305 * wptr + 6 + x = 8k, k >= 0, which in C is, 306 * (wptr + 6 + x) % 8 = 0. 307 * The expression below, is a solution of x. 308 */ 309 sdma_v7_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 310 311 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) | 312 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 313 /* base must be 32 byte aligned */ 314 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 315 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 316 amdgpu_ring_write(ring, ib->length_dw); 317 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 318 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 319 } 320 321 /** 322 * sdma_v7_0_ring_emit_mem_sync - flush the IB by graphics cache rinse 323 * 324 * @ring: amdgpu ring pointer 325 * 326 * flush the IB by graphics cache rinse. 327 */ 328 static void sdma_v7_0_ring_emit_mem_sync(struct amdgpu_ring *ring) 329 { 330 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV | 331 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 332 SDMA_GCR_GLI_INV(1); 333 334 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 335 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ)); 336 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 337 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 338 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 339 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 340 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 341 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 342 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 343 } 344 345 346 /** 347 * sdma_v7_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 348 * 349 * @ring: amdgpu ring pointer 350 * 351 * Emit an hdp flush packet on the requested DMA ring. 352 */ 353 static void sdma_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 354 { 355 struct amdgpu_device *adev = ring->adev; 356 u32 ref_and_mask = 0; 357 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 358 359 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 360 361 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 362 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 363 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 364 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 365 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 366 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 367 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 368 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 369 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 370 } 371 372 /** 373 * sdma_v7_0_ring_emit_fence - emit a fence on the DMA ring 374 * 375 * @ring: amdgpu ring pointer 376 * @addr: address 377 * @seq: fence seq number 378 * @flags: fence flags 379 * 380 * Add a DMA fence packet to the ring to write 381 * the fence seq number and DMA trap packet to generate 382 * an interrupt if needed. 383 */ 384 static void sdma_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 385 unsigned flags) 386 { 387 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 388 /* write the fence */ 389 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 390 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 391 /* zero in first two bits */ 392 BUG_ON(addr & 0x3); 393 amdgpu_ring_write(ring, lower_32_bits(addr)); 394 amdgpu_ring_write(ring, upper_32_bits(addr)); 395 amdgpu_ring_write(ring, lower_32_bits(seq)); 396 397 /* optionally write high bits as well */ 398 if (write64bit) { 399 addr += 4; 400 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 401 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 402 /* zero in first two bits */ 403 BUG_ON(addr & 0x3); 404 amdgpu_ring_write(ring, lower_32_bits(addr)); 405 amdgpu_ring_write(ring, upper_32_bits(addr)); 406 amdgpu_ring_write(ring, upper_32_bits(seq)); 407 } 408 409 if (flags & AMDGPU_FENCE_FLAG_INT) { 410 uint32_t ctx = ring->is_mes_queue ? 411 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0; 412 /* generate an interrupt */ 413 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP)); 414 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx)); 415 } 416 } 417 418 /** 419 * sdma_v7_0_gfx_stop - stop the gfx async dma engines 420 * 421 * @adev: amdgpu_device pointer 422 * 423 * Stop the gfx async dma ring buffers. 424 */ 425 static void sdma_v7_0_gfx_stop(struct amdgpu_device *adev) 426 { 427 u32 rb_cntl, ib_cntl; 428 int i; 429 430 for (i = 0; i < adev->sdma.num_instances; i++) { 431 rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 432 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0); 433 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 434 ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 435 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0); 436 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 437 } 438 } 439 440 /** 441 * sdma_v7_0_rlc_stop - stop the compute async dma engines 442 * 443 * @adev: amdgpu_device pointer 444 * 445 * Stop the compute async dma queues. 446 */ 447 static void sdma_v7_0_rlc_stop(struct amdgpu_device *adev) 448 { 449 /* XXX todo */ 450 } 451 452 /** 453 * sdma_v7_0_ctx_switch_enable - stop the async dma engines context switch 454 * 455 * @adev: amdgpu_device pointer 456 * @enable: enable/disable the DMA MEs context switch. 457 * 458 * Halt or unhalt the async dma engines context switch. 459 */ 460 static void sdma_v7_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 461 { 462 } 463 464 /** 465 * sdma_v7_0_enable - stop the async dma engines 466 * 467 * @adev: amdgpu_device pointer 468 * @enable: enable/disable the DMA MEs. 469 * 470 * Halt or unhalt the async dma engines. 471 */ 472 static void sdma_v7_0_enable(struct amdgpu_device *adev, bool enable) 473 { 474 u32 mcu_cntl; 475 int i; 476 477 if (!enable) { 478 sdma_v7_0_gfx_stop(adev); 479 sdma_v7_0_rlc_stop(adev); 480 } 481 482 if (amdgpu_sriov_vf(adev)) 483 return; 484 485 for (i = 0; i < adev->sdma.num_instances; i++) { 486 mcu_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL)); 487 mcu_cntl = REG_SET_FIELD(mcu_cntl, SDMA0_MCU_CNTL, HALT, enable ? 0 : 1); 488 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), mcu_cntl); 489 } 490 } 491 492 /** 493 * sdma_v7_0_gfx_resume_instance - start/restart a certain sdma engine 494 * 495 * @adev: amdgpu_device pointer 496 * @i: instance 497 * @restore: used to restore wptr when restart 498 * 499 * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr. 500 * Return 0 for success. 501 */ 502 static int sdma_v7_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore) 503 { 504 struct amdgpu_ring *ring; 505 u32 rb_cntl, ib_cntl; 506 u32 rb_bufsz; 507 u32 doorbell; 508 u32 doorbell_offset; 509 u32 temp; 510 u64 wptr_gpu_addr; 511 int r; 512 513 ring = &adev->sdma.instance[i].ring; 514 515 /* Set ring buffer size in dwords */ 516 rb_bufsz = order_base_2(ring->ring_size / 4); 517 rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 518 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); 519 #ifdef __BIG_ENDIAN 520 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1); 521 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, 522 RPTR_WRITEBACK_SWAP_ENABLE, 1); 523 #endif 524 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1); 525 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 526 527 /* Initialize the ring buffer's read and write pointers */ 528 if (restore) { 529 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2)); 530 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2)); 531 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2)); 532 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); 533 } else { 534 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0); 535 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0); 536 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0); 537 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0); 538 } 539 /* setup the wptr shadow polling */ 540 wptr_gpu_addr = ring->wptr_gpu_addr; 541 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO), 542 lower_32_bits(wptr_gpu_addr)); 543 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI), 544 upper_32_bits(wptr_gpu_addr)); 545 546 /* set the wb address whether it's enabled or not */ 547 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI), 548 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 549 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO), 550 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 551 552 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 553 if (amdgpu_sriov_vf(adev)) 554 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 1); 555 else 556 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0); 557 558 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, MCU_WPTR_POLL_ENABLE, 1); 559 560 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8); 561 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40); 562 563 if (!restore) 564 ring->wptr = 0; 565 566 /* before programing wptr to a less value, need set minor_ptr_update first */ 567 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1); 568 569 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 570 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2); 571 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 572 } 573 574 doorbell = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL)); 575 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET)); 576 577 if (ring->use_doorbell) { 578 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 579 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET, 580 OFFSET, ring->doorbell_index); 581 } else { 582 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0); 583 } 584 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell); 585 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset); 586 587 if (i == 0) 588 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 589 ring->doorbell_index, 590 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances); 591 592 if (amdgpu_sriov_vf(adev)) 593 sdma_v7_0_ring_set_wptr(ring); 594 595 /* set minor_ptr_update to 0 after wptr programed */ 596 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0); 597 598 /* Set up sdma hang watchdog */ 599 temp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL)); 600 /* 100ms per unit */ 601 temp = REG_SET_FIELD(temp, SDMA0_WATCHDOG_CNTL, QUEUE_HANG_COUNT, 602 max(adev->usec_timeout/100000, 1)); 603 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), temp); 604 605 /* Set up RESP_MODE to non-copy addresses */ 606 temp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL)); 607 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 608 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 609 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp); 610 611 /* program default cache read and write policy */ 612 temp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE)); 613 /* clean read policy and write policy bits */ 614 temp &= 0xFF0FFF; 615 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | 616 (CACHE_WRITE_POLICY_L2__DEFAULT << 14)); 617 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp); 618 619 if (!amdgpu_sriov_vf(adev)) { 620 /* unhalt engine */ 621 temp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL)); 622 temp = REG_SET_FIELD(temp, SDMA0_MCU_CNTL, HALT, 0); 623 temp = REG_SET_FIELD(temp, SDMA0_MCU_CNTL, RESET, 0); 624 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), temp); 625 } 626 627 /* enable DMA RB */ 628 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1); 629 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 630 631 ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 632 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1); 633 #ifdef __BIG_ENDIAN 634 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1); 635 #endif 636 /* enable DMA IBs */ 637 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 638 ring->sched.ready = true; 639 640 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 641 sdma_v7_0_ctx_switch_enable(adev, true); 642 sdma_v7_0_enable(adev, true); 643 } 644 645 r = amdgpu_ring_test_helper(ring); 646 if (r) 647 ring->sched.ready = false; 648 649 return r; 650 } 651 652 /** 653 * sdma_v7_0_gfx_resume - setup and start the async dma engines 654 * 655 * @adev: amdgpu_device pointer 656 * 657 * Set up the gfx DMA ring buffers and enable them. 658 * Returns 0 for success, error for failure. 659 */ 660 static int sdma_v7_0_gfx_resume(struct amdgpu_device *adev) 661 { 662 int i, r; 663 664 for (i = 0; i < adev->sdma.num_instances; i++) { 665 r = sdma_v7_0_gfx_resume_instance(adev, i, false); 666 if (r) 667 return r; 668 } 669 670 return 0; 671 672 } 673 674 /** 675 * sdma_v7_0_rlc_resume - setup and start the async dma engines 676 * 677 * @adev: amdgpu_device pointer 678 * 679 * Set up the compute DMA queues and enable them. 680 * Returns 0 for success, error for failure. 681 */ 682 static int sdma_v7_0_rlc_resume(struct amdgpu_device *adev) 683 { 684 return 0; 685 } 686 687 static void sdma_v12_0_free_ucode_buffer(struct amdgpu_device *adev) 688 { 689 int i; 690 691 for (i = 0; i < adev->sdma.num_instances; i++) { 692 amdgpu_bo_free_kernel(&adev->sdma.instance[i].sdma_fw_obj, 693 &adev->sdma.instance[i].sdma_fw_gpu_addr, 694 (void **)&adev->sdma.instance[i].sdma_fw_ptr); 695 } 696 } 697 698 /** 699 * sdma_v7_0_load_microcode - load the sDMA ME ucode 700 * 701 * @adev: amdgpu_device pointer 702 * 703 * Loads the sDMA0/1 ucode. 704 * Returns 0 for success, -EINVAL if the ucode is not available. 705 */ 706 static int sdma_v7_0_load_microcode(struct amdgpu_device *adev) 707 { 708 const struct sdma_firmware_header_v3_0 *hdr; 709 const __le32 *fw_data; 710 u32 fw_size; 711 uint32_t tmp, sdma_status, ic_op_cntl; 712 int i, r, j; 713 714 /* halt the MEs */ 715 sdma_v7_0_enable(adev, false); 716 717 if (!adev->sdma.instance[0].fw) 718 return -EINVAL; 719 720 hdr = (const struct sdma_firmware_header_v3_0 *) 721 adev->sdma.instance[0].fw->data; 722 amdgpu_ucode_print_sdma_hdr(&hdr->header); 723 724 fw_data = (const __le32 *)(adev->sdma.instance[0].fw->data + 725 le32_to_cpu(hdr->ucode_offset_bytes)); 726 fw_size = le32_to_cpu(hdr->ucode_size_bytes); 727 728 for (i = 0; i < adev->sdma.num_instances; i++) { 729 r = amdgpu_bo_create_reserved(adev, fw_size, 730 PAGE_SIZE, 731 AMDGPU_GEM_DOMAIN_VRAM, 732 &adev->sdma.instance[i].sdma_fw_obj, 733 &adev->sdma.instance[i].sdma_fw_gpu_addr, 734 (void **)&adev->sdma.instance[i].sdma_fw_ptr); 735 if (r) { 736 dev_err(adev->dev, "(%d) failed to create sdma ucode bo\n", r); 737 return r; 738 } 739 740 memcpy(adev->sdma.instance[i].sdma_fw_ptr, fw_data, fw_size); 741 742 amdgpu_bo_kunmap(adev->sdma.instance[i].sdma_fw_obj); 743 amdgpu_bo_unreserve(adev->sdma.instance[i].sdma_fw_obj); 744 745 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_CNTL)); 746 tmp = REG_SET_FIELD(tmp, SDMA0_IC_CNTL, GPA, 0); 747 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_CNTL), tmp); 748 749 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_BASE_LO), 750 lower_32_bits(adev->sdma.instance[i].sdma_fw_gpu_addr)); 751 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_BASE_HI), 752 upper_32_bits(adev->sdma.instance[i].sdma_fw_gpu_addr)); 753 754 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL)); 755 tmp = REG_SET_FIELD(tmp, SDMA0_IC_OP_CNTL, PRIME_ICACHE, 1); 756 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL), tmp); 757 758 /* Wait for sdma ucode init complete */ 759 for (j = 0; j < adev->usec_timeout; j++) { 760 ic_op_cntl = RREG32_SOC15_IP(GC, 761 sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL)); 762 sdma_status = RREG32_SOC15_IP(GC, 763 sdma_v7_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG)); 764 if ((REG_GET_FIELD(ic_op_cntl, SDMA0_IC_OP_CNTL, ICACHE_PRIMED) == 1) && 765 (REG_GET_FIELD(sdma_status, SDMA0_STATUS_REG, UCODE_INIT_DONE) == 1)) 766 break; 767 udelay(1); 768 } 769 770 if (j >= adev->usec_timeout) { 771 dev_err(adev->dev, "failed to init sdma ucode\n"); 772 return -EINVAL; 773 } 774 } 775 776 return 0; 777 } 778 779 static int sdma_v7_0_soft_reset(struct amdgpu_ip_block *ip_block) 780 { 781 struct amdgpu_device *adev = ip_block->adev; 782 u32 tmp; 783 int i; 784 785 sdma_v7_0_gfx_stop(adev); 786 787 for (i = 0; i < adev->sdma.num_instances; i++) { 788 //tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_FREEZE)); 789 //tmp |= SDMA0_FREEZE__FREEZE_MASK; 790 //WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp); 791 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL)); 792 tmp |= SDMA0_MCU_CNTL__HALT_MASK; 793 tmp |= SDMA0_MCU_CNTL__RESET_MASK; 794 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), tmp); 795 796 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0); 797 798 udelay(100); 799 800 tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i; 801 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); 802 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 803 804 udelay(100); 805 806 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0); 807 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 808 809 udelay(100); 810 } 811 812 return sdma_v7_0_start(adev); 813 } 814 815 static bool sdma_v7_0_check_soft_reset(struct amdgpu_ip_block *ip_block) 816 { 817 struct amdgpu_device *adev = ip_block->adev; 818 struct amdgpu_ring *ring; 819 int i, r; 820 long tmo = msecs_to_jiffies(1000); 821 822 for (i = 0; i < adev->sdma.num_instances; i++) { 823 ring = &adev->sdma.instance[i].ring; 824 r = amdgpu_ring_test_ib(ring, tmo); 825 if (r) 826 return true; 827 } 828 829 return false; 830 } 831 832 static int sdma_v7_0_reset_queue(struct amdgpu_ring *ring, unsigned int vmid) 833 { 834 struct amdgpu_device *adev = ring->adev; 835 int i, r; 836 837 if (amdgpu_sriov_vf(adev)) 838 return -EINVAL; 839 840 for (i = 0; i < adev->sdma.num_instances; i++) { 841 if (ring == &adev->sdma.instance[i].ring) 842 break; 843 } 844 845 if (i == adev->sdma.num_instances) { 846 DRM_ERROR("sdma instance not found\n"); 847 return -EINVAL; 848 } 849 850 r = amdgpu_mes_reset_legacy_queue(adev, ring, vmid, true); 851 if (r) 852 return r; 853 854 return sdma_v7_0_gfx_resume_instance(adev, i, true); 855 } 856 857 /** 858 * sdma_v7_0_start - setup and start the async dma engines 859 * 860 * @adev: amdgpu_device pointer 861 * 862 * Set up the DMA engines and enable them. 863 * Returns 0 for success, error for failure. 864 */ 865 static int sdma_v7_0_start(struct amdgpu_device *adev) 866 { 867 int r = 0; 868 869 if (amdgpu_sriov_vf(adev)) { 870 sdma_v7_0_ctx_switch_enable(adev, false); 871 sdma_v7_0_enable(adev, false); 872 873 /* set RB registers */ 874 r = sdma_v7_0_gfx_resume(adev); 875 return r; 876 } 877 878 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 879 r = sdma_v7_0_load_microcode(adev); 880 if (r) { 881 sdma_v12_0_free_ucode_buffer(adev); 882 return r; 883 } 884 885 if (amdgpu_emu_mode == 1) 886 msleep(1000); 887 } 888 889 /* unhalt the MEs */ 890 sdma_v7_0_enable(adev, true); 891 /* enable sdma ring preemption */ 892 sdma_v7_0_ctx_switch_enable(adev, true); 893 894 /* start the gfx rings and rlc compute queues */ 895 r = sdma_v7_0_gfx_resume(adev); 896 if (r) 897 return r; 898 r = sdma_v7_0_rlc_resume(adev); 899 900 return r; 901 } 902 903 static int sdma_v7_0_mqd_init(struct amdgpu_device *adev, void *mqd, 904 struct amdgpu_mqd_prop *prop) 905 { 906 struct v12_sdma_mqd *m = mqd; 907 uint64_t wb_gpu_addr; 908 909 m->sdmax_rlcx_rb_cntl = 910 order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT | 911 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 912 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | 913 1 << SDMA0_QUEUE0_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT; 914 915 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8); 916 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); 917 918 wb_gpu_addr = prop->wptr_gpu_addr; 919 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); 920 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); 921 922 wb_gpu_addr = prop->rptr_gpu_addr; 923 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); 924 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); 925 926 m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, 0, 927 regSDMA0_QUEUE0_IB_CNTL)); 928 929 m->sdmax_rlcx_doorbell_offset = 930 prop->doorbell_index << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 931 932 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 933 934 m->sdmax_rlcx_doorbell_log = 0; 935 m->sdmax_rlcx_rb_aql_cntl = 0x4000; //regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT; 936 m->sdmax_rlcx_dummy_reg = 0xf; //regSDMA0_QUEUE0_DUMMY_REG_DEFAULT; 937 938 return 0; 939 } 940 941 static void sdma_v7_0_set_mqd_funcs(struct amdgpu_device *adev) 942 { 943 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v12_sdma_mqd); 944 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v7_0_mqd_init; 945 } 946 947 /** 948 * sdma_v7_0_ring_test_ring - simple async dma engine test 949 * 950 * @ring: amdgpu_ring structure holding ring information 951 * 952 * Test the DMA engine by writing using it to write an 953 * value to memory. 954 * Returns 0 for success, error for failure. 955 */ 956 static int sdma_v7_0_ring_test_ring(struct amdgpu_ring *ring) 957 { 958 struct amdgpu_device *adev = ring->adev; 959 unsigned i; 960 unsigned index; 961 int r; 962 u32 tmp; 963 u64 gpu_addr; 964 volatile uint32_t *cpu_ptr = NULL; 965 966 tmp = 0xCAFEDEAD; 967 968 if (ring->is_mes_queue) { 969 uint32_t offset = 0; 970 offset = amdgpu_mes_ctx_get_offs(ring, 971 AMDGPU_MES_CTX_PADDING_OFFS); 972 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 973 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 974 *cpu_ptr = tmp; 975 } else { 976 r = amdgpu_device_wb_get(adev, &index); 977 if (r) { 978 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 979 return r; 980 } 981 982 gpu_addr = adev->wb.gpu_addr + (index * 4); 983 adev->wb.wb[index] = cpu_to_le32(tmp); 984 } 985 986 r = amdgpu_ring_alloc(ring, 5); 987 if (r) { 988 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 989 if (!ring->is_mes_queue) 990 amdgpu_device_wb_free(adev, index); 991 return r; 992 } 993 994 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 995 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 996 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 997 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 998 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 999 amdgpu_ring_write(ring, 0xDEADBEEF); 1000 amdgpu_ring_commit(ring); 1001 1002 for (i = 0; i < adev->usec_timeout; i++) { 1003 if (ring->is_mes_queue) 1004 tmp = le32_to_cpu(*cpu_ptr); 1005 else 1006 tmp = le32_to_cpu(adev->wb.wb[index]); 1007 if (tmp == 0xDEADBEEF) 1008 break; 1009 if (amdgpu_emu_mode == 1) 1010 msleep(1); 1011 else 1012 udelay(1); 1013 } 1014 1015 if (i >= adev->usec_timeout) 1016 r = -ETIMEDOUT; 1017 1018 if (!ring->is_mes_queue) 1019 amdgpu_device_wb_free(adev, index); 1020 1021 return r; 1022 } 1023 1024 /** 1025 * sdma_v7_0_ring_test_ib - test an IB on the DMA engine 1026 * 1027 * @ring: amdgpu_ring structure holding ring information 1028 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1029 * 1030 * Test a simple IB in the DMA ring. 1031 * Returns 0 on success, error on failure. 1032 */ 1033 static int sdma_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1034 { 1035 struct amdgpu_device *adev = ring->adev; 1036 struct amdgpu_ib ib; 1037 struct dma_fence *f = NULL; 1038 unsigned index; 1039 long r; 1040 u32 tmp = 0; 1041 u64 gpu_addr; 1042 volatile uint32_t *cpu_ptr = NULL; 1043 1044 tmp = 0xCAFEDEAD; 1045 memset(&ib, 0, sizeof(ib)); 1046 1047 if (ring->is_mes_queue) { 1048 uint32_t offset = 0; 1049 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 1050 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 1051 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 1052 1053 offset = amdgpu_mes_ctx_get_offs(ring, 1054 AMDGPU_MES_CTX_PADDING_OFFS); 1055 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 1056 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 1057 *cpu_ptr = tmp; 1058 } else { 1059 r = amdgpu_device_wb_get(adev, &index); 1060 if (r) { 1061 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 1062 return r; 1063 } 1064 1065 gpu_addr = adev->wb.gpu_addr + (index * 4); 1066 adev->wb.wb[index] = cpu_to_le32(tmp); 1067 1068 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 1069 if (r) { 1070 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 1071 goto err0; 1072 } 1073 } 1074 1075 ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 1076 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1077 ib.ptr[1] = lower_32_bits(gpu_addr); 1078 ib.ptr[2] = upper_32_bits(gpu_addr); 1079 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1080 ib.ptr[4] = 0xDEADBEEF; 1081 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1082 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1083 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1084 ib.length_dw = 8; 1085 1086 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1087 if (r) 1088 goto err1; 1089 1090 r = dma_fence_wait_timeout(f, false, timeout); 1091 if (r == 0) { 1092 DRM_ERROR("amdgpu: IB test timed out\n"); 1093 r = -ETIMEDOUT; 1094 goto err1; 1095 } else if (r < 0) { 1096 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1097 goto err1; 1098 } 1099 1100 if (ring->is_mes_queue) 1101 tmp = le32_to_cpu(*cpu_ptr); 1102 else 1103 tmp = le32_to_cpu(adev->wb.wb[index]); 1104 1105 if (tmp == 0xDEADBEEF) 1106 r = 0; 1107 else 1108 r = -EINVAL; 1109 1110 err1: 1111 amdgpu_ib_free(&ib, NULL); 1112 dma_fence_put(f); 1113 err0: 1114 if (!ring->is_mes_queue) 1115 amdgpu_device_wb_free(adev, index); 1116 return r; 1117 } 1118 1119 1120 /** 1121 * sdma_v7_0_vm_copy_pte - update PTEs by copying them from the GART 1122 * 1123 * @ib: indirect buffer to fill with commands 1124 * @pe: addr of the page entry 1125 * @src: src addr to copy from 1126 * @count: number of page entries to update 1127 * 1128 * Update PTEs by copying them from the GART using sDMA. 1129 */ 1130 static void sdma_v7_0_vm_copy_pte(struct amdgpu_ib *ib, 1131 uint64_t pe, uint64_t src, 1132 unsigned count) 1133 { 1134 unsigned bytes = count * 8; 1135 1136 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1137 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1138 SDMA_PKT_COPY_LINEAR_HEADER_CPV(1); 1139 1140 ib->ptr[ib->length_dw++] = bytes - 1; 1141 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1142 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1143 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1144 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1145 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1146 ib->ptr[ib->length_dw++] = 0; 1147 1148 } 1149 1150 /** 1151 * sdma_v7_0_vm_write_pte - update PTEs by writing them manually 1152 * 1153 * @ib: indirect buffer to fill with commands 1154 * @pe: addr of the page entry 1155 * @value: dst addr to write into pe 1156 * @count: number of page entries to update 1157 * @incr: increase next addr by incr bytes 1158 * 1159 * Update PTEs by writing them manually using sDMA. 1160 */ 1161 static void sdma_v7_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1162 uint64_t value, unsigned count, 1163 uint32_t incr) 1164 { 1165 unsigned ndw = count * 2; 1166 1167 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 1168 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1169 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1170 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1171 ib->ptr[ib->length_dw++] = ndw - 1; 1172 for (; ndw > 0; ndw -= 2) { 1173 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1174 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1175 value += incr; 1176 } 1177 } 1178 1179 /** 1180 * sdma_v7_0_vm_set_pte_pde - update the page tables using sDMA 1181 * 1182 * @ib: indirect buffer to fill with commands 1183 * @pe: addr of the page entry 1184 * @addr: dst addr to write into pe 1185 * @count: number of page entries to update 1186 * @incr: increase next addr by incr bytes 1187 * @flags: access flags 1188 * 1189 * Update the page tables using sDMA. 1190 */ 1191 static void sdma_v7_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1192 uint64_t pe, 1193 uint64_t addr, unsigned count, 1194 uint32_t incr, uint64_t flags) 1195 { 1196 /* for physically contiguous pages (vram) */ 1197 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE); 1198 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1199 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1200 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1201 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1202 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1203 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1204 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1205 ib->ptr[ib->length_dw++] = 0; 1206 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1207 } 1208 1209 /** 1210 * sdma_v7_0_ring_pad_ib - pad the IB 1211 * 1212 * @ring: amdgpu ring pointer 1213 * @ib: indirect buffer to fill with padding 1214 * 1215 * Pad the IB with NOPs to a boundary multiple of 8. 1216 */ 1217 static void sdma_v7_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1218 { 1219 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1220 u32 pad_count; 1221 int i; 1222 1223 pad_count = (-ib->length_dw) & 0x7; 1224 for (i = 0; i < pad_count; i++) 1225 if (sdma && sdma->burst_nop && (i == 0)) 1226 ib->ptr[ib->length_dw++] = 1227 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) | 1228 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1229 else 1230 ib->ptr[ib->length_dw++] = 1231 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP); 1232 } 1233 1234 /** 1235 * sdma_v7_0_ring_emit_pipeline_sync - sync the pipeline 1236 * 1237 * @ring: amdgpu_ring pointer 1238 * 1239 * Make sure all previous operations are completed (CIK). 1240 */ 1241 static void sdma_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1242 { 1243 uint32_t seq = ring->fence_drv.sync_seq; 1244 uint64_t addr = ring->fence_drv.gpu_addr; 1245 1246 /* wait for idle */ 1247 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1248 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1249 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1250 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1251 amdgpu_ring_write(ring, addr & 0xfffffffc); 1252 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1253 amdgpu_ring_write(ring, seq); /* reference */ 1254 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1255 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1256 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1257 } 1258 1259 /** 1260 * sdma_v7_0_ring_emit_vm_flush - vm flush using sDMA 1261 * 1262 * @ring: amdgpu_ring pointer 1263 * @vmid: vmid number to use 1264 * @pd_addr: address 1265 * 1266 * Update the page table base and flush the VM TLB 1267 * using sDMA. 1268 */ 1269 static void sdma_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1270 unsigned vmid, uint64_t pd_addr) 1271 { 1272 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1273 } 1274 1275 static void sdma_v7_0_ring_emit_wreg(struct amdgpu_ring *ring, 1276 uint32_t reg, uint32_t val) 1277 { 1278 /* SRBM WRITE command will not support on sdma v7. 1279 * Use Register WRITE command instead, which OPCODE is same as SRBM WRITE 1280 */ 1281 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE)); 1282 amdgpu_ring_write(ring, reg << 2); 1283 amdgpu_ring_write(ring, val); 1284 } 1285 1286 static void sdma_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1287 uint32_t val, uint32_t mask) 1288 { 1289 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1290 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1291 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1292 amdgpu_ring_write(ring, reg << 2); 1293 amdgpu_ring_write(ring, 0); 1294 amdgpu_ring_write(ring, val); /* reference */ 1295 amdgpu_ring_write(ring, mask); /* mask */ 1296 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1297 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1298 } 1299 1300 static void sdma_v7_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1301 uint32_t reg0, uint32_t reg1, 1302 uint32_t ref, uint32_t mask) 1303 { 1304 amdgpu_ring_emit_wreg(ring, reg0, ref); 1305 /* wait for a cycle to reset vm_inv_eng*_ack */ 1306 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1307 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1308 } 1309 1310 static int sdma_v7_0_early_init(struct amdgpu_ip_block *ip_block) 1311 { 1312 struct amdgpu_device *adev = ip_block->adev; 1313 int r; 1314 1315 r = amdgpu_sdma_init_microcode(adev, 0, true); 1316 if (r) { 1317 DRM_ERROR("Failed to init sdma firmware!\n"); 1318 return r; 1319 } 1320 1321 sdma_v7_0_set_ring_funcs(adev); 1322 sdma_v7_0_set_buffer_funcs(adev); 1323 sdma_v7_0_set_vm_pte_funcs(adev); 1324 sdma_v7_0_set_irq_funcs(adev); 1325 sdma_v7_0_set_mqd_funcs(adev); 1326 1327 return 0; 1328 } 1329 1330 static int sdma_v7_0_sw_init(struct amdgpu_ip_block *ip_block) 1331 { 1332 struct amdgpu_ring *ring; 1333 int r, i; 1334 struct amdgpu_device *adev = ip_block->adev; 1335 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_0); 1336 uint32_t *ptr; 1337 1338 /* SDMA trap event */ 1339 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1340 GFX_11_0_0__SRCID__SDMA_TRAP, 1341 &adev->sdma.trap_irq); 1342 if (r) 1343 return r; 1344 1345 for (i = 0; i < adev->sdma.num_instances; i++) { 1346 ring = &adev->sdma.instance[i].ring; 1347 ring->ring_obj = NULL; 1348 ring->use_doorbell = true; 1349 ring->me = i; 1350 1351 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1352 ring->use_doorbell?"true":"false"); 1353 1354 ring->doorbell_index = 1355 (adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset 1356 1357 ring->vm_hub = AMDGPU_GFXHUB(0); 1358 sprintf(ring->name, "sdma%d", i); 1359 r = amdgpu_ring_init(adev, ring, 1024, 1360 &adev->sdma.trap_irq, 1361 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1362 AMDGPU_RING_PRIO_DEFAULT, NULL); 1363 if (r) 1364 return r; 1365 } 1366 1367 adev->sdma.supported_reset = 1368 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); 1369 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1370 1371 r = amdgpu_sdma_sysfs_reset_mask_init(adev); 1372 if (r) 1373 return r; 1374 /* Allocate memory for SDMA IP Dump buffer */ 1375 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); 1376 if (ptr) 1377 adev->sdma.ip_dump = ptr; 1378 else 1379 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n"); 1380 1381 return r; 1382 } 1383 1384 static int sdma_v7_0_sw_fini(struct amdgpu_ip_block *ip_block) 1385 { 1386 struct amdgpu_device *adev = ip_block->adev; 1387 int i; 1388 1389 for (i = 0; i < adev->sdma.num_instances; i++) 1390 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1391 1392 amdgpu_sdma_sysfs_reset_mask_fini(adev); 1393 amdgpu_sdma_destroy_inst_ctx(adev, true); 1394 1395 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) 1396 sdma_v12_0_free_ucode_buffer(adev); 1397 1398 kfree(adev->sdma.ip_dump); 1399 1400 return 0; 1401 } 1402 1403 static int sdma_v7_0_hw_init(struct amdgpu_ip_block *ip_block) 1404 { 1405 struct amdgpu_device *adev = ip_block->adev; 1406 1407 return sdma_v7_0_start(adev); 1408 } 1409 1410 static int sdma_v7_0_hw_fini(struct amdgpu_ip_block *ip_block) 1411 { 1412 struct amdgpu_device *adev = ip_block->adev; 1413 1414 if (amdgpu_sriov_vf(adev)) 1415 return 0; 1416 1417 sdma_v7_0_ctx_switch_enable(adev, false); 1418 sdma_v7_0_enable(adev, false); 1419 1420 return 0; 1421 } 1422 1423 static int sdma_v7_0_suspend(struct amdgpu_ip_block *ip_block) 1424 { 1425 return sdma_v7_0_hw_fini(ip_block); 1426 } 1427 1428 static int sdma_v7_0_resume(struct amdgpu_ip_block *ip_block) 1429 { 1430 return sdma_v7_0_hw_init(ip_block); 1431 } 1432 1433 static bool sdma_v7_0_is_idle(void *handle) 1434 { 1435 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1436 u32 i; 1437 1438 for (i = 0; i < adev->sdma.num_instances; i++) { 1439 u32 tmp = RREG32(sdma_v7_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG)); 1440 1441 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1442 return false; 1443 } 1444 1445 return true; 1446 } 1447 1448 static int sdma_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1449 { 1450 unsigned i; 1451 u32 sdma0, sdma1; 1452 struct amdgpu_device *adev = ip_block->adev; 1453 1454 for (i = 0; i < adev->usec_timeout; i++) { 1455 sdma0 = RREG32(sdma_v7_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG)); 1456 sdma1 = RREG32(sdma_v7_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG)); 1457 1458 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1459 return 0; 1460 udelay(1); 1461 } 1462 return -ETIMEDOUT; 1463 } 1464 1465 static int sdma_v7_0_ring_preempt_ib(struct amdgpu_ring *ring) 1466 { 1467 int i, r = 0; 1468 struct amdgpu_device *adev = ring->adev; 1469 u32 index = 0; 1470 u64 sdma_gfx_preempt; 1471 1472 amdgpu_sdma_get_index_from_ring(ring, &index); 1473 sdma_gfx_preempt = 1474 sdma_v7_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT); 1475 1476 /* assert preemption condition */ 1477 amdgpu_ring_set_preempt_cond_exec(ring, false); 1478 1479 /* emit the trailing fence */ 1480 ring->trail_seq += 1; 1481 r = amdgpu_ring_alloc(ring, 10); 1482 if (r) { 1483 DRM_ERROR("ring %d failed to be allocated \n", ring->idx); 1484 return r; 1485 } 1486 sdma_v7_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1487 ring->trail_seq, 0); 1488 amdgpu_ring_commit(ring); 1489 1490 /* assert IB preemption */ 1491 WREG32(sdma_gfx_preempt, 1); 1492 1493 /* poll the trailing fence */ 1494 for (i = 0; i < adev->usec_timeout; i++) { 1495 if (ring->trail_seq == 1496 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1497 break; 1498 udelay(1); 1499 } 1500 1501 if (i >= adev->usec_timeout) { 1502 r = -EINVAL; 1503 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1504 } 1505 1506 /* deassert IB preemption */ 1507 WREG32(sdma_gfx_preempt, 0); 1508 1509 /* deassert the preemption condition */ 1510 amdgpu_ring_set_preempt_cond_exec(ring, true); 1511 return r; 1512 } 1513 1514 static int sdma_v7_0_set_trap_irq_state(struct amdgpu_device *adev, 1515 struct amdgpu_irq_src *source, 1516 unsigned type, 1517 enum amdgpu_interrupt_state state) 1518 { 1519 u32 sdma_cntl; 1520 1521 u32 reg_offset = sdma_v7_0_get_reg_offset(adev, type, regSDMA0_CNTL); 1522 1523 sdma_cntl = RREG32(reg_offset); 1524 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1525 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1526 WREG32(reg_offset, sdma_cntl); 1527 1528 return 0; 1529 } 1530 1531 static int sdma_v7_0_process_trap_irq(struct amdgpu_device *adev, 1532 struct amdgpu_irq_src *source, 1533 struct amdgpu_iv_entry *entry) 1534 { 1535 int instances, queue; 1536 uint32_t mes_queue_id = entry->src_data[0]; 1537 1538 DRM_DEBUG("IH: SDMA trap\n"); 1539 1540 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 1541 struct amdgpu_mes_queue *queue; 1542 1543 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 1544 1545 spin_lock(&adev->mes.queue_id_lock); 1546 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 1547 if (queue) { 1548 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); 1549 amdgpu_fence_process(queue->ring); 1550 } 1551 spin_unlock(&adev->mes.queue_id_lock); 1552 return 0; 1553 } 1554 1555 queue = entry->ring_id & 0xf; 1556 instances = (entry->ring_id & 0xf0) >> 4; 1557 if (instances > 1) { 1558 DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n"); 1559 return -EINVAL; 1560 } 1561 1562 switch (entry->client_id) { 1563 case SOC21_IH_CLIENTID_GFX: 1564 switch (queue) { 1565 case 0: 1566 amdgpu_fence_process(&adev->sdma.instance[instances].ring); 1567 break; 1568 default: 1569 break; 1570 } 1571 break; 1572 } 1573 return 0; 1574 } 1575 1576 static int sdma_v7_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1577 struct amdgpu_irq_src *source, 1578 struct amdgpu_iv_entry *entry) 1579 { 1580 return 0; 1581 } 1582 1583 static int sdma_v7_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1584 enum amd_clockgating_state state) 1585 { 1586 return 0; 1587 } 1588 1589 static int sdma_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 1590 enum amd_powergating_state state) 1591 { 1592 return 0; 1593 } 1594 1595 static void sdma_v7_0_get_clockgating_state(void *handle, u64 *flags) 1596 { 1597 } 1598 1599 static void sdma_v7_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 1600 { 1601 struct amdgpu_device *adev = ip_block->adev; 1602 int i, j; 1603 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_0); 1604 uint32_t instance_offset; 1605 1606 if (!adev->sdma.ip_dump) 1607 return; 1608 1609 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances); 1610 for (i = 0; i < adev->sdma.num_instances; i++) { 1611 instance_offset = i * reg_count; 1612 drm_printf(p, "\nInstance:%d\n", i); 1613 1614 for (j = 0; j < reg_count; j++) 1615 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_7_0[j].reg_name, 1616 adev->sdma.ip_dump[instance_offset + j]); 1617 } 1618 } 1619 1620 static void sdma_v7_0_dump_ip_state(struct amdgpu_ip_block *ip_block) 1621 { 1622 struct amdgpu_device *adev = ip_block->adev; 1623 int i, j; 1624 uint32_t instance_offset; 1625 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_0); 1626 1627 if (!adev->sdma.ip_dump) 1628 return; 1629 1630 amdgpu_gfx_off_ctrl(adev, false); 1631 for (i = 0; i < adev->sdma.num_instances; i++) { 1632 instance_offset = i * reg_count; 1633 for (j = 0; j < reg_count; j++) 1634 adev->sdma.ip_dump[instance_offset + j] = 1635 RREG32(sdma_v7_0_get_reg_offset(adev, i, 1636 sdma_reg_list_7_0[j].reg_offset)); 1637 } 1638 amdgpu_gfx_off_ctrl(adev, true); 1639 } 1640 1641 const struct amd_ip_funcs sdma_v7_0_ip_funcs = { 1642 .name = "sdma_v7_0", 1643 .early_init = sdma_v7_0_early_init, 1644 .late_init = NULL, 1645 .sw_init = sdma_v7_0_sw_init, 1646 .sw_fini = sdma_v7_0_sw_fini, 1647 .hw_init = sdma_v7_0_hw_init, 1648 .hw_fini = sdma_v7_0_hw_fini, 1649 .suspend = sdma_v7_0_suspend, 1650 .resume = sdma_v7_0_resume, 1651 .is_idle = sdma_v7_0_is_idle, 1652 .wait_for_idle = sdma_v7_0_wait_for_idle, 1653 .soft_reset = sdma_v7_0_soft_reset, 1654 .check_soft_reset = sdma_v7_0_check_soft_reset, 1655 .set_clockgating_state = sdma_v7_0_set_clockgating_state, 1656 .set_powergating_state = sdma_v7_0_set_powergating_state, 1657 .get_clockgating_state = sdma_v7_0_get_clockgating_state, 1658 .dump_ip_state = sdma_v7_0_dump_ip_state, 1659 .print_ip_state = sdma_v7_0_print_ip_state, 1660 }; 1661 1662 static const struct amdgpu_ring_funcs sdma_v7_0_ring_funcs = { 1663 .type = AMDGPU_RING_TYPE_SDMA, 1664 .align_mask = 0xf, 1665 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1666 .support_64bit_ptrs = true, 1667 .secure_submission_supported = true, 1668 .get_rptr = sdma_v7_0_ring_get_rptr, 1669 .get_wptr = sdma_v7_0_ring_get_wptr, 1670 .set_wptr = sdma_v7_0_ring_set_wptr, 1671 .emit_frame_size = 1672 5 + /* sdma_v7_0_ring_init_cond_exec */ 1673 6 + /* sdma_v7_0_ring_emit_hdp_flush */ 1674 6 + /* sdma_v7_0_ring_emit_pipeline_sync */ 1675 /* sdma_v7_0_ring_emit_vm_flush */ 1676 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1677 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1678 10 + 10 + 10, /* sdma_v7_0_ring_emit_fence x3 for user fence, vm fence */ 1679 .emit_ib_size = 5 + 7 + 6, /* sdma_v7_0_ring_emit_ib */ 1680 .emit_ib = sdma_v7_0_ring_emit_ib, 1681 .emit_mem_sync = sdma_v7_0_ring_emit_mem_sync, 1682 .emit_fence = sdma_v7_0_ring_emit_fence, 1683 .emit_pipeline_sync = sdma_v7_0_ring_emit_pipeline_sync, 1684 .emit_vm_flush = sdma_v7_0_ring_emit_vm_flush, 1685 .emit_hdp_flush = sdma_v7_0_ring_emit_hdp_flush, 1686 .test_ring = sdma_v7_0_ring_test_ring, 1687 .test_ib = sdma_v7_0_ring_test_ib, 1688 .insert_nop = sdma_v7_0_ring_insert_nop, 1689 .pad_ib = sdma_v7_0_ring_pad_ib, 1690 .emit_wreg = sdma_v7_0_ring_emit_wreg, 1691 .emit_reg_wait = sdma_v7_0_ring_emit_reg_wait, 1692 .emit_reg_write_reg_wait = sdma_v7_0_ring_emit_reg_write_reg_wait, 1693 .init_cond_exec = sdma_v7_0_ring_init_cond_exec, 1694 .preempt_ib = sdma_v7_0_ring_preempt_ib, 1695 .reset = sdma_v7_0_reset_queue, 1696 }; 1697 1698 static void sdma_v7_0_set_ring_funcs(struct amdgpu_device *adev) 1699 { 1700 int i; 1701 1702 for (i = 0; i < adev->sdma.num_instances; i++) { 1703 adev->sdma.instance[i].ring.funcs = &sdma_v7_0_ring_funcs; 1704 adev->sdma.instance[i].ring.me = i; 1705 } 1706 } 1707 1708 static const struct amdgpu_irq_src_funcs sdma_v7_0_trap_irq_funcs = { 1709 .set = sdma_v7_0_set_trap_irq_state, 1710 .process = sdma_v7_0_process_trap_irq, 1711 }; 1712 1713 static const struct amdgpu_irq_src_funcs sdma_v7_0_illegal_inst_irq_funcs = { 1714 .process = sdma_v7_0_process_illegal_inst_irq, 1715 }; 1716 1717 static void sdma_v7_0_set_irq_funcs(struct amdgpu_device *adev) 1718 { 1719 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1720 adev->sdma.num_instances; 1721 adev->sdma.trap_irq.funcs = &sdma_v7_0_trap_irq_funcs; 1722 adev->sdma.illegal_inst_irq.funcs = &sdma_v7_0_illegal_inst_irq_funcs; 1723 } 1724 1725 /** 1726 * sdma_v7_0_emit_copy_buffer - copy buffer using the sDMA engine 1727 * 1728 * @ib: indirect buffer to fill with commands 1729 * @src_offset: src GPU address 1730 * @dst_offset: dst GPU address 1731 * @byte_count: number of bytes to xfer 1732 * @copy_flags: copy flags for the buffers 1733 * 1734 * Copy GPU buffers using the DMA engine. 1735 * Used by the amdgpu ttm implementation to move pages if 1736 * registered as the asic copy callback. 1737 */ 1738 static void sdma_v7_0_emit_copy_buffer(struct amdgpu_ib *ib, 1739 uint64_t src_offset, 1740 uint64_t dst_offset, 1741 uint32_t byte_count, 1742 uint32_t copy_flags) 1743 { 1744 uint32_t num_type, data_format, max_com; 1745 1746 max_com = AMDGPU_COPY_FLAGS_GET(copy_flags, MAX_COMPRESSED); 1747 data_format = AMDGPU_COPY_FLAGS_GET(copy_flags, DATA_FORMAT); 1748 num_type = AMDGPU_COPY_FLAGS_GET(copy_flags, NUMBER_TYPE); 1749 1750 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1751 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1752 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0) | 1753 SDMA_PKT_COPY_LINEAR_HEADER_CPV(1); 1754 1755 ib->ptr[ib->length_dw++] = byte_count - 1; 1756 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1757 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1758 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1759 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1760 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1761 1762 if ((copy_flags & (AMDGPU_COPY_FLAGS_READ_DECOMPRESSED | AMDGPU_COPY_FLAGS_WRITE_COMPRESSED))) 1763 ib->ptr[ib->length_dw++] = SDMA_DCC_DATA_FORMAT(data_format) | SDMA_DCC_NUM_TYPE(num_type) | 1764 ((copy_flags & AMDGPU_COPY_FLAGS_READ_DECOMPRESSED) ? SDMA_DCC_READ_CM(2) : 0) | 1765 ((copy_flags & AMDGPU_COPY_FLAGS_WRITE_COMPRESSED) ? SDMA_DCC_WRITE_CM(1) : 0) | 1766 SDMA_DCC_MAX_COM(max_com) | SDMA_DCC_MAX_UCOM(1); 1767 else 1768 ib->ptr[ib->length_dw++] = 0; 1769 } 1770 1771 /** 1772 * sdma_v7_0_emit_fill_buffer - fill buffer using the sDMA engine 1773 * 1774 * @ib: indirect buffer to fill 1775 * @src_data: value to write to buffer 1776 * @dst_offset: dst GPU address 1777 * @byte_count: number of bytes to xfer 1778 * 1779 * Fill GPU buffers using the DMA engine. 1780 */ 1781 static void sdma_v7_0_emit_fill_buffer(struct amdgpu_ib *ib, 1782 uint32_t src_data, 1783 uint64_t dst_offset, 1784 uint32_t byte_count) 1785 { 1786 ib->ptr[ib->length_dw++] = SDMA_PKT_CONSTANT_FILL_HEADER_OP(SDMA_OP_CONST_FILL) | 1787 SDMA_PKT_CONSTANT_FILL_HEADER_COMPRESS(1); 1788 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1789 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1790 ib->ptr[ib->length_dw++] = src_data; 1791 ib->ptr[ib->length_dw++] = byte_count - 1; 1792 } 1793 1794 static const struct amdgpu_buffer_funcs sdma_v7_0_buffer_funcs = { 1795 .copy_max_bytes = 0x400000, 1796 .copy_num_dw = 8, 1797 .emit_copy_buffer = sdma_v7_0_emit_copy_buffer, 1798 .fill_max_bytes = 0x400000, 1799 .fill_num_dw = 5, 1800 .emit_fill_buffer = sdma_v7_0_emit_fill_buffer, 1801 }; 1802 1803 static void sdma_v7_0_set_buffer_funcs(struct amdgpu_device *adev) 1804 { 1805 adev->mman.buffer_funcs = &sdma_v7_0_buffer_funcs; 1806 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1807 } 1808 1809 static const struct amdgpu_vm_pte_funcs sdma_v7_0_vm_pte_funcs = { 1810 .copy_pte_num_dw = 8, 1811 .copy_pte = sdma_v7_0_vm_copy_pte, 1812 .write_pte = sdma_v7_0_vm_write_pte, 1813 .set_pte_pde = sdma_v7_0_vm_set_pte_pde, 1814 }; 1815 1816 static void sdma_v7_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1817 { 1818 unsigned i; 1819 1820 adev->vm_manager.vm_pte_funcs = &sdma_v7_0_vm_pte_funcs; 1821 for (i = 0; i < adev->sdma.num_instances; i++) { 1822 adev->vm_manager.vm_pte_scheds[i] = 1823 &adev->sdma.instance[i].ring.sched; 1824 } 1825 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1826 } 1827 1828 const struct amdgpu_ip_block_version sdma_v7_0_ip_block = { 1829 .type = AMD_IP_BLOCK_TYPE_SDMA, 1830 .major = 7, 1831 .minor = 0, 1832 .rev = 0, 1833 .funcs = &sdma_v7_0_ip_funcs, 1834 }; 1835