1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_12_0_0_offset.h" 34 #include "gc/gc_12_0_0_sh_mask.h" 35 #include "hdp/hdp_6_0_0_offset.h" 36 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 37 38 #include "soc15_common.h" 39 #include "soc15.h" 40 #include "sdma_v6_0_0_pkt_open.h" 41 #include "nbio_v4_3.h" 42 #include "sdma_common.h" 43 #include "sdma_v7_0.h" 44 #include "v12_structs.h" 45 #include "mes_userqueue.h" 46 47 MODULE_FIRMWARE("amdgpu/sdma_7_0_0.bin"); 48 MODULE_FIRMWARE("amdgpu/sdma_7_0_1.bin"); 49 50 #define SDMA1_REG_OFFSET 0x600 51 #define SDMA0_HYP_DEC_REG_START 0x5880 52 #define SDMA0_HYP_DEC_REG_END 0x589a 53 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 54 55 /*define for compression field for sdma7*/ 56 #define SDMA_PKT_CONSTANT_FILL_HEADER_compress_offset 0 57 #define SDMA_PKT_CONSTANT_FILL_HEADER_compress_mask 0x00000001 58 #define SDMA_PKT_CONSTANT_FILL_HEADER_compress_shift 16 59 #define SDMA_PKT_CONSTANT_FILL_HEADER_COMPRESS(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_compress_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_compress_shift) 60 61 static const struct amdgpu_hwip_reg_entry sdma_reg_list_7_0[] = { 62 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS_REG), 63 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS1_REG), 64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS2_REG), 65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS3_REG), 66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS4_REG), 67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS5_REG), 68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS6_REG), 69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UCODE_REV), 70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH_HI), 71 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH), 72 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_STATUS), 73 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_STATUS), 74 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK0), 75 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK1), 76 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK0), 77 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK1), 78 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_CNTL), 79 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR), 80 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR_HI), 81 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR), 82 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR_HI), 83 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_OFFSET), 84 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_LO), 85 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_HI), 86 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_CNTL), 87 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_RPTR), 88 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_SUB_REMAIN), 89 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_DUMMY_REG), 90 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE_STATUS0), 91 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_CNTL), 92 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR), 93 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR_HI), 94 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR), 95 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR_HI), 96 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_OFFSET), 97 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_LO), 98 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_HI), 99 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_RPTR), 100 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_SUB_REMAIN), 101 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_DUMMY_REG), 102 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_CNTL), 103 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR), 104 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR_HI), 105 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR), 106 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR_HI), 107 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_OFFSET), 108 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_LO), 109 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_HI), 110 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_RPTR), 111 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_SUB_REMAIN), 112 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_DUMMY_REG), 113 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_INT_STATUS), 114 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_VM_CNTL), 115 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 116 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_CHICKEN_BITS), 117 }; 118 119 static void sdma_v7_0_set_ring_funcs(struct amdgpu_device *adev); 120 static void sdma_v7_0_set_buffer_funcs(struct amdgpu_device *adev); 121 static void sdma_v7_0_set_vm_pte_funcs(struct amdgpu_device *adev); 122 static void sdma_v7_0_set_irq_funcs(struct amdgpu_device *adev); 123 static int sdma_v7_0_start(struct amdgpu_device *adev); 124 125 static u32 sdma_v7_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 126 { 127 u32 base; 128 129 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 130 internal_offset <= SDMA0_HYP_DEC_REG_END) { 131 base = adev->reg_offset[GC_HWIP][0][1]; 132 if (instance != 0) 133 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance; 134 } else { 135 base = adev->reg_offset[GC_HWIP][0][0]; 136 if (instance == 1) 137 internal_offset += SDMA1_REG_OFFSET; 138 } 139 140 return base + internal_offset; 141 } 142 143 static unsigned sdma_v7_0_ring_init_cond_exec(struct amdgpu_ring *ring, 144 uint64_t addr) 145 { 146 unsigned ret; 147 148 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE)); 149 amdgpu_ring_write(ring, lower_32_bits(addr)); 150 amdgpu_ring_write(ring, upper_32_bits(addr)); 151 amdgpu_ring_write(ring, 1); 152 /* this is the offset we need patch later */ 153 ret = ring->wptr & ring->buf_mask; 154 /* insert dummy here and patch it later */ 155 amdgpu_ring_write(ring, 0); 156 157 return ret; 158 } 159 160 /** 161 * sdma_v7_0_ring_get_rptr - get the current read pointer 162 * 163 * @ring: amdgpu ring pointer 164 * 165 * Get the current rptr from the hardware. 166 */ 167 static uint64_t sdma_v7_0_ring_get_rptr(struct amdgpu_ring *ring) 168 { 169 u64 *rptr; 170 171 /* XXX check if swapping is necessary on BE */ 172 rptr = (u64 *)ring->rptr_cpu_addr; 173 174 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 175 return ((*rptr) >> 2); 176 } 177 178 /** 179 * sdma_v7_0_ring_get_wptr - get the current write pointer 180 * 181 * @ring: amdgpu ring pointer 182 * 183 * Get the current wptr from the hardware. 184 */ 185 static uint64_t sdma_v7_0_ring_get_wptr(struct amdgpu_ring *ring) 186 { 187 u64 wptr = 0; 188 189 if (ring->use_doorbell) { 190 /* XXX check if swapping is necessary on BE */ 191 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 192 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 193 } 194 195 return wptr >> 2; 196 } 197 198 /** 199 * sdma_v7_0_ring_set_wptr - commit the write pointer 200 * 201 * @ring: amdgpu ring pointer 202 * 203 * Write the wptr back to the hardware. 204 */ 205 static void sdma_v7_0_ring_set_wptr(struct amdgpu_ring *ring) 206 { 207 struct amdgpu_device *adev = ring->adev; 208 209 DRM_DEBUG("Setting write pointer\n"); 210 211 if (ring->use_doorbell) { 212 DRM_DEBUG("Using doorbell -- " 213 "wptr_offs == 0x%08x " 214 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 215 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 216 ring->wptr_offs, 217 lower_32_bits(ring->wptr << 2), 218 upper_32_bits(ring->wptr << 2)); 219 /* XXX check if swapping is necessary on BE */ 220 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 221 ring->wptr << 2); 222 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 223 ring->doorbell_index, ring->wptr << 2); 224 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 225 } else { 226 DRM_DEBUG("Not using doorbell -- " 227 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 228 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 229 ring->me, 230 lower_32_bits(ring->wptr << 2), 231 ring->me, 232 upper_32_bits(ring->wptr << 2)); 233 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, 234 ring->me, 235 regSDMA0_QUEUE0_RB_WPTR), 236 lower_32_bits(ring->wptr << 2)); 237 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, 238 ring->me, 239 regSDMA0_QUEUE0_RB_WPTR_HI), 240 upper_32_bits(ring->wptr << 2)); 241 } 242 } 243 244 static void sdma_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 245 { 246 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 247 int i; 248 249 for (i = 0; i < count; i++) 250 if (sdma && sdma->burst_nop && (i == 0)) 251 amdgpu_ring_write(ring, ring->funcs->nop | 252 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 253 else 254 amdgpu_ring_write(ring, ring->funcs->nop); 255 } 256 257 /** 258 * sdma_v7_0_ring_emit_ib - Schedule an IB on the DMA engine 259 * 260 * @ring: amdgpu ring pointer 261 * @job: job to retrieve vmid from 262 * @ib: IB object to schedule 263 * @flags: unused 264 * 265 * Schedule an IB in the DMA ring. 266 */ 267 static void sdma_v7_0_ring_emit_ib(struct amdgpu_ring *ring, 268 struct amdgpu_job *job, 269 struct amdgpu_ib *ib, 270 uint32_t flags) 271 { 272 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 273 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 274 275 /* An IB packet must end on a 8 DW boundary--the next dword 276 * must be on a 8-dword boundary. Our IB packet below is 6 277 * dwords long, thus add x number of NOPs, such that, in 278 * modular arithmetic, 279 * wptr + 6 + x = 8k, k >= 0, which in C is, 280 * (wptr + 6 + x) % 8 = 0. 281 * The expression below, is a solution of x. 282 */ 283 sdma_v7_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 284 285 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) | 286 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 287 /* base must be 32 byte aligned */ 288 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 289 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 290 amdgpu_ring_write(ring, ib->length_dw); 291 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 292 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 293 } 294 295 /** 296 * sdma_v7_0_ring_emit_mem_sync - flush the IB by graphics cache rinse 297 * 298 * @ring: amdgpu ring pointer 299 * 300 * flush the IB by graphics cache rinse. 301 */ 302 static void sdma_v7_0_ring_emit_mem_sync(struct amdgpu_ring *ring) 303 { 304 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV | 305 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 306 SDMA_GCR_GLI_INV(1); 307 308 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 309 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ)); 310 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 311 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 312 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 313 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 314 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 315 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 316 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 317 } 318 319 320 /** 321 * sdma_v7_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 322 * 323 * @ring: amdgpu ring pointer 324 * 325 * Emit an hdp flush packet on the requested DMA ring. 326 */ 327 static void sdma_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 328 { 329 struct amdgpu_device *adev = ring->adev; 330 u32 ref_and_mask = 0; 331 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 332 333 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 334 335 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 336 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 337 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 338 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 339 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 340 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 341 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 342 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 343 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 344 } 345 346 /** 347 * sdma_v7_0_ring_emit_fence - emit a fence on the DMA ring 348 * 349 * @ring: amdgpu ring pointer 350 * @addr: address 351 * @seq: fence seq number 352 * @flags: fence flags 353 * 354 * Add a DMA fence packet to the ring to write 355 * the fence seq number and DMA trap packet to generate 356 * an interrupt if needed. 357 */ 358 static void sdma_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 359 unsigned flags) 360 { 361 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 362 /* write the fence */ 363 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 364 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 365 /* zero in first two bits */ 366 BUG_ON(addr & 0x3); 367 amdgpu_ring_write(ring, lower_32_bits(addr)); 368 amdgpu_ring_write(ring, upper_32_bits(addr)); 369 amdgpu_ring_write(ring, lower_32_bits(seq)); 370 371 /* optionally write high bits as well */ 372 if (write64bit) { 373 addr += 4; 374 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 375 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 376 /* zero in first two bits */ 377 BUG_ON(addr & 0x3); 378 amdgpu_ring_write(ring, lower_32_bits(addr)); 379 amdgpu_ring_write(ring, upper_32_bits(addr)); 380 amdgpu_ring_write(ring, upper_32_bits(seq)); 381 } 382 383 if (flags & AMDGPU_FENCE_FLAG_INT) { 384 /* generate an interrupt */ 385 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP)); 386 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 387 } 388 } 389 390 /** 391 * sdma_v7_0_gfx_stop - stop the gfx async dma engines 392 * 393 * @adev: amdgpu_device pointer 394 * 395 * Stop the gfx async dma ring buffers. 396 */ 397 static void sdma_v7_0_gfx_stop(struct amdgpu_device *adev) 398 { 399 u32 rb_cntl, ib_cntl; 400 int i; 401 402 for (i = 0; i < adev->sdma.num_instances; i++) { 403 rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 404 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0); 405 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 406 ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 407 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0); 408 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 409 } 410 } 411 412 /** 413 * sdma_v7_0_rlc_stop - stop the compute async dma engines 414 * 415 * @adev: amdgpu_device pointer 416 * 417 * Stop the compute async dma queues. 418 */ 419 static void sdma_v7_0_rlc_stop(struct amdgpu_device *adev) 420 { 421 /* XXX todo */ 422 } 423 424 /** 425 * sdma_v7_0_ctx_switch_enable - stop the async dma engines context switch 426 * 427 * @adev: amdgpu_device pointer 428 * @enable: enable/disable the DMA MEs context switch. 429 * 430 * Halt or unhalt the async dma engines context switch. 431 */ 432 static void sdma_v7_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 433 { 434 } 435 436 /** 437 * sdma_v7_0_enable - stop the async dma engines 438 * 439 * @adev: amdgpu_device pointer 440 * @enable: enable/disable the DMA MEs. 441 * 442 * Halt or unhalt the async dma engines. 443 */ 444 static void sdma_v7_0_enable(struct amdgpu_device *adev, bool enable) 445 { 446 u32 mcu_cntl; 447 int i; 448 449 if (!enable) { 450 sdma_v7_0_gfx_stop(adev); 451 sdma_v7_0_rlc_stop(adev); 452 } 453 454 if (amdgpu_sriov_vf(adev)) 455 return; 456 457 for (i = 0; i < adev->sdma.num_instances; i++) { 458 mcu_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL)); 459 mcu_cntl = REG_SET_FIELD(mcu_cntl, SDMA0_MCU_CNTL, HALT, enable ? 0 : 1); 460 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), mcu_cntl); 461 } 462 } 463 464 /** 465 * sdma_v7_0_gfx_resume_instance - start/restart a certain sdma engine 466 * 467 * @adev: amdgpu_device pointer 468 * @i: instance 469 * @restore: used to restore wptr when restart 470 * 471 * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr. 472 * Return 0 for success. 473 */ 474 static int sdma_v7_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore) 475 { 476 struct amdgpu_ring *ring; 477 u32 rb_cntl, ib_cntl; 478 u32 rb_bufsz; 479 u32 doorbell; 480 u32 doorbell_offset; 481 u32 temp; 482 u64 wptr_gpu_addr; 483 int r; 484 485 ring = &adev->sdma.instance[i].ring; 486 487 /* Set ring buffer size in dwords */ 488 rb_bufsz = order_base_2(ring->ring_size / 4); 489 rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 490 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); 491 #ifdef __BIG_ENDIAN 492 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1); 493 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, 494 RPTR_WRITEBACK_SWAP_ENABLE, 1); 495 #endif 496 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1); 497 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 498 499 /* Initialize the ring buffer's read and write pointers */ 500 if (restore) { 501 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2)); 502 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2)); 503 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2)); 504 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); 505 } else { 506 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0); 507 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0); 508 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0); 509 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0); 510 } 511 /* setup the wptr shadow polling */ 512 wptr_gpu_addr = ring->wptr_gpu_addr; 513 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO), 514 lower_32_bits(wptr_gpu_addr)); 515 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI), 516 upper_32_bits(wptr_gpu_addr)); 517 518 /* set the wb address whether it's enabled or not */ 519 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI), 520 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 521 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO), 522 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 523 524 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 525 if (amdgpu_sriov_vf(adev)) 526 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 1); 527 else 528 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0); 529 530 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, MCU_WPTR_POLL_ENABLE, 1); 531 532 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8); 533 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40); 534 535 if (!restore) 536 ring->wptr = 0; 537 538 /* before programing wptr to a less value, need set minor_ptr_update first */ 539 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1); 540 541 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 542 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2); 543 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 544 } 545 546 doorbell = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL)); 547 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET)); 548 549 if (ring->use_doorbell) { 550 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 551 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET, 552 OFFSET, ring->doorbell_index); 553 } else { 554 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0); 555 } 556 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell); 557 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset); 558 559 if (i == 0) 560 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 561 ring->doorbell_index, 562 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances); 563 564 if (amdgpu_sriov_vf(adev)) 565 sdma_v7_0_ring_set_wptr(ring); 566 567 /* set minor_ptr_update to 0 after wptr programed */ 568 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0); 569 570 /* Set up sdma hang watchdog */ 571 temp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL)); 572 /* 100ms per unit */ 573 temp = REG_SET_FIELD(temp, SDMA0_WATCHDOG_CNTL, QUEUE_HANG_COUNT, 574 max(adev->usec_timeout/100000, 1)); 575 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), temp); 576 577 /* Set up RESP_MODE to non-copy addresses */ 578 temp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL)); 579 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 580 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 581 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp); 582 583 /* program default cache read and write policy */ 584 temp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE)); 585 /* clean read policy and write policy bits */ 586 temp &= 0xFF0FFF; 587 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | 588 (CACHE_WRITE_POLICY_L2__DEFAULT << 14)); 589 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp); 590 591 if (!amdgpu_sriov_vf(adev)) { 592 /* unhalt engine */ 593 temp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL)); 594 temp = REG_SET_FIELD(temp, SDMA0_MCU_CNTL, HALT, 0); 595 temp = REG_SET_FIELD(temp, SDMA0_MCU_CNTL, RESET, 0); 596 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), temp); 597 } 598 599 /* enable DMA RB */ 600 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1); 601 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 602 603 ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 604 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1); 605 #ifdef __BIG_ENDIAN 606 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1); 607 #endif 608 /* enable DMA IBs */ 609 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 610 ring->sched.ready = true; 611 612 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 613 sdma_v7_0_ctx_switch_enable(adev, true); 614 sdma_v7_0_enable(adev, true); 615 } 616 617 r = amdgpu_ring_test_helper(ring); 618 if (r) 619 ring->sched.ready = false; 620 621 return r; 622 } 623 624 /** 625 * sdma_v7_0_gfx_resume - setup and start the async dma engines 626 * 627 * @adev: amdgpu_device pointer 628 * 629 * Set up the gfx DMA ring buffers and enable them. 630 * Returns 0 for success, error for failure. 631 */ 632 static int sdma_v7_0_gfx_resume(struct amdgpu_device *adev) 633 { 634 int i, r; 635 636 for (i = 0; i < adev->sdma.num_instances; i++) { 637 r = sdma_v7_0_gfx_resume_instance(adev, i, false); 638 if (r) 639 return r; 640 } 641 642 return 0; 643 644 } 645 646 /** 647 * sdma_v7_0_rlc_resume - setup and start the async dma engines 648 * 649 * @adev: amdgpu_device pointer 650 * 651 * Set up the compute DMA queues and enable them. 652 * Returns 0 for success, error for failure. 653 */ 654 static int sdma_v7_0_rlc_resume(struct amdgpu_device *adev) 655 { 656 return 0; 657 } 658 659 static void sdma_v12_0_free_ucode_buffer(struct amdgpu_device *adev) 660 { 661 int i; 662 663 for (i = 0; i < adev->sdma.num_instances; i++) { 664 amdgpu_bo_free_kernel(&adev->sdma.instance[i].sdma_fw_obj, 665 &adev->sdma.instance[i].sdma_fw_gpu_addr, 666 (void **)&adev->sdma.instance[i].sdma_fw_ptr); 667 } 668 } 669 670 /** 671 * sdma_v7_0_load_microcode - load the sDMA ME ucode 672 * 673 * @adev: amdgpu_device pointer 674 * 675 * Loads the sDMA0/1 ucode. 676 * Returns 0 for success, -EINVAL if the ucode is not available. 677 */ 678 static int sdma_v7_0_load_microcode(struct amdgpu_device *adev) 679 { 680 const struct sdma_firmware_header_v3_0 *hdr; 681 const __le32 *fw_data; 682 u32 fw_size; 683 uint32_t tmp, sdma_status, ic_op_cntl; 684 int i, r, j; 685 686 /* halt the MEs */ 687 sdma_v7_0_enable(adev, false); 688 689 if (!adev->sdma.instance[0].fw) 690 return -EINVAL; 691 692 hdr = (const struct sdma_firmware_header_v3_0 *) 693 adev->sdma.instance[0].fw->data; 694 amdgpu_ucode_print_sdma_hdr(&hdr->header); 695 696 fw_data = (const __le32 *)(adev->sdma.instance[0].fw->data + 697 le32_to_cpu(hdr->ucode_offset_bytes)); 698 fw_size = le32_to_cpu(hdr->ucode_size_bytes); 699 700 for (i = 0; i < adev->sdma.num_instances; i++) { 701 r = amdgpu_bo_create_reserved(adev, fw_size, 702 PAGE_SIZE, 703 AMDGPU_GEM_DOMAIN_VRAM, 704 &adev->sdma.instance[i].sdma_fw_obj, 705 &adev->sdma.instance[i].sdma_fw_gpu_addr, 706 (void **)&adev->sdma.instance[i].sdma_fw_ptr); 707 if (r) { 708 dev_err(adev->dev, "(%d) failed to create sdma ucode bo\n", r); 709 return r; 710 } 711 712 memcpy(adev->sdma.instance[i].sdma_fw_ptr, fw_data, fw_size); 713 714 amdgpu_bo_kunmap(adev->sdma.instance[i].sdma_fw_obj); 715 amdgpu_bo_unreserve(adev->sdma.instance[i].sdma_fw_obj); 716 717 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_CNTL)); 718 tmp = REG_SET_FIELD(tmp, SDMA0_IC_CNTL, GPA, 0); 719 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_CNTL), tmp); 720 721 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_BASE_LO), 722 lower_32_bits(adev->sdma.instance[i].sdma_fw_gpu_addr)); 723 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_BASE_HI), 724 upper_32_bits(adev->sdma.instance[i].sdma_fw_gpu_addr)); 725 726 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL)); 727 tmp = REG_SET_FIELD(tmp, SDMA0_IC_OP_CNTL, PRIME_ICACHE, 1); 728 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL), tmp); 729 730 /* Wait for sdma ucode init complete */ 731 for (j = 0; j < adev->usec_timeout; j++) { 732 ic_op_cntl = RREG32_SOC15_IP(GC, 733 sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL)); 734 sdma_status = RREG32_SOC15_IP(GC, 735 sdma_v7_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG)); 736 if ((REG_GET_FIELD(ic_op_cntl, SDMA0_IC_OP_CNTL, ICACHE_PRIMED) == 1) && 737 (REG_GET_FIELD(sdma_status, SDMA0_STATUS_REG, UCODE_INIT_DONE) == 1)) 738 break; 739 udelay(1); 740 } 741 742 if (j >= adev->usec_timeout) { 743 dev_err(adev->dev, "failed to init sdma ucode\n"); 744 return -EINVAL; 745 } 746 } 747 748 return 0; 749 } 750 751 static int sdma_v7_0_soft_reset(struct amdgpu_ip_block *ip_block) 752 { 753 struct amdgpu_device *adev = ip_block->adev; 754 u32 tmp; 755 int i; 756 757 sdma_v7_0_gfx_stop(adev); 758 759 for (i = 0; i < adev->sdma.num_instances; i++) { 760 //tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_FREEZE)); 761 //tmp |= SDMA0_FREEZE__FREEZE_MASK; 762 //WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp); 763 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL)); 764 tmp |= SDMA0_MCU_CNTL__HALT_MASK; 765 tmp |= SDMA0_MCU_CNTL__RESET_MASK; 766 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), tmp); 767 768 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0); 769 770 udelay(100); 771 772 tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i; 773 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); 774 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 775 776 udelay(100); 777 778 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0); 779 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 780 781 udelay(100); 782 } 783 784 return sdma_v7_0_start(adev); 785 } 786 787 static bool sdma_v7_0_check_soft_reset(struct amdgpu_ip_block *ip_block) 788 { 789 struct amdgpu_device *adev = ip_block->adev; 790 struct amdgpu_ring *ring; 791 int i, r; 792 long tmo = msecs_to_jiffies(1000); 793 794 for (i = 0; i < adev->sdma.num_instances; i++) { 795 ring = &adev->sdma.instance[i].ring; 796 r = amdgpu_ring_test_ib(ring, tmo); 797 if (r) 798 return true; 799 } 800 801 return false; 802 } 803 804 static int sdma_v7_0_reset_queue(struct amdgpu_ring *ring, unsigned int vmid) 805 { 806 struct amdgpu_device *adev = ring->adev; 807 int i, r; 808 809 if (amdgpu_sriov_vf(adev)) 810 return -EINVAL; 811 812 for (i = 0; i < adev->sdma.num_instances; i++) { 813 if (ring == &adev->sdma.instance[i].ring) 814 break; 815 } 816 817 if (i == adev->sdma.num_instances) { 818 DRM_ERROR("sdma instance not found\n"); 819 return -EINVAL; 820 } 821 822 r = amdgpu_mes_reset_legacy_queue(adev, ring, vmid, true); 823 if (r) 824 return r; 825 826 return sdma_v7_0_gfx_resume_instance(adev, i, true); 827 } 828 829 /** 830 * sdma_v7_0_start - setup and start the async dma engines 831 * 832 * @adev: amdgpu_device pointer 833 * 834 * Set up the DMA engines and enable them. 835 * Returns 0 for success, error for failure. 836 */ 837 static int sdma_v7_0_start(struct amdgpu_device *adev) 838 { 839 int r = 0; 840 841 if (amdgpu_sriov_vf(adev)) { 842 sdma_v7_0_ctx_switch_enable(adev, false); 843 sdma_v7_0_enable(adev, false); 844 845 /* set RB registers */ 846 r = sdma_v7_0_gfx_resume(adev); 847 return r; 848 } 849 850 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 851 r = sdma_v7_0_load_microcode(adev); 852 if (r) { 853 sdma_v12_0_free_ucode_buffer(adev); 854 return r; 855 } 856 857 if (amdgpu_emu_mode == 1) 858 msleep(1000); 859 } 860 861 /* unhalt the MEs */ 862 sdma_v7_0_enable(adev, true); 863 /* enable sdma ring preemption */ 864 sdma_v7_0_ctx_switch_enable(adev, true); 865 866 /* start the gfx rings and rlc compute queues */ 867 r = sdma_v7_0_gfx_resume(adev); 868 if (r) 869 return r; 870 r = sdma_v7_0_rlc_resume(adev); 871 872 return r; 873 } 874 875 static int sdma_v7_0_mqd_init(struct amdgpu_device *adev, void *mqd, 876 struct amdgpu_mqd_prop *prop) 877 { 878 struct v12_sdma_mqd *m = mqd; 879 uint64_t wb_gpu_addr; 880 881 m->sdmax_rlcx_rb_cntl = 882 order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT | 883 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 884 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | 885 1 << SDMA0_QUEUE0_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT; 886 887 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8); 888 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); 889 890 wb_gpu_addr = prop->wptr_gpu_addr; 891 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); 892 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); 893 894 wb_gpu_addr = prop->rptr_gpu_addr; 895 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); 896 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); 897 898 m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, 0, 899 regSDMA0_QUEUE0_IB_CNTL)); 900 901 m->sdmax_rlcx_doorbell_offset = 902 prop->doorbell_index << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 903 904 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 905 906 m->sdmax_rlcx_doorbell_log = 0; 907 m->sdmax_rlcx_rb_aql_cntl = 0x4000; //regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT; 908 m->sdmax_rlcx_dummy_reg = 0xf; //regSDMA0_QUEUE0_DUMMY_REG_DEFAULT; 909 910 m->sdmax_rlcx_csa_addr_lo = lower_32_bits(prop->csa_addr); 911 m->sdmax_rlcx_csa_addr_hi = upper_32_bits(prop->csa_addr); 912 913 return 0; 914 } 915 916 static void sdma_v7_0_set_mqd_funcs(struct amdgpu_device *adev) 917 { 918 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v12_sdma_mqd); 919 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v7_0_mqd_init; 920 } 921 922 /** 923 * sdma_v7_0_ring_test_ring - simple async dma engine test 924 * 925 * @ring: amdgpu_ring structure holding ring information 926 * 927 * Test the DMA engine by writing using it to write an 928 * value to memory. 929 * Returns 0 for success, error for failure. 930 */ 931 static int sdma_v7_0_ring_test_ring(struct amdgpu_ring *ring) 932 { 933 struct amdgpu_device *adev = ring->adev; 934 unsigned i; 935 unsigned index; 936 int r; 937 u32 tmp; 938 u64 gpu_addr; 939 940 tmp = 0xCAFEDEAD; 941 942 r = amdgpu_device_wb_get(adev, &index); 943 if (r) { 944 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 945 return r; 946 } 947 948 gpu_addr = adev->wb.gpu_addr + (index * 4); 949 adev->wb.wb[index] = cpu_to_le32(tmp); 950 951 r = amdgpu_ring_alloc(ring, 5); 952 if (r) { 953 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 954 amdgpu_device_wb_free(adev, index); 955 return r; 956 } 957 958 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 959 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 960 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 961 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 962 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 963 amdgpu_ring_write(ring, 0xDEADBEEF); 964 amdgpu_ring_commit(ring); 965 966 for (i = 0; i < adev->usec_timeout; i++) { 967 tmp = le32_to_cpu(adev->wb.wb[index]); 968 if (tmp == 0xDEADBEEF) 969 break; 970 if (amdgpu_emu_mode == 1) 971 msleep(1); 972 else 973 udelay(1); 974 } 975 976 if (i >= adev->usec_timeout) 977 r = -ETIMEDOUT; 978 979 amdgpu_device_wb_free(adev, index); 980 981 return r; 982 } 983 984 /** 985 * sdma_v7_0_ring_test_ib - test an IB on the DMA engine 986 * 987 * @ring: amdgpu_ring structure holding ring information 988 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 989 * 990 * Test a simple IB in the DMA ring. 991 * Returns 0 on success, error on failure. 992 */ 993 static int sdma_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 994 { 995 struct amdgpu_device *adev = ring->adev; 996 struct amdgpu_ib ib; 997 struct dma_fence *f = NULL; 998 unsigned index; 999 long r; 1000 u32 tmp = 0; 1001 u64 gpu_addr; 1002 1003 tmp = 0xCAFEDEAD; 1004 memset(&ib, 0, sizeof(ib)); 1005 1006 r = amdgpu_device_wb_get(adev, &index); 1007 if (r) { 1008 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 1009 return r; 1010 } 1011 1012 gpu_addr = adev->wb.gpu_addr + (index * 4); 1013 adev->wb.wb[index] = cpu_to_le32(tmp); 1014 1015 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 1016 if (r) { 1017 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 1018 goto err0; 1019 } 1020 1021 ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 1022 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1023 ib.ptr[1] = lower_32_bits(gpu_addr); 1024 ib.ptr[2] = upper_32_bits(gpu_addr); 1025 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1026 ib.ptr[4] = 0xDEADBEEF; 1027 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1028 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1029 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1030 ib.length_dw = 8; 1031 1032 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1033 if (r) 1034 goto err1; 1035 1036 r = dma_fence_wait_timeout(f, false, timeout); 1037 if (r == 0) { 1038 DRM_ERROR("amdgpu: IB test timed out\n"); 1039 r = -ETIMEDOUT; 1040 goto err1; 1041 } else if (r < 0) { 1042 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1043 goto err1; 1044 } 1045 1046 tmp = le32_to_cpu(adev->wb.wb[index]); 1047 1048 if (tmp == 0xDEADBEEF) 1049 r = 0; 1050 else 1051 r = -EINVAL; 1052 1053 err1: 1054 amdgpu_ib_free(&ib, NULL); 1055 dma_fence_put(f); 1056 err0: 1057 amdgpu_device_wb_free(adev, index); 1058 return r; 1059 } 1060 1061 1062 /** 1063 * sdma_v7_0_vm_copy_pte - update PTEs by copying them from the GART 1064 * 1065 * @ib: indirect buffer to fill with commands 1066 * @pe: addr of the page entry 1067 * @src: src addr to copy from 1068 * @count: number of page entries to update 1069 * 1070 * Update PTEs by copying them from the GART using sDMA. 1071 */ 1072 static void sdma_v7_0_vm_copy_pte(struct amdgpu_ib *ib, 1073 uint64_t pe, uint64_t src, 1074 unsigned count) 1075 { 1076 unsigned bytes = count * 8; 1077 1078 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1079 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1080 SDMA_PKT_COPY_LINEAR_HEADER_CPV(1); 1081 1082 ib->ptr[ib->length_dw++] = bytes - 1; 1083 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1084 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1085 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1086 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1087 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1088 ib->ptr[ib->length_dw++] = 0; 1089 1090 } 1091 1092 /** 1093 * sdma_v7_0_vm_write_pte - update PTEs by writing them manually 1094 * 1095 * @ib: indirect buffer to fill with commands 1096 * @pe: addr of the page entry 1097 * @value: dst addr to write into pe 1098 * @count: number of page entries to update 1099 * @incr: increase next addr by incr bytes 1100 * 1101 * Update PTEs by writing them manually using sDMA. 1102 */ 1103 static void sdma_v7_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1104 uint64_t value, unsigned count, 1105 uint32_t incr) 1106 { 1107 unsigned ndw = count * 2; 1108 1109 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 1110 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1111 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1112 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1113 ib->ptr[ib->length_dw++] = ndw - 1; 1114 for (; ndw > 0; ndw -= 2) { 1115 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1116 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1117 value += incr; 1118 } 1119 } 1120 1121 /** 1122 * sdma_v7_0_vm_set_pte_pde - update the page tables using sDMA 1123 * 1124 * @ib: indirect buffer to fill with commands 1125 * @pe: addr of the page entry 1126 * @addr: dst addr to write into pe 1127 * @count: number of page entries to update 1128 * @incr: increase next addr by incr bytes 1129 * @flags: access flags 1130 * 1131 * Update the page tables using sDMA. 1132 */ 1133 static void sdma_v7_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1134 uint64_t pe, 1135 uint64_t addr, unsigned count, 1136 uint32_t incr, uint64_t flags) 1137 { 1138 /* for physically contiguous pages (vram) */ 1139 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE); 1140 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1141 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1142 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1143 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1144 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1145 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1146 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1147 ib->ptr[ib->length_dw++] = 0; 1148 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1149 } 1150 1151 /** 1152 * sdma_v7_0_ring_pad_ib - pad the IB 1153 * 1154 * @ring: amdgpu ring pointer 1155 * @ib: indirect buffer to fill with padding 1156 * 1157 * Pad the IB with NOPs to a boundary multiple of 8. 1158 */ 1159 static void sdma_v7_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1160 { 1161 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1162 u32 pad_count; 1163 int i; 1164 1165 pad_count = (-ib->length_dw) & 0x7; 1166 for (i = 0; i < pad_count; i++) 1167 if (sdma && sdma->burst_nop && (i == 0)) 1168 ib->ptr[ib->length_dw++] = 1169 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) | 1170 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1171 else 1172 ib->ptr[ib->length_dw++] = 1173 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP); 1174 } 1175 1176 /** 1177 * sdma_v7_0_ring_emit_pipeline_sync - sync the pipeline 1178 * 1179 * @ring: amdgpu_ring pointer 1180 * 1181 * Make sure all previous operations are completed (CIK). 1182 */ 1183 static void sdma_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1184 { 1185 uint32_t seq = ring->fence_drv.sync_seq; 1186 uint64_t addr = ring->fence_drv.gpu_addr; 1187 1188 /* wait for idle */ 1189 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1190 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1191 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1192 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1193 amdgpu_ring_write(ring, addr & 0xfffffffc); 1194 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1195 amdgpu_ring_write(ring, seq); /* reference */ 1196 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1197 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1198 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1199 } 1200 1201 /** 1202 * sdma_v7_0_ring_emit_vm_flush - vm flush using sDMA 1203 * 1204 * @ring: amdgpu_ring pointer 1205 * @vmid: vmid number to use 1206 * @pd_addr: address 1207 * 1208 * Update the page table base and flush the VM TLB 1209 * using sDMA. 1210 */ 1211 static void sdma_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1212 unsigned vmid, uint64_t pd_addr) 1213 { 1214 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1215 } 1216 1217 static void sdma_v7_0_ring_emit_wreg(struct amdgpu_ring *ring, 1218 uint32_t reg, uint32_t val) 1219 { 1220 /* SRBM WRITE command will not support on sdma v7. 1221 * Use Register WRITE command instead, which OPCODE is same as SRBM WRITE 1222 */ 1223 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE)); 1224 amdgpu_ring_write(ring, reg << 2); 1225 amdgpu_ring_write(ring, val); 1226 } 1227 1228 static void sdma_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1229 uint32_t val, uint32_t mask) 1230 { 1231 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1232 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1233 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1234 amdgpu_ring_write(ring, reg << 2); 1235 amdgpu_ring_write(ring, 0); 1236 amdgpu_ring_write(ring, val); /* reference */ 1237 amdgpu_ring_write(ring, mask); /* mask */ 1238 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1239 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1240 } 1241 1242 static void sdma_v7_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1243 uint32_t reg0, uint32_t reg1, 1244 uint32_t ref, uint32_t mask) 1245 { 1246 amdgpu_ring_emit_wreg(ring, reg0, ref); 1247 /* wait for a cycle to reset vm_inv_eng*_ack */ 1248 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1249 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1250 } 1251 1252 static int sdma_v7_0_early_init(struct amdgpu_ip_block *ip_block) 1253 { 1254 struct amdgpu_device *adev = ip_block->adev; 1255 int r; 1256 1257 if (amdgpu_disable_kq == 1) 1258 adev->sdma.no_user_submission = true; 1259 1260 r = amdgpu_sdma_init_microcode(adev, 0, true); 1261 if (r) { 1262 DRM_ERROR("Failed to init sdma firmware!\n"); 1263 return r; 1264 } 1265 1266 sdma_v7_0_set_ring_funcs(adev); 1267 sdma_v7_0_set_buffer_funcs(adev); 1268 sdma_v7_0_set_vm_pte_funcs(adev); 1269 sdma_v7_0_set_irq_funcs(adev); 1270 sdma_v7_0_set_mqd_funcs(adev); 1271 1272 return 0; 1273 } 1274 1275 static int sdma_v7_0_sw_init(struct amdgpu_ip_block *ip_block) 1276 { 1277 struct amdgpu_ring *ring; 1278 int r, i; 1279 struct amdgpu_device *adev = ip_block->adev; 1280 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_0); 1281 uint32_t *ptr; 1282 1283 /* SDMA trap event */ 1284 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1285 GFX_11_0_0__SRCID__SDMA_TRAP, 1286 &adev->sdma.trap_irq); 1287 if (r) 1288 return r; 1289 1290 for (i = 0; i < adev->sdma.num_instances; i++) { 1291 ring = &adev->sdma.instance[i].ring; 1292 ring->ring_obj = NULL; 1293 ring->use_doorbell = true; 1294 ring->me = i; 1295 ring->no_user_submission = adev->sdma.no_user_submission; 1296 1297 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1298 ring->use_doorbell?"true":"false"); 1299 1300 ring->doorbell_index = 1301 (adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset 1302 1303 ring->vm_hub = AMDGPU_GFXHUB(0); 1304 sprintf(ring->name, "sdma%d", i); 1305 r = amdgpu_ring_init(adev, ring, 1024, 1306 &adev->sdma.trap_irq, 1307 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1308 AMDGPU_RING_PRIO_DEFAULT, NULL); 1309 if (r) 1310 return r; 1311 } 1312 1313 adev->sdma.supported_reset = 1314 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); 1315 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1316 1317 r = amdgpu_sdma_sysfs_reset_mask_init(adev); 1318 if (r) 1319 return r; 1320 /* Allocate memory for SDMA IP Dump buffer */ 1321 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); 1322 if (ptr) 1323 adev->sdma.ip_dump = ptr; 1324 else 1325 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n"); 1326 1327 #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ 1328 /* add firmware version checks here */ 1329 if (0) 1330 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1331 #endif 1332 1333 1334 return r; 1335 } 1336 1337 static int sdma_v7_0_sw_fini(struct amdgpu_ip_block *ip_block) 1338 { 1339 struct amdgpu_device *adev = ip_block->adev; 1340 int i; 1341 1342 for (i = 0; i < adev->sdma.num_instances; i++) 1343 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1344 1345 amdgpu_sdma_sysfs_reset_mask_fini(adev); 1346 amdgpu_sdma_destroy_inst_ctx(adev, true); 1347 1348 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) 1349 sdma_v12_0_free_ucode_buffer(adev); 1350 1351 kfree(adev->sdma.ip_dump); 1352 1353 return 0; 1354 } 1355 1356 static int sdma_v7_0_hw_init(struct amdgpu_ip_block *ip_block) 1357 { 1358 struct amdgpu_device *adev = ip_block->adev; 1359 1360 return sdma_v7_0_start(adev); 1361 } 1362 1363 static int sdma_v7_0_hw_fini(struct amdgpu_ip_block *ip_block) 1364 { 1365 struct amdgpu_device *adev = ip_block->adev; 1366 1367 if (amdgpu_sriov_vf(adev)) 1368 return 0; 1369 1370 sdma_v7_0_ctx_switch_enable(adev, false); 1371 sdma_v7_0_enable(adev, false); 1372 1373 return 0; 1374 } 1375 1376 static int sdma_v7_0_suspend(struct amdgpu_ip_block *ip_block) 1377 { 1378 return sdma_v7_0_hw_fini(ip_block); 1379 } 1380 1381 static int sdma_v7_0_resume(struct amdgpu_ip_block *ip_block) 1382 { 1383 return sdma_v7_0_hw_init(ip_block); 1384 } 1385 1386 static bool sdma_v7_0_is_idle(struct amdgpu_ip_block *ip_block) 1387 { 1388 struct amdgpu_device *adev = ip_block->adev; 1389 u32 i; 1390 1391 for (i = 0; i < adev->sdma.num_instances; i++) { 1392 u32 tmp = RREG32(sdma_v7_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG)); 1393 1394 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1395 return false; 1396 } 1397 1398 return true; 1399 } 1400 1401 static int sdma_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1402 { 1403 unsigned i; 1404 u32 sdma0, sdma1; 1405 struct amdgpu_device *adev = ip_block->adev; 1406 1407 for (i = 0; i < adev->usec_timeout; i++) { 1408 sdma0 = RREG32(sdma_v7_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG)); 1409 sdma1 = RREG32(sdma_v7_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG)); 1410 1411 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1412 return 0; 1413 udelay(1); 1414 } 1415 return -ETIMEDOUT; 1416 } 1417 1418 static int sdma_v7_0_ring_preempt_ib(struct amdgpu_ring *ring) 1419 { 1420 int i, r = 0; 1421 struct amdgpu_device *adev = ring->adev; 1422 u32 index = 0; 1423 u64 sdma_gfx_preempt; 1424 1425 amdgpu_sdma_get_index_from_ring(ring, &index); 1426 sdma_gfx_preempt = 1427 sdma_v7_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT); 1428 1429 /* assert preemption condition */ 1430 amdgpu_ring_set_preempt_cond_exec(ring, false); 1431 1432 /* emit the trailing fence */ 1433 ring->trail_seq += 1; 1434 r = amdgpu_ring_alloc(ring, 10); 1435 if (r) { 1436 DRM_ERROR("ring %d failed to be allocated \n", ring->idx); 1437 return r; 1438 } 1439 sdma_v7_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1440 ring->trail_seq, 0); 1441 amdgpu_ring_commit(ring); 1442 1443 /* assert IB preemption */ 1444 WREG32(sdma_gfx_preempt, 1); 1445 1446 /* poll the trailing fence */ 1447 for (i = 0; i < adev->usec_timeout; i++) { 1448 if (ring->trail_seq == 1449 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1450 break; 1451 udelay(1); 1452 } 1453 1454 if (i >= adev->usec_timeout) { 1455 r = -EINVAL; 1456 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1457 } 1458 1459 /* deassert IB preemption */ 1460 WREG32(sdma_gfx_preempt, 0); 1461 1462 /* deassert the preemption condition */ 1463 amdgpu_ring_set_preempt_cond_exec(ring, true); 1464 return r; 1465 } 1466 1467 static int sdma_v7_0_set_trap_irq_state(struct amdgpu_device *adev, 1468 struct amdgpu_irq_src *source, 1469 unsigned type, 1470 enum amdgpu_interrupt_state state) 1471 { 1472 u32 sdma_cntl; 1473 1474 u32 reg_offset = sdma_v7_0_get_reg_offset(adev, type, regSDMA0_CNTL); 1475 1476 sdma_cntl = RREG32(reg_offset); 1477 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1478 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1479 WREG32(reg_offset, sdma_cntl); 1480 1481 return 0; 1482 } 1483 1484 static int sdma_v7_0_process_trap_irq(struct amdgpu_device *adev, 1485 struct amdgpu_irq_src *source, 1486 struct amdgpu_iv_entry *entry) 1487 { 1488 int instances, queue; 1489 uint32_t mes_queue_id = entry->src_data[0]; 1490 1491 DRM_DEBUG("IH: SDMA trap\n"); 1492 1493 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 1494 struct amdgpu_mes_queue *queue; 1495 1496 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 1497 1498 spin_lock(&adev->mes.queue_id_lock); 1499 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 1500 if (queue) { 1501 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); 1502 amdgpu_fence_process(queue->ring); 1503 } 1504 spin_unlock(&adev->mes.queue_id_lock); 1505 return 0; 1506 } 1507 1508 queue = entry->ring_id & 0xf; 1509 instances = (entry->ring_id & 0xf0) >> 4; 1510 if (instances > 1) { 1511 DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n"); 1512 return -EINVAL; 1513 } 1514 1515 switch (entry->client_id) { 1516 case SOC21_IH_CLIENTID_GFX: 1517 switch (queue) { 1518 case 0: 1519 amdgpu_fence_process(&adev->sdma.instance[instances].ring); 1520 break; 1521 default: 1522 break; 1523 } 1524 break; 1525 } 1526 return 0; 1527 } 1528 1529 static int sdma_v7_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1530 struct amdgpu_irq_src *source, 1531 struct amdgpu_iv_entry *entry) 1532 { 1533 return 0; 1534 } 1535 1536 static int sdma_v7_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1537 enum amd_clockgating_state state) 1538 { 1539 return 0; 1540 } 1541 1542 static int sdma_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 1543 enum amd_powergating_state state) 1544 { 1545 return 0; 1546 } 1547 1548 static void sdma_v7_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1549 { 1550 } 1551 1552 static void sdma_v7_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 1553 { 1554 struct amdgpu_device *adev = ip_block->adev; 1555 int i, j; 1556 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_0); 1557 uint32_t instance_offset; 1558 1559 if (!adev->sdma.ip_dump) 1560 return; 1561 1562 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances); 1563 for (i = 0; i < adev->sdma.num_instances; i++) { 1564 instance_offset = i * reg_count; 1565 drm_printf(p, "\nInstance:%d\n", i); 1566 1567 for (j = 0; j < reg_count; j++) 1568 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_7_0[j].reg_name, 1569 adev->sdma.ip_dump[instance_offset + j]); 1570 } 1571 } 1572 1573 static void sdma_v7_0_dump_ip_state(struct amdgpu_ip_block *ip_block) 1574 { 1575 struct amdgpu_device *adev = ip_block->adev; 1576 int i, j; 1577 uint32_t instance_offset; 1578 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_0); 1579 1580 if (!adev->sdma.ip_dump) 1581 return; 1582 1583 amdgpu_gfx_off_ctrl(adev, false); 1584 for (i = 0; i < adev->sdma.num_instances; i++) { 1585 instance_offset = i * reg_count; 1586 for (j = 0; j < reg_count; j++) 1587 adev->sdma.ip_dump[instance_offset + j] = 1588 RREG32(sdma_v7_0_get_reg_offset(adev, i, 1589 sdma_reg_list_7_0[j].reg_offset)); 1590 } 1591 amdgpu_gfx_off_ctrl(adev, true); 1592 } 1593 1594 const struct amd_ip_funcs sdma_v7_0_ip_funcs = { 1595 .name = "sdma_v7_0", 1596 .early_init = sdma_v7_0_early_init, 1597 .late_init = NULL, 1598 .sw_init = sdma_v7_0_sw_init, 1599 .sw_fini = sdma_v7_0_sw_fini, 1600 .hw_init = sdma_v7_0_hw_init, 1601 .hw_fini = sdma_v7_0_hw_fini, 1602 .suspend = sdma_v7_0_suspend, 1603 .resume = sdma_v7_0_resume, 1604 .is_idle = sdma_v7_0_is_idle, 1605 .wait_for_idle = sdma_v7_0_wait_for_idle, 1606 .soft_reset = sdma_v7_0_soft_reset, 1607 .check_soft_reset = sdma_v7_0_check_soft_reset, 1608 .set_clockgating_state = sdma_v7_0_set_clockgating_state, 1609 .set_powergating_state = sdma_v7_0_set_powergating_state, 1610 .get_clockgating_state = sdma_v7_0_get_clockgating_state, 1611 .dump_ip_state = sdma_v7_0_dump_ip_state, 1612 .print_ip_state = sdma_v7_0_print_ip_state, 1613 }; 1614 1615 static const struct amdgpu_ring_funcs sdma_v7_0_ring_funcs = { 1616 .type = AMDGPU_RING_TYPE_SDMA, 1617 .align_mask = 0xf, 1618 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1619 .support_64bit_ptrs = true, 1620 .secure_submission_supported = true, 1621 .get_rptr = sdma_v7_0_ring_get_rptr, 1622 .get_wptr = sdma_v7_0_ring_get_wptr, 1623 .set_wptr = sdma_v7_0_ring_set_wptr, 1624 .emit_frame_size = 1625 5 + /* sdma_v7_0_ring_init_cond_exec */ 1626 6 + /* sdma_v7_0_ring_emit_hdp_flush */ 1627 6 + /* sdma_v7_0_ring_emit_pipeline_sync */ 1628 /* sdma_v7_0_ring_emit_vm_flush */ 1629 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1630 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1631 10 + 10 + 10, /* sdma_v7_0_ring_emit_fence x3 for user fence, vm fence */ 1632 .emit_ib_size = 5 + 7 + 6, /* sdma_v7_0_ring_emit_ib */ 1633 .emit_ib = sdma_v7_0_ring_emit_ib, 1634 .emit_mem_sync = sdma_v7_0_ring_emit_mem_sync, 1635 .emit_fence = sdma_v7_0_ring_emit_fence, 1636 .emit_pipeline_sync = sdma_v7_0_ring_emit_pipeline_sync, 1637 .emit_vm_flush = sdma_v7_0_ring_emit_vm_flush, 1638 .emit_hdp_flush = sdma_v7_0_ring_emit_hdp_flush, 1639 .test_ring = sdma_v7_0_ring_test_ring, 1640 .test_ib = sdma_v7_0_ring_test_ib, 1641 .insert_nop = sdma_v7_0_ring_insert_nop, 1642 .pad_ib = sdma_v7_0_ring_pad_ib, 1643 .emit_wreg = sdma_v7_0_ring_emit_wreg, 1644 .emit_reg_wait = sdma_v7_0_ring_emit_reg_wait, 1645 .emit_reg_write_reg_wait = sdma_v7_0_ring_emit_reg_write_reg_wait, 1646 .init_cond_exec = sdma_v7_0_ring_init_cond_exec, 1647 .preempt_ib = sdma_v7_0_ring_preempt_ib, 1648 .reset = sdma_v7_0_reset_queue, 1649 }; 1650 1651 static void sdma_v7_0_set_ring_funcs(struct amdgpu_device *adev) 1652 { 1653 int i; 1654 1655 for (i = 0; i < adev->sdma.num_instances; i++) { 1656 adev->sdma.instance[i].ring.funcs = &sdma_v7_0_ring_funcs; 1657 adev->sdma.instance[i].ring.me = i; 1658 } 1659 } 1660 1661 static const struct amdgpu_irq_src_funcs sdma_v7_0_trap_irq_funcs = { 1662 .set = sdma_v7_0_set_trap_irq_state, 1663 .process = sdma_v7_0_process_trap_irq, 1664 }; 1665 1666 static const struct amdgpu_irq_src_funcs sdma_v7_0_illegal_inst_irq_funcs = { 1667 .process = sdma_v7_0_process_illegal_inst_irq, 1668 }; 1669 1670 static void sdma_v7_0_set_irq_funcs(struct amdgpu_device *adev) 1671 { 1672 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1673 adev->sdma.num_instances; 1674 adev->sdma.trap_irq.funcs = &sdma_v7_0_trap_irq_funcs; 1675 adev->sdma.illegal_inst_irq.funcs = &sdma_v7_0_illegal_inst_irq_funcs; 1676 } 1677 1678 /** 1679 * sdma_v7_0_emit_copy_buffer - copy buffer using the sDMA engine 1680 * 1681 * @ib: indirect buffer to fill with commands 1682 * @src_offset: src GPU address 1683 * @dst_offset: dst GPU address 1684 * @byte_count: number of bytes to xfer 1685 * @copy_flags: copy flags for the buffers 1686 * 1687 * Copy GPU buffers using the DMA engine. 1688 * Used by the amdgpu ttm implementation to move pages if 1689 * registered as the asic copy callback. 1690 */ 1691 static void sdma_v7_0_emit_copy_buffer(struct amdgpu_ib *ib, 1692 uint64_t src_offset, 1693 uint64_t dst_offset, 1694 uint32_t byte_count, 1695 uint32_t copy_flags) 1696 { 1697 uint32_t num_type, data_format, max_com, write_cm; 1698 1699 max_com = AMDGPU_COPY_FLAGS_GET(copy_flags, MAX_COMPRESSED); 1700 data_format = AMDGPU_COPY_FLAGS_GET(copy_flags, DATA_FORMAT); 1701 num_type = AMDGPU_COPY_FLAGS_GET(copy_flags, NUMBER_TYPE); 1702 write_cm = AMDGPU_COPY_FLAGS_GET(copy_flags, WRITE_COMPRESS_DISABLE) ? 2 : 1; 1703 1704 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1705 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1706 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0) | 1707 SDMA_PKT_COPY_LINEAR_HEADER_CPV(1); 1708 1709 ib->ptr[ib->length_dw++] = byte_count - 1; 1710 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1711 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1712 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1713 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1714 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1715 1716 if ((copy_flags & (AMDGPU_COPY_FLAGS_READ_DECOMPRESSED | AMDGPU_COPY_FLAGS_WRITE_COMPRESSED))) 1717 ib->ptr[ib->length_dw++] = SDMA_DCC_DATA_FORMAT(data_format) | SDMA_DCC_NUM_TYPE(num_type) | 1718 ((copy_flags & AMDGPU_COPY_FLAGS_READ_DECOMPRESSED) ? SDMA_DCC_READ_CM(2) : 0) | 1719 ((copy_flags & AMDGPU_COPY_FLAGS_WRITE_COMPRESSED) ? SDMA_DCC_WRITE_CM(write_cm) : 0) | 1720 SDMA_DCC_MAX_COM(max_com) | SDMA_DCC_MAX_UCOM(1); 1721 else 1722 ib->ptr[ib->length_dw++] = 0; 1723 } 1724 1725 /** 1726 * sdma_v7_0_emit_fill_buffer - fill buffer using the sDMA engine 1727 * 1728 * @ib: indirect buffer to fill 1729 * @src_data: value to write to buffer 1730 * @dst_offset: dst GPU address 1731 * @byte_count: number of bytes to xfer 1732 * 1733 * Fill GPU buffers using the DMA engine. 1734 */ 1735 static void sdma_v7_0_emit_fill_buffer(struct amdgpu_ib *ib, 1736 uint32_t src_data, 1737 uint64_t dst_offset, 1738 uint32_t byte_count) 1739 { 1740 ib->ptr[ib->length_dw++] = SDMA_PKT_CONSTANT_FILL_HEADER_OP(SDMA_OP_CONST_FILL) | 1741 SDMA_PKT_CONSTANT_FILL_HEADER_COMPRESS(1); 1742 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1743 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1744 ib->ptr[ib->length_dw++] = src_data; 1745 ib->ptr[ib->length_dw++] = byte_count - 1; 1746 } 1747 1748 static const struct amdgpu_buffer_funcs sdma_v7_0_buffer_funcs = { 1749 .copy_max_bytes = 0x400000, 1750 .copy_num_dw = 8, 1751 .emit_copy_buffer = sdma_v7_0_emit_copy_buffer, 1752 .fill_max_bytes = 0x400000, 1753 .fill_num_dw = 5, 1754 .emit_fill_buffer = sdma_v7_0_emit_fill_buffer, 1755 }; 1756 1757 static void sdma_v7_0_set_buffer_funcs(struct amdgpu_device *adev) 1758 { 1759 adev->mman.buffer_funcs = &sdma_v7_0_buffer_funcs; 1760 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1761 } 1762 1763 static const struct amdgpu_vm_pte_funcs sdma_v7_0_vm_pte_funcs = { 1764 .copy_pte_num_dw = 8, 1765 .copy_pte = sdma_v7_0_vm_copy_pte, 1766 .write_pte = sdma_v7_0_vm_write_pte, 1767 .set_pte_pde = sdma_v7_0_vm_set_pte_pde, 1768 }; 1769 1770 static void sdma_v7_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1771 { 1772 unsigned i; 1773 1774 adev->vm_manager.vm_pte_funcs = &sdma_v7_0_vm_pte_funcs; 1775 for (i = 0; i < adev->sdma.num_instances; i++) { 1776 adev->vm_manager.vm_pte_scheds[i] = 1777 &adev->sdma.instance[i].ring.sched; 1778 } 1779 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1780 } 1781 1782 const struct amdgpu_ip_block_version sdma_v7_0_ip_block = { 1783 .type = AMD_IP_BLOCK_TYPE_SDMA, 1784 .major = 7, 1785 .minor = 0, 1786 .rev = 0, 1787 .funcs = &sdma_v7_0_ip_funcs, 1788 }; 1789