1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_12_0_0_offset.h" 34 #include "gc/gc_12_0_0_sh_mask.h" 35 #include "hdp/hdp_6_0_0_offset.h" 36 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 37 38 #include "soc15_common.h" 39 #include "soc15.h" 40 #include "sdma_v6_0_0_pkt_open.h" 41 #include "nbio_v4_3.h" 42 #include "sdma_common.h" 43 #include "sdma_v7_0.h" 44 #include "v12_structs.h" 45 46 MODULE_FIRMWARE("amdgpu/sdma_7_0_0.bin"); 47 MODULE_FIRMWARE("amdgpu/sdma_7_0_1.bin"); 48 49 #define SDMA1_REG_OFFSET 0x600 50 #define SDMA0_HYP_DEC_REG_START 0x5880 51 #define SDMA0_HYP_DEC_REG_END 0x589a 52 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 53 54 static const struct amdgpu_hwip_reg_entry sdma_reg_list_7_0[] = { 55 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS_REG), 56 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS1_REG), 57 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS2_REG), 58 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS3_REG), 59 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS4_REG), 60 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS5_REG), 61 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS6_REG), 62 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UCODE_REV), 63 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH_HI), 64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH), 65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_STATUS), 66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_STATUS), 67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK0), 68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK1), 69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK0), 70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK1), 71 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_CNTL), 72 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR), 73 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR_HI), 74 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR), 75 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR_HI), 76 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_OFFSET), 77 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_LO), 78 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_HI), 79 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_CNTL), 80 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_RPTR), 81 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_SUB_REMAIN), 82 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_DUMMY_REG), 83 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE_STATUS0), 84 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_CNTL), 85 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR), 86 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR_HI), 87 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR), 88 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR_HI), 89 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_OFFSET), 90 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_LO), 91 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_HI), 92 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_RPTR), 93 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_SUB_REMAIN), 94 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_DUMMY_REG), 95 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_CNTL), 96 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR), 97 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR_HI), 98 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR), 99 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR_HI), 100 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_OFFSET), 101 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_LO), 102 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_HI), 103 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_RPTR), 104 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_SUB_REMAIN), 105 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_DUMMY_REG), 106 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_INT_STATUS), 107 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_VM_CNTL), 108 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 109 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_CHICKEN_BITS), 110 }; 111 112 static void sdma_v7_0_set_ring_funcs(struct amdgpu_device *adev); 113 static void sdma_v7_0_set_buffer_funcs(struct amdgpu_device *adev); 114 static void sdma_v7_0_set_vm_pte_funcs(struct amdgpu_device *adev); 115 static void sdma_v7_0_set_irq_funcs(struct amdgpu_device *adev); 116 static int sdma_v7_0_start(struct amdgpu_device *adev); 117 118 static u32 sdma_v7_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 119 { 120 u32 base; 121 122 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 123 internal_offset <= SDMA0_HYP_DEC_REG_END) { 124 base = adev->reg_offset[GC_HWIP][0][1]; 125 if (instance != 0) 126 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance; 127 } else { 128 base = adev->reg_offset[GC_HWIP][0][0]; 129 if (instance == 1) 130 internal_offset += SDMA1_REG_OFFSET; 131 } 132 133 return base + internal_offset; 134 } 135 136 static unsigned sdma_v7_0_ring_init_cond_exec(struct amdgpu_ring *ring, 137 uint64_t addr) 138 { 139 unsigned ret; 140 141 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE)); 142 amdgpu_ring_write(ring, lower_32_bits(addr)); 143 amdgpu_ring_write(ring, upper_32_bits(addr)); 144 amdgpu_ring_write(ring, 1); 145 /* this is the offset we need patch later */ 146 ret = ring->wptr & ring->buf_mask; 147 /* insert dummy here and patch it later */ 148 amdgpu_ring_write(ring, 0); 149 150 return ret; 151 } 152 153 /** 154 * sdma_v7_0_ring_get_rptr - get the current read pointer 155 * 156 * @ring: amdgpu ring pointer 157 * 158 * Get the current rptr from the hardware. 159 */ 160 static uint64_t sdma_v7_0_ring_get_rptr(struct amdgpu_ring *ring) 161 { 162 u64 *rptr; 163 164 /* XXX check if swapping is necessary on BE */ 165 rptr = (u64 *)ring->rptr_cpu_addr; 166 167 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 168 return ((*rptr) >> 2); 169 } 170 171 /** 172 * sdma_v7_0_ring_get_wptr - get the current write pointer 173 * 174 * @ring: amdgpu ring pointer 175 * 176 * Get the current wptr from the hardware. 177 */ 178 static uint64_t sdma_v7_0_ring_get_wptr(struct amdgpu_ring *ring) 179 { 180 u64 wptr = 0; 181 182 if (ring->use_doorbell) { 183 /* XXX check if swapping is necessary on BE */ 184 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 185 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 186 } 187 188 return wptr >> 2; 189 } 190 191 /** 192 * sdma_v7_0_ring_set_wptr - commit the write pointer 193 * 194 * @ring: amdgpu ring pointer 195 * 196 * Write the wptr back to the hardware. 197 */ 198 static void sdma_v7_0_ring_set_wptr(struct amdgpu_ring *ring) 199 { 200 struct amdgpu_device *adev = ring->adev; 201 uint32_t *wptr_saved; 202 uint32_t *is_queue_unmap; 203 uint64_t aggregated_db_index; 204 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_DMA].mqd_size; 205 206 DRM_DEBUG("Setting write pointer\n"); 207 208 if (ring->is_mes_queue) { 209 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 210 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 211 sizeof(uint32_t)); 212 aggregated_db_index = 213 amdgpu_mes_get_aggregated_doorbell_index(adev, 214 ring->hw_prio); 215 216 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 217 ring->wptr << 2); 218 *wptr_saved = ring->wptr << 2; 219 if (*is_queue_unmap) { 220 WDOORBELL64(aggregated_db_index, ring->wptr << 2); 221 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 222 ring->doorbell_index, ring->wptr << 2); 223 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 224 } else { 225 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 226 ring->doorbell_index, ring->wptr << 2); 227 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 228 } 229 } else { 230 if (ring->use_doorbell) { 231 DRM_DEBUG("Using doorbell -- " 232 "wptr_offs == 0x%08x " 233 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 234 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 235 ring->wptr_offs, 236 lower_32_bits(ring->wptr << 2), 237 upper_32_bits(ring->wptr << 2)); 238 /* XXX check if swapping is necessary on BE */ 239 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 240 ring->wptr << 2); 241 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 242 ring->doorbell_index, ring->wptr << 2); 243 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 244 } else { 245 DRM_DEBUG("Not using doorbell -- " 246 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 247 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 248 ring->me, 249 lower_32_bits(ring->wptr << 2), 250 ring->me, 251 upper_32_bits(ring->wptr << 2)); 252 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, 253 ring->me, 254 regSDMA0_QUEUE0_RB_WPTR), 255 lower_32_bits(ring->wptr << 2)); 256 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, 257 ring->me, 258 regSDMA0_QUEUE0_RB_WPTR_HI), 259 upper_32_bits(ring->wptr << 2)); 260 } 261 } 262 } 263 264 static void sdma_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 265 { 266 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 267 int i; 268 269 for (i = 0; i < count; i++) 270 if (sdma && sdma->burst_nop && (i == 0)) 271 amdgpu_ring_write(ring, ring->funcs->nop | 272 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 273 else 274 amdgpu_ring_write(ring, ring->funcs->nop); 275 } 276 277 /** 278 * sdma_v7_0_ring_emit_ib - Schedule an IB on the DMA engine 279 * 280 * @ring: amdgpu ring pointer 281 * @job: job to retrieve vmid from 282 * @ib: IB object to schedule 283 * @flags: unused 284 * 285 * Schedule an IB in the DMA ring. 286 */ 287 static void sdma_v7_0_ring_emit_ib(struct amdgpu_ring *ring, 288 struct amdgpu_job *job, 289 struct amdgpu_ib *ib, 290 uint32_t flags) 291 { 292 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 293 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 294 295 /* An IB packet must end on a 8 DW boundary--the next dword 296 * must be on a 8-dword boundary. Our IB packet below is 6 297 * dwords long, thus add x number of NOPs, such that, in 298 * modular arithmetic, 299 * wptr + 6 + x = 8k, k >= 0, which in C is, 300 * (wptr + 6 + x) % 8 = 0. 301 * The expression below, is a solution of x. 302 */ 303 sdma_v7_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 304 305 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) | 306 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 307 /* base must be 32 byte aligned */ 308 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 309 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 310 amdgpu_ring_write(ring, ib->length_dw); 311 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 312 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 313 } 314 315 /** 316 * sdma_v7_0_ring_emit_mem_sync - flush the IB by graphics cache rinse 317 * 318 * @ring: amdgpu ring pointer 319 * 320 * flush the IB by graphics cache rinse. 321 */ 322 static void sdma_v7_0_ring_emit_mem_sync(struct amdgpu_ring *ring) 323 { 324 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV | 325 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 326 SDMA_GCR_GLI_INV(1); 327 328 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 329 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ)); 330 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 331 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 332 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 333 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 334 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 335 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 336 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 337 } 338 339 340 /** 341 * sdma_v7_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 342 * 343 * @ring: amdgpu ring pointer 344 * 345 * Emit an hdp flush packet on the requested DMA ring. 346 */ 347 static void sdma_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 348 { 349 struct amdgpu_device *adev = ring->adev; 350 u32 ref_and_mask = 0; 351 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 352 353 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 354 355 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 356 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 357 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 358 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 359 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 360 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 361 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 362 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 363 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 364 } 365 366 /** 367 * sdma_v7_0_ring_emit_fence - emit a fence on the DMA ring 368 * 369 * @ring: amdgpu ring pointer 370 * @addr: address 371 * @seq: fence seq number 372 * @flags: fence flags 373 * 374 * Add a DMA fence packet to the ring to write 375 * the fence seq number and DMA trap packet to generate 376 * an interrupt if needed. 377 */ 378 static void sdma_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 379 unsigned flags) 380 { 381 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 382 /* write the fence */ 383 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 384 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 385 /* zero in first two bits */ 386 BUG_ON(addr & 0x3); 387 amdgpu_ring_write(ring, lower_32_bits(addr)); 388 amdgpu_ring_write(ring, upper_32_bits(addr)); 389 amdgpu_ring_write(ring, lower_32_bits(seq)); 390 391 /* optionally write high bits as well */ 392 if (write64bit) { 393 addr += 4; 394 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 395 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 396 /* zero in first two bits */ 397 BUG_ON(addr & 0x3); 398 amdgpu_ring_write(ring, lower_32_bits(addr)); 399 amdgpu_ring_write(ring, upper_32_bits(addr)); 400 amdgpu_ring_write(ring, upper_32_bits(seq)); 401 } 402 403 if (flags & AMDGPU_FENCE_FLAG_INT) { 404 uint32_t ctx = ring->is_mes_queue ? 405 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0; 406 /* generate an interrupt */ 407 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP)); 408 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx)); 409 } 410 } 411 412 /** 413 * sdma_v7_0_gfx_stop - stop the gfx async dma engines 414 * 415 * @adev: amdgpu_device pointer 416 * 417 * Stop the gfx async dma ring buffers. 418 */ 419 static void sdma_v7_0_gfx_stop(struct amdgpu_device *adev) 420 { 421 u32 rb_cntl, ib_cntl; 422 int i; 423 424 for (i = 0; i < adev->sdma.num_instances; i++) { 425 rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 426 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0); 427 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 428 ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 429 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0); 430 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 431 } 432 } 433 434 /** 435 * sdma_v7_0_rlc_stop - stop the compute async dma engines 436 * 437 * @adev: amdgpu_device pointer 438 * 439 * Stop the compute async dma queues. 440 */ 441 static void sdma_v7_0_rlc_stop(struct amdgpu_device *adev) 442 { 443 /* XXX todo */ 444 } 445 446 /** 447 * sdma_v7_0_ctx_switch_enable - stop the async dma engines context switch 448 * 449 * @adev: amdgpu_device pointer 450 * @enable: enable/disable the DMA MEs context switch. 451 * 452 * Halt or unhalt the async dma engines context switch. 453 */ 454 static void sdma_v7_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 455 { 456 } 457 458 /** 459 * sdma_v7_0_enable - stop the async dma engines 460 * 461 * @adev: amdgpu_device pointer 462 * @enable: enable/disable the DMA MEs. 463 * 464 * Halt or unhalt the async dma engines. 465 */ 466 static void sdma_v7_0_enable(struct amdgpu_device *adev, bool enable) 467 { 468 u32 mcu_cntl; 469 int i; 470 471 if (!enable) { 472 sdma_v7_0_gfx_stop(adev); 473 sdma_v7_0_rlc_stop(adev); 474 } 475 476 if (amdgpu_sriov_vf(adev)) 477 return; 478 479 for (i = 0; i < adev->sdma.num_instances; i++) { 480 mcu_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL)); 481 mcu_cntl = REG_SET_FIELD(mcu_cntl, SDMA0_MCU_CNTL, HALT, enable ? 0 : 1); 482 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), mcu_cntl); 483 } 484 } 485 486 /** 487 * sdma_v7_0_gfx_resume - setup and start the async dma engines 488 * 489 * @adev: amdgpu_device pointer 490 * 491 * Set up the gfx DMA ring buffers and enable them. 492 * Returns 0 for success, error for failure. 493 */ 494 static int sdma_v7_0_gfx_resume(struct amdgpu_device *adev) 495 { 496 struct amdgpu_ring *ring; 497 u32 rb_cntl, ib_cntl; 498 u32 rb_bufsz; 499 u32 doorbell; 500 u32 doorbell_offset; 501 u32 tmp; 502 u64 wptr_gpu_addr; 503 int i, r; 504 505 for (i = 0; i < adev->sdma.num_instances; i++) { 506 ring = &adev->sdma.instance[i].ring; 507 508 //if (!amdgpu_sriov_vf(adev)) 509 // WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 510 511 /* Set ring buffer size in dwords */ 512 rb_bufsz = order_base_2(ring->ring_size / 4); 513 rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 514 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); 515 #ifdef __BIG_ENDIAN 516 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1); 517 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, 518 RPTR_WRITEBACK_SWAP_ENABLE, 1); 519 #endif 520 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1); 521 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 522 523 /* Initialize the ring buffer's read and write pointers */ 524 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0); 525 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0); 526 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0); 527 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0); 528 529 /* setup the wptr shadow polling */ 530 wptr_gpu_addr = ring->wptr_gpu_addr; 531 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO), 532 lower_32_bits(wptr_gpu_addr)); 533 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI), 534 upper_32_bits(wptr_gpu_addr)); 535 536 /* set the wb address whether it's enabled or not */ 537 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI), 538 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 539 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO), 540 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 541 542 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 543 if (amdgpu_sriov_vf(adev)) 544 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 1); 545 else 546 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0); 547 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, MCU_WPTR_POLL_ENABLE, 1); 548 549 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8); 550 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40); 551 552 ring->wptr = 0; 553 554 /* before programing wptr to a less value, need set minor_ptr_update first */ 555 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1); 556 557 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 558 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2); 559 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 560 } 561 562 doorbell = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL)); 563 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET)); 564 565 if (ring->use_doorbell) { 566 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 567 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET, 568 OFFSET, ring->doorbell_index); 569 } else { 570 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0); 571 } 572 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell); 573 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset); 574 575 if (i == 0) 576 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 577 ring->doorbell_index, 578 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances); 579 580 if (amdgpu_sriov_vf(adev)) 581 sdma_v7_0_ring_set_wptr(ring); 582 583 /* set minor_ptr_update to 0 after wptr programed */ 584 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0); 585 586 /* Set up sdma hang watchdog */ 587 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL)); 588 /* 100ms per unit */ 589 tmp = REG_SET_FIELD(tmp, SDMA0_WATCHDOG_CNTL, QUEUE_HANG_COUNT, 590 max(adev->usec_timeout/100000, 1)); 591 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), tmp); 592 593 /* Set up RESP_MODE to non-copy addresses */ 594 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL)); 595 tmp = REG_SET_FIELD(tmp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 596 tmp = REG_SET_FIELD(tmp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 597 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), tmp); 598 599 /* program default cache read and write policy */ 600 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE)); 601 /* clean read policy and write policy bits */ 602 tmp &= 0xFF0FFF; 603 tmp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | 604 (CACHE_WRITE_POLICY_L2__DEFAULT << 14)); 605 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), tmp); 606 607 if (!amdgpu_sriov_vf(adev)) { 608 /* unhalt engine */ 609 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL)); 610 tmp = REG_SET_FIELD(tmp, SDMA0_MCU_CNTL, HALT, 0); 611 tmp = REG_SET_FIELD(tmp, SDMA0_MCU_CNTL, RESET, 0); 612 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), tmp); 613 } 614 615 /* enable DMA RB */ 616 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1); 617 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 618 619 ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 620 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1); 621 #ifdef __BIG_ENDIAN 622 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1); 623 #endif 624 /* enable DMA IBs */ 625 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 626 627 ring->sched.ready = true; 628 629 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 630 sdma_v7_0_ctx_switch_enable(adev, true); 631 sdma_v7_0_enable(adev, true); 632 } 633 634 r = amdgpu_ring_test_helper(ring); 635 if (r) { 636 ring->sched.ready = false; 637 return r; 638 } 639 640 } 641 642 return 0; 643 } 644 645 /** 646 * sdma_v7_0_rlc_resume - setup and start the async dma engines 647 * 648 * @adev: amdgpu_device pointer 649 * 650 * Set up the compute DMA queues and enable them. 651 * Returns 0 for success, error for failure. 652 */ 653 static int sdma_v7_0_rlc_resume(struct amdgpu_device *adev) 654 { 655 return 0; 656 } 657 658 static void sdma_v12_0_free_ucode_buffer(struct amdgpu_device *adev) 659 { 660 int i; 661 662 for (i = 0; i < adev->sdma.num_instances; i++) { 663 amdgpu_bo_free_kernel(&adev->sdma.instance[i].sdma_fw_obj, 664 &adev->sdma.instance[i].sdma_fw_gpu_addr, 665 (void **)&adev->sdma.instance[i].sdma_fw_ptr); 666 } 667 } 668 669 /** 670 * sdma_v7_0_load_microcode - load the sDMA ME ucode 671 * 672 * @adev: amdgpu_device pointer 673 * 674 * Loads the sDMA0/1 ucode. 675 * Returns 0 for success, -EINVAL if the ucode is not available. 676 */ 677 static int sdma_v7_0_load_microcode(struct amdgpu_device *adev) 678 { 679 const struct sdma_firmware_header_v3_0 *hdr; 680 const __le32 *fw_data; 681 u32 fw_size; 682 uint32_t tmp, sdma_status, ic_op_cntl; 683 int i, r, j; 684 685 /* halt the MEs */ 686 sdma_v7_0_enable(adev, false); 687 688 if (!adev->sdma.instance[0].fw) 689 return -EINVAL; 690 691 hdr = (const struct sdma_firmware_header_v3_0 *) 692 adev->sdma.instance[0].fw->data; 693 amdgpu_ucode_print_sdma_hdr(&hdr->header); 694 695 fw_data = (const __le32 *)(adev->sdma.instance[0].fw->data + 696 le32_to_cpu(hdr->ucode_offset_bytes)); 697 fw_size = le32_to_cpu(hdr->ucode_size_bytes); 698 699 for (i = 0; i < adev->sdma.num_instances; i++) { 700 r = amdgpu_bo_create_reserved(adev, fw_size, 701 PAGE_SIZE, 702 AMDGPU_GEM_DOMAIN_VRAM, 703 &adev->sdma.instance[i].sdma_fw_obj, 704 &adev->sdma.instance[i].sdma_fw_gpu_addr, 705 (void **)&adev->sdma.instance[i].sdma_fw_ptr); 706 if (r) { 707 dev_err(adev->dev, "(%d) failed to create sdma ucode bo\n", r); 708 return r; 709 } 710 711 memcpy(adev->sdma.instance[i].sdma_fw_ptr, fw_data, fw_size); 712 713 amdgpu_bo_kunmap(adev->sdma.instance[i].sdma_fw_obj); 714 amdgpu_bo_unreserve(adev->sdma.instance[i].sdma_fw_obj); 715 716 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_CNTL)); 717 tmp = REG_SET_FIELD(tmp, SDMA0_IC_CNTL, GPA, 0); 718 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_CNTL), tmp); 719 720 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_BASE_LO), 721 lower_32_bits(adev->sdma.instance[i].sdma_fw_gpu_addr)); 722 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_BASE_HI), 723 upper_32_bits(adev->sdma.instance[i].sdma_fw_gpu_addr)); 724 725 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL)); 726 tmp = REG_SET_FIELD(tmp, SDMA0_IC_OP_CNTL, PRIME_ICACHE, 1); 727 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL), tmp); 728 729 /* Wait for sdma ucode init complete */ 730 for (j = 0; j < adev->usec_timeout; j++) { 731 ic_op_cntl = RREG32_SOC15_IP(GC, 732 sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL)); 733 sdma_status = RREG32_SOC15_IP(GC, 734 sdma_v7_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG)); 735 if ((REG_GET_FIELD(ic_op_cntl, SDMA0_IC_OP_CNTL, ICACHE_PRIMED) == 1) && 736 (REG_GET_FIELD(sdma_status, SDMA0_STATUS_REG, UCODE_INIT_DONE) == 1)) 737 break; 738 udelay(1); 739 } 740 741 if (j >= adev->usec_timeout) { 742 dev_err(adev->dev, "failed to init sdma ucode\n"); 743 return -EINVAL; 744 } 745 } 746 747 return 0; 748 } 749 750 static int sdma_v7_0_soft_reset(void *handle) 751 { 752 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 753 u32 tmp; 754 int i; 755 756 sdma_v7_0_gfx_stop(adev); 757 758 for (i = 0; i < adev->sdma.num_instances; i++) { 759 //tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_FREEZE)); 760 //tmp |= SDMA0_FREEZE__FREEZE_MASK; 761 //WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp); 762 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL)); 763 tmp |= SDMA0_MCU_CNTL__HALT_MASK; 764 tmp |= SDMA0_MCU_CNTL__RESET_MASK; 765 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), tmp); 766 767 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0); 768 769 udelay(100); 770 771 tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i; 772 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); 773 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 774 775 udelay(100); 776 777 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0); 778 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 779 780 udelay(100); 781 } 782 783 return sdma_v7_0_start(adev); 784 } 785 786 static bool sdma_v7_0_check_soft_reset(void *handle) 787 { 788 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 789 struct amdgpu_ring *ring; 790 int i, r; 791 long tmo = msecs_to_jiffies(1000); 792 793 for (i = 0; i < adev->sdma.num_instances; i++) { 794 ring = &adev->sdma.instance[i].ring; 795 r = amdgpu_ring_test_ib(ring, tmo); 796 if (r) 797 return true; 798 } 799 800 return false; 801 } 802 803 /** 804 * sdma_v7_0_start - setup and start the async dma engines 805 * 806 * @adev: amdgpu_device pointer 807 * 808 * Set up the DMA engines and enable them. 809 * Returns 0 for success, error for failure. 810 */ 811 static int sdma_v7_0_start(struct amdgpu_device *adev) 812 { 813 int r = 0; 814 815 if (amdgpu_sriov_vf(adev)) { 816 sdma_v7_0_ctx_switch_enable(adev, false); 817 sdma_v7_0_enable(adev, false); 818 819 /* set RB registers */ 820 r = sdma_v7_0_gfx_resume(adev); 821 return r; 822 } 823 824 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 825 r = sdma_v7_0_load_microcode(adev); 826 if (r) { 827 sdma_v12_0_free_ucode_buffer(adev); 828 return r; 829 } 830 831 if (amdgpu_emu_mode == 1) 832 msleep(1000); 833 } 834 835 /* unhalt the MEs */ 836 sdma_v7_0_enable(adev, true); 837 /* enable sdma ring preemption */ 838 sdma_v7_0_ctx_switch_enable(adev, true); 839 840 /* start the gfx rings and rlc compute queues */ 841 r = sdma_v7_0_gfx_resume(adev); 842 if (r) 843 return r; 844 r = sdma_v7_0_rlc_resume(adev); 845 846 return r; 847 } 848 849 static int sdma_v7_0_mqd_init(struct amdgpu_device *adev, void *mqd, 850 struct amdgpu_mqd_prop *prop) 851 { 852 struct v12_sdma_mqd *m = mqd; 853 uint64_t wb_gpu_addr; 854 855 m->sdmax_rlcx_rb_cntl = 856 order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT | 857 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 858 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | 859 1 << SDMA0_QUEUE0_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT; 860 861 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8); 862 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); 863 864 wb_gpu_addr = prop->wptr_gpu_addr; 865 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); 866 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); 867 868 wb_gpu_addr = prop->rptr_gpu_addr; 869 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); 870 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); 871 872 m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, 0, 873 regSDMA0_QUEUE0_IB_CNTL)); 874 875 m->sdmax_rlcx_doorbell_offset = 876 prop->doorbell_index << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 877 878 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 879 880 m->sdmax_rlcx_doorbell_log = 0; 881 m->sdmax_rlcx_rb_aql_cntl = 0x4000; //regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT; 882 m->sdmax_rlcx_dummy_reg = 0xf; //regSDMA0_QUEUE0_DUMMY_REG_DEFAULT; 883 884 return 0; 885 } 886 887 static void sdma_v7_0_set_mqd_funcs(struct amdgpu_device *adev) 888 { 889 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v12_sdma_mqd); 890 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v7_0_mqd_init; 891 } 892 893 /** 894 * sdma_v7_0_ring_test_ring - simple async dma engine test 895 * 896 * @ring: amdgpu_ring structure holding ring information 897 * 898 * Test the DMA engine by writing using it to write an 899 * value to memory. 900 * Returns 0 for success, error for failure. 901 */ 902 static int sdma_v7_0_ring_test_ring(struct amdgpu_ring *ring) 903 { 904 struct amdgpu_device *adev = ring->adev; 905 unsigned i; 906 unsigned index; 907 int r; 908 u32 tmp; 909 u64 gpu_addr; 910 volatile uint32_t *cpu_ptr = NULL; 911 912 tmp = 0xCAFEDEAD; 913 914 if (ring->is_mes_queue) { 915 uint32_t offset = 0; 916 offset = amdgpu_mes_ctx_get_offs(ring, 917 AMDGPU_MES_CTX_PADDING_OFFS); 918 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 919 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 920 *cpu_ptr = tmp; 921 } else { 922 r = amdgpu_device_wb_get(adev, &index); 923 if (r) { 924 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 925 return r; 926 } 927 928 gpu_addr = adev->wb.gpu_addr + (index * 4); 929 adev->wb.wb[index] = cpu_to_le32(tmp); 930 } 931 932 r = amdgpu_ring_alloc(ring, 5); 933 if (r) { 934 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 935 if (!ring->is_mes_queue) 936 amdgpu_device_wb_free(adev, index); 937 return r; 938 } 939 940 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 941 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 942 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 943 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 944 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 945 amdgpu_ring_write(ring, 0xDEADBEEF); 946 amdgpu_ring_commit(ring); 947 948 for (i = 0; i < adev->usec_timeout; i++) { 949 if (ring->is_mes_queue) 950 tmp = le32_to_cpu(*cpu_ptr); 951 else 952 tmp = le32_to_cpu(adev->wb.wb[index]); 953 if (tmp == 0xDEADBEEF) 954 break; 955 if (amdgpu_emu_mode == 1) 956 msleep(1); 957 else 958 udelay(1); 959 } 960 961 if (i >= adev->usec_timeout) 962 r = -ETIMEDOUT; 963 964 if (!ring->is_mes_queue) 965 amdgpu_device_wb_free(adev, index); 966 967 return r; 968 } 969 970 /** 971 * sdma_v7_0_ring_test_ib - test an IB on the DMA engine 972 * 973 * @ring: amdgpu_ring structure holding ring information 974 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 975 * 976 * Test a simple IB in the DMA ring. 977 * Returns 0 on success, error on failure. 978 */ 979 static int sdma_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 980 { 981 struct amdgpu_device *adev = ring->adev; 982 struct amdgpu_ib ib; 983 struct dma_fence *f = NULL; 984 unsigned index; 985 long r; 986 u32 tmp = 0; 987 u64 gpu_addr; 988 volatile uint32_t *cpu_ptr = NULL; 989 990 tmp = 0xCAFEDEAD; 991 memset(&ib, 0, sizeof(ib)); 992 993 if (ring->is_mes_queue) { 994 uint32_t offset = 0; 995 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 996 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 997 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 998 999 offset = amdgpu_mes_ctx_get_offs(ring, 1000 AMDGPU_MES_CTX_PADDING_OFFS); 1001 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 1002 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 1003 *cpu_ptr = tmp; 1004 } else { 1005 r = amdgpu_device_wb_get(adev, &index); 1006 if (r) { 1007 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 1008 return r; 1009 } 1010 1011 gpu_addr = adev->wb.gpu_addr + (index * 4); 1012 adev->wb.wb[index] = cpu_to_le32(tmp); 1013 1014 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 1015 if (r) { 1016 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 1017 goto err0; 1018 } 1019 } 1020 1021 ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 1022 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1023 ib.ptr[1] = lower_32_bits(gpu_addr); 1024 ib.ptr[2] = upper_32_bits(gpu_addr); 1025 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1026 ib.ptr[4] = 0xDEADBEEF; 1027 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1028 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1029 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1030 ib.length_dw = 8; 1031 1032 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1033 if (r) 1034 goto err1; 1035 1036 r = dma_fence_wait_timeout(f, false, timeout); 1037 if (r == 0) { 1038 DRM_ERROR("amdgpu: IB test timed out\n"); 1039 r = -ETIMEDOUT; 1040 goto err1; 1041 } else if (r < 0) { 1042 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1043 goto err1; 1044 } 1045 1046 if (ring->is_mes_queue) 1047 tmp = le32_to_cpu(*cpu_ptr); 1048 else 1049 tmp = le32_to_cpu(adev->wb.wb[index]); 1050 1051 if (tmp == 0xDEADBEEF) 1052 r = 0; 1053 else 1054 r = -EINVAL; 1055 1056 err1: 1057 amdgpu_ib_free(adev, &ib, NULL); 1058 dma_fence_put(f); 1059 err0: 1060 if (!ring->is_mes_queue) 1061 amdgpu_device_wb_free(adev, index); 1062 return r; 1063 } 1064 1065 1066 /** 1067 * sdma_v7_0_vm_copy_pte - update PTEs by copying them from the GART 1068 * 1069 * @ib: indirect buffer to fill with commands 1070 * @pe: addr of the page entry 1071 * @src: src addr to copy from 1072 * @count: number of page entries to update 1073 * 1074 * Update PTEs by copying them from the GART using sDMA. 1075 */ 1076 static void sdma_v7_0_vm_copy_pte(struct amdgpu_ib *ib, 1077 uint64_t pe, uint64_t src, 1078 unsigned count) 1079 { 1080 unsigned bytes = count * 8; 1081 1082 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1083 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1084 ib->ptr[ib->length_dw++] = bytes - 1; 1085 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1086 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1087 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1088 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1089 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1090 1091 } 1092 1093 /** 1094 * sdma_v7_0_vm_write_pte - update PTEs by writing them manually 1095 * 1096 * @ib: indirect buffer to fill with commands 1097 * @pe: addr of the page entry 1098 * @value: dst addr to write into pe 1099 * @count: number of page entries to update 1100 * @incr: increase next addr by incr bytes 1101 * 1102 * Update PTEs by writing them manually using sDMA. 1103 */ 1104 static void sdma_v7_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1105 uint64_t value, unsigned count, 1106 uint32_t incr) 1107 { 1108 unsigned ndw = count * 2; 1109 1110 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 1111 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1112 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1113 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1114 ib->ptr[ib->length_dw++] = ndw - 1; 1115 for (; ndw > 0; ndw -= 2) { 1116 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1117 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1118 value += incr; 1119 } 1120 } 1121 1122 /** 1123 * sdma_v7_0_vm_set_pte_pde - update the page tables using sDMA 1124 * 1125 * @ib: indirect buffer to fill with commands 1126 * @pe: addr of the page entry 1127 * @addr: dst addr to write into pe 1128 * @count: number of page entries to update 1129 * @incr: increase next addr by incr bytes 1130 * @flags: access flags 1131 * 1132 * Update the page tables using sDMA. 1133 */ 1134 static void sdma_v7_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1135 uint64_t pe, 1136 uint64_t addr, unsigned count, 1137 uint32_t incr, uint64_t flags) 1138 { 1139 /* for physically contiguous pages (vram) */ 1140 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE); 1141 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1142 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1143 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1144 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1145 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1146 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1147 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1148 ib->ptr[ib->length_dw++] = 0; 1149 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1150 } 1151 1152 /** 1153 * sdma_v7_0_ring_pad_ib - pad the IB 1154 * 1155 * @ring: amdgpu ring pointer 1156 * @ib: indirect buffer to fill with padding 1157 * 1158 * Pad the IB with NOPs to a boundary multiple of 8. 1159 */ 1160 static void sdma_v7_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1161 { 1162 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1163 u32 pad_count; 1164 int i; 1165 1166 pad_count = (-ib->length_dw) & 0x7; 1167 for (i = 0; i < pad_count; i++) 1168 if (sdma && sdma->burst_nop && (i == 0)) 1169 ib->ptr[ib->length_dw++] = 1170 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) | 1171 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1172 else 1173 ib->ptr[ib->length_dw++] = 1174 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP); 1175 } 1176 1177 /** 1178 * sdma_v7_0_ring_emit_pipeline_sync - sync the pipeline 1179 * 1180 * @ring: amdgpu_ring pointer 1181 * 1182 * Make sure all previous operations are completed (CIK). 1183 */ 1184 static void sdma_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1185 { 1186 uint32_t seq = ring->fence_drv.sync_seq; 1187 uint64_t addr = ring->fence_drv.gpu_addr; 1188 1189 /* wait for idle */ 1190 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1191 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1192 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1193 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1194 amdgpu_ring_write(ring, addr & 0xfffffffc); 1195 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1196 amdgpu_ring_write(ring, seq); /* reference */ 1197 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1198 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1199 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1200 } 1201 1202 /** 1203 * sdma_v7_0_ring_emit_vm_flush - vm flush using sDMA 1204 * 1205 * @ring: amdgpu_ring pointer 1206 * @vmid: vmid number to use 1207 * @pd_addr: address 1208 * 1209 * Update the page table base and flush the VM TLB 1210 * using sDMA. 1211 */ 1212 static void sdma_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1213 unsigned vmid, uint64_t pd_addr) 1214 { 1215 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1216 } 1217 1218 static void sdma_v7_0_ring_emit_wreg(struct amdgpu_ring *ring, 1219 uint32_t reg, uint32_t val) 1220 { 1221 /* SRBM WRITE command will not support on sdma v7. 1222 * Use Register WRITE command instead, which OPCODE is same as SRBM WRITE 1223 */ 1224 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE)); 1225 amdgpu_ring_write(ring, reg << 2); 1226 amdgpu_ring_write(ring, val); 1227 } 1228 1229 static void sdma_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1230 uint32_t val, uint32_t mask) 1231 { 1232 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1233 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1234 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1235 amdgpu_ring_write(ring, reg << 2); 1236 amdgpu_ring_write(ring, 0); 1237 amdgpu_ring_write(ring, val); /* reference */ 1238 amdgpu_ring_write(ring, mask); /* mask */ 1239 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1240 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1241 } 1242 1243 static void sdma_v7_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1244 uint32_t reg0, uint32_t reg1, 1245 uint32_t ref, uint32_t mask) 1246 { 1247 amdgpu_ring_emit_wreg(ring, reg0, ref); 1248 /* wait for a cycle to reset vm_inv_eng*_ack */ 1249 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1250 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1251 } 1252 1253 static int sdma_v7_0_early_init(void *handle) 1254 { 1255 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1256 int r; 1257 1258 r = amdgpu_sdma_init_microcode(adev, 0, true); 1259 if (r) { 1260 DRM_ERROR("Failed to init sdma firmware!\n"); 1261 return r; 1262 } 1263 1264 sdma_v7_0_set_ring_funcs(adev); 1265 sdma_v7_0_set_buffer_funcs(adev); 1266 sdma_v7_0_set_vm_pte_funcs(adev); 1267 sdma_v7_0_set_irq_funcs(adev); 1268 sdma_v7_0_set_mqd_funcs(adev); 1269 1270 return 0; 1271 } 1272 1273 static int sdma_v7_0_sw_init(void *handle) 1274 { 1275 struct amdgpu_ring *ring; 1276 int r, i; 1277 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1278 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_0); 1279 uint32_t *ptr; 1280 1281 /* SDMA trap event */ 1282 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1283 GFX_11_0_0__SRCID__SDMA_TRAP, 1284 &adev->sdma.trap_irq); 1285 if (r) 1286 return r; 1287 1288 for (i = 0; i < adev->sdma.num_instances; i++) { 1289 ring = &adev->sdma.instance[i].ring; 1290 ring->ring_obj = NULL; 1291 ring->use_doorbell = true; 1292 ring->me = i; 1293 1294 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1295 ring->use_doorbell?"true":"false"); 1296 1297 ring->doorbell_index = 1298 (adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset 1299 1300 ring->vm_hub = AMDGPU_GFXHUB(0); 1301 sprintf(ring->name, "sdma%d", i); 1302 r = amdgpu_ring_init(adev, ring, 1024, 1303 &adev->sdma.trap_irq, 1304 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1305 AMDGPU_RING_PRIO_DEFAULT, NULL); 1306 if (r) 1307 return r; 1308 } 1309 1310 /* Allocate memory for SDMA IP Dump buffer */ 1311 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); 1312 if (ptr) 1313 adev->sdma.ip_dump = ptr; 1314 else 1315 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n"); 1316 1317 return r; 1318 } 1319 1320 static int sdma_v7_0_sw_fini(void *handle) 1321 { 1322 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1323 int i; 1324 1325 for (i = 0; i < adev->sdma.num_instances; i++) 1326 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1327 1328 amdgpu_sdma_destroy_inst_ctx(adev, true); 1329 1330 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) 1331 sdma_v12_0_free_ucode_buffer(adev); 1332 1333 kfree(adev->sdma.ip_dump); 1334 1335 return 0; 1336 } 1337 1338 static int sdma_v7_0_hw_init(void *handle) 1339 { 1340 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1341 1342 return sdma_v7_0_start(adev); 1343 } 1344 1345 static int sdma_v7_0_hw_fini(void *handle) 1346 { 1347 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1348 1349 if (amdgpu_sriov_vf(adev)) 1350 return 0; 1351 1352 sdma_v7_0_ctx_switch_enable(adev, false); 1353 sdma_v7_0_enable(adev, false); 1354 1355 return 0; 1356 } 1357 1358 static int sdma_v7_0_suspend(void *handle) 1359 { 1360 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1361 1362 return sdma_v7_0_hw_fini(adev); 1363 } 1364 1365 static int sdma_v7_0_resume(void *handle) 1366 { 1367 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1368 1369 return sdma_v7_0_hw_init(adev); 1370 } 1371 1372 static bool sdma_v7_0_is_idle(void *handle) 1373 { 1374 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1375 u32 i; 1376 1377 for (i = 0; i < adev->sdma.num_instances; i++) { 1378 u32 tmp = RREG32(sdma_v7_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG)); 1379 1380 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1381 return false; 1382 } 1383 1384 return true; 1385 } 1386 1387 static int sdma_v7_0_wait_for_idle(void *handle) 1388 { 1389 unsigned i; 1390 u32 sdma0, sdma1; 1391 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1392 1393 for (i = 0; i < adev->usec_timeout; i++) { 1394 sdma0 = RREG32(sdma_v7_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG)); 1395 sdma1 = RREG32(sdma_v7_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG)); 1396 1397 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1398 return 0; 1399 udelay(1); 1400 } 1401 return -ETIMEDOUT; 1402 } 1403 1404 static int sdma_v7_0_ring_preempt_ib(struct amdgpu_ring *ring) 1405 { 1406 int i, r = 0; 1407 struct amdgpu_device *adev = ring->adev; 1408 u32 index = 0; 1409 u64 sdma_gfx_preempt; 1410 1411 amdgpu_sdma_get_index_from_ring(ring, &index); 1412 sdma_gfx_preempt = 1413 sdma_v7_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT); 1414 1415 /* assert preemption condition */ 1416 amdgpu_ring_set_preempt_cond_exec(ring, false); 1417 1418 /* emit the trailing fence */ 1419 ring->trail_seq += 1; 1420 r = amdgpu_ring_alloc(ring, 10); 1421 if (r) { 1422 DRM_ERROR("ring %d failed to be allocated \n", ring->idx); 1423 return r; 1424 } 1425 sdma_v7_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1426 ring->trail_seq, 0); 1427 amdgpu_ring_commit(ring); 1428 1429 /* assert IB preemption */ 1430 WREG32(sdma_gfx_preempt, 1); 1431 1432 /* poll the trailing fence */ 1433 for (i = 0; i < adev->usec_timeout; i++) { 1434 if (ring->trail_seq == 1435 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1436 break; 1437 udelay(1); 1438 } 1439 1440 if (i >= adev->usec_timeout) { 1441 r = -EINVAL; 1442 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1443 } 1444 1445 /* deassert IB preemption */ 1446 WREG32(sdma_gfx_preempt, 0); 1447 1448 /* deassert the preemption condition */ 1449 amdgpu_ring_set_preempt_cond_exec(ring, true); 1450 return r; 1451 } 1452 1453 static int sdma_v7_0_set_trap_irq_state(struct amdgpu_device *adev, 1454 struct amdgpu_irq_src *source, 1455 unsigned type, 1456 enum amdgpu_interrupt_state state) 1457 { 1458 u32 sdma_cntl; 1459 1460 u32 reg_offset = sdma_v7_0_get_reg_offset(adev, type, regSDMA0_CNTL); 1461 1462 sdma_cntl = RREG32(reg_offset); 1463 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1464 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1465 WREG32(reg_offset, sdma_cntl); 1466 1467 return 0; 1468 } 1469 1470 static int sdma_v7_0_process_trap_irq(struct amdgpu_device *adev, 1471 struct amdgpu_irq_src *source, 1472 struct amdgpu_iv_entry *entry) 1473 { 1474 int instances, queue; 1475 uint32_t mes_queue_id = entry->src_data[0]; 1476 1477 DRM_DEBUG("IH: SDMA trap\n"); 1478 1479 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 1480 struct amdgpu_mes_queue *queue; 1481 1482 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 1483 1484 spin_lock(&adev->mes.queue_id_lock); 1485 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 1486 if (queue) { 1487 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); 1488 amdgpu_fence_process(queue->ring); 1489 } 1490 spin_unlock(&adev->mes.queue_id_lock); 1491 return 0; 1492 } 1493 1494 queue = entry->ring_id & 0xf; 1495 instances = (entry->ring_id & 0xf0) >> 4; 1496 if (instances > 1) { 1497 DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n"); 1498 return -EINVAL; 1499 } 1500 1501 switch (entry->client_id) { 1502 case SOC21_IH_CLIENTID_GFX: 1503 switch (queue) { 1504 case 0: 1505 amdgpu_fence_process(&adev->sdma.instance[instances].ring); 1506 break; 1507 default: 1508 break; 1509 } 1510 break; 1511 } 1512 return 0; 1513 } 1514 1515 static int sdma_v7_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1516 struct amdgpu_irq_src *source, 1517 struct amdgpu_iv_entry *entry) 1518 { 1519 return 0; 1520 } 1521 1522 static int sdma_v7_0_set_clockgating_state(void *handle, 1523 enum amd_clockgating_state state) 1524 { 1525 return 0; 1526 } 1527 1528 static int sdma_v7_0_set_powergating_state(void *handle, 1529 enum amd_powergating_state state) 1530 { 1531 return 0; 1532 } 1533 1534 static void sdma_v7_0_get_clockgating_state(void *handle, u64 *flags) 1535 { 1536 } 1537 1538 static void sdma_v7_0_print_ip_state(void *handle, struct drm_printer *p) 1539 { 1540 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1541 int i, j; 1542 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_0); 1543 uint32_t instance_offset; 1544 1545 if (!adev->sdma.ip_dump) 1546 return; 1547 1548 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances); 1549 for (i = 0; i < adev->sdma.num_instances; i++) { 1550 instance_offset = i * reg_count; 1551 drm_printf(p, "\nInstance:%d\n", i); 1552 1553 for (j = 0; j < reg_count; j++) 1554 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_7_0[j].reg_name, 1555 adev->sdma.ip_dump[instance_offset + j]); 1556 } 1557 } 1558 1559 static void sdma_v7_0_dump_ip_state(void *handle) 1560 { 1561 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1562 int i, j; 1563 uint32_t instance_offset; 1564 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_0); 1565 1566 if (!adev->sdma.ip_dump) 1567 return; 1568 1569 amdgpu_gfx_off_ctrl(adev, false); 1570 for (i = 0; i < adev->sdma.num_instances; i++) { 1571 instance_offset = i * reg_count; 1572 for (j = 0; j < reg_count; j++) 1573 adev->sdma.ip_dump[instance_offset + j] = 1574 RREG32(sdma_v7_0_get_reg_offset(adev, i, 1575 sdma_reg_list_7_0[j].reg_offset)); 1576 } 1577 amdgpu_gfx_off_ctrl(adev, true); 1578 } 1579 1580 const struct amd_ip_funcs sdma_v7_0_ip_funcs = { 1581 .name = "sdma_v7_0", 1582 .early_init = sdma_v7_0_early_init, 1583 .late_init = NULL, 1584 .sw_init = sdma_v7_0_sw_init, 1585 .sw_fini = sdma_v7_0_sw_fini, 1586 .hw_init = sdma_v7_0_hw_init, 1587 .hw_fini = sdma_v7_0_hw_fini, 1588 .suspend = sdma_v7_0_suspend, 1589 .resume = sdma_v7_0_resume, 1590 .is_idle = sdma_v7_0_is_idle, 1591 .wait_for_idle = sdma_v7_0_wait_for_idle, 1592 .soft_reset = sdma_v7_0_soft_reset, 1593 .check_soft_reset = sdma_v7_0_check_soft_reset, 1594 .set_clockgating_state = sdma_v7_0_set_clockgating_state, 1595 .set_powergating_state = sdma_v7_0_set_powergating_state, 1596 .get_clockgating_state = sdma_v7_0_get_clockgating_state, 1597 .dump_ip_state = sdma_v7_0_dump_ip_state, 1598 .print_ip_state = sdma_v7_0_print_ip_state, 1599 }; 1600 1601 static const struct amdgpu_ring_funcs sdma_v7_0_ring_funcs = { 1602 .type = AMDGPU_RING_TYPE_SDMA, 1603 .align_mask = 0xf, 1604 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1605 .support_64bit_ptrs = true, 1606 .secure_submission_supported = true, 1607 .get_rptr = sdma_v7_0_ring_get_rptr, 1608 .get_wptr = sdma_v7_0_ring_get_wptr, 1609 .set_wptr = sdma_v7_0_ring_set_wptr, 1610 .emit_frame_size = 1611 5 + /* sdma_v7_0_ring_init_cond_exec */ 1612 6 + /* sdma_v7_0_ring_emit_hdp_flush */ 1613 6 + /* sdma_v7_0_ring_emit_pipeline_sync */ 1614 /* sdma_v7_0_ring_emit_vm_flush */ 1615 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1616 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1617 10 + 10 + 10, /* sdma_v7_0_ring_emit_fence x3 for user fence, vm fence */ 1618 .emit_ib_size = 5 + 7 + 6, /* sdma_v7_0_ring_emit_ib */ 1619 .emit_ib = sdma_v7_0_ring_emit_ib, 1620 .emit_mem_sync = sdma_v7_0_ring_emit_mem_sync, 1621 .emit_fence = sdma_v7_0_ring_emit_fence, 1622 .emit_pipeline_sync = sdma_v7_0_ring_emit_pipeline_sync, 1623 .emit_vm_flush = sdma_v7_0_ring_emit_vm_flush, 1624 .emit_hdp_flush = sdma_v7_0_ring_emit_hdp_flush, 1625 .test_ring = sdma_v7_0_ring_test_ring, 1626 .test_ib = sdma_v7_0_ring_test_ib, 1627 .insert_nop = sdma_v7_0_ring_insert_nop, 1628 .pad_ib = sdma_v7_0_ring_pad_ib, 1629 .emit_wreg = sdma_v7_0_ring_emit_wreg, 1630 .emit_reg_wait = sdma_v7_0_ring_emit_reg_wait, 1631 .emit_reg_write_reg_wait = sdma_v7_0_ring_emit_reg_write_reg_wait, 1632 .init_cond_exec = sdma_v7_0_ring_init_cond_exec, 1633 .preempt_ib = sdma_v7_0_ring_preempt_ib, 1634 }; 1635 1636 static void sdma_v7_0_set_ring_funcs(struct amdgpu_device *adev) 1637 { 1638 int i; 1639 1640 for (i = 0; i < adev->sdma.num_instances; i++) { 1641 adev->sdma.instance[i].ring.funcs = &sdma_v7_0_ring_funcs; 1642 adev->sdma.instance[i].ring.me = i; 1643 } 1644 } 1645 1646 static const struct amdgpu_irq_src_funcs sdma_v7_0_trap_irq_funcs = { 1647 .set = sdma_v7_0_set_trap_irq_state, 1648 .process = sdma_v7_0_process_trap_irq, 1649 }; 1650 1651 static const struct amdgpu_irq_src_funcs sdma_v7_0_illegal_inst_irq_funcs = { 1652 .process = sdma_v7_0_process_illegal_inst_irq, 1653 }; 1654 1655 static void sdma_v7_0_set_irq_funcs(struct amdgpu_device *adev) 1656 { 1657 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1658 adev->sdma.num_instances; 1659 adev->sdma.trap_irq.funcs = &sdma_v7_0_trap_irq_funcs; 1660 adev->sdma.illegal_inst_irq.funcs = &sdma_v7_0_illegal_inst_irq_funcs; 1661 } 1662 1663 /** 1664 * sdma_v7_0_emit_copy_buffer - copy buffer using the sDMA engine 1665 * 1666 * @ib: indirect buffer to fill with commands 1667 * @src_offset: src GPU address 1668 * @dst_offset: dst GPU address 1669 * @byte_count: number of bytes to xfer 1670 * @copy_flags: copy flags for the buffers 1671 * 1672 * Copy GPU buffers using the DMA engine. 1673 * Used by the amdgpu ttm implementation to move pages if 1674 * registered as the asic copy callback. 1675 */ 1676 static void sdma_v7_0_emit_copy_buffer(struct amdgpu_ib *ib, 1677 uint64_t src_offset, 1678 uint64_t dst_offset, 1679 uint32_t byte_count, 1680 uint32_t copy_flags) 1681 { 1682 uint32_t num_type, data_format, max_com; 1683 1684 max_com = AMDGPU_COPY_FLAGS_GET(copy_flags, MAX_COMPRESSED); 1685 data_format = AMDGPU_COPY_FLAGS_GET(copy_flags, DATA_FORMAT); 1686 num_type = AMDGPU_COPY_FLAGS_GET(copy_flags, NUMBER_TYPE); 1687 1688 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1689 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1690 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0) | 1691 SDMA_PKT_COPY_LINEAR_HEADER_CPV(1); 1692 1693 ib->ptr[ib->length_dw++] = byte_count - 1; 1694 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1695 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1696 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1697 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1698 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1699 1700 if ((copy_flags & (AMDGPU_COPY_FLAGS_READ_DECOMPRESSED | AMDGPU_COPY_FLAGS_WRITE_COMPRESSED))) 1701 ib->ptr[ib->length_dw++] = SDMA_DCC_DATA_FORMAT(data_format) | SDMA_DCC_NUM_TYPE(num_type) | 1702 ((copy_flags & AMDGPU_COPY_FLAGS_READ_DECOMPRESSED) ? SDMA_DCC_READ_CM(2) : 0) | 1703 ((copy_flags & AMDGPU_COPY_FLAGS_WRITE_COMPRESSED) ? SDMA_DCC_WRITE_CM(1) : 0) | 1704 SDMA_DCC_MAX_COM(max_com) | SDMA_DCC_MAX_UCOM(1); 1705 else 1706 ib->ptr[ib->length_dw++] = 0; 1707 } 1708 1709 /** 1710 * sdma_v7_0_emit_fill_buffer - fill buffer using the sDMA engine 1711 * 1712 * @ib: indirect buffer to fill 1713 * @src_data: value to write to buffer 1714 * @dst_offset: dst GPU address 1715 * @byte_count: number of bytes to xfer 1716 * 1717 * Fill GPU buffers using the DMA engine. 1718 */ 1719 static void sdma_v7_0_emit_fill_buffer(struct amdgpu_ib *ib, 1720 uint32_t src_data, 1721 uint64_t dst_offset, 1722 uint32_t byte_count) 1723 { 1724 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_CONST_FILL); 1725 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1726 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1727 ib->ptr[ib->length_dw++] = src_data; 1728 ib->ptr[ib->length_dw++] = byte_count - 1; 1729 } 1730 1731 static const struct amdgpu_buffer_funcs sdma_v7_0_buffer_funcs = { 1732 .copy_max_bytes = 0x400000, 1733 .copy_num_dw = 8, 1734 .emit_copy_buffer = sdma_v7_0_emit_copy_buffer, 1735 .fill_max_bytes = 0x400000, 1736 .fill_num_dw = 5, 1737 .emit_fill_buffer = sdma_v7_0_emit_fill_buffer, 1738 }; 1739 1740 static void sdma_v7_0_set_buffer_funcs(struct amdgpu_device *adev) 1741 { 1742 adev->mman.buffer_funcs = &sdma_v7_0_buffer_funcs; 1743 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1744 } 1745 1746 static const struct amdgpu_vm_pte_funcs sdma_v7_0_vm_pte_funcs = { 1747 .copy_pte_num_dw = 7, 1748 .copy_pte = sdma_v7_0_vm_copy_pte, 1749 .write_pte = sdma_v7_0_vm_write_pte, 1750 .set_pte_pde = sdma_v7_0_vm_set_pte_pde, 1751 }; 1752 1753 static void sdma_v7_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1754 { 1755 unsigned i; 1756 1757 adev->vm_manager.vm_pte_funcs = &sdma_v7_0_vm_pte_funcs; 1758 for (i = 0; i < adev->sdma.num_instances; i++) { 1759 adev->vm_manager.vm_pte_scheds[i] = 1760 &adev->sdma.instance[i].ring.sched; 1761 } 1762 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1763 } 1764 1765 const struct amdgpu_ip_block_version sdma_v7_0_ip_block = { 1766 .type = AMD_IP_BLOCK_TYPE_SDMA, 1767 .major = 7, 1768 .minor = 0, 1769 .rev = 0, 1770 .funcs = &sdma_v7_0_ip_funcs, 1771 }; 1772