1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_12_0_0_offset.h" 34 #include "gc/gc_12_0_0_sh_mask.h" 35 #include "hdp/hdp_6_0_0_offset.h" 36 #include "ivsrcid/gfx/irqsrcs_gfx_12_0_0.h" 37 38 #include "soc15_common.h" 39 #include "soc15.h" 40 #include "sdma_v6_0_0_pkt_open.h" 41 #include "nbio_v4_3.h" 42 #include "sdma_common.h" 43 #include "sdma_v7_0.h" 44 #include "v12_structs.h" 45 #include "mes_userqueue.h" 46 #include "amdgpu_userq_fence.h" 47 48 MODULE_FIRMWARE("amdgpu/sdma_7_0_0.bin"); 49 MODULE_FIRMWARE("amdgpu/sdma_7_0_1.bin"); 50 51 #define SDMA1_REG_OFFSET 0x600 52 #define SDMA0_HYP_DEC_REG_START 0x5880 53 #define SDMA0_HYP_DEC_REG_END 0x589a 54 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 55 56 /*define for compression field for sdma7*/ 57 #define SDMA_PKT_CONSTANT_FILL_HEADER_compress_offset 0 58 #define SDMA_PKT_CONSTANT_FILL_HEADER_compress_mask 0x00000001 59 #define SDMA_PKT_CONSTANT_FILL_HEADER_compress_shift 16 60 #define SDMA_PKT_CONSTANT_FILL_HEADER_COMPRESS(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_compress_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_compress_shift) 61 62 static const struct amdgpu_hwip_reg_entry sdma_reg_list_7_0[] = { 63 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS_REG), 64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS1_REG), 65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS2_REG), 66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS3_REG), 67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS4_REG), 68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS5_REG), 69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS6_REG), 70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UCODE_REV), 71 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH_HI), 72 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH), 73 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_STATUS), 74 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_STATUS), 75 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK0), 76 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK1), 77 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK0), 78 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK1), 79 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_CNTL), 80 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR), 81 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR_HI), 82 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR), 83 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR_HI), 84 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_OFFSET), 85 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_LO), 86 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_HI), 87 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_CNTL), 88 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_RPTR), 89 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_SUB_REMAIN), 90 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_DUMMY_REG), 91 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE_STATUS0), 92 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_CNTL), 93 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR), 94 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR_HI), 95 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR), 96 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR_HI), 97 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_OFFSET), 98 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_LO), 99 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_HI), 100 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_RPTR), 101 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_SUB_REMAIN), 102 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_DUMMY_REG), 103 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_CNTL), 104 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR), 105 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR_HI), 106 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR), 107 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR_HI), 108 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_OFFSET), 109 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_LO), 110 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_HI), 111 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_RPTR), 112 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_SUB_REMAIN), 113 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_DUMMY_REG), 114 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_INT_STATUS), 115 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_VM_CNTL), 116 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 117 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_CHICKEN_BITS), 118 }; 119 120 static void sdma_v7_0_set_ring_funcs(struct amdgpu_device *adev); 121 static void sdma_v7_0_set_buffer_funcs(struct amdgpu_device *adev); 122 static void sdma_v7_0_set_vm_pte_funcs(struct amdgpu_device *adev); 123 static void sdma_v7_0_set_irq_funcs(struct amdgpu_device *adev); 124 static int sdma_v7_0_start(struct amdgpu_device *adev); 125 126 static u32 sdma_v7_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 127 { 128 u32 base; 129 130 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 131 internal_offset <= SDMA0_HYP_DEC_REG_END) { 132 base = adev->reg_offset[GC_HWIP][0][1]; 133 if (instance != 0) 134 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance; 135 } else { 136 base = adev->reg_offset[GC_HWIP][0][0]; 137 if (instance == 1) 138 internal_offset += SDMA1_REG_OFFSET; 139 } 140 141 return base + internal_offset; 142 } 143 144 static unsigned sdma_v7_0_ring_init_cond_exec(struct amdgpu_ring *ring, 145 uint64_t addr) 146 { 147 unsigned ret; 148 149 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE)); 150 amdgpu_ring_write(ring, lower_32_bits(addr)); 151 amdgpu_ring_write(ring, upper_32_bits(addr)); 152 amdgpu_ring_write(ring, 1); 153 /* this is the offset we need patch later */ 154 ret = ring->wptr & ring->buf_mask; 155 /* insert dummy here and patch it later */ 156 amdgpu_ring_write(ring, 0); 157 158 return ret; 159 } 160 161 /** 162 * sdma_v7_0_ring_get_rptr - get the current read pointer 163 * 164 * @ring: amdgpu ring pointer 165 * 166 * Get the current rptr from the hardware. 167 */ 168 static uint64_t sdma_v7_0_ring_get_rptr(struct amdgpu_ring *ring) 169 { 170 u64 *rptr; 171 172 /* XXX check if swapping is necessary on BE */ 173 rptr = (u64 *)ring->rptr_cpu_addr; 174 175 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 176 return ((*rptr) >> 2); 177 } 178 179 /** 180 * sdma_v7_0_ring_get_wptr - get the current write pointer 181 * 182 * @ring: amdgpu ring pointer 183 * 184 * Get the current wptr from the hardware. 185 */ 186 static uint64_t sdma_v7_0_ring_get_wptr(struct amdgpu_ring *ring) 187 { 188 u64 wptr = 0; 189 190 if (ring->use_doorbell) { 191 /* XXX check if swapping is necessary on BE */ 192 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 193 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 194 } 195 196 return wptr >> 2; 197 } 198 199 /** 200 * sdma_v7_0_ring_set_wptr - commit the write pointer 201 * 202 * @ring: amdgpu ring pointer 203 * 204 * Write the wptr back to the hardware. 205 */ 206 static void sdma_v7_0_ring_set_wptr(struct amdgpu_ring *ring) 207 { 208 struct amdgpu_device *adev = ring->adev; 209 210 DRM_DEBUG("Setting write pointer\n"); 211 212 if (ring->use_doorbell) { 213 DRM_DEBUG("Using doorbell -- " 214 "wptr_offs == 0x%08x " 215 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 216 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 217 ring->wptr_offs, 218 lower_32_bits(ring->wptr << 2), 219 upper_32_bits(ring->wptr << 2)); 220 /* XXX check if swapping is necessary on BE */ 221 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 222 ring->wptr << 2); 223 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 224 ring->doorbell_index, ring->wptr << 2); 225 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 226 } else { 227 DRM_DEBUG("Not using doorbell -- " 228 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 229 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 230 ring->me, 231 lower_32_bits(ring->wptr << 2), 232 ring->me, 233 upper_32_bits(ring->wptr << 2)); 234 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, 235 ring->me, 236 regSDMA0_QUEUE0_RB_WPTR), 237 lower_32_bits(ring->wptr << 2)); 238 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, 239 ring->me, 240 regSDMA0_QUEUE0_RB_WPTR_HI), 241 upper_32_bits(ring->wptr << 2)); 242 } 243 } 244 245 static void sdma_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 246 { 247 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 248 int i; 249 250 for (i = 0; i < count; i++) 251 if (sdma && sdma->burst_nop && (i == 0)) 252 amdgpu_ring_write(ring, ring->funcs->nop | 253 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 254 else 255 amdgpu_ring_write(ring, ring->funcs->nop); 256 } 257 258 /** 259 * sdma_v7_0_ring_emit_ib - Schedule an IB on the DMA engine 260 * 261 * @ring: amdgpu ring pointer 262 * @job: job to retrieve vmid from 263 * @ib: IB object to schedule 264 * @flags: unused 265 * 266 * Schedule an IB in the DMA ring. 267 */ 268 static void sdma_v7_0_ring_emit_ib(struct amdgpu_ring *ring, 269 struct amdgpu_job *job, 270 struct amdgpu_ib *ib, 271 uint32_t flags) 272 { 273 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 274 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 275 276 /* An IB packet must end on a 8 DW boundary--the next dword 277 * must be on a 8-dword boundary. Our IB packet below is 6 278 * dwords long, thus add x number of NOPs, such that, in 279 * modular arithmetic, 280 * wptr + 6 + x = 8k, k >= 0, which in C is, 281 * (wptr + 6 + x) % 8 = 0. 282 * The expression below, is a solution of x. 283 */ 284 sdma_v7_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 285 286 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) | 287 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 288 /* base must be 32 byte aligned */ 289 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 290 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 291 amdgpu_ring_write(ring, ib->length_dw); 292 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 293 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 294 } 295 296 /** 297 * sdma_v7_0_ring_emit_mem_sync - flush the IB by graphics cache rinse 298 * 299 * @ring: amdgpu ring pointer 300 * 301 * flush the IB by graphics cache rinse. 302 */ 303 static void sdma_v7_0_ring_emit_mem_sync(struct amdgpu_ring *ring) 304 { 305 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV | 306 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 307 SDMA_GCR_GLI_INV(1); 308 309 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 310 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ)); 311 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 312 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 313 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 314 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 315 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 316 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 317 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 318 } 319 320 321 /** 322 * sdma_v7_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 323 * 324 * @ring: amdgpu ring pointer 325 * 326 * Emit an hdp flush packet on the requested DMA ring. 327 */ 328 static void sdma_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 329 { 330 struct amdgpu_device *adev = ring->adev; 331 u32 ref_and_mask = 0; 332 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 333 334 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 335 336 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 337 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 338 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 339 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 340 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 341 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 342 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 343 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 344 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 345 } 346 347 /** 348 * sdma_v7_0_ring_emit_fence - emit a fence on the DMA ring 349 * 350 * @ring: amdgpu ring pointer 351 * @addr: address 352 * @seq: fence seq number 353 * @flags: fence flags 354 * 355 * Add a DMA fence packet to the ring to write 356 * the fence seq number and DMA trap packet to generate 357 * an interrupt if needed. 358 */ 359 static void sdma_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 360 unsigned flags) 361 { 362 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 363 /* write the fence */ 364 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 365 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 366 /* zero in first two bits */ 367 BUG_ON(addr & 0x3); 368 amdgpu_ring_write(ring, lower_32_bits(addr)); 369 amdgpu_ring_write(ring, upper_32_bits(addr)); 370 amdgpu_ring_write(ring, lower_32_bits(seq)); 371 372 /* optionally write high bits as well */ 373 if (write64bit) { 374 addr += 4; 375 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 376 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 377 /* zero in first two bits */ 378 BUG_ON(addr & 0x3); 379 amdgpu_ring_write(ring, lower_32_bits(addr)); 380 amdgpu_ring_write(ring, upper_32_bits(addr)); 381 amdgpu_ring_write(ring, upper_32_bits(seq)); 382 } 383 384 if (flags & AMDGPU_FENCE_FLAG_INT) { 385 /* generate an interrupt */ 386 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP)); 387 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 388 } 389 } 390 391 /** 392 * sdma_v7_0_gfx_stop - stop the gfx async dma engines 393 * 394 * @adev: amdgpu_device pointer 395 * 396 * Stop the gfx async dma ring buffers. 397 */ 398 static void sdma_v7_0_gfx_stop(struct amdgpu_device *adev) 399 { 400 u32 rb_cntl, ib_cntl; 401 int i; 402 403 for (i = 0; i < adev->sdma.num_instances; i++) { 404 rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 405 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0); 406 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 407 ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 408 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0); 409 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 410 } 411 } 412 413 /** 414 * sdma_v7_0_rlc_stop - stop the compute async dma engines 415 * 416 * @adev: amdgpu_device pointer 417 * 418 * Stop the compute async dma queues. 419 */ 420 static void sdma_v7_0_rlc_stop(struct amdgpu_device *adev) 421 { 422 /* XXX todo */ 423 } 424 425 /** 426 * sdma_v7_0_ctx_switch_enable - stop the async dma engines context switch 427 * 428 * @adev: amdgpu_device pointer 429 * @enable: enable/disable the DMA MEs context switch. 430 * 431 * Halt or unhalt the async dma engines context switch. 432 */ 433 static void sdma_v7_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 434 { 435 } 436 437 /** 438 * sdma_v7_0_enable - stop the async dma engines 439 * 440 * @adev: amdgpu_device pointer 441 * @enable: enable/disable the DMA MEs. 442 * 443 * Halt or unhalt the async dma engines. 444 */ 445 static void sdma_v7_0_enable(struct amdgpu_device *adev, bool enable) 446 { 447 u32 mcu_cntl; 448 int i; 449 450 if (!enable) { 451 sdma_v7_0_gfx_stop(adev); 452 sdma_v7_0_rlc_stop(adev); 453 } 454 455 if (amdgpu_sriov_vf(adev)) 456 return; 457 458 for (i = 0; i < adev->sdma.num_instances; i++) { 459 mcu_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL)); 460 mcu_cntl = REG_SET_FIELD(mcu_cntl, SDMA0_MCU_CNTL, HALT, enable ? 0 : 1); 461 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), mcu_cntl); 462 } 463 } 464 465 /** 466 * sdma_v7_0_gfx_resume_instance - start/restart a certain sdma engine 467 * 468 * @adev: amdgpu_device pointer 469 * @i: instance 470 * @restore: used to restore wptr when restart 471 * 472 * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr. 473 * Return 0 for success. 474 */ 475 static int sdma_v7_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore) 476 { 477 struct amdgpu_ring *ring; 478 u32 rb_cntl, ib_cntl; 479 u32 rb_bufsz; 480 u32 doorbell; 481 u32 doorbell_offset; 482 u32 temp; 483 u64 wptr_gpu_addr; 484 int r; 485 486 ring = &adev->sdma.instance[i].ring; 487 488 /* Set ring buffer size in dwords */ 489 rb_bufsz = order_base_2(ring->ring_size / 4); 490 rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 491 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); 492 #ifdef __BIG_ENDIAN 493 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1); 494 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, 495 RPTR_WRITEBACK_SWAP_ENABLE, 1); 496 #endif 497 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1); 498 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 499 500 /* Initialize the ring buffer's read and write pointers */ 501 if (restore) { 502 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2)); 503 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2)); 504 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2)); 505 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); 506 } else { 507 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0); 508 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0); 509 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0); 510 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0); 511 } 512 /* setup the wptr shadow polling */ 513 wptr_gpu_addr = ring->wptr_gpu_addr; 514 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO), 515 lower_32_bits(wptr_gpu_addr)); 516 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI), 517 upper_32_bits(wptr_gpu_addr)); 518 519 /* set the wb address whether it's enabled or not */ 520 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI), 521 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 522 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO), 523 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 524 525 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 526 if (amdgpu_sriov_vf(adev)) 527 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 1); 528 else 529 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0); 530 531 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, MCU_WPTR_POLL_ENABLE, 1); 532 533 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8); 534 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40); 535 536 if (!restore) 537 ring->wptr = 0; 538 539 /* before programing wptr to a less value, need set minor_ptr_update first */ 540 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1); 541 542 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 543 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2); 544 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 545 } 546 547 doorbell = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL)); 548 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET)); 549 550 if (ring->use_doorbell) { 551 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 552 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET, 553 OFFSET, ring->doorbell_index); 554 } else { 555 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0); 556 } 557 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell); 558 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset); 559 560 if (i == 0) 561 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 562 ring->doorbell_index, 563 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances); 564 565 if (amdgpu_sriov_vf(adev)) 566 sdma_v7_0_ring_set_wptr(ring); 567 568 /* set minor_ptr_update to 0 after wptr programed */ 569 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0); 570 571 /* Set up sdma hang watchdog */ 572 temp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL)); 573 /* 100ms per unit */ 574 temp = REG_SET_FIELD(temp, SDMA0_WATCHDOG_CNTL, QUEUE_HANG_COUNT, 575 max(adev->usec_timeout/100000, 1)); 576 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), temp); 577 578 /* Set up RESP_MODE to non-copy addresses */ 579 temp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL)); 580 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 581 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 582 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp); 583 584 /* program default cache read and write policy */ 585 temp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE)); 586 /* clean read policy and write policy bits */ 587 temp &= 0xFF0FFF; 588 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | 589 (CACHE_WRITE_POLICY_L2__DEFAULT << 14)); 590 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp); 591 592 if (!amdgpu_sriov_vf(adev)) { 593 /* unhalt engine */ 594 temp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL)); 595 temp = REG_SET_FIELD(temp, SDMA0_MCU_CNTL, HALT, 0); 596 temp = REG_SET_FIELD(temp, SDMA0_MCU_CNTL, RESET, 0); 597 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), temp); 598 } 599 600 /* enable DMA RB */ 601 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1); 602 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 603 604 ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 605 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1); 606 #ifdef __BIG_ENDIAN 607 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1); 608 #endif 609 /* enable DMA IBs */ 610 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 611 ring->sched.ready = true; 612 613 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 614 sdma_v7_0_ctx_switch_enable(adev, true); 615 sdma_v7_0_enable(adev, true); 616 } 617 618 r = amdgpu_ring_test_helper(ring); 619 if (r) 620 ring->sched.ready = false; 621 622 return r; 623 } 624 625 /** 626 * sdma_v7_0_gfx_resume - setup and start the async dma engines 627 * 628 * @adev: amdgpu_device pointer 629 * 630 * Set up the gfx DMA ring buffers and enable them. 631 * Returns 0 for success, error for failure. 632 */ 633 static int sdma_v7_0_gfx_resume(struct amdgpu_device *adev) 634 { 635 int i, r; 636 637 for (i = 0; i < adev->sdma.num_instances; i++) { 638 r = sdma_v7_0_gfx_resume_instance(adev, i, false); 639 if (r) 640 return r; 641 } 642 643 return 0; 644 645 } 646 647 /** 648 * sdma_v7_0_rlc_resume - setup and start the async dma engines 649 * 650 * @adev: amdgpu_device pointer 651 * 652 * Set up the compute DMA queues and enable them. 653 * Returns 0 for success, error for failure. 654 */ 655 static int sdma_v7_0_rlc_resume(struct amdgpu_device *adev) 656 { 657 return 0; 658 } 659 660 static void sdma_v12_0_free_ucode_buffer(struct amdgpu_device *adev) 661 { 662 int i; 663 664 for (i = 0; i < adev->sdma.num_instances; i++) { 665 amdgpu_bo_free_kernel(&adev->sdma.instance[i].sdma_fw_obj, 666 &adev->sdma.instance[i].sdma_fw_gpu_addr, 667 (void **)&adev->sdma.instance[i].sdma_fw_ptr); 668 } 669 } 670 671 /** 672 * sdma_v7_0_load_microcode - load the sDMA ME ucode 673 * 674 * @adev: amdgpu_device pointer 675 * 676 * Loads the sDMA0/1 ucode. 677 * Returns 0 for success, -EINVAL if the ucode is not available. 678 */ 679 static int sdma_v7_0_load_microcode(struct amdgpu_device *adev) 680 { 681 const struct sdma_firmware_header_v3_0 *hdr; 682 const __le32 *fw_data; 683 u32 fw_size; 684 uint32_t tmp, sdma_status, ic_op_cntl; 685 int i, r, j; 686 687 /* halt the MEs */ 688 sdma_v7_0_enable(adev, false); 689 690 if (!adev->sdma.instance[0].fw) 691 return -EINVAL; 692 693 hdr = (const struct sdma_firmware_header_v3_0 *) 694 adev->sdma.instance[0].fw->data; 695 amdgpu_ucode_print_sdma_hdr(&hdr->header); 696 697 fw_data = (const __le32 *)(adev->sdma.instance[0].fw->data + 698 le32_to_cpu(hdr->ucode_offset_bytes)); 699 fw_size = le32_to_cpu(hdr->ucode_size_bytes); 700 701 for (i = 0; i < adev->sdma.num_instances; i++) { 702 r = amdgpu_bo_create_reserved(adev, fw_size, 703 PAGE_SIZE, 704 AMDGPU_GEM_DOMAIN_VRAM, 705 &adev->sdma.instance[i].sdma_fw_obj, 706 &adev->sdma.instance[i].sdma_fw_gpu_addr, 707 (void **)&adev->sdma.instance[i].sdma_fw_ptr); 708 if (r) { 709 dev_err(adev->dev, "(%d) failed to create sdma ucode bo\n", r); 710 return r; 711 } 712 713 memcpy(adev->sdma.instance[i].sdma_fw_ptr, fw_data, fw_size); 714 715 amdgpu_bo_kunmap(adev->sdma.instance[i].sdma_fw_obj); 716 amdgpu_bo_unreserve(adev->sdma.instance[i].sdma_fw_obj); 717 718 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_CNTL)); 719 tmp = REG_SET_FIELD(tmp, SDMA0_IC_CNTL, GPA, 0); 720 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_CNTL), tmp); 721 722 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_BASE_LO), 723 lower_32_bits(adev->sdma.instance[i].sdma_fw_gpu_addr)); 724 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_BASE_HI), 725 upper_32_bits(adev->sdma.instance[i].sdma_fw_gpu_addr)); 726 727 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL)); 728 tmp = REG_SET_FIELD(tmp, SDMA0_IC_OP_CNTL, PRIME_ICACHE, 1); 729 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL), tmp); 730 731 /* Wait for sdma ucode init complete */ 732 for (j = 0; j < adev->usec_timeout; j++) { 733 ic_op_cntl = RREG32_SOC15_IP(GC, 734 sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL)); 735 sdma_status = RREG32_SOC15_IP(GC, 736 sdma_v7_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG)); 737 if ((REG_GET_FIELD(ic_op_cntl, SDMA0_IC_OP_CNTL, ICACHE_PRIMED) == 1) && 738 (REG_GET_FIELD(sdma_status, SDMA0_STATUS_REG, UCODE_INIT_DONE) == 1)) 739 break; 740 udelay(1); 741 } 742 743 if (j >= adev->usec_timeout) { 744 dev_err(adev->dev, "failed to init sdma ucode\n"); 745 return -EINVAL; 746 } 747 } 748 749 return 0; 750 } 751 752 static int sdma_v7_0_soft_reset(struct amdgpu_ip_block *ip_block) 753 { 754 struct amdgpu_device *adev = ip_block->adev; 755 u32 tmp; 756 int i; 757 758 sdma_v7_0_gfx_stop(adev); 759 760 for (i = 0; i < adev->sdma.num_instances; i++) { 761 //tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_FREEZE)); 762 //tmp |= SDMA0_FREEZE__FREEZE_MASK; 763 //WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp); 764 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL)); 765 tmp |= SDMA0_MCU_CNTL__HALT_MASK; 766 tmp |= SDMA0_MCU_CNTL__RESET_MASK; 767 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), tmp); 768 769 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0); 770 771 udelay(100); 772 773 tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i; 774 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); 775 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 776 777 udelay(100); 778 779 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0); 780 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 781 782 udelay(100); 783 } 784 785 return sdma_v7_0_start(adev); 786 } 787 788 static bool sdma_v7_0_check_soft_reset(struct amdgpu_ip_block *ip_block) 789 { 790 struct amdgpu_device *adev = ip_block->adev; 791 struct amdgpu_ring *ring; 792 int i, r; 793 long tmo = msecs_to_jiffies(1000); 794 795 for (i = 0; i < adev->sdma.num_instances; i++) { 796 ring = &adev->sdma.instance[i].ring; 797 r = amdgpu_ring_test_ib(ring, tmo); 798 if (r) 799 return true; 800 } 801 802 return false; 803 } 804 805 static int sdma_v7_0_reset_queue(struct amdgpu_ring *ring, 806 unsigned int vmid, 807 struct amdgpu_fence *timedout_fence) 808 { 809 struct amdgpu_device *adev = ring->adev; 810 int i, r; 811 812 if (amdgpu_sriov_vf(adev)) 813 return -EINVAL; 814 815 for (i = 0; i < adev->sdma.num_instances; i++) { 816 if (ring == &adev->sdma.instance[i].ring) 817 break; 818 } 819 820 if (i == adev->sdma.num_instances) { 821 DRM_ERROR("sdma instance not found\n"); 822 return -EINVAL; 823 } 824 825 drm_sched_wqueue_stop(&ring->sched); 826 827 r = amdgpu_mes_reset_legacy_queue(adev, ring, vmid, true); 828 if (r) 829 return r; 830 831 r = sdma_v7_0_gfx_resume_instance(adev, i, true); 832 if (r) 833 return r; 834 amdgpu_fence_driver_force_completion(ring); 835 drm_sched_wqueue_start(&ring->sched); 836 return 0; 837 } 838 839 /** 840 * sdma_v7_0_start - setup and start the async dma engines 841 * 842 * @adev: amdgpu_device pointer 843 * 844 * Set up the DMA engines and enable them. 845 * Returns 0 for success, error for failure. 846 */ 847 static int sdma_v7_0_start(struct amdgpu_device *adev) 848 { 849 int r = 0; 850 851 if (amdgpu_sriov_vf(adev)) { 852 sdma_v7_0_ctx_switch_enable(adev, false); 853 sdma_v7_0_enable(adev, false); 854 855 /* set RB registers */ 856 r = sdma_v7_0_gfx_resume(adev); 857 return r; 858 } 859 860 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 861 r = sdma_v7_0_load_microcode(adev); 862 if (r) { 863 sdma_v12_0_free_ucode_buffer(adev); 864 return r; 865 } 866 867 if (amdgpu_emu_mode == 1) 868 msleep(1000); 869 } 870 871 /* unhalt the MEs */ 872 sdma_v7_0_enable(adev, true); 873 /* enable sdma ring preemption */ 874 sdma_v7_0_ctx_switch_enable(adev, true); 875 876 /* start the gfx rings and rlc compute queues */ 877 r = sdma_v7_0_gfx_resume(adev); 878 if (r) 879 return r; 880 r = sdma_v7_0_rlc_resume(adev); 881 882 return r; 883 } 884 885 static int sdma_v7_0_mqd_init(struct amdgpu_device *adev, void *mqd, 886 struct amdgpu_mqd_prop *prop) 887 { 888 struct v12_sdma_mqd *m = mqd; 889 uint64_t wb_gpu_addr; 890 891 m->sdmax_rlcx_rb_cntl = 892 order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT | 893 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 894 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | 895 1 << SDMA0_QUEUE0_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT; 896 897 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8); 898 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); 899 900 wb_gpu_addr = prop->wptr_gpu_addr; 901 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); 902 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); 903 904 wb_gpu_addr = prop->rptr_gpu_addr; 905 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); 906 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); 907 908 m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, 0, 909 regSDMA0_QUEUE0_IB_CNTL)); 910 911 m->sdmax_rlcx_doorbell_offset = 912 prop->doorbell_index << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 913 914 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 915 916 m->sdmax_rlcx_doorbell_log = 0; 917 m->sdmax_rlcx_rb_aql_cntl = 0x4000; //regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT; 918 m->sdmax_rlcx_dummy_reg = 0xf; //regSDMA0_QUEUE0_DUMMY_REG_DEFAULT; 919 920 m->sdmax_rlcx_csa_addr_lo = lower_32_bits(prop->csa_addr); 921 m->sdmax_rlcx_csa_addr_hi = upper_32_bits(prop->csa_addr); 922 923 m->sdmax_rlcx_mcu_dbg0 = lower_32_bits(prop->fence_address); 924 m->sdmax_rlcx_mcu_dbg1 = upper_32_bits(prop->fence_address); 925 926 return 0; 927 } 928 929 static void sdma_v7_0_set_mqd_funcs(struct amdgpu_device *adev) 930 { 931 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v12_sdma_mqd); 932 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v7_0_mqd_init; 933 } 934 935 /** 936 * sdma_v7_0_ring_test_ring - simple async dma engine test 937 * 938 * @ring: amdgpu_ring structure holding ring information 939 * 940 * Test the DMA engine by writing using it to write an 941 * value to memory. 942 * Returns 0 for success, error for failure. 943 */ 944 static int sdma_v7_0_ring_test_ring(struct amdgpu_ring *ring) 945 { 946 struct amdgpu_device *adev = ring->adev; 947 unsigned i; 948 unsigned index; 949 int r; 950 u32 tmp; 951 u64 gpu_addr; 952 953 tmp = 0xCAFEDEAD; 954 955 r = amdgpu_device_wb_get(adev, &index); 956 if (r) { 957 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 958 return r; 959 } 960 961 gpu_addr = adev->wb.gpu_addr + (index * 4); 962 adev->wb.wb[index] = cpu_to_le32(tmp); 963 964 r = amdgpu_ring_alloc(ring, 5); 965 if (r) { 966 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 967 amdgpu_device_wb_free(adev, index); 968 return r; 969 } 970 971 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 972 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 973 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 974 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 975 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 976 amdgpu_ring_write(ring, 0xDEADBEEF); 977 amdgpu_ring_commit(ring); 978 979 for (i = 0; i < adev->usec_timeout; i++) { 980 tmp = le32_to_cpu(adev->wb.wb[index]); 981 if (tmp == 0xDEADBEEF) 982 break; 983 if (amdgpu_emu_mode == 1) 984 msleep(1); 985 else 986 udelay(1); 987 } 988 989 if (i >= adev->usec_timeout) 990 r = -ETIMEDOUT; 991 992 amdgpu_device_wb_free(adev, index); 993 994 return r; 995 } 996 997 /** 998 * sdma_v7_0_ring_test_ib - test an IB on the DMA engine 999 * 1000 * @ring: amdgpu_ring structure holding ring information 1001 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1002 * 1003 * Test a simple IB in the DMA ring. 1004 * Returns 0 on success, error on failure. 1005 */ 1006 static int sdma_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1007 { 1008 struct amdgpu_device *adev = ring->adev; 1009 struct amdgpu_ib ib; 1010 struct dma_fence *f = NULL; 1011 unsigned index; 1012 long r; 1013 u32 tmp = 0; 1014 u64 gpu_addr; 1015 1016 tmp = 0xCAFEDEAD; 1017 memset(&ib, 0, sizeof(ib)); 1018 1019 r = amdgpu_device_wb_get(adev, &index); 1020 if (r) { 1021 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 1022 return r; 1023 } 1024 1025 gpu_addr = adev->wb.gpu_addr + (index * 4); 1026 adev->wb.wb[index] = cpu_to_le32(tmp); 1027 1028 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 1029 if (r) { 1030 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 1031 goto err0; 1032 } 1033 1034 ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 1035 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1036 ib.ptr[1] = lower_32_bits(gpu_addr); 1037 ib.ptr[2] = upper_32_bits(gpu_addr); 1038 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1039 ib.ptr[4] = 0xDEADBEEF; 1040 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1041 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1042 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1043 ib.length_dw = 8; 1044 1045 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1046 if (r) 1047 goto err1; 1048 1049 r = dma_fence_wait_timeout(f, false, timeout); 1050 if (r == 0) { 1051 DRM_ERROR("amdgpu: IB test timed out\n"); 1052 r = -ETIMEDOUT; 1053 goto err1; 1054 } else if (r < 0) { 1055 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1056 goto err1; 1057 } 1058 1059 tmp = le32_to_cpu(adev->wb.wb[index]); 1060 1061 if (tmp == 0xDEADBEEF) 1062 r = 0; 1063 else 1064 r = -EINVAL; 1065 1066 err1: 1067 amdgpu_ib_free(&ib, NULL); 1068 dma_fence_put(f); 1069 err0: 1070 amdgpu_device_wb_free(adev, index); 1071 return r; 1072 } 1073 1074 1075 /** 1076 * sdma_v7_0_vm_copy_pte - update PTEs by copying them from the GART 1077 * 1078 * @ib: indirect buffer to fill with commands 1079 * @pe: addr of the page entry 1080 * @src: src addr to copy from 1081 * @count: number of page entries to update 1082 * 1083 * Update PTEs by copying them from the GART using sDMA. 1084 */ 1085 static void sdma_v7_0_vm_copy_pte(struct amdgpu_ib *ib, 1086 uint64_t pe, uint64_t src, 1087 unsigned count) 1088 { 1089 unsigned bytes = count * 8; 1090 1091 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1092 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1093 SDMA_PKT_COPY_LINEAR_HEADER_CPV(1); 1094 1095 ib->ptr[ib->length_dw++] = bytes - 1; 1096 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1097 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1098 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1099 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1100 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1101 ib->ptr[ib->length_dw++] = 0; 1102 1103 } 1104 1105 /** 1106 * sdma_v7_0_vm_write_pte - update PTEs by writing them manually 1107 * 1108 * @ib: indirect buffer to fill with commands 1109 * @pe: addr of the page entry 1110 * @value: dst addr to write into pe 1111 * @count: number of page entries to update 1112 * @incr: increase next addr by incr bytes 1113 * 1114 * Update PTEs by writing them manually using sDMA. 1115 */ 1116 static void sdma_v7_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1117 uint64_t value, unsigned count, 1118 uint32_t incr) 1119 { 1120 unsigned ndw = count * 2; 1121 1122 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 1123 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1124 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1125 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1126 ib->ptr[ib->length_dw++] = ndw - 1; 1127 for (; ndw > 0; ndw -= 2) { 1128 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1129 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1130 value += incr; 1131 } 1132 } 1133 1134 /** 1135 * sdma_v7_0_vm_set_pte_pde - update the page tables using sDMA 1136 * 1137 * @ib: indirect buffer to fill with commands 1138 * @pe: addr of the page entry 1139 * @addr: dst addr to write into pe 1140 * @count: number of page entries to update 1141 * @incr: increase next addr by incr bytes 1142 * @flags: access flags 1143 * 1144 * Update the page tables using sDMA. 1145 */ 1146 static void sdma_v7_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1147 uint64_t pe, 1148 uint64_t addr, unsigned count, 1149 uint32_t incr, uint64_t flags) 1150 { 1151 /* for physically contiguous pages (vram) */ 1152 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE); 1153 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1154 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1155 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1156 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1157 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1158 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1159 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1160 ib->ptr[ib->length_dw++] = 0; 1161 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1162 } 1163 1164 /** 1165 * sdma_v7_0_ring_pad_ib - pad the IB 1166 * 1167 * @ring: amdgpu ring pointer 1168 * @ib: indirect buffer to fill with padding 1169 * 1170 * Pad the IB with NOPs to a boundary multiple of 8. 1171 */ 1172 static void sdma_v7_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1173 { 1174 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1175 u32 pad_count; 1176 int i; 1177 1178 pad_count = (-ib->length_dw) & 0x7; 1179 for (i = 0; i < pad_count; i++) 1180 if (sdma && sdma->burst_nop && (i == 0)) 1181 ib->ptr[ib->length_dw++] = 1182 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) | 1183 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1184 else 1185 ib->ptr[ib->length_dw++] = 1186 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP); 1187 } 1188 1189 /** 1190 * sdma_v7_0_ring_emit_pipeline_sync - sync the pipeline 1191 * 1192 * @ring: amdgpu_ring pointer 1193 * 1194 * Make sure all previous operations are completed (CIK). 1195 */ 1196 static void sdma_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1197 { 1198 uint32_t seq = ring->fence_drv.sync_seq; 1199 uint64_t addr = ring->fence_drv.gpu_addr; 1200 1201 /* wait for idle */ 1202 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1203 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1204 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1205 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1206 amdgpu_ring_write(ring, addr & 0xfffffffc); 1207 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1208 amdgpu_ring_write(ring, seq); /* reference */ 1209 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1210 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1211 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1212 } 1213 1214 /** 1215 * sdma_v7_0_ring_emit_vm_flush - vm flush using sDMA 1216 * 1217 * @ring: amdgpu_ring pointer 1218 * @vmid: vmid number to use 1219 * @pd_addr: address 1220 * 1221 * Update the page table base and flush the VM TLB 1222 * using sDMA. 1223 */ 1224 static void sdma_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1225 unsigned vmid, uint64_t pd_addr) 1226 { 1227 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1228 } 1229 1230 static void sdma_v7_0_ring_emit_wreg(struct amdgpu_ring *ring, 1231 uint32_t reg, uint32_t val) 1232 { 1233 /* SRBM WRITE command will not support on sdma v7. 1234 * Use Register WRITE command instead, which OPCODE is same as SRBM WRITE 1235 */ 1236 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE)); 1237 amdgpu_ring_write(ring, reg << 2); 1238 amdgpu_ring_write(ring, val); 1239 } 1240 1241 static void sdma_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1242 uint32_t val, uint32_t mask) 1243 { 1244 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1245 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1246 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1247 amdgpu_ring_write(ring, reg << 2); 1248 amdgpu_ring_write(ring, 0); 1249 amdgpu_ring_write(ring, val); /* reference */ 1250 amdgpu_ring_write(ring, mask); /* mask */ 1251 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1252 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1253 } 1254 1255 static void sdma_v7_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1256 uint32_t reg0, uint32_t reg1, 1257 uint32_t ref, uint32_t mask) 1258 { 1259 amdgpu_ring_emit_wreg(ring, reg0, ref); 1260 /* wait for a cycle to reset vm_inv_eng*_ack */ 1261 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1262 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1263 } 1264 1265 static int sdma_v7_0_early_init(struct amdgpu_ip_block *ip_block) 1266 { 1267 struct amdgpu_device *adev = ip_block->adev; 1268 int r; 1269 1270 switch (amdgpu_user_queue) { 1271 case -1: 1272 case 0: 1273 default: 1274 adev->sdma.no_user_submission = false; 1275 adev->sdma.disable_uq = true; 1276 break; 1277 case 1: 1278 adev->sdma.no_user_submission = false; 1279 adev->sdma.disable_uq = false; 1280 break; 1281 case 2: 1282 adev->sdma.no_user_submission = true; 1283 adev->sdma.disable_uq = false; 1284 break; 1285 } 1286 1287 r = amdgpu_sdma_init_microcode(adev, 0, true); 1288 if (r) { 1289 DRM_ERROR("Failed to init sdma firmware!\n"); 1290 return r; 1291 } 1292 1293 sdma_v7_0_set_ring_funcs(adev); 1294 sdma_v7_0_set_buffer_funcs(adev); 1295 sdma_v7_0_set_vm_pte_funcs(adev); 1296 sdma_v7_0_set_irq_funcs(adev); 1297 sdma_v7_0_set_mqd_funcs(adev); 1298 1299 return 0; 1300 } 1301 1302 static int sdma_v7_0_sw_init(struct amdgpu_ip_block *ip_block) 1303 { 1304 struct amdgpu_ring *ring; 1305 int r, i; 1306 struct amdgpu_device *adev = ip_block->adev; 1307 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_0); 1308 uint32_t *ptr; 1309 1310 /* SDMA trap event */ 1311 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1312 GFX_12_0_0__SRCID__SDMA_TRAP, 1313 &adev->sdma.trap_irq); 1314 if (r) 1315 return r; 1316 1317 /* SDMA user fence event */ 1318 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1319 GFX_12_0_0__SRCID__SDMA_FENCE, 1320 &adev->sdma.fence_irq); 1321 if (r) 1322 return r; 1323 1324 for (i = 0; i < adev->sdma.num_instances; i++) { 1325 ring = &adev->sdma.instance[i].ring; 1326 ring->ring_obj = NULL; 1327 ring->use_doorbell = true; 1328 ring->me = i; 1329 ring->no_user_submission = adev->sdma.no_user_submission; 1330 1331 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1332 ring->use_doorbell?"true":"false"); 1333 1334 ring->doorbell_index = 1335 (adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset 1336 1337 ring->vm_hub = AMDGPU_GFXHUB(0); 1338 sprintf(ring->name, "sdma%d", i); 1339 r = amdgpu_ring_init(adev, ring, 1024, 1340 &adev->sdma.trap_irq, 1341 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1342 AMDGPU_RING_PRIO_DEFAULT, NULL); 1343 if (r) 1344 return r; 1345 } 1346 1347 adev->sdma.supported_reset = 1348 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); 1349 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1350 1351 r = amdgpu_sdma_sysfs_reset_mask_init(adev); 1352 if (r) 1353 return r; 1354 /* Allocate memory for SDMA IP Dump buffer */ 1355 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); 1356 if (ptr) 1357 adev->sdma.ip_dump = ptr; 1358 else 1359 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n"); 1360 1361 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1362 case IP_VERSION(7, 0, 0): 1363 case IP_VERSION(7, 0, 1): 1364 if ((adev->sdma.instance[0].fw_version >= 7836028) && !adev->sdma.disable_uq) 1365 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1366 break; 1367 default: 1368 break; 1369 } 1370 1371 return r; 1372 } 1373 1374 static int sdma_v7_0_sw_fini(struct amdgpu_ip_block *ip_block) 1375 { 1376 struct amdgpu_device *adev = ip_block->adev; 1377 int i; 1378 1379 for (i = 0; i < adev->sdma.num_instances; i++) 1380 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1381 1382 amdgpu_sdma_sysfs_reset_mask_fini(adev); 1383 amdgpu_sdma_destroy_inst_ctx(adev, true); 1384 1385 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) 1386 sdma_v12_0_free_ucode_buffer(adev); 1387 1388 kfree(adev->sdma.ip_dump); 1389 1390 return 0; 1391 } 1392 1393 static int sdma_v7_0_set_userq_trap_interrupts(struct amdgpu_device *adev, 1394 bool enable) 1395 { 1396 unsigned int irq_type; 1397 int i, r; 1398 1399 if (adev->userq_funcs[AMDGPU_HW_IP_DMA]) { 1400 for (i = 0; i < adev->sdma.num_instances; i++) { 1401 irq_type = AMDGPU_SDMA_IRQ_INSTANCE0 + i; 1402 if (enable) 1403 r = amdgpu_irq_get(adev, &adev->sdma.trap_irq, 1404 irq_type); 1405 else 1406 r = amdgpu_irq_put(adev, &adev->sdma.trap_irq, 1407 irq_type); 1408 if (r) 1409 return r; 1410 } 1411 } 1412 1413 return 0; 1414 } 1415 1416 static int sdma_v7_0_hw_init(struct amdgpu_ip_block *ip_block) 1417 { 1418 struct amdgpu_device *adev = ip_block->adev; 1419 int r; 1420 1421 r = sdma_v7_0_start(adev); 1422 if (r) 1423 return r; 1424 1425 return sdma_v7_0_set_userq_trap_interrupts(adev, true); 1426 } 1427 1428 static int sdma_v7_0_hw_fini(struct amdgpu_ip_block *ip_block) 1429 { 1430 struct amdgpu_device *adev = ip_block->adev; 1431 1432 if (amdgpu_sriov_vf(adev)) 1433 return 0; 1434 1435 sdma_v7_0_ctx_switch_enable(adev, false); 1436 sdma_v7_0_enable(adev, false); 1437 sdma_v7_0_set_userq_trap_interrupts(adev, false); 1438 1439 return 0; 1440 } 1441 1442 static int sdma_v7_0_suspend(struct amdgpu_ip_block *ip_block) 1443 { 1444 return sdma_v7_0_hw_fini(ip_block); 1445 } 1446 1447 static int sdma_v7_0_resume(struct amdgpu_ip_block *ip_block) 1448 { 1449 return sdma_v7_0_hw_init(ip_block); 1450 } 1451 1452 static bool sdma_v7_0_is_idle(struct amdgpu_ip_block *ip_block) 1453 { 1454 struct amdgpu_device *adev = ip_block->adev; 1455 u32 i; 1456 1457 for (i = 0; i < adev->sdma.num_instances; i++) { 1458 u32 tmp = RREG32(sdma_v7_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG)); 1459 1460 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1461 return false; 1462 } 1463 1464 return true; 1465 } 1466 1467 static int sdma_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1468 { 1469 unsigned i; 1470 u32 sdma0, sdma1; 1471 struct amdgpu_device *adev = ip_block->adev; 1472 1473 for (i = 0; i < adev->usec_timeout; i++) { 1474 sdma0 = RREG32(sdma_v7_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG)); 1475 sdma1 = RREG32(sdma_v7_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG)); 1476 1477 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1478 return 0; 1479 udelay(1); 1480 } 1481 return -ETIMEDOUT; 1482 } 1483 1484 static int sdma_v7_0_ring_preempt_ib(struct amdgpu_ring *ring) 1485 { 1486 int i, r = 0; 1487 struct amdgpu_device *adev = ring->adev; 1488 u32 index = 0; 1489 u64 sdma_gfx_preempt; 1490 1491 amdgpu_sdma_get_index_from_ring(ring, &index); 1492 sdma_gfx_preempt = 1493 sdma_v7_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT); 1494 1495 /* assert preemption condition */ 1496 amdgpu_ring_set_preempt_cond_exec(ring, false); 1497 1498 /* emit the trailing fence */ 1499 ring->trail_seq += 1; 1500 r = amdgpu_ring_alloc(ring, 10); 1501 if (r) { 1502 DRM_ERROR("ring %d failed to be allocated \n", ring->idx); 1503 return r; 1504 } 1505 sdma_v7_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1506 ring->trail_seq, 0); 1507 amdgpu_ring_commit(ring); 1508 1509 /* assert IB preemption */ 1510 WREG32(sdma_gfx_preempt, 1); 1511 1512 /* poll the trailing fence */ 1513 for (i = 0; i < adev->usec_timeout; i++) { 1514 if (ring->trail_seq == 1515 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1516 break; 1517 udelay(1); 1518 } 1519 1520 if (i >= adev->usec_timeout) { 1521 r = -EINVAL; 1522 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1523 } 1524 1525 /* deassert IB preemption */ 1526 WREG32(sdma_gfx_preempt, 0); 1527 1528 /* deassert the preemption condition */ 1529 amdgpu_ring_set_preempt_cond_exec(ring, true); 1530 return r; 1531 } 1532 1533 static int sdma_v7_0_set_trap_irq_state(struct amdgpu_device *adev, 1534 struct amdgpu_irq_src *source, 1535 unsigned type, 1536 enum amdgpu_interrupt_state state) 1537 { 1538 u32 sdma_cntl; 1539 1540 u32 reg_offset = sdma_v7_0_get_reg_offset(adev, type, regSDMA0_CNTL); 1541 1542 sdma_cntl = RREG32(reg_offset); 1543 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1544 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1545 WREG32(reg_offset, sdma_cntl); 1546 1547 return 0; 1548 } 1549 1550 static int sdma_v7_0_process_trap_irq(struct amdgpu_device *adev, 1551 struct amdgpu_irq_src *source, 1552 struct amdgpu_iv_entry *entry) 1553 { 1554 int instances, queue; 1555 1556 DRM_DEBUG("IH: SDMA trap\n"); 1557 1558 queue = entry->ring_id & 0xf; 1559 instances = (entry->ring_id & 0xf0) >> 4; 1560 if (instances > 1) { 1561 DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n"); 1562 return -EINVAL; 1563 } 1564 1565 switch (entry->client_id) { 1566 case SOC21_IH_CLIENTID_GFX: 1567 switch (queue) { 1568 case 0: 1569 amdgpu_fence_process(&adev->sdma.instance[instances].ring); 1570 break; 1571 default: 1572 break; 1573 } 1574 break; 1575 } 1576 return 0; 1577 } 1578 1579 static int sdma_v7_0_process_fence_irq(struct amdgpu_device *adev, 1580 struct amdgpu_irq_src *source, 1581 struct amdgpu_iv_entry *entry) 1582 { 1583 u32 doorbell_offset = entry->src_data[0]; 1584 1585 if (adev->enable_mes && doorbell_offset) { 1586 struct amdgpu_userq_fence_driver *fence_drv = NULL; 1587 struct xarray *xa = &adev->userq_xa; 1588 unsigned long flags; 1589 1590 doorbell_offset >>= SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 1591 1592 xa_lock_irqsave(xa, flags); 1593 fence_drv = xa_load(xa, doorbell_offset); 1594 if (fence_drv) 1595 amdgpu_userq_fence_driver_process(fence_drv); 1596 xa_unlock_irqrestore(xa, flags); 1597 } 1598 1599 return 0; 1600 } 1601 1602 static int sdma_v7_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1603 struct amdgpu_irq_src *source, 1604 struct amdgpu_iv_entry *entry) 1605 { 1606 return 0; 1607 } 1608 1609 static int sdma_v7_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1610 enum amd_clockgating_state state) 1611 { 1612 return 0; 1613 } 1614 1615 static int sdma_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 1616 enum amd_powergating_state state) 1617 { 1618 return 0; 1619 } 1620 1621 static void sdma_v7_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1622 { 1623 } 1624 1625 static void sdma_v7_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 1626 { 1627 struct amdgpu_device *adev = ip_block->adev; 1628 int i, j; 1629 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_0); 1630 uint32_t instance_offset; 1631 1632 if (!adev->sdma.ip_dump) 1633 return; 1634 1635 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances); 1636 for (i = 0; i < adev->sdma.num_instances; i++) { 1637 instance_offset = i * reg_count; 1638 drm_printf(p, "\nInstance:%d\n", i); 1639 1640 for (j = 0; j < reg_count; j++) 1641 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_7_0[j].reg_name, 1642 adev->sdma.ip_dump[instance_offset + j]); 1643 } 1644 } 1645 1646 static void sdma_v7_0_dump_ip_state(struct amdgpu_ip_block *ip_block) 1647 { 1648 struct amdgpu_device *adev = ip_block->adev; 1649 int i, j; 1650 uint32_t instance_offset; 1651 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_0); 1652 1653 if (!adev->sdma.ip_dump) 1654 return; 1655 1656 amdgpu_gfx_off_ctrl(adev, false); 1657 for (i = 0; i < adev->sdma.num_instances; i++) { 1658 instance_offset = i * reg_count; 1659 for (j = 0; j < reg_count; j++) 1660 adev->sdma.ip_dump[instance_offset + j] = 1661 RREG32(sdma_v7_0_get_reg_offset(adev, i, 1662 sdma_reg_list_7_0[j].reg_offset)); 1663 } 1664 amdgpu_gfx_off_ctrl(adev, true); 1665 } 1666 1667 const struct amd_ip_funcs sdma_v7_0_ip_funcs = { 1668 .name = "sdma_v7_0", 1669 .early_init = sdma_v7_0_early_init, 1670 .late_init = NULL, 1671 .sw_init = sdma_v7_0_sw_init, 1672 .sw_fini = sdma_v7_0_sw_fini, 1673 .hw_init = sdma_v7_0_hw_init, 1674 .hw_fini = sdma_v7_0_hw_fini, 1675 .suspend = sdma_v7_0_suspend, 1676 .resume = sdma_v7_0_resume, 1677 .is_idle = sdma_v7_0_is_idle, 1678 .wait_for_idle = sdma_v7_0_wait_for_idle, 1679 .soft_reset = sdma_v7_0_soft_reset, 1680 .check_soft_reset = sdma_v7_0_check_soft_reset, 1681 .set_clockgating_state = sdma_v7_0_set_clockgating_state, 1682 .set_powergating_state = sdma_v7_0_set_powergating_state, 1683 .get_clockgating_state = sdma_v7_0_get_clockgating_state, 1684 .dump_ip_state = sdma_v7_0_dump_ip_state, 1685 .print_ip_state = sdma_v7_0_print_ip_state, 1686 }; 1687 1688 static const struct amdgpu_ring_funcs sdma_v7_0_ring_funcs = { 1689 .type = AMDGPU_RING_TYPE_SDMA, 1690 .align_mask = 0xf, 1691 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1692 .support_64bit_ptrs = true, 1693 .secure_submission_supported = true, 1694 .get_rptr = sdma_v7_0_ring_get_rptr, 1695 .get_wptr = sdma_v7_0_ring_get_wptr, 1696 .set_wptr = sdma_v7_0_ring_set_wptr, 1697 .emit_frame_size = 1698 5 + /* sdma_v7_0_ring_init_cond_exec */ 1699 6 + /* sdma_v7_0_ring_emit_hdp_flush */ 1700 6 + /* sdma_v7_0_ring_emit_pipeline_sync */ 1701 /* sdma_v7_0_ring_emit_vm_flush */ 1702 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1703 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1704 10 + 10 + 10, /* sdma_v7_0_ring_emit_fence x3 for user fence, vm fence */ 1705 .emit_ib_size = 5 + 7 + 6, /* sdma_v7_0_ring_emit_ib */ 1706 .emit_ib = sdma_v7_0_ring_emit_ib, 1707 .emit_mem_sync = sdma_v7_0_ring_emit_mem_sync, 1708 .emit_fence = sdma_v7_0_ring_emit_fence, 1709 .emit_pipeline_sync = sdma_v7_0_ring_emit_pipeline_sync, 1710 .emit_vm_flush = sdma_v7_0_ring_emit_vm_flush, 1711 .emit_hdp_flush = sdma_v7_0_ring_emit_hdp_flush, 1712 .test_ring = sdma_v7_0_ring_test_ring, 1713 .test_ib = sdma_v7_0_ring_test_ib, 1714 .insert_nop = sdma_v7_0_ring_insert_nop, 1715 .pad_ib = sdma_v7_0_ring_pad_ib, 1716 .emit_wreg = sdma_v7_0_ring_emit_wreg, 1717 .emit_reg_wait = sdma_v7_0_ring_emit_reg_wait, 1718 .emit_reg_write_reg_wait = sdma_v7_0_ring_emit_reg_write_reg_wait, 1719 .init_cond_exec = sdma_v7_0_ring_init_cond_exec, 1720 .preempt_ib = sdma_v7_0_ring_preempt_ib, 1721 .reset = sdma_v7_0_reset_queue, 1722 }; 1723 1724 static void sdma_v7_0_set_ring_funcs(struct amdgpu_device *adev) 1725 { 1726 int i; 1727 1728 for (i = 0; i < adev->sdma.num_instances; i++) { 1729 adev->sdma.instance[i].ring.funcs = &sdma_v7_0_ring_funcs; 1730 adev->sdma.instance[i].ring.me = i; 1731 } 1732 } 1733 1734 static const struct amdgpu_irq_src_funcs sdma_v7_0_trap_irq_funcs = { 1735 .set = sdma_v7_0_set_trap_irq_state, 1736 .process = sdma_v7_0_process_trap_irq, 1737 }; 1738 1739 static const struct amdgpu_irq_src_funcs sdma_v7_0_fence_irq_funcs = { 1740 .process = sdma_v7_0_process_fence_irq, 1741 }; 1742 1743 static const struct amdgpu_irq_src_funcs sdma_v7_0_illegal_inst_irq_funcs = { 1744 .process = sdma_v7_0_process_illegal_inst_irq, 1745 }; 1746 1747 static void sdma_v7_0_set_irq_funcs(struct amdgpu_device *adev) 1748 { 1749 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1750 adev->sdma.num_instances; 1751 adev->sdma.trap_irq.funcs = &sdma_v7_0_trap_irq_funcs; 1752 adev->sdma.fence_irq.funcs = &sdma_v7_0_fence_irq_funcs; 1753 adev->sdma.illegal_inst_irq.funcs = &sdma_v7_0_illegal_inst_irq_funcs; 1754 } 1755 1756 /** 1757 * sdma_v7_0_emit_copy_buffer - copy buffer using the sDMA engine 1758 * 1759 * @ib: indirect buffer to fill with commands 1760 * @src_offset: src GPU address 1761 * @dst_offset: dst GPU address 1762 * @byte_count: number of bytes to xfer 1763 * @copy_flags: copy flags for the buffers 1764 * 1765 * Copy GPU buffers using the DMA engine. 1766 * Used by the amdgpu ttm implementation to move pages if 1767 * registered as the asic copy callback. 1768 */ 1769 static void sdma_v7_0_emit_copy_buffer(struct amdgpu_ib *ib, 1770 uint64_t src_offset, 1771 uint64_t dst_offset, 1772 uint32_t byte_count, 1773 uint32_t copy_flags) 1774 { 1775 uint32_t num_type, data_format, max_com, write_cm; 1776 1777 max_com = AMDGPU_COPY_FLAGS_GET(copy_flags, MAX_COMPRESSED); 1778 data_format = AMDGPU_COPY_FLAGS_GET(copy_flags, DATA_FORMAT); 1779 num_type = AMDGPU_COPY_FLAGS_GET(copy_flags, NUMBER_TYPE); 1780 write_cm = AMDGPU_COPY_FLAGS_GET(copy_flags, WRITE_COMPRESS_DISABLE) ? 2 : 1; 1781 1782 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1783 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1784 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0) | 1785 SDMA_PKT_COPY_LINEAR_HEADER_CPV(1); 1786 1787 ib->ptr[ib->length_dw++] = byte_count - 1; 1788 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1789 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1790 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1791 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1792 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1793 1794 if ((copy_flags & (AMDGPU_COPY_FLAGS_READ_DECOMPRESSED | AMDGPU_COPY_FLAGS_WRITE_COMPRESSED))) 1795 ib->ptr[ib->length_dw++] = SDMA_DCC_DATA_FORMAT(data_format) | SDMA_DCC_NUM_TYPE(num_type) | 1796 ((copy_flags & AMDGPU_COPY_FLAGS_READ_DECOMPRESSED) ? SDMA_DCC_READ_CM(2) : 0) | 1797 ((copy_flags & AMDGPU_COPY_FLAGS_WRITE_COMPRESSED) ? SDMA_DCC_WRITE_CM(write_cm) : 0) | 1798 SDMA_DCC_MAX_COM(max_com) | SDMA_DCC_MAX_UCOM(1); 1799 else 1800 ib->ptr[ib->length_dw++] = 0; 1801 } 1802 1803 /** 1804 * sdma_v7_0_emit_fill_buffer - fill buffer using the sDMA engine 1805 * 1806 * @ib: indirect buffer to fill 1807 * @src_data: value to write to buffer 1808 * @dst_offset: dst GPU address 1809 * @byte_count: number of bytes to xfer 1810 * 1811 * Fill GPU buffers using the DMA engine. 1812 */ 1813 static void sdma_v7_0_emit_fill_buffer(struct amdgpu_ib *ib, 1814 uint32_t src_data, 1815 uint64_t dst_offset, 1816 uint32_t byte_count) 1817 { 1818 ib->ptr[ib->length_dw++] = SDMA_PKT_CONSTANT_FILL_HEADER_OP(SDMA_OP_CONST_FILL) | 1819 SDMA_PKT_CONSTANT_FILL_HEADER_COMPRESS(1); 1820 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1821 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1822 ib->ptr[ib->length_dw++] = src_data; 1823 ib->ptr[ib->length_dw++] = byte_count - 1; 1824 } 1825 1826 static const struct amdgpu_buffer_funcs sdma_v7_0_buffer_funcs = { 1827 .copy_max_bytes = 0x400000, 1828 .copy_num_dw = 8, 1829 .emit_copy_buffer = sdma_v7_0_emit_copy_buffer, 1830 .fill_max_bytes = 0x400000, 1831 .fill_num_dw = 5, 1832 .emit_fill_buffer = sdma_v7_0_emit_fill_buffer, 1833 }; 1834 1835 static void sdma_v7_0_set_buffer_funcs(struct amdgpu_device *adev) 1836 { 1837 adev->mman.buffer_funcs = &sdma_v7_0_buffer_funcs; 1838 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1839 } 1840 1841 static const struct amdgpu_vm_pte_funcs sdma_v7_0_vm_pte_funcs = { 1842 .copy_pte_num_dw = 8, 1843 .copy_pte = sdma_v7_0_vm_copy_pte, 1844 .write_pte = sdma_v7_0_vm_write_pte, 1845 .set_pte_pde = sdma_v7_0_vm_set_pte_pde, 1846 }; 1847 1848 static void sdma_v7_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1849 { 1850 unsigned i; 1851 1852 adev->vm_manager.vm_pte_funcs = &sdma_v7_0_vm_pte_funcs; 1853 for (i = 0; i < adev->sdma.num_instances; i++) { 1854 adev->vm_manager.vm_pte_scheds[i] = 1855 &adev->sdma.instance[i].ring.sched; 1856 } 1857 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1858 } 1859 1860 const struct amdgpu_ip_block_version sdma_v7_0_ip_block = { 1861 .type = AMD_IP_BLOCK_TYPE_SDMA, 1862 .major = 7, 1863 .minor = 0, 1864 .rev = 0, 1865 .funcs = &sdma_v7_0_ip_funcs, 1866 }; 1867