1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_11_0_0_offset.h" 34 #include "gc/gc_11_0_0_sh_mask.h" 35 #include "gc/gc_11_0_0_default.h" 36 #include "hdp/hdp_6_0_0_offset.h" 37 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 38 39 #include "soc15_common.h" 40 #include "soc15.h" 41 #include "sdma_v6_0_0_pkt_open.h" 42 #include "nbio_v4_3.h" 43 #include "sdma_common.h" 44 #include "sdma_v6_0.h" 45 #include "v11_structs.h" 46 47 MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin"); 48 MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin"); 49 MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin"); 50 MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin"); 51 MODULE_FIRMWARE("amdgpu/sdma_6_1_0.bin"); 52 MODULE_FIRMWARE("amdgpu/sdma_6_1_1.bin"); 53 54 #define SDMA1_REG_OFFSET 0x600 55 #define SDMA0_HYP_DEC_REG_START 0x5880 56 #define SDMA0_HYP_DEC_REG_END 0x589a 57 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 58 59 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev); 60 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev); 61 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev); 62 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev); 63 static int sdma_v6_0_start(struct amdgpu_device *adev); 64 65 static u32 sdma_v6_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 66 { 67 u32 base; 68 69 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 70 internal_offset <= SDMA0_HYP_DEC_REG_END) { 71 base = adev->reg_offset[GC_HWIP][0][1]; 72 if (instance != 0) 73 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance; 74 } else { 75 base = adev->reg_offset[GC_HWIP][0][0]; 76 if (instance == 1) 77 internal_offset += SDMA1_REG_OFFSET; 78 } 79 80 return base + internal_offset; 81 } 82 83 static unsigned sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring *ring, 84 uint64_t addr) 85 { 86 unsigned ret; 87 88 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE)); 89 amdgpu_ring_write(ring, lower_32_bits(addr)); 90 amdgpu_ring_write(ring, upper_32_bits(addr)); 91 amdgpu_ring_write(ring, 1); 92 /* this is the offset we need patch later */ 93 ret = ring->wptr & ring->buf_mask; 94 /* insert dummy here and patch it later */ 95 amdgpu_ring_write(ring, 0); 96 97 return ret; 98 } 99 100 /** 101 * sdma_v6_0_ring_get_rptr - get the current read pointer 102 * 103 * @ring: amdgpu ring pointer 104 * 105 * Get the current rptr from the hardware. 106 */ 107 static uint64_t sdma_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 108 { 109 u64 *rptr; 110 111 /* XXX check if swapping is necessary on BE */ 112 rptr = (u64 *)ring->rptr_cpu_addr; 113 114 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 115 return ((*rptr) >> 2); 116 } 117 118 /** 119 * sdma_v6_0_ring_get_wptr - get the current write pointer 120 * 121 * @ring: amdgpu ring pointer 122 * 123 * Get the current wptr from the hardware. 124 */ 125 static uint64_t sdma_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 126 { 127 u64 wptr = 0; 128 129 if (ring->use_doorbell) { 130 /* XXX check if swapping is necessary on BE */ 131 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 132 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 133 } 134 135 return wptr >> 2; 136 } 137 138 /** 139 * sdma_v6_0_ring_set_wptr - commit the write pointer 140 * 141 * @ring: amdgpu ring pointer 142 * 143 * Write the wptr back to the hardware. 144 */ 145 static void sdma_v6_0_ring_set_wptr(struct amdgpu_ring *ring) 146 { 147 struct amdgpu_device *adev = ring->adev; 148 149 if (ring->use_doorbell) { 150 DRM_DEBUG("Using doorbell -- " 151 "wptr_offs == 0x%08x " 152 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 153 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 154 ring->wptr_offs, 155 lower_32_bits(ring->wptr << 2), 156 upper_32_bits(ring->wptr << 2)); 157 /* XXX check if swapping is necessary on BE */ 158 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 159 ring->wptr << 2); 160 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 161 ring->doorbell_index, ring->wptr << 2); 162 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 163 } else { 164 DRM_DEBUG("Not using doorbell -- " 165 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 166 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 167 ring->me, 168 lower_32_bits(ring->wptr << 2), 169 ring->me, 170 upper_32_bits(ring->wptr << 2)); 171 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 172 ring->me, regSDMA0_QUEUE0_RB_WPTR), 173 lower_32_bits(ring->wptr << 2)); 174 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 175 ring->me, regSDMA0_QUEUE0_RB_WPTR_HI), 176 upper_32_bits(ring->wptr << 2)); 177 } 178 } 179 180 static void sdma_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 181 { 182 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 183 int i; 184 185 for (i = 0; i < count; i++) 186 if (sdma && sdma->burst_nop && (i == 0)) 187 amdgpu_ring_write(ring, ring->funcs->nop | 188 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 189 else 190 amdgpu_ring_write(ring, ring->funcs->nop); 191 } 192 193 /* 194 * sdma_v6_0_ring_emit_ib - Schedule an IB on the DMA engine 195 * 196 * @ring: amdgpu ring pointer 197 * @ib: IB object to schedule 198 * @flags: unused 199 * @job: job to retrieve vmid from 200 * 201 * Schedule an IB in the DMA ring. 202 */ 203 static void sdma_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 204 struct amdgpu_job *job, 205 struct amdgpu_ib *ib, 206 uint32_t flags) 207 { 208 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 209 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 210 211 /* An IB packet must end on a 8 DW boundary--the next dword 212 * must be on a 8-dword boundary. Our IB packet below is 6 213 * dwords long, thus add x number of NOPs, such that, in 214 * modular arithmetic, 215 * wptr + 6 + x = 8k, k >= 0, which in C is, 216 * (wptr + 6 + x) % 8 = 0. 217 * The expression below, is a solution of x. 218 */ 219 sdma_v6_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 220 221 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) | 222 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 223 /* base must be 32 byte aligned */ 224 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 225 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 226 amdgpu_ring_write(ring, ib->length_dw); 227 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 228 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 229 } 230 231 /** 232 * sdma_v6_0_ring_emit_mem_sync - flush the IB by graphics cache rinse 233 * 234 * @ring: amdgpu ring pointer 235 * 236 * flush the IB by graphics cache rinse. 237 */ 238 static void sdma_v6_0_ring_emit_mem_sync(struct amdgpu_ring *ring) 239 { 240 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV | 241 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 242 SDMA_GCR_GLI_INV(1); 243 244 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 245 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ)); 246 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 247 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 248 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 249 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 250 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 251 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 252 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 253 } 254 255 256 /** 257 * sdma_v6_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 258 * 259 * @ring: amdgpu ring pointer 260 * 261 * Emit an hdp flush packet on the requested DMA ring. 262 */ 263 static void sdma_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 264 { 265 struct amdgpu_device *adev = ring->adev; 266 u32 ref_and_mask = 0; 267 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 268 269 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 270 271 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 272 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 273 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 274 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 275 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 276 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 277 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 278 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 279 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 280 } 281 282 /** 283 * sdma_v6_0_ring_emit_fence - emit a fence on the DMA ring 284 * 285 * @ring: amdgpu ring pointer 286 * @addr: address 287 * @seq: fence seq number 288 * @flags: fence flags 289 * 290 * Add a DMA fence packet to the ring to write 291 * the fence seq number and DMA trap packet to generate 292 * an interrupt if needed. 293 */ 294 static void sdma_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 295 unsigned flags) 296 { 297 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 298 /* write the fence */ 299 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 300 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 301 /* zero in first two bits */ 302 BUG_ON(addr & 0x3); 303 amdgpu_ring_write(ring, lower_32_bits(addr)); 304 amdgpu_ring_write(ring, upper_32_bits(addr)); 305 amdgpu_ring_write(ring, lower_32_bits(seq)); 306 307 /* optionally write high bits as well */ 308 if (write64bit) { 309 addr += 4; 310 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 311 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 312 /* zero in first two bits */ 313 BUG_ON(addr & 0x3); 314 amdgpu_ring_write(ring, lower_32_bits(addr)); 315 amdgpu_ring_write(ring, upper_32_bits(addr)); 316 amdgpu_ring_write(ring, upper_32_bits(seq)); 317 } 318 319 if (flags & AMDGPU_FENCE_FLAG_INT) { 320 uint32_t ctx = ring->is_mes_queue ? 321 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0; 322 /* generate an interrupt */ 323 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP)); 324 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx)); 325 } 326 } 327 328 /** 329 * sdma_v6_0_gfx_stop - stop the gfx async dma engines 330 * 331 * @adev: amdgpu_device pointer 332 * 333 * Stop the gfx async dma ring buffers. 334 */ 335 static void sdma_v6_0_gfx_stop(struct amdgpu_device *adev) 336 { 337 u32 rb_cntl, ib_cntl; 338 int i; 339 340 for (i = 0; i < adev->sdma.num_instances; i++) { 341 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 342 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0); 343 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 344 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 345 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0); 346 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 347 } 348 } 349 350 /** 351 * sdma_v6_0_rlc_stop - stop the compute async dma engines 352 * 353 * @adev: amdgpu_device pointer 354 * 355 * Stop the compute async dma queues. 356 */ 357 static void sdma_v6_0_rlc_stop(struct amdgpu_device *adev) 358 { 359 /* XXX todo */ 360 } 361 362 /** 363 * sdma_v6_0_ctxempty_int_enable - enable or disable context empty interrupts 364 * 365 * @adev: amdgpu_device pointer 366 * @enable: enable/disable context switching due to queue empty conditions 367 * 368 * Enable or disable the async dma engines queue empty context switch. 369 */ 370 static void sdma_v6_0_ctxempty_int_enable(struct amdgpu_device *adev, bool enable) 371 { 372 u32 f32_cntl; 373 int i; 374 375 if (!amdgpu_sriov_vf(adev)) { 376 for (i = 0; i < adev->sdma.num_instances; i++) { 377 f32_cntl = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL)); 378 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 379 CTXEMPTY_INT_ENABLE, enable ? 1 : 0); 380 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL), f32_cntl); 381 } 382 } 383 } 384 385 /** 386 * sdma_v6_0_enable - stop the async dma engines 387 * 388 * @adev: amdgpu_device pointer 389 * @enable: enable/disable the DMA MEs. 390 * 391 * Halt or unhalt the async dma engines. 392 */ 393 static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable) 394 { 395 u32 f32_cntl; 396 int i; 397 398 if (!enable) { 399 sdma_v6_0_gfx_stop(adev); 400 sdma_v6_0_rlc_stop(adev); 401 } 402 403 if (amdgpu_sriov_vf(adev)) 404 return; 405 406 for (i = 0; i < adev->sdma.num_instances; i++) { 407 f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 408 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 409 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl); 410 } 411 } 412 413 /** 414 * sdma_v6_0_gfx_resume - setup and start the async dma engines 415 * 416 * @adev: amdgpu_device pointer 417 * 418 * Set up the gfx DMA ring buffers and enable them. 419 * Returns 0 for success, error for failure. 420 */ 421 static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev) 422 { 423 struct amdgpu_ring *ring; 424 u32 rb_cntl, ib_cntl; 425 u32 rb_bufsz; 426 u32 doorbell; 427 u32 doorbell_offset; 428 u32 temp; 429 u64 wptr_gpu_addr; 430 int i, r; 431 432 for (i = 0; i < adev->sdma.num_instances; i++) { 433 ring = &adev->sdma.instance[i].ring; 434 435 if (!amdgpu_sriov_vf(adev)) 436 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 437 438 /* Set ring buffer size in dwords */ 439 rb_bufsz = order_base_2(ring->ring_size / 4); 440 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 441 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); 442 #ifdef __BIG_ENDIAN 443 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1); 444 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, 445 RPTR_WRITEBACK_SWAP_ENABLE, 1); 446 #endif 447 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1); 448 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 449 450 /* Initialize the ring buffer's read and write pointers */ 451 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0); 452 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0); 453 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0); 454 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0); 455 456 /* setup the wptr shadow polling */ 457 wptr_gpu_addr = ring->wptr_gpu_addr; 458 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO), 459 lower_32_bits(wptr_gpu_addr)); 460 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI), 461 upper_32_bits(wptr_gpu_addr)); 462 463 /* set the wb address whether it's enabled or not */ 464 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI), 465 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 466 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO), 467 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 468 469 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 470 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0); 471 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1); 472 473 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8); 474 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40); 475 476 ring->wptr = 0; 477 478 /* before programing wptr to a less value, need set minor_ptr_update first */ 479 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1); 480 481 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 482 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2); 483 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 484 } 485 486 doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL)); 487 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET)); 488 489 if (ring->use_doorbell) { 490 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 491 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET, 492 OFFSET, ring->doorbell_index); 493 } else { 494 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0); 495 } 496 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell); 497 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset); 498 499 if (i == 0) 500 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 501 ring->doorbell_index, 502 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances); 503 504 if (amdgpu_sriov_vf(adev)) 505 sdma_v6_0_ring_set_wptr(ring); 506 507 /* set minor_ptr_update to 0 after wptr programed */ 508 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0); 509 510 /* Set up sdma hang watchdog */ 511 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL)); 512 /* 100ms per unit */ 513 temp = REG_SET_FIELD(temp, SDMA0_WATCHDOG_CNTL, QUEUE_HANG_COUNT, 514 max(adev->usec_timeout/100000, 1)); 515 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), temp); 516 517 /* Set up RESP_MODE to non-copy addresses */ 518 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL)); 519 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 520 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 521 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp); 522 523 /* program default cache read and write policy */ 524 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE)); 525 /* clean read policy and write policy bits */ 526 temp &= 0xFF0FFF; 527 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | 528 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | 529 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK); 530 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp); 531 532 if (!amdgpu_sriov_vf(adev)) { 533 /* unhalt engine */ 534 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 535 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 536 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0); 537 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp); 538 } 539 540 /* enable DMA RB */ 541 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1); 542 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 543 544 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 545 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1); 546 #ifdef __BIG_ENDIAN 547 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1); 548 #endif 549 /* enable DMA IBs */ 550 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 551 552 if (amdgpu_sriov_vf(adev)) 553 sdma_v6_0_enable(adev, true); 554 555 r = amdgpu_ring_test_helper(ring); 556 if (r) 557 return r; 558 } 559 560 return 0; 561 } 562 563 /** 564 * sdma_v6_0_rlc_resume - setup and start the async dma engines 565 * 566 * @adev: amdgpu_device pointer 567 * 568 * Set up the compute DMA queues and enable them. 569 * Returns 0 for success, error for failure. 570 */ 571 static int sdma_v6_0_rlc_resume(struct amdgpu_device *adev) 572 { 573 return 0; 574 } 575 576 /** 577 * sdma_v6_0_load_microcode - load the sDMA ME ucode 578 * 579 * @adev: amdgpu_device pointer 580 * 581 * Loads the sDMA0/1 ucode. 582 * Returns 0 for success, -EINVAL if the ucode is not available. 583 */ 584 static int sdma_v6_0_load_microcode(struct amdgpu_device *adev) 585 { 586 const struct sdma_firmware_header_v2_0 *hdr; 587 const __le32 *fw_data; 588 u32 fw_size; 589 int i, j; 590 bool use_broadcast; 591 592 /* halt the MEs */ 593 sdma_v6_0_enable(adev, false); 594 595 if (!adev->sdma.instance[0].fw) 596 return -EINVAL; 597 598 /* use broadcast mode to load SDMA microcode by default */ 599 use_broadcast = true; 600 601 if (use_broadcast) { 602 dev_info(adev->dev, "Use broadcast method to load SDMA firmware\n"); 603 /* load Control Thread microcode */ 604 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data; 605 amdgpu_ucode_print_sdma_hdr(&hdr->header); 606 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4; 607 608 fw_data = (const __le32 *) 609 (adev->sdma.instance[0].fw->data + 610 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 611 612 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0); 613 614 for (j = 0; j < fw_size; j++) { 615 if (amdgpu_emu_mode == 1 && j % 500 == 0) 616 msleep(1); 617 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++)); 618 } 619 620 /* load Context Switch microcode */ 621 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4; 622 623 fw_data = (const __le32 *) 624 (adev->sdma.instance[0].fw->data + 625 le32_to_cpu(hdr->ctl_ucode_offset)); 626 627 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0x8000); 628 629 for (j = 0; j < fw_size; j++) { 630 if (amdgpu_emu_mode == 1 && j % 500 == 0) 631 msleep(1); 632 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++)); 633 } 634 } else { 635 dev_info(adev->dev, "Use legacy method to load SDMA firmware\n"); 636 for (i = 0; i < adev->sdma.num_instances; i++) { 637 /* load Control Thread microcode */ 638 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data; 639 amdgpu_ucode_print_sdma_hdr(&hdr->header); 640 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4; 641 642 fw_data = (const __le32 *) 643 (adev->sdma.instance[0].fw->data + 644 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 645 646 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0); 647 648 for (j = 0; j < fw_size; j++) { 649 if (amdgpu_emu_mode == 1 && j % 500 == 0) 650 msleep(1); 651 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 652 } 653 654 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version); 655 656 /* load Context Switch microcode */ 657 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4; 658 659 fw_data = (const __le32 *) 660 (adev->sdma.instance[0].fw->data + 661 le32_to_cpu(hdr->ctl_ucode_offset)); 662 663 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0x8000); 664 665 for (j = 0; j < fw_size; j++) { 666 if (amdgpu_emu_mode == 1 && j % 500 == 0) 667 msleep(1); 668 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 669 } 670 671 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version); 672 } 673 } 674 675 return 0; 676 } 677 678 static int sdma_v6_0_soft_reset(void *handle) 679 { 680 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 681 u32 tmp; 682 int i; 683 684 sdma_v6_0_gfx_stop(adev); 685 686 for (i = 0; i < adev->sdma.num_instances; i++) { 687 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE)); 688 tmp |= SDMA0_FREEZE__FREEZE_MASK; 689 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp); 690 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 691 tmp |= SDMA0_F32_CNTL__HALT_MASK; 692 tmp |= SDMA0_F32_CNTL__TH1_RESET_MASK; 693 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp); 694 695 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0); 696 697 udelay(100); 698 699 tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i; 700 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); 701 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 702 703 udelay(100); 704 705 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0); 706 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 707 708 udelay(100); 709 } 710 711 return sdma_v6_0_start(adev); 712 } 713 714 static bool sdma_v6_0_check_soft_reset(void *handle) 715 { 716 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 717 struct amdgpu_ring *ring; 718 int i, r; 719 long tmo = msecs_to_jiffies(1000); 720 721 for (i = 0; i < adev->sdma.num_instances; i++) { 722 ring = &adev->sdma.instance[i].ring; 723 r = amdgpu_ring_test_ib(ring, tmo); 724 if (r) 725 return true; 726 } 727 728 return false; 729 } 730 731 /** 732 * sdma_v6_0_start - setup and start the async dma engines 733 * 734 * @adev: amdgpu_device pointer 735 * 736 * Set up the DMA engines and enable them. 737 * Returns 0 for success, error for failure. 738 */ 739 static int sdma_v6_0_start(struct amdgpu_device *adev) 740 { 741 int r = 0; 742 743 if (amdgpu_sriov_vf(adev)) { 744 sdma_v6_0_enable(adev, false); 745 746 /* set RB registers */ 747 r = sdma_v6_0_gfx_resume(adev); 748 return r; 749 } 750 751 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 752 r = sdma_v6_0_load_microcode(adev); 753 if (r) 754 return r; 755 756 /* The value of regSDMA_F32_CNTL is invalid the moment after loading fw */ 757 if (amdgpu_emu_mode == 1) 758 msleep(1000); 759 } 760 761 /* unhalt the MEs */ 762 sdma_v6_0_enable(adev, true); 763 /* enable sdma ring preemption */ 764 sdma_v6_0_ctxempty_int_enable(adev, true); 765 766 /* start the gfx rings and rlc compute queues */ 767 r = sdma_v6_0_gfx_resume(adev); 768 if (r) 769 return r; 770 r = sdma_v6_0_rlc_resume(adev); 771 772 return r; 773 } 774 775 static int sdma_v6_0_mqd_init(struct amdgpu_device *adev, void *mqd, 776 struct amdgpu_mqd_prop *prop) 777 { 778 struct v11_sdma_mqd *m = mqd; 779 uint64_t wb_gpu_addr; 780 781 m->sdmax_rlcx_rb_cntl = 782 order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT | 783 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 784 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | 785 1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT; 786 787 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8); 788 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); 789 790 wb_gpu_addr = prop->wptr_gpu_addr; 791 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); 792 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); 793 794 wb_gpu_addr = prop->rptr_gpu_addr; 795 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); 796 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); 797 798 m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 0, 799 regSDMA0_QUEUE0_IB_CNTL)); 800 801 m->sdmax_rlcx_doorbell_offset = 802 prop->doorbell_index << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 803 804 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 805 806 m->sdmax_rlcx_skip_cntl = 0; 807 m->sdmax_rlcx_context_status = 0; 808 m->sdmax_rlcx_doorbell_log = 0; 809 810 m->sdmax_rlcx_rb_aql_cntl = regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT; 811 m->sdmax_rlcx_dummy_reg = regSDMA0_QUEUE0_DUMMY_REG_DEFAULT; 812 813 return 0; 814 } 815 816 static void sdma_v6_0_set_mqd_funcs(struct amdgpu_device *adev) 817 { 818 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v11_sdma_mqd); 819 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v6_0_mqd_init; 820 } 821 822 /** 823 * sdma_v6_0_ring_test_ring - simple async dma engine test 824 * 825 * @ring: amdgpu_ring structure holding ring information 826 * 827 * Test the DMA engine by writing using it to write an 828 * value to memory. 829 * Returns 0 for success, error for failure. 830 */ 831 static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring) 832 { 833 struct amdgpu_device *adev = ring->adev; 834 unsigned i; 835 unsigned index; 836 int r; 837 u32 tmp; 838 u64 gpu_addr; 839 volatile uint32_t *cpu_ptr = NULL; 840 841 tmp = 0xCAFEDEAD; 842 843 if (ring->is_mes_queue) { 844 uint32_t offset = 0; 845 offset = amdgpu_mes_ctx_get_offs(ring, 846 AMDGPU_MES_CTX_PADDING_OFFS); 847 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 848 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 849 *cpu_ptr = tmp; 850 } else { 851 r = amdgpu_device_wb_get(adev, &index); 852 if (r) { 853 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 854 return r; 855 } 856 857 gpu_addr = adev->wb.gpu_addr + (index * 4); 858 adev->wb.wb[index] = cpu_to_le32(tmp); 859 } 860 861 r = amdgpu_ring_alloc(ring, 5); 862 if (r) { 863 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 864 amdgpu_device_wb_free(adev, index); 865 return r; 866 } 867 868 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 869 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 870 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 871 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 872 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 873 amdgpu_ring_write(ring, 0xDEADBEEF); 874 amdgpu_ring_commit(ring); 875 876 for (i = 0; i < adev->usec_timeout; i++) { 877 if (ring->is_mes_queue) 878 tmp = le32_to_cpu(*cpu_ptr); 879 else 880 tmp = le32_to_cpu(adev->wb.wb[index]); 881 if (tmp == 0xDEADBEEF) 882 break; 883 if (amdgpu_emu_mode == 1) 884 msleep(1); 885 else 886 udelay(1); 887 } 888 889 if (i >= adev->usec_timeout) 890 r = -ETIMEDOUT; 891 892 if (!ring->is_mes_queue) 893 amdgpu_device_wb_free(adev, index); 894 895 return r; 896 } 897 898 /* 899 * sdma_v6_0_ring_test_ib - test an IB on the DMA engine 900 * 901 * @ring: amdgpu_ring structure holding ring information 902 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 903 * 904 * Test a simple IB in the DMA ring. 905 * Returns 0 on success, error on failure. 906 */ 907 static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 908 { 909 struct amdgpu_device *adev = ring->adev; 910 struct amdgpu_ib ib; 911 struct dma_fence *f = NULL; 912 unsigned index; 913 long r; 914 u32 tmp = 0; 915 u64 gpu_addr; 916 volatile uint32_t *cpu_ptr = NULL; 917 918 tmp = 0xCAFEDEAD; 919 memset(&ib, 0, sizeof(ib)); 920 921 if (ring->is_mes_queue) { 922 uint32_t offset = 0; 923 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 924 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 925 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 926 927 offset = amdgpu_mes_ctx_get_offs(ring, 928 AMDGPU_MES_CTX_PADDING_OFFS); 929 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 930 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 931 *cpu_ptr = tmp; 932 } else { 933 r = amdgpu_device_wb_get(adev, &index); 934 if (r) { 935 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 936 return r; 937 } 938 939 gpu_addr = adev->wb.gpu_addr + (index * 4); 940 adev->wb.wb[index] = cpu_to_le32(tmp); 941 942 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 943 if (r) { 944 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 945 goto err0; 946 } 947 } 948 949 ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 950 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 951 ib.ptr[1] = lower_32_bits(gpu_addr); 952 ib.ptr[2] = upper_32_bits(gpu_addr); 953 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 954 ib.ptr[4] = 0xDEADBEEF; 955 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 956 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 957 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 958 ib.length_dw = 8; 959 960 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 961 if (r) 962 goto err1; 963 964 r = dma_fence_wait_timeout(f, false, timeout); 965 if (r == 0) { 966 DRM_ERROR("amdgpu: IB test timed out\n"); 967 r = -ETIMEDOUT; 968 goto err1; 969 } else if (r < 0) { 970 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 971 goto err1; 972 } 973 974 if (ring->is_mes_queue) 975 tmp = le32_to_cpu(*cpu_ptr); 976 else 977 tmp = le32_to_cpu(adev->wb.wb[index]); 978 979 if (tmp == 0xDEADBEEF) 980 r = 0; 981 else 982 r = -EINVAL; 983 984 err1: 985 amdgpu_ib_free(adev, &ib, NULL); 986 dma_fence_put(f); 987 err0: 988 if (!ring->is_mes_queue) 989 amdgpu_device_wb_free(adev, index); 990 return r; 991 } 992 993 994 /** 995 * sdma_v6_0_vm_copy_pte - update PTEs by copying them from the GART 996 * 997 * @ib: indirect buffer to fill with commands 998 * @pe: addr of the page entry 999 * @src: src addr to copy from 1000 * @count: number of page entries to update 1001 * 1002 * Update PTEs by copying them from the GART using sDMA. 1003 */ 1004 static void sdma_v6_0_vm_copy_pte(struct amdgpu_ib *ib, 1005 uint64_t pe, uint64_t src, 1006 unsigned count) 1007 { 1008 unsigned bytes = count * 8; 1009 1010 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1011 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1012 ib->ptr[ib->length_dw++] = bytes - 1; 1013 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1014 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1015 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1016 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1017 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1018 1019 } 1020 1021 /** 1022 * sdma_v6_0_vm_write_pte - update PTEs by writing them manually 1023 * 1024 * @ib: indirect buffer to fill with commands 1025 * @pe: addr of the page entry 1026 * @value: dst addr to write into pe 1027 * @count: number of page entries to update 1028 * @incr: increase next addr by incr bytes 1029 * 1030 * Update PTEs by writing them manually using sDMA. 1031 */ 1032 static void sdma_v6_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1033 uint64_t value, unsigned count, 1034 uint32_t incr) 1035 { 1036 unsigned ndw = count * 2; 1037 1038 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 1039 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1040 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1041 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1042 ib->ptr[ib->length_dw++] = ndw - 1; 1043 for (; ndw > 0; ndw -= 2) { 1044 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1045 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1046 value += incr; 1047 } 1048 } 1049 1050 /** 1051 * sdma_v6_0_vm_set_pte_pde - update the page tables using sDMA 1052 * 1053 * @ib: indirect buffer to fill with commands 1054 * @pe: addr of the page entry 1055 * @addr: dst addr to write into pe 1056 * @count: number of page entries to update 1057 * @incr: increase next addr by incr bytes 1058 * @flags: access flags 1059 * 1060 * Update the page tables using sDMA. 1061 */ 1062 static void sdma_v6_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1063 uint64_t pe, 1064 uint64_t addr, unsigned count, 1065 uint32_t incr, uint64_t flags) 1066 { 1067 /* for physically contiguous pages (vram) */ 1068 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE); 1069 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1070 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1071 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1072 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1073 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1074 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1075 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1076 ib->ptr[ib->length_dw++] = 0; 1077 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1078 } 1079 1080 /* 1081 * sdma_v6_0_ring_pad_ib - pad the IB 1082 * @ib: indirect buffer to fill with padding 1083 * @ring: amdgpu ring pointer 1084 * 1085 * Pad the IB with NOPs to a boundary multiple of 8. 1086 */ 1087 static void sdma_v6_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1088 { 1089 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1090 u32 pad_count; 1091 int i; 1092 1093 pad_count = (-ib->length_dw) & 0x7; 1094 for (i = 0; i < pad_count; i++) 1095 if (sdma && sdma->burst_nop && (i == 0)) 1096 ib->ptr[ib->length_dw++] = 1097 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) | 1098 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1099 else 1100 ib->ptr[ib->length_dw++] = 1101 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP); 1102 } 1103 1104 /** 1105 * sdma_v6_0_ring_emit_pipeline_sync - sync the pipeline 1106 * 1107 * @ring: amdgpu_ring pointer 1108 * 1109 * Make sure all previous operations are completed (CIK). 1110 */ 1111 static void sdma_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1112 { 1113 uint32_t seq = ring->fence_drv.sync_seq; 1114 uint64_t addr = ring->fence_drv.gpu_addr; 1115 1116 /* wait for idle */ 1117 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1118 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1119 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1120 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1121 amdgpu_ring_write(ring, addr & 0xfffffffc); 1122 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1123 amdgpu_ring_write(ring, seq); /* reference */ 1124 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1125 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1126 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1127 } 1128 1129 /* 1130 * sdma_v6_0_ring_emit_vm_flush - vm flush using sDMA 1131 * 1132 * @ring: amdgpu_ring pointer 1133 * @vmid: vmid number to use 1134 * @pd_addr: address 1135 * 1136 * Update the page table base and flush the VM TLB 1137 * using sDMA. 1138 */ 1139 static void sdma_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1140 unsigned vmid, uint64_t pd_addr) 1141 { 1142 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1143 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 1144 1145 /* Update the PD address for this VMID. */ 1146 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 1147 (hub->ctx_addr_distance * vmid), 1148 lower_32_bits(pd_addr)); 1149 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 1150 (hub->ctx_addr_distance * vmid), 1151 upper_32_bits(pd_addr)); 1152 1153 /* Trigger invalidation. */ 1154 amdgpu_ring_write(ring, 1155 SDMA_PKT_VM_INVALIDATION_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1156 SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(SDMA_SUBOP_VM_INVALIDATION) | 1157 SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(ring->vm_inv_eng) | 1158 SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(0x1f)); 1159 amdgpu_ring_write(ring, req); 1160 amdgpu_ring_write(ring, 0xFFFFFFFF); 1161 amdgpu_ring_write(ring, 1162 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(1 << vmid) | 1163 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(0x1F)); 1164 } 1165 1166 static void sdma_v6_0_ring_emit_wreg(struct amdgpu_ring *ring, 1167 uint32_t reg, uint32_t val) 1168 { 1169 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1170 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1171 amdgpu_ring_write(ring, reg); 1172 amdgpu_ring_write(ring, val); 1173 } 1174 1175 static void sdma_v6_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1176 uint32_t val, uint32_t mask) 1177 { 1178 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1179 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1180 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1181 amdgpu_ring_write(ring, reg << 2); 1182 amdgpu_ring_write(ring, 0); 1183 amdgpu_ring_write(ring, val); /* reference */ 1184 amdgpu_ring_write(ring, mask); /* mask */ 1185 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1186 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1187 } 1188 1189 static void sdma_v6_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1190 uint32_t reg0, uint32_t reg1, 1191 uint32_t ref, uint32_t mask) 1192 { 1193 amdgpu_ring_emit_wreg(ring, reg0, ref); 1194 /* wait for a cycle to reset vm_inv_eng*_ack */ 1195 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1196 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1197 } 1198 1199 static struct amdgpu_sdma_ras sdma_v6_0_3_ras = { 1200 .ras_block = { 1201 .ras_late_init = amdgpu_ras_block_late_init, 1202 }, 1203 }; 1204 1205 static void sdma_v6_0_set_ras_funcs(struct amdgpu_device *adev) 1206 { 1207 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1208 case IP_VERSION(6, 0, 3): 1209 adev->sdma.ras = &sdma_v6_0_3_ras; 1210 break; 1211 default: 1212 break; 1213 } 1214 } 1215 1216 static int sdma_v6_0_early_init(void *handle) 1217 { 1218 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1219 int r; 1220 1221 r = amdgpu_sdma_init_microcode(adev, 0, true); 1222 if (r) 1223 return r; 1224 1225 sdma_v6_0_set_ring_funcs(adev); 1226 sdma_v6_0_set_buffer_funcs(adev); 1227 sdma_v6_0_set_vm_pte_funcs(adev); 1228 sdma_v6_0_set_irq_funcs(adev); 1229 sdma_v6_0_set_mqd_funcs(adev); 1230 sdma_v6_0_set_ras_funcs(adev); 1231 1232 return 0; 1233 } 1234 1235 static int sdma_v6_0_sw_init(void *handle) 1236 { 1237 struct amdgpu_ring *ring; 1238 int r, i; 1239 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1240 1241 /* SDMA trap event */ 1242 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1243 GFX_11_0_0__SRCID__SDMA_TRAP, 1244 &adev->sdma.trap_irq); 1245 if (r) 1246 return r; 1247 1248 for (i = 0; i < adev->sdma.num_instances; i++) { 1249 ring = &adev->sdma.instance[i].ring; 1250 ring->ring_obj = NULL; 1251 ring->use_doorbell = true; 1252 ring->me = i; 1253 1254 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1255 ring->use_doorbell?"true":"false"); 1256 1257 ring->doorbell_index = 1258 (adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset 1259 1260 ring->vm_hub = AMDGPU_GFXHUB(0); 1261 sprintf(ring->name, "sdma%d", i); 1262 r = amdgpu_ring_init(adev, ring, 1024, 1263 &adev->sdma.trap_irq, 1264 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1265 AMDGPU_RING_PRIO_DEFAULT, NULL); 1266 if (r) 1267 return r; 1268 } 1269 1270 if (amdgpu_sdma_ras_sw_init(adev)) { 1271 dev_err(adev->dev, "Failed to initialize sdma ras block!\n"); 1272 return -EINVAL; 1273 } 1274 1275 return r; 1276 } 1277 1278 static int sdma_v6_0_sw_fini(void *handle) 1279 { 1280 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1281 int i; 1282 1283 for (i = 0; i < adev->sdma.num_instances; i++) 1284 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1285 1286 amdgpu_sdma_destroy_inst_ctx(adev, true); 1287 1288 return 0; 1289 } 1290 1291 static int sdma_v6_0_hw_init(void *handle) 1292 { 1293 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1294 1295 return sdma_v6_0_start(adev); 1296 } 1297 1298 static int sdma_v6_0_hw_fini(void *handle) 1299 { 1300 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1301 1302 if (amdgpu_sriov_vf(adev)) 1303 return 0; 1304 1305 sdma_v6_0_ctxempty_int_enable(adev, false); 1306 sdma_v6_0_enable(adev, false); 1307 1308 return 0; 1309 } 1310 1311 static int sdma_v6_0_suspend(void *handle) 1312 { 1313 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1314 1315 return sdma_v6_0_hw_fini(adev); 1316 } 1317 1318 static int sdma_v6_0_resume(void *handle) 1319 { 1320 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1321 1322 return sdma_v6_0_hw_init(adev); 1323 } 1324 1325 static bool sdma_v6_0_is_idle(void *handle) 1326 { 1327 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1328 u32 i; 1329 1330 for (i = 0; i < adev->sdma.num_instances; i++) { 1331 u32 tmp = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG)); 1332 1333 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1334 return false; 1335 } 1336 1337 return true; 1338 } 1339 1340 static int sdma_v6_0_wait_for_idle(void *handle) 1341 { 1342 unsigned i; 1343 u32 sdma0, sdma1; 1344 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1345 1346 for (i = 0; i < adev->usec_timeout; i++) { 1347 sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG)); 1348 sdma1 = RREG32(sdma_v6_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG)); 1349 1350 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1351 return 0; 1352 udelay(1); 1353 } 1354 return -ETIMEDOUT; 1355 } 1356 1357 static int sdma_v6_0_ring_preempt_ib(struct amdgpu_ring *ring) 1358 { 1359 int i, r = 0; 1360 struct amdgpu_device *adev = ring->adev; 1361 u32 index = 0; 1362 u64 sdma_gfx_preempt; 1363 1364 amdgpu_sdma_get_index_from_ring(ring, &index); 1365 sdma_gfx_preempt = 1366 sdma_v6_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT); 1367 1368 /* assert preemption condition */ 1369 amdgpu_ring_set_preempt_cond_exec(ring, false); 1370 1371 /* emit the trailing fence */ 1372 ring->trail_seq += 1; 1373 amdgpu_ring_alloc(ring, 10); 1374 sdma_v6_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1375 ring->trail_seq, 0); 1376 amdgpu_ring_commit(ring); 1377 1378 /* assert IB preemption */ 1379 WREG32(sdma_gfx_preempt, 1); 1380 1381 /* poll the trailing fence */ 1382 for (i = 0; i < adev->usec_timeout; i++) { 1383 if (ring->trail_seq == 1384 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1385 break; 1386 udelay(1); 1387 } 1388 1389 if (i >= adev->usec_timeout) { 1390 r = -EINVAL; 1391 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1392 } 1393 1394 /* deassert IB preemption */ 1395 WREG32(sdma_gfx_preempt, 0); 1396 1397 /* deassert the preemption condition */ 1398 amdgpu_ring_set_preempt_cond_exec(ring, true); 1399 return r; 1400 } 1401 1402 static int sdma_v6_0_set_trap_irq_state(struct amdgpu_device *adev, 1403 struct amdgpu_irq_src *source, 1404 unsigned type, 1405 enum amdgpu_interrupt_state state) 1406 { 1407 u32 sdma_cntl; 1408 1409 u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL); 1410 1411 if (!amdgpu_sriov_vf(adev)) { 1412 sdma_cntl = RREG32(reg_offset); 1413 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1414 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1415 WREG32(reg_offset, sdma_cntl); 1416 } 1417 1418 return 0; 1419 } 1420 1421 static int sdma_v6_0_process_trap_irq(struct amdgpu_device *adev, 1422 struct amdgpu_irq_src *source, 1423 struct amdgpu_iv_entry *entry) 1424 { 1425 int instances, queue; 1426 uint32_t mes_queue_id = entry->src_data[0]; 1427 1428 DRM_DEBUG("IH: SDMA trap\n"); 1429 1430 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 1431 struct amdgpu_mes_queue *queue; 1432 1433 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 1434 1435 spin_lock(&adev->mes.queue_id_lock); 1436 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 1437 if (queue) { 1438 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); 1439 amdgpu_fence_process(queue->ring); 1440 } 1441 spin_unlock(&adev->mes.queue_id_lock); 1442 return 0; 1443 } 1444 1445 queue = entry->ring_id & 0xf; 1446 instances = (entry->ring_id & 0xf0) >> 4; 1447 if (instances > 1) { 1448 DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n"); 1449 return -EINVAL; 1450 } 1451 1452 switch (entry->client_id) { 1453 case SOC21_IH_CLIENTID_GFX: 1454 switch (queue) { 1455 case 0: 1456 amdgpu_fence_process(&adev->sdma.instance[instances].ring); 1457 break; 1458 default: 1459 break; 1460 } 1461 break; 1462 } 1463 return 0; 1464 } 1465 1466 static int sdma_v6_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1467 struct amdgpu_irq_src *source, 1468 struct amdgpu_iv_entry *entry) 1469 { 1470 return 0; 1471 } 1472 1473 static int sdma_v6_0_set_clockgating_state(void *handle, 1474 enum amd_clockgating_state state) 1475 { 1476 return 0; 1477 } 1478 1479 static int sdma_v6_0_set_powergating_state(void *handle, 1480 enum amd_powergating_state state) 1481 { 1482 return 0; 1483 } 1484 1485 static void sdma_v6_0_get_clockgating_state(void *handle, u64 *flags) 1486 { 1487 } 1488 1489 const struct amd_ip_funcs sdma_v6_0_ip_funcs = { 1490 .name = "sdma_v6_0", 1491 .early_init = sdma_v6_0_early_init, 1492 .late_init = NULL, 1493 .sw_init = sdma_v6_0_sw_init, 1494 .sw_fini = sdma_v6_0_sw_fini, 1495 .hw_init = sdma_v6_0_hw_init, 1496 .hw_fini = sdma_v6_0_hw_fini, 1497 .suspend = sdma_v6_0_suspend, 1498 .resume = sdma_v6_0_resume, 1499 .is_idle = sdma_v6_0_is_idle, 1500 .wait_for_idle = sdma_v6_0_wait_for_idle, 1501 .soft_reset = sdma_v6_0_soft_reset, 1502 .check_soft_reset = sdma_v6_0_check_soft_reset, 1503 .set_clockgating_state = sdma_v6_0_set_clockgating_state, 1504 .set_powergating_state = sdma_v6_0_set_powergating_state, 1505 .get_clockgating_state = sdma_v6_0_get_clockgating_state, 1506 }; 1507 1508 static const struct amdgpu_ring_funcs sdma_v6_0_ring_funcs = { 1509 .type = AMDGPU_RING_TYPE_SDMA, 1510 .align_mask = 0xf, 1511 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1512 .support_64bit_ptrs = true, 1513 .secure_submission_supported = true, 1514 .get_rptr = sdma_v6_0_ring_get_rptr, 1515 .get_wptr = sdma_v6_0_ring_get_wptr, 1516 .set_wptr = sdma_v6_0_ring_set_wptr, 1517 .emit_frame_size = 1518 5 + /* sdma_v6_0_ring_init_cond_exec */ 1519 6 + /* sdma_v6_0_ring_emit_hdp_flush */ 1520 6 + /* sdma_v6_0_ring_emit_pipeline_sync */ 1521 /* sdma_v6_0_ring_emit_vm_flush */ 1522 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1523 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1524 10 + 10 + 10, /* sdma_v6_0_ring_emit_fence x3 for user fence, vm fence */ 1525 .emit_ib_size = 5 + 7 + 6, /* sdma_v6_0_ring_emit_ib */ 1526 .emit_ib = sdma_v6_0_ring_emit_ib, 1527 .emit_mem_sync = sdma_v6_0_ring_emit_mem_sync, 1528 .emit_fence = sdma_v6_0_ring_emit_fence, 1529 .emit_pipeline_sync = sdma_v6_0_ring_emit_pipeline_sync, 1530 .emit_vm_flush = sdma_v6_0_ring_emit_vm_flush, 1531 .emit_hdp_flush = sdma_v6_0_ring_emit_hdp_flush, 1532 .test_ring = sdma_v6_0_ring_test_ring, 1533 .test_ib = sdma_v6_0_ring_test_ib, 1534 .insert_nop = sdma_v6_0_ring_insert_nop, 1535 .pad_ib = sdma_v6_0_ring_pad_ib, 1536 .emit_wreg = sdma_v6_0_ring_emit_wreg, 1537 .emit_reg_wait = sdma_v6_0_ring_emit_reg_wait, 1538 .emit_reg_write_reg_wait = sdma_v6_0_ring_emit_reg_write_reg_wait, 1539 .init_cond_exec = sdma_v6_0_ring_init_cond_exec, 1540 .preempt_ib = sdma_v6_0_ring_preempt_ib, 1541 }; 1542 1543 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev) 1544 { 1545 int i; 1546 1547 for (i = 0; i < adev->sdma.num_instances; i++) { 1548 adev->sdma.instance[i].ring.funcs = &sdma_v6_0_ring_funcs; 1549 adev->sdma.instance[i].ring.me = i; 1550 } 1551 } 1552 1553 static const struct amdgpu_irq_src_funcs sdma_v6_0_trap_irq_funcs = { 1554 .set = sdma_v6_0_set_trap_irq_state, 1555 .process = sdma_v6_0_process_trap_irq, 1556 }; 1557 1558 static const struct amdgpu_irq_src_funcs sdma_v6_0_illegal_inst_irq_funcs = { 1559 .process = sdma_v6_0_process_illegal_inst_irq, 1560 }; 1561 1562 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev) 1563 { 1564 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1565 adev->sdma.num_instances; 1566 adev->sdma.trap_irq.funcs = &sdma_v6_0_trap_irq_funcs; 1567 adev->sdma.illegal_inst_irq.funcs = &sdma_v6_0_illegal_inst_irq_funcs; 1568 } 1569 1570 /** 1571 * sdma_v6_0_emit_copy_buffer - copy buffer using the sDMA engine 1572 * 1573 * @ib: indirect buffer to fill with commands 1574 * @src_offset: src GPU address 1575 * @dst_offset: dst GPU address 1576 * @byte_count: number of bytes to xfer 1577 * @tmz: if a secure copy should be used 1578 * 1579 * Copy GPU buffers using the DMA engine. 1580 * Used by the amdgpu ttm implementation to move pages if 1581 * registered as the asic copy callback. 1582 */ 1583 static void sdma_v6_0_emit_copy_buffer(struct amdgpu_ib *ib, 1584 uint64_t src_offset, 1585 uint64_t dst_offset, 1586 uint32_t byte_count, 1587 bool tmz) 1588 { 1589 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1590 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1591 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 1592 ib->ptr[ib->length_dw++] = byte_count - 1; 1593 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1594 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1595 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1596 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1597 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1598 } 1599 1600 /** 1601 * sdma_v6_0_emit_fill_buffer - fill buffer using the sDMA engine 1602 * 1603 * @ib: indirect buffer to fill 1604 * @src_data: value to write to buffer 1605 * @dst_offset: dst GPU address 1606 * @byte_count: number of bytes to xfer 1607 * 1608 * Fill GPU buffers using the DMA engine. 1609 */ 1610 static void sdma_v6_0_emit_fill_buffer(struct amdgpu_ib *ib, 1611 uint32_t src_data, 1612 uint64_t dst_offset, 1613 uint32_t byte_count) 1614 { 1615 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_CONST_FILL); 1616 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1617 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1618 ib->ptr[ib->length_dw++] = src_data; 1619 ib->ptr[ib->length_dw++] = byte_count - 1; 1620 } 1621 1622 static const struct amdgpu_buffer_funcs sdma_v6_0_buffer_funcs = { 1623 .copy_max_bytes = 0x400000, 1624 .copy_num_dw = 7, 1625 .emit_copy_buffer = sdma_v6_0_emit_copy_buffer, 1626 1627 .fill_max_bytes = 0x400000, 1628 .fill_num_dw = 5, 1629 .emit_fill_buffer = sdma_v6_0_emit_fill_buffer, 1630 }; 1631 1632 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev) 1633 { 1634 adev->mman.buffer_funcs = &sdma_v6_0_buffer_funcs; 1635 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1636 } 1637 1638 static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = { 1639 .copy_pte_num_dw = 7, 1640 .copy_pte = sdma_v6_0_vm_copy_pte, 1641 .write_pte = sdma_v6_0_vm_write_pte, 1642 .set_pte_pde = sdma_v6_0_vm_set_pte_pde, 1643 }; 1644 1645 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1646 { 1647 unsigned i; 1648 1649 adev->vm_manager.vm_pte_funcs = &sdma_v6_0_vm_pte_funcs; 1650 for (i = 0; i < adev->sdma.num_instances; i++) { 1651 adev->vm_manager.vm_pte_scheds[i] = 1652 &adev->sdma.instance[i].ring.sched; 1653 } 1654 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1655 } 1656 1657 const struct amdgpu_ip_block_version sdma_v6_0_ip_block = { 1658 .type = AMD_IP_BLOCK_TYPE_SDMA, 1659 .major = 6, 1660 .minor = 0, 1661 .rev = 0, 1662 .funcs = &sdma_v6_0_ip_funcs, 1663 }; 1664