1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_11_0_0_offset.h" 34 #include "gc/gc_11_0_0_sh_mask.h" 35 #include "gc/gc_11_0_0_default.h" 36 #include "hdp/hdp_6_0_0_offset.h" 37 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 38 39 #include "soc15_common.h" 40 #include "soc15.h" 41 #include "sdma_v6_0_0_pkt_open.h" 42 #include "nbio_v4_3.h" 43 #include "sdma_common.h" 44 #include "sdma_v6_0.h" 45 #include "v11_structs.h" 46 #include "mes_userqueue.h" 47 48 MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin"); 49 MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin"); 50 MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin"); 51 MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin"); 52 MODULE_FIRMWARE("amdgpu/sdma_6_1_0.bin"); 53 MODULE_FIRMWARE("amdgpu/sdma_6_1_1.bin"); 54 MODULE_FIRMWARE("amdgpu/sdma_6_1_2.bin"); 55 MODULE_FIRMWARE("amdgpu/sdma_6_1_3.bin"); 56 57 #define SDMA1_REG_OFFSET 0x600 58 #define SDMA0_HYP_DEC_REG_START 0x5880 59 #define SDMA0_HYP_DEC_REG_END 0x589a 60 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 61 62 static const struct amdgpu_hwip_reg_entry sdma_reg_list_6_0[] = { 63 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS_REG), 64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS1_REG), 65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS2_REG), 66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS3_REG), 67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS4_REG), 68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS5_REG), 69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS6_REG), 70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UCODE_CHECKSUM), 71 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH_HI), 72 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH), 73 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_STATUS), 74 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_STATUS), 75 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK0), 76 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK1), 77 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK0), 78 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK1), 79 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_CNTL), 80 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR), 81 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR_HI), 82 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR), 83 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR_HI), 84 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_OFFSET), 85 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_LO), 86 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_HI), 87 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_CNTL), 88 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_RPTR), 89 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_SUB_REMAIN), 90 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_DUMMY_REG), 91 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE_STATUS0), 92 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_CNTL), 93 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR), 94 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR_HI), 95 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR), 96 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR_HI), 97 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_OFFSET), 98 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_LO), 99 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_HI), 100 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_RPTR), 101 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_SUB_REMAIN), 102 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_DUMMY_REG), 103 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_CNTL), 104 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR), 105 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR_HI), 106 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR), 107 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR_HI), 108 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_OFFSET), 109 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_LO), 110 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_HI), 111 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_RPTR), 112 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_SUB_REMAIN), 113 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_DUMMY_REG), 114 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_INT_STATUS), 115 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 116 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_CHICKEN_BITS), 117 }; 118 119 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev); 120 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev); 121 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev); 122 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev); 123 static int sdma_v6_0_start(struct amdgpu_device *adev); 124 125 static u32 sdma_v6_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 126 { 127 u32 base; 128 129 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 130 internal_offset <= SDMA0_HYP_DEC_REG_END) { 131 base = adev->reg_offset[GC_HWIP][0][1]; 132 if (instance != 0) 133 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance; 134 } else { 135 base = adev->reg_offset[GC_HWIP][0][0]; 136 if (instance == 1) 137 internal_offset += SDMA1_REG_OFFSET; 138 } 139 140 return base + internal_offset; 141 } 142 143 static unsigned sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring *ring, 144 uint64_t addr) 145 { 146 unsigned ret; 147 148 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE)); 149 amdgpu_ring_write(ring, lower_32_bits(addr)); 150 amdgpu_ring_write(ring, upper_32_bits(addr)); 151 amdgpu_ring_write(ring, 1); 152 /* this is the offset we need patch later */ 153 ret = ring->wptr & ring->buf_mask; 154 /* insert dummy here and patch it later */ 155 amdgpu_ring_write(ring, 0); 156 157 return ret; 158 } 159 160 /** 161 * sdma_v6_0_ring_get_rptr - get the current read pointer 162 * 163 * @ring: amdgpu ring pointer 164 * 165 * Get the current rptr from the hardware. 166 */ 167 static uint64_t sdma_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 168 { 169 u64 *rptr; 170 171 /* XXX check if swapping is necessary on BE */ 172 rptr = (u64 *)ring->rptr_cpu_addr; 173 174 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 175 return ((*rptr) >> 2); 176 } 177 178 /** 179 * sdma_v6_0_ring_get_wptr - get the current write pointer 180 * 181 * @ring: amdgpu ring pointer 182 * 183 * Get the current wptr from the hardware. 184 */ 185 static uint64_t sdma_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 186 { 187 u64 wptr = 0; 188 189 if (ring->use_doorbell) { 190 /* XXX check if swapping is necessary on BE */ 191 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 192 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 193 } 194 195 return wptr >> 2; 196 } 197 198 /** 199 * sdma_v6_0_ring_set_wptr - commit the write pointer 200 * 201 * @ring: amdgpu ring pointer 202 * 203 * Write the wptr back to the hardware. 204 */ 205 static void sdma_v6_0_ring_set_wptr(struct amdgpu_ring *ring) 206 { 207 struct amdgpu_device *adev = ring->adev; 208 209 if (ring->use_doorbell) { 210 DRM_DEBUG("Using doorbell -- " 211 "wptr_offs == 0x%08x " 212 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 213 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 214 ring->wptr_offs, 215 lower_32_bits(ring->wptr << 2), 216 upper_32_bits(ring->wptr << 2)); 217 /* XXX check if swapping is necessary on BE */ 218 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 219 ring->wptr << 2); 220 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 221 ring->doorbell_index, ring->wptr << 2); 222 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 223 } else { 224 DRM_DEBUG("Not using doorbell -- " 225 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 226 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 227 ring->me, 228 lower_32_bits(ring->wptr << 2), 229 ring->me, 230 upper_32_bits(ring->wptr << 2)); 231 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 232 ring->me, regSDMA0_QUEUE0_RB_WPTR), 233 lower_32_bits(ring->wptr << 2)); 234 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 235 ring->me, regSDMA0_QUEUE0_RB_WPTR_HI), 236 upper_32_bits(ring->wptr << 2)); 237 } 238 } 239 240 static void sdma_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 241 { 242 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 243 int i; 244 245 for (i = 0; i < count; i++) 246 if (sdma && sdma->burst_nop && (i == 0)) 247 amdgpu_ring_write(ring, ring->funcs->nop | 248 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 249 else 250 amdgpu_ring_write(ring, ring->funcs->nop); 251 } 252 253 /* 254 * sdma_v6_0_ring_emit_ib - Schedule an IB on the DMA engine 255 * 256 * @ring: amdgpu ring pointer 257 * @ib: IB object to schedule 258 * @flags: unused 259 * @job: job to retrieve vmid from 260 * 261 * Schedule an IB in the DMA ring. 262 */ 263 static void sdma_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 264 struct amdgpu_job *job, 265 struct amdgpu_ib *ib, 266 uint32_t flags) 267 { 268 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 269 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 270 271 /* An IB packet must end on a 8 DW boundary--the next dword 272 * must be on a 8-dword boundary. Our IB packet below is 6 273 * dwords long, thus add x number of NOPs, such that, in 274 * modular arithmetic, 275 * wptr + 6 + x = 8k, k >= 0, which in C is, 276 * (wptr + 6 + x) % 8 = 0. 277 * The expression below, is a solution of x. 278 */ 279 sdma_v6_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 280 281 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) | 282 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 283 /* base must be 32 byte aligned */ 284 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 285 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 286 amdgpu_ring_write(ring, ib->length_dw); 287 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 288 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 289 } 290 291 /** 292 * sdma_v6_0_ring_emit_mem_sync - flush the IB by graphics cache rinse 293 * 294 * @ring: amdgpu ring pointer 295 * 296 * flush the IB by graphics cache rinse. 297 */ 298 static void sdma_v6_0_ring_emit_mem_sync(struct amdgpu_ring *ring) 299 { 300 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV | 301 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 302 SDMA_GCR_GLI_INV(1); 303 304 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 305 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ)); 306 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 307 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 308 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 309 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 310 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 311 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 312 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 313 } 314 315 316 /** 317 * sdma_v6_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 318 * 319 * @ring: amdgpu ring pointer 320 * 321 * Emit an hdp flush packet on the requested DMA ring. 322 */ 323 static void sdma_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 324 { 325 struct amdgpu_device *adev = ring->adev; 326 u32 ref_and_mask = 0; 327 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 328 329 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 330 331 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 332 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 333 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 334 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 335 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 336 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 337 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 338 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 339 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 340 } 341 342 /** 343 * sdma_v6_0_ring_emit_fence - emit a fence on the DMA ring 344 * 345 * @ring: amdgpu ring pointer 346 * @addr: address 347 * @seq: fence seq number 348 * @flags: fence flags 349 * 350 * Add a DMA fence packet to the ring to write 351 * the fence seq number and DMA trap packet to generate 352 * an interrupt if needed. 353 */ 354 static void sdma_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 355 unsigned flags) 356 { 357 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 358 /* write the fence */ 359 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 360 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 361 /* zero in first two bits */ 362 BUG_ON(addr & 0x3); 363 amdgpu_ring_write(ring, lower_32_bits(addr)); 364 amdgpu_ring_write(ring, upper_32_bits(addr)); 365 amdgpu_ring_write(ring, lower_32_bits(seq)); 366 367 /* optionally write high bits as well */ 368 if (write64bit) { 369 addr += 4; 370 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 371 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 372 /* zero in first two bits */ 373 BUG_ON(addr & 0x3); 374 amdgpu_ring_write(ring, lower_32_bits(addr)); 375 amdgpu_ring_write(ring, upper_32_bits(addr)); 376 amdgpu_ring_write(ring, upper_32_bits(seq)); 377 } 378 379 if (flags & AMDGPU_FENCE_FLAG_INT) { 380 /* generate an interrupt */ 381 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP)); 382 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 383 } 384 } 385 386 /** 387 * sdma_v6_0_gfx_stop - stop the gfx async dma engines 388 * 389 * @adev: amdgpu_device pointer 390 * 391 * Stop the gfx async dma ring buffers. 392 */ 393 static void sdma_v6_0_gfx_stop(struct amdgpu_device *adev) 394 { 395 u32 rb_cntl, ib_cntl; 396 int i; 397 398 for (i = 0; i < adev->sdma.num_instances; i++) { 399 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 400 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0); 401 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 402 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 403 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0); 404 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 405 } 406 } 407 408 /** 409 * sdma_v6_0_rlc_stop - stop the compute async dma engines 410 * 411 * @adev: amdgpu_device pointer 412 * 413 * Stop the compute async dma queues. 414 */ 415 static void sdma_v6_0_rlc_stop(struct amdgpu_device *adev) 416 { 417 /* XXX todo */ 418 } 419 420 /** 421 * sdma_v6_0_ctxempty_int_enable - enable or disable context empty interrupts 422 * 423 * @adev: amdgpu_device pointer 424 * @enable: enable/disable context switching due to queue empty conditions 425 * 426 * Enable or disable the async dma engines queue empty context switch. 427 */ 428 static void sdma_v6_0_ctxempty_int_enable(struct amdgpu_device *adev, bool enable) 429 { 430 u32 f32_cntl; 431 int i; 432 433 if (!amdgpu_sriov_vf(adev)) { 434 for (i = 0; i < adev->sdma.num_instances; i++) { 435 f32_cntl = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL)); 436 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 437 CTXEMPTY_INT_ENABLE, enable ? 1 : 0); 438 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL), f32_cntl); 439 } 440 } 441 } 442 443 /** 444 * sdma_v6_0_enable - stop the async dma engines 445 * 446 * @adev: amdgpu_device pointer 447 * @enable: enable/disable the DMA MEs. 448 * 449 * Halt or unhalt the async dma engines. 450 */ 451 static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable) 452 { 453 u32 f32_cntl; 454 int i; 455 456 if (!enable) { 457 sdma_v6_0_gfx_stop(adev); 458 sdma_v6_0_rlc_stop(adev); 459 } 460 461 if (amdgpu_sriov_vf(adev)) 462 return; 463 464 for (i = 0; i < adev->sdma.num_instances; i++) { 465 f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 466 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 467 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl); 468 } 469 } 470 471 /** 472 * sdma_v6_0_gfx_resume_instance - start/restart a certain sdma engine 473 * 474 * @adev: amdgpu_device pointer 475 * @i: instance 476 * @restore: used to restore wptr when restart 477 * 478 * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr. 479 * Return 0 for success. 480 */ 481 static int sdma_v6_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore) 482 { 483 struct amdgpu_ring *ring; 484 u32 rb_cntl, ib_cntl; 485 u32 rb_bufsz; 486 u32 doorbell; 487 u32 doorbell_offset; 488 u32 temp; 489 u64 wptr_gpu_addr; 490 491 ring = &adev->sdma.instance[i].ring; 492 if (!amdgpu_sriov_vf(adev)) 493 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 494 495 /* Set ring buffer size in dwords */ 496 rb_bufsz = order_base_2(ring->ring_size / 4); 497 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 498 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); 499 #ifdef __BIG_ENDIAN 500 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1); 501 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, 502 RPTR_WRITEBACK_SWAP_ENABLE, 1); 503 #endif 504 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1); 505 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 506 507 /* Initialize the ring buffer's read and write pointers */ 508 if (restore) { 509 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2)); 510 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2)); 511 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2)); 512 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); 513 } else { 514 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0); 515 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0); 516 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0); 517 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0); 518 } 519 /* setup the wptr shadow polling */ 520 wptr_gpu_addr = ring->wptr_gpu_addr; 521 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO), 522 lower_32_bits(wptr_gpu_addr)); 523 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI), 524 upper_32_bits(wptr_gpu_addr)); 525 526 /* set the wb address whether it's enabled or not */ 527 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI), 528 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 529 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO), 530 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 531 532 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 533 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0); 534 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1); 535 536 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8); 537 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40); 538 539 if (!restore) 540 ring->wptr = 0; 541 542 /* before programing wptr to a less value, need set minor_ptr_update first */ 543 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1); 544 545 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 546 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2); 547 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 548 } 549 550 doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL)); 551 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET)); 552 553 if (ring->use_doorbell) { 554 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 555 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET, 556 OFFSET, ring->doorbell_index); 557 } else { 558 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0); 559 } 560 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell); 561 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset); 562 563 if (i == 0) 564 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 565 ring->doorbell_index, 566 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances); 567 568 if (amdgpu_sriov_vf(adev)) 569 sdma_v6_0_ring_set_wptr(ring); 570 571 /* set minor_ptr_update to 0 after wptr programed */ 572 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0); 573 574 /* Set up sdma hang watchdog */ 575 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL)); 576 /* 100ms per unit */ 577 temp = REG_SET_FIELD(temp, SDMA0_WATCHDOG_CNTL, QUEUE_HANG_COUNT, 578 max(adev->usec_timeout/100000, 1)); 579 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), temp); 580 581 /* Set up RESP_MODE to non-copy addresses */ 582 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL)); 583 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 584 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 585 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp); 586 587 /* program default cache read and write policy */ 588 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE)); 589 /* clean read policy and write policy bits */ 590 temp &= 0xFF0FFF; 591 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | 592 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | 593 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK); 594 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp); 595 596 if (!amdgpu_sriov_vf(adev)) { 597 /* unhalt engine */ 598 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 599 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 600 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0); 601 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp); 602 } 603 604 /* enable DMA RB */ 605 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1); 606 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 607 608 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 609 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1); 610 #ifdef __BIG_ENDIAN 611 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1); 612 #endif 613 /* enable DMA IBs */ 614 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 615 616 if (amdgpu_sriov_vf(adev)) 617 sdma_v6_0_enable(adev, true); 618 619 return amdgpu_ring_test_helper(ring); 620 } 621 622 /** 623 * sdma_v6_0_gfx_resume - setup and start the async dma engines 624 * 625 * @adev: amdgpu_device pointer 626 * 627 * Set up the gfx DMA ring buffers and enable them. 628 * Returns 0 for success, error for failure. 629 */ 630 static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev) 631 { 632 int i, r; 633 634 for (i = 0; i < adev->sdma.num_instances; i++) { 635 r = sdma_v6_0_gfx_resume_instance(adev, i, false); 636 if (r) 637 return r; 638 } 639 640 return 0; 641 } 642 643 /** 644 * sdma_v6_0_rlc_resume - setup and start the async dma engines 645 * 646 * @adev: amdgpu_device pointer 647 * 648 * Set up the compute DMA queues and enable them. 649 * Returns 0 for success, error for failure. 650 */ 651 static int sdma_v6_0_rlc_resume(struct amdgpu_device *adev) 652 { 653 return 0; 654 } 655 656 /** 657 * sdma_v6_0_load_microcode - load the sDMA ME ucode 658 * 659 * @adev: amdgpu_device pointer 660 * 661 * Loads the sDMA0/1 ucode. 662 * Returns 0 for success, -EINVAL if the ucode is not available. 663 */ 664 static int sdma_v6_0_load_microcode(struct amdgpu_device *adev) 665 { 666 const struct sdma_firmware_header_v2_0 *hdr; 667 const __le32 *fw_data; 668 u32 fw_size; 669 int i, j; 670 bool use_broadcast; 671 672 /* halt the MEs */ 673 sdma_v6_0_enable(adev, false); 674 675 if (!adev->sdma.instance[0].fw) 676 return -EINVAL; 677 678 /* use broadcast mode to load SDMA microcode by default */ 679 use_broadcast = true; 680 681 if (use_broadcast) { 682 dev_info(adev->dev, "Use broadcast method to load SDMA firmware\n"); 683 /* load Control Thread microcode */ 684 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data; 685 amdgpu_ucode_print_sdma_hdr(&hdr->header); 686 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4; 687 688 fw_data = (const __le32 *) 689 (adev->sdma.instance[0].fw->data + 690 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 691 692 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0); 693 694 for (j = 0; j < fw_size; j++) { 695 if (amdgpu_emu_mode == 1 && j % 500 == 0) 696 msleep(1); 697 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++)); 698 } 699 700 /* load Context Switch microcode */ 701 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4; 702 703 fw_data = (const __le32 *) 704 (adev->sdma.instance[0].fw->data + 705 le32_to_cpu(hdr->ctl_ucode_offset)); 706 707 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0x8000); 708 709 for (j = 0; j < fw_size; j++) { 710 if (amdgpu_emu_mode == 1 && j % 500 == 0) 711 msleep(1); 712 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++)); 713 } 714 } else { 715 dev_info(adev->dev, "Use legacy method to load SDMA firmware\n"); 716 for (i = 0; i < adev->sdma.num_instances; i++) { 717 /* load Control Thread microcode */ 718 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data; 719 amdgpu_ucode_print_sdma_hdr(&hdr->header); 720 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4; 721 722 fw_data = (const __le32 *) 723 (adev->sdma.instance[0].fw->data + 724 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 725 726 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0); 727 728 for (j = 0; j < fw_size; j++) { 729 if (amdgpu_emu_mode == 1 && j % 500 == 0) 730 msleep(1); 731 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 732 } 733 734 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version); 735 736 /* load Context Switch microcode */ 737 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4; 738 739 fw_data = (const __le32 *) 740 (adev->sdma.instance[0].fw->data + 741 le32_to_cpu(hdr->ctl_ucode_offset)); 742 743 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0x8000); 744 745 for (j = 0; j < fw_size; j++) { 746 if (amdgpu_emu_mode == 1 && j % 500 == 0) 747 msleep(1); 748 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 749 } 750 751 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version); 752 } 753 } 754 755 return 0; 756 } 757 758 static int sdma_v6_0_soft_reset(struct amdgpu_ip_block *ip_block) 759 { 760 struct amdgpu_device *adev = ip_block->adev; 761 u32 tmp; 762 int i; 763 764 sdma_v6_0_gfx_stop(adev); 765 766 for (i = 0; i < adev->sdma.num_instances; i++) { 767 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE)); 768 tmp |= SDMA0_FREEZE__FREEZE_MASK; 769 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp); 770 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 771 tmp |= SDMA0_F32_CNTL__HALT_MASK; 772 tmp |= SDMA0_F32_CNTL__TH1_RESET_MASK; 773 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp); 774 775 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0); 776 777 udelay(100); 778 779 tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i; 780 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); 781 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 782 783 udelay(100); 784 785 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0); 786 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 787 788 udelay(100); 789 } 790 791 return sdma_v6_0_start(adev); 792 } 793 794 static bool sdma_v6_0_check_soft_reset(struct amdgpu_ip_block *ip_block) 795 { 796 struct amdgpu_device *adev = ip_block->adev; 797 struct amdgpu_ring *ring; 798 int i, r; 799 long tmo = msecs_to_jiffies(1000); 800 801 for (i = 0; i < adev->sdma.num_instances; i++) { 802 ring = &adev->sdma.instance[i].ring; 803 r = amdgpu_ring_test_ib(ring, tmo); 804 if (r) 805 return true; 806 } 807 808 return false; 809 } 810 811 /** 812 * sdma_v6_0_start - setup and start the async dma engines 813 * 814 * @adev: amdgpu_device pointer 815 * 816 * Set up the DMA engines and enable them. 817 * Returns 0 for success, error for failure. 818 */ 819 static int sdma_v6_0_start(struct amdgpu_device *adev) 820 { 821 int r = 0; 822 823 if (amdgpu_sriov_vf(adev)) { 824 sdma_v6_0_enable(adev, false); 825 826 /* set RB registers */ 827 r = sdma_v6_0_gfx_resume(adev); 828 return r; 829 } 830 831 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 832 r = sdma_v6_0_load_microcode(adev); 833 if (r) 834 return r; 835 836 /* The value of regSDMA_F32_CNTL is invalid the moment after loading fw */ 837 if (amdgpu_emu_mode == 1) 838 msleep(1000); 839 } 840 841 /* unhalt the MEs */ 842 sdma_v6_0_enable(adev, true); 843 /* enable sdma ring preemption */ 844 sdma_v6_0_ctxempty_int_enable(adev, true); 845 846 /* start the gfx rings and rlc compute queues */ 847 r = sdma_v6_0_gfx_resume(adev); 848 if (r) 849 return r; 850 r = sdma_v6_0_rlc_resume(adev); 851 852 return r; 853 } 854 855 static int sdma_v6_0_mqd_init(struct amdgpu_device *adev, void *mqd, 856 struct amdgpu_mqd_prop *prop) 857 { 858 struct v11_sdma_mqd *m = mqd; 859 uint64_t wb_gpu_addr; 860 861 m->sdmax_rlcx_rb_cntl = 862 order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT | 863 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 864 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | 865 1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT; 866 867 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8); 868 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); 869 870 wb_gpu_addr = prop->wptr_gpu_addr; 871 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); 872 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); 873 874 wb_gpu_addr = prop->rptr_gpu_addr; 875 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); 876 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); 877 878 m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 0, 879 regSDMA0_QUEUE0_IB_CNTL)); 880 881 m->sdmax_rlcx_doorbell_offset = 882 prop->doorbell_index << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 883 884 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 885 886 m->sdmax_rlcx_skip_cntl = 0; 887 m->sdmax_rlcx_context_status = 0; 888 m->sdmax_rlcx_doorbell_log = 0; 889 890 m->sdmax_rlcx_rb_aql_cntl = regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT; 891 m->sdmax_rlcx_dummy_reg = regSDMA0_QUEUE0_DUMMY_REG_DEFAULT; 892 893 m->sdmax_rlcx_csa_addr_lo = lower_32_bits(prop->csa_addr); 894 m->sdmax_rlcx_csa_addr_hi = upper_32_bits(prop->csa_addr); 895 896 return 0; 897 } 898 899 static void sdma_v6_0_set_mqd_funcs(struct amdgpu_device *adev) 900 { 901 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v11_sdma_mqd); 902 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v6_0_mqd_init; 903 } 904 905 /** 906 * sdma_v6_0_ring_test_ring - simple async dma engine test 907 * 908 * @ring: amdgpu_ring structure holding ring information 909 * 910 * Test the DMA engine by writing using it to write an 911 * value to memory. 912 * Returns 0 for success, error for failure. 913 */ 914 static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring) 915 { 916 struct amdgpu_device *adev = ring->adev; 917 unsigned i; 918 unsigned index; 919 int r; 920 u32 tmp; 921 u64 gpu_addr; 922 923 tmp = 0xCAFEDEAD; 924 925 r = amdgpu_device_wb_get(adev, &index); 926 if (r) { 927 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 928 return r; 929 } 930 931 gpu_addr = adev->wb.gpu_addr + (index * 4); 932 adev->wb.wb[index] = cpu_to_le32(tmp); 933 934 r = amdgpu_ring_alloc(ring, 5); 935 if (r) { 936 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 937 amdgpu_device_wb_free(adev, index); 938 return r; 939 } 940 941 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 942 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 943 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 944 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 945 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 946 amdgpu_ring_write(ring, 0xDEADBEEF); 947 amdgpu_ring_commit(ring); 948 949 for (i = 0; i < adev->usec_timeout; i++) { 950 tmp = le32_to_cpu(adev->wb.wb[index]); 951 if (tmp == 0xDEADBEEF) 952 break; 953 if (amdgpu_emu_mode == 1) 954 msleep(1); 955 else 956 udelay(1); 957 } 958 959 if (i >= adev->usec_timeout) 960 r = -ETIMEDOUT; 961 962 amdgpu_device_wb_free(adev, index); 963 964 return r; 965 } 966 967 /* 968 * sdma_v6_0_ring_test_ib - test an IB on the DMA engine 969 * 970 * @ring: amdgpu_ring structure holding ring information 971 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 972 * 973 * Test a simple IB in the DMA ring. 974 * Returns 0 on success, error on failure. 975 */ 976 static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 977 { 978 struct amdgpu_device *adev = ring->adev; 979 struct amdgpu_ib ib; 980 struct dma_fence *f = NULL; 981 unsigned index; 982 long r; 983 u32 tmp = 0; 984 u64 gpu_addr; 985 986 tmp = 0xCAFEDEAD; 987 memset(&ib, 0, sizeof(ib)); 988 989 r = amdgpu_device_wb_get(adev, &index); 990 if (r) { 991 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 992 return r; 993 } 994 995 gpu_addr = adev->wb.gpu_addr + (index * 4); 996 adev->wb.wb[index] = cpu_to_le32(tmp); 997 998 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 999 if (r) { 1000 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 1001 goto err0; 1002 } 1003 1004 ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 1005 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1006 ib.ptr[1] = lower_32_bits(gpu_addr); 1007 ib.ptr[2] = upper_32_bits(gpu_addr); 1008 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1009 ib.ptr[4] = 0xDEADBEEF; 1010 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1011 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1012 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1013 ib.length_dw = 8; 1014 1015 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1016 if (r) 1017 goto err1; 1018 1019 r = dma_fence_wait_timeout(f, false, timeout); 1020 if (r == 0) { 1021 DRM_ERROR("amdgpu: IB test timed out\n"); 1022 r = -ETIMEDOUT; 1023 goto err1; 1024 } else if (r < 0) { 1025 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1026 goto err1; 1027 } 1028 1029 tmp = le32_to_cpu(adev->wb.wb[index]); 1030 1031 if (tmp == 0xDEADBEEF) 1032 r = 0; 1033 else 1034 r = -EINVAL; 1035 1036 err1: 1037 amdgpu_ib_free(&ib, NULL); 1038 dma_fence_put(f); 1039 err0: 1040 amdgpu_device_wb_free(adev, index); 1041 return r; 1042 } 1043 1044 1045 /** 1046 * sdma_v6_0_vm_copy_pte - update PTEs by copying them from the GART 1047 * 1048 * @ib: indirect buffer to fill with commands 1049 * @pe: addr of the page entry 1050 * @src: src addr to copy from 1051 * @count: number of page entries to update 1052 * 1053 * Update PTEs by copying them from the GART using sDMA. 1054 */ 1055 static void sdma_v6_0_vm_copy_pte(struct amdgpu_ib *ib, 1056 uint64_t pe, uint64_t src, 1057 unsigned count) 1058 { 1059 unsigned bytes = count * 8; 1060 1061 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1062 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1063 ib->ptr[ib->length_dw++] = bytes - 1; 1064 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1065 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1066 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1067 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1068 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1069 1070 } 1071 1072 /** 1073 * sdma_v6_0_vm_write_pte - update PTEs by writing them manually 1074 * 1075 * @ib: indirect buffer to fill with commands 1076 * @pe: addr of the page entry 1077 * @value: dst addr to write into pe 1078 * @count: number of page entries to update 1079 * @incr: increase next addr by incr bytes 1080 * 1081 * Update PTEs by writing them manually using sDMA. 1082 */ 1083 static void sdma_v6_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1084 uint64_t value, unsigned count, 1085 uint32_t incr) 1086 { 1087 unsigned ndw = count * 2; 1088 1089 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 1090 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1091 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1092 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1093 ib->ptr[ib->length_dw++] = ndw - 1; 1094 for (; ndw > 0; ndw -= 2) { 1095 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1096 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1097 value += incr; 1098 } 1099 } 1100 1101 /** 1102 * sdma_v6_0_vm_set_pte_pde - update the page tables using sDMA 1103 * 1104 * @ib: indirect buffer to fill with commands 1105 * @pe: addr of the page entry 1106 * @addr: dst addr to write into pe 1107 * @count: number of page entries to update 1108 * @incr: increase next addr by incr bytes 1109 * @flags: access flags 1110 * 1111 * Update the page tables using sDMA. 1112 */ 1113 static void sdma_v6_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1114 uint64_t pe, 1115 uint64_t addr, unsigned count, 1116 uint32_t incr, uint64_t flags) 1117 { 1118 /* for physically contiguous pages (vram) */ 1119 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE); 1120 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1121 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1122 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1123 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1124 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1125 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1126 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1127 ib->ptr[ib->length_dw++] = 0; 1128 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1129 } 1130 1131 /* 1132 * sdma_v6_0_ring_pad_ib - pad the IB 1133 * @ib: indirect buffer to fill with padding 1134 * @ring: amdgpu ring pointer 1135 * 1136 * Pad the IB with NOPs to a boundary multiple of 8. 1137 */ 1138 static void sdma_v6_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1139 { 1140 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1141 u32 pad_count; 1142 int i; 1143 1144 pad_count = (-ib->length_dw) & 0x7; 1145 for (i = 0; i < pad_count; i++) 1146 if (sdma && sdma->burst_nop && (i == 0)) 1147 ib->ptr[ib->length_dw++] = 1148 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) | 1149 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1150 else 1151 ib->ptr[ib->length_dw++] = 1152 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP); 1153 } 1154 1155 /** 1156 * sdma_v6_0_ring_emit_pipeline_sync - sync the pipeline 1157 * 1158 * @ring: amdgpu_ring pointer 1159 * 1160 * Make sure all previous operations are completed (CIK). 1161 */ 1162 static void sdma_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1163 { 1164 uint32_t seq = ring->fence_drv.sync_seq; 1165 uint64_t addr = ring->fence_drv.gpu_addr; 1166 1167 /* wait for idle */ 1168 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1169 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1170 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1171 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1172 amdgpu_ring_write(ring, addr & 0xfffffffc); 1173 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1174 amdgpu_ring_write(ring, seq); /* reference */ 1175 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1176 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1177 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1178 } 1179 1180 /* 1181 * sdma_v6_0_ring_emit_vm_flush - vm flush using sDMA 1182 * 1183 * @ring: amdgpu_ring pointer 1184 * @vmid: vmid number to use 1185 * @pd_addr: address 1186 * 1187 * Update the page table base and flush the VM TLB 1188 * using sDMA. 1189 */ 1190 static void sdma_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1191 unsigned vmid, uint64_t pd_addr) 1192 { 1193 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1194 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 1195 1196 /* Update the PD address for this VMID. */ 1197 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 1198 (hub->ctx_addr_distance * vmid), 1199 lower_32_bits(pd_addr)); 1200 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 1201 (hub->ctx_addr_distance * vmid), 1202 upper_32_bits(pd_addr)); 1203 1204 /* Trigger invalidation. */ 1205 amdgpu_ring_write(ring, 1206 SDMA_PKT_VM_INVALIDATION_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1207 SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(SDMA_SUBOP_VM_INVALIDATION) | 1208 SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(ring->vm_inv_eng) | 1209 SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(0x1f)); 1210 amdgpu_ring_write(ring, req); 1211 amdgpu_ring_write(ring, 0xFFFFFFFF); 1212 amdgpu_ring_write(ring, 1213 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(1 << vmid) | 1214 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(0x1F)); 1215 } 1216 1217 static void sdma_v6_0_ring_emit_wreg(struct amdgpu_ring *ring, 1218 uint32_t reg, uint32_t val) 1219 { 1220 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1221 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1222 amdgpu_ring_write(ring, reg); 1223 amdgpu_ring_write(ring, val); 1224 } 1225 1226 static void sdma_v6_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1227 uint32_t val, uint32_t mask) 1228 { 1229 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1230 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1231 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1232 amdgpu_ring_write(ring, reg << 2); 1233 amdgpu_ring_write(ring, 0); 1234 amdgpu_ring_write(ring, val); /* reference */ 1235 amdgpu_ring_write(ring, mask); /* mask */ 1236 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1237 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1238 } 1239 1240 static void sdma_v6_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1241 uint32_t reg0, uint32_t reg1, 1242 uint32_t ref, uint32_t mask) 1243 { 1244 amdgpu_ring_emit_wreg(ring, reg0, ref); 1245 /* wait for a cycle to reset vm_inv_eng*_ack */ 1246 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1247 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1248 } 1249 1250 static struct amdgpu_sdma_ras sdma_v6_0_3_ras = { 1251 .ras_block = { 1252 .ras_late_init = amdgpu_ras_block_late_init, 1253 }, 1254 }; 1255 1256 static void sdma_v6_0_set_ras_funcs(struct amdgpu_device *adev) 1257 { 1258 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1259 case IP_VERSION(6, 0, 3): 1260 adev->sdma.ras = &sdma_v6_0_3_ras; 1261 break; 1262 default: 1263 break; 1264 } 1265 } 1266 1267 static int sdma_v6_0_early_init(struct amdgpu_ip_block *ip_block) 1268 { 1269 struct amdgpu_device *adev = ip_block->adev; 1270 int r; 1271 1272 switch (amdgpu_user_queue) { 1273 case -1: 1274 case 0: 1275 default: 1276 adev->sdma.no_user_submission = false; 1277 adev->sdma.disable_uq = true; 1278 break; 1279 case 1: 1280 adev->sdma.no_user_submission = false; 1281 adev->sdma.disable_uq = false; 1282 break; 1283 case 2: 1284 adev->sdma.no_user_submission = true; 1285 adev->sdma.disable_uq = false; 1286 break; 1287 } 1288 1289 r = amdgpu_sdma_init_microcode(adev, 0, true); 1290 if (r) 1291 return r; 1292 1293 sdma_v6_0_set_ring_funcs(adev); 1294 sdma_v6_0_set_buffer_funcs(adev); 1295 sdma_v6_0_set_vm_pte_funcs(adev); 1296 sdma_v6_0_set_irq_funcs(adev); 1297 sdma_v6_0_set_mqd_funcs(adev); 1298 sdma_v6_0_set_ras_funcs(adev); 1299 1300 return 0; 1301 } 1302 1303 static int sdma_v6_0_sw_init(struct amdgpu_ip_block *ip_block) 1304 { 1305 struct amdgpu_ring *ring; 1306 int r, i; 1307 struct amdgpu_device *adev = ip_block->adev; 1308 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0); 1309 uint32_t *ptr; 1310 1311 /* SDMA trap event */ 1312 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1313 GFX_11_0_0__SRCID__SDMA_TRAP, 1314 &adev->sdma.trap_irq); 1315 if (r) 1316 return r; 1317 1318 for (i = 0; i < adev->sdma.num_instances; i++) { 1319 ring = &adev->sdma.instance[i].ring; 1320 ring->ring_obj = NULL; 1321 ring->use_doorbell = true; 1322 ring->me = i; 1323 ring->no_user_submission = adev->sdma.no_user_submission; 1324 1325 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1326 ring->use_doorbell?"true":"false"); 1327 1328 ring->doorbell_index = 1329 (adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset 1330 1331 ring->vm_hub = AMDGPU_GFXHUB(0); 1332 sprintf(ring->name, "sdma%d", i); 1333 r = amdgpu_ring_init(adev, ring, 1024, 1334 &adev->sdma.trap_irq, 1335 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1336 AMDGPU_RING_PRIO_DEFAULT, NULL); 1337 if (r) 1338 return r; 1339 } 1340 1341 adev->sdma.supported_reset = 1342 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); 1343 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1344 case IP_VERSION(6, 0, 0): 1345 case IP_VERSION(6, 0, 2): 1346 case IP_VERSION(6, 0, 3): 1347 if (adev->sdma.instance[0].fw_version >= 21) 1348 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1349 break; 1350 default: 1351 break; 1352 } 1353 1354 if (amdgpu_sdma_ras_sw_init(adev)) { 1355 dev_err(adev->dev, "Failed to initialize sdma ras block!\n"); 1356 return -EINVAL; 1357 } 1358 1359 /* Allocate memory for SDMA IP Dump buffer */ 1360 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); 1361 if (ptr) 1362 adev->sdma.ip_dump = ptr; 1363 else 1364 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n"); 1365 1366 /* add firmware version checks here */ 1367 if (0 && !adev->sdma.disable_uq) 1368 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1369 1370 r = amdgpu_sdma_sysfs_reset_mask_init(adev); 1371 if (r) 1372 return r; 1373 1374 return r; 1375 } 1376 1377 static int sdma_v6_0_sw_fini(struct amdgpu_ip_block *ip_block) 1378 { 1379 struct amdgpu_device *adev = ip_block->adev; 1380 int i; 1381 1382 for (i = 0; i < adev->sdma.num_instances; i++) 1383 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1384 1385 amdgpu_sdma_sysfs_reset_mask_fini(adev); 1386 amdgpu_sdma_destroy_inst_ctx(adev, true); 1387 1388 kfree(adev->sdma.ip_dump); 1389 1390 return 0; 1391 } 1392 1393 static int sdma_v6_0_set_userq_trap_interrupts(struct amdgpu_device *adev, 1394 bool enable) 1395 { 1396 unsigned int irq_type; 1397 int i, r; 1398 1399 if (adev->userq_funcs[AMDGPU_HW_IP_DMA]) { 1400 for (i = 0; i < adev->sdma.num_instances; i++) { 1401 irq_type = AMDGPU_SDMA_IRQ_INSTANCE0 + i; 1402 if (enable) 1403 r = amdgpu_irq_get(adev, &adev->sdma.trap_irq, 1404 irq_type); 1405 else 1406 r = amdgpu_irq_put(adev, &adev->sdma.trap_irq, 1407 irq_type); 1408 if (r) 1409 return r; 1410 } 1411 } 1412 1413 return 0; 1414 } 1415 1416 static int sdma_v6_0_hw_init(struct amdgpu_ip_block *ip_block) 1417 { 1418 struct amdgpu_device *adev = ip_block->adev; 1419 int r; 1420 1421 r = sdma_v6_0_start(adev); 1422 if (r) 1423 return r; 1424 1425 return sdma_v6_0_set_userq_trap_interrupts(adev, true); 1426 } 1427 1428 static int sdma_v6_0_hw_fini(struct amdgpu_ip_block *ip_block) 1429 { 1430 struct amdgpu_device *adev = ip_block->adev; 1431 1432 if (amdgpu_sriov_vf(adev)) 1433 return 0; 1434 1435 sdma_v6_0_ctxempty_int_enable(adev, false); 1436 sdma_v6_0_enable(adev, false); 1437 sdma_v6_0_set_userq_trap_interrupts(adev, false); 1438 1439 return 0; 1440 } 1441 1442 static int sdma_v6_0_suspend(struct amdgpu_ip_block *ip_block) 1443 { 1444 return sdma_v6_0_hw_fini(ip_block); 1445 } 1446 1447 static int sdma_v6_0_resume(struct amdgpu_ip_block *ip_block) 1448 { 1449 return sdma_v6_0_hw_init(ip_block); 1450 } 1451 1452 static bool sdma_v6_0_is_idle(struct amdgpu_ip_block *ip_block) 1453 { 1454 struct amdgpu_device *adev = ip_block->adev; 1455 u32 i; 1456 1457 for (i = 0; i < adev->sdma.num_instances; i++) { 1458 u32 tmp = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG)); 1459 1460 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1461 return false; 1462 } 1463 1464 return true; 1465 } 1466 1467 static int sdma_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1468 { 1469 unsigned i; 1470 u32 sdma0, sdma1; 1471 struct amdgpu_device *adev = ip_block->adev; 1472 1473 for (i = 0; i < adev->usec_timeout; i++) { 1474 sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG)); 1475 sdma1 = RREG32(sdma_v6_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG)); 1476 1477 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1478 return 0; 1479 udelay(1); 1480 } 1481 return -ETIMEDOUT; 1482 } 1483 1484 static int sdma_v6_0_ring_preempt_ib(struct amdgpu_ring *ring) 1485 { 1486 int i, r = 0; 1487 struct amdgpu_device *adev = ring->adev; 1488 u32 index = 0; 1489 u64 sdma_gfx_preempt; 1490 1491 amdgpu_sdma_get_index_from_ring(ring, &index); 1492 sdma_gfx_preempt = 1493 sdma_v6_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT); 1494 1495 /* assert preemption condition */ 1496 amdgpu_ring_set_preempt_cond_exec(ring, false); 1497 1498 /* emit the trailing fence */ 1499 ring->trail_seq += 1; 1500 amdgpu_ring_alloc(ring, 10); 1501 sdma_v6_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1502 ring->trail_seq, 0); 1503 amdgpu_ring_commit(ring); 1504 1505 /* assert IB preemption */ 1506 WREG32(sdma_gfx_preempt, 1); 1507 1508 /* poll the trailing fence */ 1509 for (i = 0; i < adev->usec_timeout; i++) { 1510 if (ring->trail_seq == 1511 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1512 break; 1513 udelay(1); 1514 } 1515 1516 if (i >= adev->usec_timeout) { 1517 r = -EINVAL; 1518 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1519 } 1520 1521 /* deassert IB preemption */ 1522 WREG32(sdma_gfx_preempt, 0); 1523 1524 /* deassert the preemption condition */ 1525 amdgpu_ring_set_preempt_cond_exec(ring, true); 1526 return r; 1527 } 1528 1529 static int sdma_v6_0_reset_queue(struct amdgpu_ring *ring, unsigned int vmid) 1530 { 1531 struct amdgpu_device *adev = ring->adev; 1532 int i, r; 1533 1534 if (amdgpu_sriov_vf(adev)) 1535 return -EINVAL; 1536 1537 for (i = 0; i < adev->sdma.num_instances; i++) { 1538 if (ring == &adev->sdma.instance[i].ring) 1539 break; 1540 } 1541 1542 if (i == adev->sdma.num_instances) { 1543 DRM_ERROR("sdma instance not found\n"); 1544 return -EINVAL; 1545 } 1546 1547 r = amdgpu_mes_reset_legacy_queue(adev, ring, vmid, true); 1548 if (r) 1549 return r; 1550 1551 return sdma_v6_0_gfx_resume_instance(adev, i, true); 1552 } 1553 1554 static int sdma_v6_0_set_trap_irq_state(struct amdgpu_device *adev, 1555 struct amdgpu_irq_src *source, 1556 unsigned type, 1557 enum amdgpu_interrupt_state state) 1558 { 1559 u32 sdma_cntl; 1560 1561 u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL); 1562 1563 if (!amdgpu_sriov_vf(adev)) { 1564 sdma_cntl = RREG32(reg_offset); 1565 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1566 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1567 WREG32(reg_offset, sdma_cntl); 1568 } 1569 1570 return 0; 1571 } 1572 1573 static int sdma_v6_0_process_trap_irq(struct amdgpu_device *adev, 1574 struct amdgpu_irq_src *source, 1575 struct amdgpu_iv_entry *entry) 1576 { 1577 int instances, queue; 1578 uint32_t mes_queue_id = entry->src_data[0]; 1579 1580 DRM_DEBUG("IH: SDMA trap\n"); 1581 1582 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 1583 struct amdgpu_mes_queue *queue; 1584 1585 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 1586 1587 spin_lock(&adev->mes.queue_id_lock); 1588 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 1589 if (queue) { 1590 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); 1591 amdgpu_fence_process(queue->ring); 1592 } 1593 spin_unlock(&adev->mes.queue_id_lock); 1594 return 0; 1595 } 1596 1597 queue = entry->ring_id & 0xf; 1598 instances = (entry->ring_id & 0xf0) >> 4; 1599 if (instances > 1) { 1600 DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n"); 1601 return -EINVAL; 1602 } 1603 1604 switch (entry->client_id) { 1605 case SOC21_IH_CLIENTID_GFX: 1606 switch (queue) { 1607 case 0: 1608 amdgpu_fence_process(&adev->sdma.instance[instances].ring); 1609 break; 1610 default: 1611 break; 1612 } 1613 break; 1614 } 1615 return 0; 1616 } 1617 1618 static int sdma_v6_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1619 struct amdgpu_irq_src *source, 1620 struct amdgpu_iv_entry *entry) 1621 { 1622 return 0; 1623 } 1624 1625 static int sdma_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1626 enum amd_clockgating_state state) 1627 { 1628 return 0; 1629 } 1630 1631 static int sdma_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 1632 enum amd_powergating_state state) 1633 { 1634 return 0; 1635 } 1636 1637 static void sdma_v6_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1638 { 1639 } 1640 1641 static void sdma_v6_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 1642 { 1643 struct amdgpu_device *adev = ip_block->adev; 1644 int i, j; 1645 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0); 1646 uint32_t instance_offset; 1647 1648 if (!adev->sdma.ip_dump) 1649 return; 1650 1651 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances); 1652 for (i = 0; i < adev->sdma.num_instances; i++) { 1653 instance_offset = i * reg_count; 1654 drm_printf(p, "\nInstance:%d\n", i); 1655 1656 for (j = 0; j < reg_count; j++) 1657 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_6_0[j].reg_name, 1658 adev->sdma.ip_dump[instance_offset + j]); 1659 } 1660 } 1661 1662 static void sdma_v6_0_dump_ip_state(struct amdgpu_ip_block *ip_block) 1663 { 1664 struct amdgpu_device *adev = ip_block->adev; 1665 int i, j; 1666 uint32_t instance_offset; 1667 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0); 1668 1669 if (!adev->sdma.ip_dump) 1670 return; 1671 1672 amdgpu_gfx_off_ctrl(adev, false); 1673 for (i = 0; i < adev->sdma.num_instances; i++) { 1674 instance_offset = i * reg_count; 1675 for (j = 0; j < reg_count; j++) 1676 adev->sdma.ip_dump[instance_offset + j] = 1677 RREG32(sdma_v6_0_get_reg_offset(adev, i, 1678 sdma_reg_list_6_0[j].reg_offset)); 1679 } 1680 amdgpu_gfx_off_ctrl(adev, true); 1681 } 1682 1683 const struct amd_ip_funcs sdma_v6_0_ip_funcs = { 1684 .name = "sdma_v6_0", 1685 .early_init = sdma_v6_0_early_init, 1686 .sw_init = sdma_v6_0_sw_init, 1687 .sw_fini = sdma_v6_0_sw_fini, 1688 .hw_init = sdma_v6_0_hw_init, 1689 .hw_fini = sdma_v6_0_hw_fini, 1690 .suspend = sdma_v6_0_suspend, 1691 .resume = sdma_v6_0_resume, 1692 .is_idle = sdma_v6_0_is_idle, 1693 .wait_for_idle = sdma_v6_0_wait_for_idle, 1694 .soft_reset = sdma_v6_0_soft_reset, 1695 .check_soft_reset = sdma_v6_0_check_soft_reset, 1696 .set_clockgating_state = sdma_v6_0_set_clockgating_state, 1697 .set_powergating_state = sdma_v6_0_set_powergating_state, 1698 .get_clockgating_state = sdma_v6_0_get_clockgating_state, 1699 .dump_ip_state = sdma_v6_0_dump_ip_state, 1700 .print_ip_state = sdma_v6_0_print_ip_state, 1701 }; 1702 1703 static const struct amdgpu_ring_funcs sdma_v6_0_ring_funcs = { 1704 .type = AMDGPU_RING_TYPE_SDMA, 1705 .align_mask = 0xf, 1706 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1707 .support_64bit_ptrs = true, 1708 .secure_submission_supported = true, 1709 .get_rptr = sdma_v6_0_ring_get_rptr, 1710 .get_wptr = sdma_v6_0_ring_get_wptr, 1711 .set_wptr = sdma_v6_0_ring_set_wptr, 1712 .emit_frame_size = 1713 5 + /* sdma_v6_0_ring_init_cond_exec */ 1714 6 + /* sdma_v6_0_ring_emit_hdp_flush */ 1715 6 + /* sdma_v6_0_ring_emit_pipeline_sync */ 1716 /* sdma_v6_0_ring_emit_vm_flush */ 1717 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1718 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1719 10 + 10 + 10, /* sdma_v6_0_ring_emit_fence x3 for user fence, vm fence */ 1720 .emit_ib_size = 5 + 7 + 6, /* sdma_v6_0_ring_emit_ib */ 1721 .emit_ib = sdma_v6_0_ring_emit_ib, 1722 .emit_mem_sync = sdma_v6_0_ring_emit_mem_sync, 1723 .emit_fence = sdma_v6_0_ring_emit_fence, 1724 .emit_pipeline_sync = sdma_v6_0_ring_emit_pipeline_sync, 1725 .emit_vm_flush = sdma_v6_0_ring_emit_vm_flush, 1726 .emit_hdp_flush = sdma_v6_0_ring_emit_hdp_flush, 1727 .test_ring = sdma_v6_0_ring_test_ring, 1728 .test_ib = sdma_v6_0_ring_test_ib, 1729 .insert_nop = sdma_v6_0_ring_insert_nop, 1730 .pad_ib = sdma_v6_0_ring_pad_ib, 1731 .emit_wreg = sdma_v6_0_ring_emit_wreg, 1732 .emit_reg_wait = sdma_v6_0_ring_emit_reg_wait, 1733 .emit_reg_write_reg_wait = sdma_v6_0_ring_emit_reg_write_reg_wait, 1734 .init_cond_exec = sdma_v6_0_ring_init_cond_exec, 1735 .preempt_ib = sdma_v6_0_ring_preempt_ib, 1736 .reset = sdma_v6_0_reset_queue, 1737 }; 1738 1739 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev) 1740 { 1741 int i; 1742 1743 for (i = 0; i < adev->sdma.num_instances; i++) { 1744 adev->sdma.instance[i].ring.funcs = &sdma_v6_0_ring_funcs; 1745 adev->sdma.instance[i].ring.me = i; 1746 } 1747 } 1748 1749 static const struct amdgpu_irq_src_funcs sdma_v6_0_trap_irq_funcs = { 1750 .set = sdma_v6_0_set_trap_irq_state, 1751 .process = sdma_v6_0_process_trap_irq, 1752 }; 1753 1754 static const struct amdgpu_irq_src_funcs sdma_v6_0_illegal_inst_irq_funcs = { 1755 .process = sdma_v6_0_process_illegal_inst_irq, 1756 }; 1757 1758 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev) 1759 { 1760 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1761 adev->sdma.num_instances; 1762 adev->sdma.trap_irq.funcs = &sdma_v6_0_trap_irq_funcs; 1763 adev->sdma.illegal_inst_irq.funcs = &sdma_v6_0_illegal_inst_irq_funcs; 1764 } 1765 1766 /** 1767 * sdma_v6_0_emit_copy_buffer - copy buffer using the sDMA engine 1768 * 1769 * @ib: indirect buffer to fill with commands 1770 * @src_offset: src GPU address 1771 * @dst_offset: dst GPU address 1772 * @byte_count: number of bytes to xfer 1773 * @copy_flags: copy flags for the buffers 1774 * 1775 * Copy GPU buffers using the DMA engine. 1776 * Used by the amdgpu ttm implementation to move pages if 1777 * registered as the asic copy callback. 1778 */ 1779 static void sdma_v6_0_emit_copy_buffer(struct amdgpu_ib *ib, 1780 uint64_t src_offset, 1781 uint64_t dst_offset, 1782 uint32_t byte_count, 1783 uint32_t copy_flags) 1784 { 1785 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1786 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1787 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0); 1788 ib->ptr[ib->length_dw++] = byte_count - 1; 1789 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1790 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1791 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1792 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1793 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1794 } 1795 1796 /** 1797 * sdma_v6_0_emit_fill_buffer - fill buffer using the sDMA engine 1798 * 1799 * @ib: indirect buffer to fill 1800 * @src_data: value to write to buffer 1801 * @dst_offset: dst GPU address 1802 * @byte_count: number of bytes to xfer 1803 * 1804 * Fill GPU buffers using the DMA engine. 1805 */ 1806 static void sdma_v6_0_emit_fill_buffer(struct amdgpu_ib *ib, 1807 uint32_t src_data, 1808 uint64_t dst_offset, 1809 uint32_t byte_count) 1810 { 1811 ib->ptr[ib->length_dw++] = SDMA_PKT_CONSTANT_FILL_HEADER_OP(SDMA_OP_CONST_FILL); 1812 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1813 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1814 ib->ptr[ib->length_dw++] = src_data; 1815 ib->ptr[ib->length_dw++] = byte_count - 1; 1816 } 1817 1818 static const struct amdgpu_buffer_funcs sdma_v6_0_buffer_funcs = { 1819 .copy_max_bytes = 0x400000, 1820 .copy_num_dw = 7, 1821 .emit_copy_buffer = sdma_v6_0_emit_copy_buffer, 1822 1823 .fill_max_bytes = 0x400000, 1824 .fill_num_dw = 5, 1825 .emit_fill_buffer = sdma_v6_0_emit_fill_buffer, 1826 }; 1827 1828 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev) 1829 { 1830 adev->mman.buffer_funcs = &sdma_v6_0_buffer_funcs; 1831 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1832 } 1833 1834 static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = { 1835 .copy_pte_num_dw = 7, 1836 .copy_pte = sdma_v6_0_vm_copy_pte, 1837 .write_pte = sdma_v6_0_vm_write_pte, 1838 .set_pte_pde = sdma_v6_0_vm_set_pte_pde, 1839 }; 1840 1841 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1842 { 1843 unsigned i; 1844 1845 adev->vm_manager.vm_pte_funcs = &sdma_v6_0_vm_pte_funcs; 1846 for (i = 0; i < adev->sdma.num_instances; i++) { 1847 adev->vm_manager.vm_pte_scheds[i] = 1848 &adev->sdma.instance[i].ring.sched; 1849 } 1850 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1851 } 1852 1853 const struct amdgpu_ip_block_version sdma_v6_0_ip_block = { 1854 .type = AMD_IP_BLOCK_TYPE_SDMA, 1855 .major = 6, 1856 .minor = 0, 1857 .rev = 0, 1858 .funcs = &sdma_v6_0_ip_funcs, 1859 }; 1860