1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_11_0_0_offset.h" 34 #include "gc/gc_11_0_0_sh_mask.h" 35 #include "gc/gc_11_0_0_default.h" 36 #include "hdp/hdp_6_0_0_offset.h" 37 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 38 39 #include "soc15_common.h" 40 #include "soc15.h" 41 #include "sdma_v6_0_0_pkt_open.h" 42 #include "nbio_v4_3.h" 43 #include "sdma_common.h" 44 #include "sdma_v6_0.h" 45 #include "v11_structs.h" 46 #include "mes_userqueue.h" 47 #include "amdgpu_userq_fence.h" 48 49 MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin"); 50 MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin"); 51 MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin"); 52 MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin"); 53 MODULE_FIRMWARE("amdgpu/sdma_6_1_0.bin"); 54 MODULE_FIRMWARE("amdgpu/sdma_6_1_1.bin"); 55 MODULE_FIRMWARE("amdgpu/sdma_6_1_2.bin"); 56 MODULE_FIRMWARE("amdgpu/sdma_6_1_3.bin"); 57 MODULE_FIRMWARE("amdgpu/sdma_6_1_4.bin"); 58 MODULE_FIRMWARE("amdgpu/sdma_6_4_0.bin"); 59 60 #define SDMA1_REG_OFFSET 0x600 61 #define SDMA0_HYP_DEC_REG_START 0x5880 62 #define SDMA0_HYP_DEC_REG_END 0x589a 63 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 64 65 static const struct amdgpu_hwip_reg_entry sdma_reg_list_6_0[] = { 66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS_REG), 67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS1_REG), 68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS2_REG), 69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS3_REG), 70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS4_REG), 71 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS5_REG), 72 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS6_REG), 73 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UCODE_CHECKSUM), 74 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH_HI), 75 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH), 76 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_STATUS), 77 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_STATUS), 78 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK0), 79 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK1), 80 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK0), 81 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK1), 82 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_CNTL), 83 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR), 84 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR_HI), 85 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR), 86 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR_HI), 87 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_OFFSET), 88 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_LO), 89 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_HI), 90 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_CNTL), 91 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_RPTR), 92 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_SUB_REMAIN), 93 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_DUMMY_REG), 94 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE_STATUS0), 95 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_CNTL), 96 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR), 97 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR_HI), 98 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR), 99 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR_HI), 100 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_OFFSET), 101 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_LO), 102 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_HI), 103 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_RPTR), 104 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_SUB_REMAIN), 105 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_DUMMY_REG), 106 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_CNTL), 107 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR), 108 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR_HI), 109 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR), 110 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR_HI), 111 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_OFFSET), 112 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_LO), 113 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_HI), 114 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_RPTR), 115 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_SUB_REMAIN), 116 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_DUMMY_REG), 117 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_INT_STATUS), 118 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 119 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_CHICKEN_BITS), 120 }; 121 122 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev); 123 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev); 124 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev); 125 static int sdma_v6_0_start(struct amdgpu_device *adev); 126 127 static u32 sdma_v6_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 128 { 129 u32 base; 130 131 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 132 internal_offset <= SDMA0_HYP_DEC_REG_END) { 133 base = adev->reg_offset[GC_HWIP][0][1]; 134 if (instance != 0) 135 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance; 136 } else { 137 base = adev->reg_offset[GC_HWIP][0][0]; 138 if (instance == 1) 139 internal_offset += SDMA1_REG_OFFSET; 140 } 141 142 return base + internal_offset; 143 } 144 145 static unsigned sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring *ring, 146 uint64_t addr) 147 { 148 unsigned ret; 149 150 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE)); 151 amdgpu_ring_write(ring, lower_32_bits(addr)); 152 amdgpu_ring_write(ring, upper_32_bits(addr)); 153 amdgpu_ring_write(ring, 1); 154 /* this is the offset we need patch later */ 155 ret = ring->wptr & ring->buf_mask; 156 /* insert dummy here and patch it later */ 157 amdgpu_ring_write(ring, 0); 158 159 return ret; 160 } 161 162 /** 163 * sdma_v6_0_ring_get_rptr - get the current read pointer 164 * 165 * @ring: amdgpu ring pointer 166 * 167 * Get the current rptr from the hardware. 168 */ 169 static uint64_t sdma_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 170 { 171 u64 *rptr; 172 173 /* XXX check if swapping is necessary on BE */ 174 rptr = (u64 *)ring->rptr_cpu_addr; 175 176 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 177 return ((*rptr) >> 2); 178 } 179 180 /** 181 * sdma_v6_0_ring_get_wptr - get the current write pointer 182 * 183 * @ring: amdgpu ring pointer 184 * 185 * Get the current wptr from the hardware. 186 */ 187 static uint64_t sdma_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 188 { 189 u64 wptr = 0; 190 191 if (ring->use_doorbell) { 192 /* XXX check if swapping is necessary on BE */ 193 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 194 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 195 } 196 197 return wptr >> 2; 198 } 199 200 /** 201 * sdma_v6_0_ring_set_wptr - commit the write pointer 202 * 203 * @ring: amdgpu ring pointer 204 * 205 * Write the wptr back to the hardware. 206 */ 207 static void sdma_v6_0_ring_set_wptr(struct amdgpu_ring *ring) 208 { 209 struct amdgpu_device *adev = ring->adev; 210 211 if (ring->use_doorbell) { 212 DRM_DEBUG("Using doorbell -- " 213 "wptr_offs == 0x%08x " 214 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 215 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 216 ring->wptr_offs, 217 lower_32_bits(ring->wptr << 2), 218 upper_32_bits(ring->wptr << 2)); 219 /* XXX check if swapping is necessary on BE */ 220 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 221 ring->wptr << 2); 222 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 223 ring->doorbell_index, ring->wptr << 2); 224 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 225 } else { 226 DRM_DEBUG("Not using doorbell -- " 227 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 228 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 229 ring->me, 230 lower_32_bits(ring->wptr << 2), 231 ring->me, 232 upper_32_bits(ring->wptr << 2)); 233 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 234 ring->me, regSDMA0_QUEUE0_RB_WPTR), 235 lower_32_bits(ring->wptr << 2)); 236 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 237 ring->me, regSDMA0_QUEUE0_RB_WPTR_HI), 238 upper_32_bits(ring->wptr << 2)); 239 } 240 } 241 242 static void sdma_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 243 { 244 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 245 int i; 246 247 for (i = 0; i < count; i++) 248 if (sdma && sdma->burst_nop && (i == 0)) 249 amdgpu_ring_write(ring, ring->funcs->nop | 250 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 251 else 252 amdgpu_ring_write(ring, ring->funcs->nop); 253 } 254 255 /* 256 * sdma_v6_0_ring_emit_ib - Schedule an IB on the DMA engine 257 * 258 * @ring: amdgpu ring pointer 259 * @ib: IB object to schedule 260 * @flags: unused 261 * @job: job to retrieve vmid from 262 * 263 * Schedule an IB in the DMA ring. 264 */ 265 static void sdma_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 266 struct amdgpu_job *job, 267 struct amdgpu_ib *ib, 268 uint32_t flags) 269 { 270 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 271 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 272 273 /* An IB packet must end on a 8 DW boundary--the next dword 274 * must be on a 8-dword boundary. Our IB packet below is 6 275 * dwords long, thus add x number of NOPs, such that, in 276 * modular arithmetic, 277 * wptr + 6 + x = 8k, k >= 0, which in C is, 278 * (wptr + 6 + x) % 8 = 0. 279 * The expression below, is a solution of x. 280 */ 281 sdma_v6_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 282 283 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) | 284 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 285 /* base must be 32 byte aligned */ 286 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 287 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 288 amdgpu_ring_write(ring, ib->length_dw); 289 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 290 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 291 } 292 293 /** 294 * sdma_v6_0_ring_emit_mem_sync - flush the IB by graphics cache rinse 295 * 296 * @ring: amdgpu ring pointer 297 * 298 * flush the IB by graphics cache rinse. 299 */ 300 static void sdma_v6_0_ring_emit_mem_sync(struct amdgpu_ring *ring) 301 { 302 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV | 303 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 304 SDMA_GCR_GLI_INV(1); 305 306 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 307 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ)); 308 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 309 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 310 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 311 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 312 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 313 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 314 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 315 } 316 317 318 /** 319 * sdma_v6_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 320 * 321 * @ring: amdgpu ring pointer 322 * 323 * Emit an hdp flush packet on the requested DMA ring. 324 */ 325 static void sdma_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 326 { 327 struct amdgpu_device *adev = ring->adev; 328 u32 ref_and_mask = 0; 329 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 330 331 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 332 333 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 334 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 335 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 336 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 337 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 338 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 339 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 340 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 341 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 342 } 343 344 /** 345 * sdma_v6_0_ring_emit_fence - emit a fence on the DMA ring 346 * 347 * @ring: amdgpu ring pointer 348 * @addr: address 349 * @seq: fence seq number 350 * @flags: fence flags 351 * 352 * Add a DMA fence packet to the ring to write 353 * the fence seq number and DMA trap packet to generate 354 * an interrupt if needed. 355 */ 356 static void sdma_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 357 unsigned flags) 358 { 359 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 360 /* write the fence */ 361 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 362 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 363 /* zero in first two bits */ 364 WARN_ON(addr & 0x3); 365 amdgpu_ring_write(ring, lower_32_bits(addr)); 366 amdgpu_ring_write(ring, upper_32_bits(addr)); 367 amdgpu_ring_write(ring, lower_32_bits(seq)); 368 369 /* optionally write high bits as well */ 370 if (write64bit) { 371 addr += 4; 372 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 373 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 374 /* zero in first two bits */ 375 WARN_ON(addr & 0x3); 376 amdgpu_ring_write(ring, lower_32_bits(addr)); 377 amdgpu_ring_write(ring, upper_32_bits(addr)); 378 amdgpu_ring_write(ring, upper_32_bits(seq)); 379 } 380 381 if (flags & AMDGPU_FENCE_FLAG_INT) { 382 /* generate an interrupt */ 383 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP)); 384 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 385 } 386 } 387 388 /** 389 * sdma_v6_0_gfx_stop - stop the gfx async dma engines 390 * 391 * @adev: amdgpu_device pointer 392 * 393 * Stop the gfx async dma ring buffers. 394 */ 395 static void sdma_v6_0_gfx_stop(struct amdgpu_device *adev) 396 { 397 u32 rb_cntl, ib_cntl; 398 int i; 399 400 for (i = 0; i < adev->sdma.num_instances; i++) { 401 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 402 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0); 403 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 404 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 405 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0); 406 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 407 } 408 } 409 410 /** 411 * sdma_v6_0_rlc_stop - stop the compute async dma engines 412 * 413 * @adev: amdgpu_device pointer 414 * 415 * Stop the compute async dma queues. 416 */ 417 static void sdma_v6_0_rlc_stop(struct amdgpu_device *adev) 418 { 419 /* XXX todo */ 420 } 421 422 /** 423 * sdma_v6_0_ctxempty_int_enable - enable or disable context empty interrupts 424 * 425 * @adev: amdgpu_device pointer 426 * @enable: enable/disable context switching due to queue empty conditions 427 * 428 * Enable or disable the async dma engines queue empty context switch. 429 */ 430 static void sdma_v6_0_ctxempty_int_enable(struct amdgpu_device *adev, bool enable) 431 { 432 u32 f32_cntl; 433 int i; 434 435 if (!amdgpu_sriov_vf(adev)) { 436 for (i = 0; i < adev->sdma.num_instances; i++) { 437 f32_cntl = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL)); 438 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 439 CTXEMPTY_INT_ENABLE, enable ? 1 : 0); 440 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL), f32_cntl); 441 } 442 } 443 } 444 445 /** 446 * sdma_v6_0_enable - stop the async dma engines 447 * 448 * @adev: amdgpu_device pointer 449 * @enable: enable/disable the DMA MEs. 450 * 451 * Halt or unhalt the async dma engines. 452 */ 453 static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable) 454 { 455 u32 f32_cntl; 456 int i; 457 458 if (!enable) { 459 sdma_v6_0_gfx_stop(adev); 460 sdma_v6_0_rlc_stop(adev); 461 } 462 463 if (amdgpu_sriov_vf(adev)) 464 return; 465 466 for (i = 0; i < adev->sdma.num_instances; i++) { 467 f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 468 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 469 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl); 470 } 471 } 472 473 /** 474 * sdma_v6_0_gfx_resume_instance - start/restart a certain sdma engine 475 * 476 * @adev: amdgpu_device pointer 477 * @i: instance 478 * @restore: used to restore wptr when restart 479 * 480 * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr. 481 * Return 0 for success. 482 */ 483 static int sdma_v6_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore) 484 { 485 struct amdgpu_ring *ring; 486 u32 rb_cntl, ib_cntl; 487 u32 rb_bufsz; 488 u32 doorbell; 489 u32 doorbell_offset; 490 u32 temp; 491 u64 wptr_gpu_addr; 492 493 ring = &adev->sdma.instance[i].ring; 494 if (!amdgpu_sriov_vf(adev)) 495 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 496 497 /* Set ring buffer size in dwords */ 498 rb_bufsz = order_base_2(ring->ring_size / 4); 499 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 500 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); 501 #ifdef __BIG_ENDIAN 502 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1); 503 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, 504 RPTR_WRITEBACK_SWAP_ENABLE, 1); 505 #endif 506 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1); 507 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 508 509 /* Initialize the ring buffer's read and write pointers */ 510 if (restore) { 511 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2)); 512 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2)); 513 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2)); 514 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); 515 } else { 516 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0); 517 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0); 518 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0); 519 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0); 520 } 521 /* setup the wptr shadow polling */ 522 wptr_gpu_addr = ring->wptr_gpu_addr; 523 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO), 524 lower_32_bits(wptr_gpu_addr)); 525 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI), 526 upper_32_bits(wptr_gpu_addr)); 527 528 /* set the wb address whether it's enabled or not */ 529 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI), 530 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 531 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO), 532 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 533 534 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 535 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0); 536 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1); 537 538 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8); 539 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40); 540 541 if (!restore) 542 ring->wptr = 0; 543 544 /* before programing wptr to a less value, need set minor_ptr_update first */ 545 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1); 546 547 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 548 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2); 549 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 550 } 551 552 doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL)); 553 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET)); 554 555 if (ring->use_doorbell) { 556 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 557 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET, 558 OFFSET, ring->doorbell_index); 559 } else { 560 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0); 561 } 562 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell); 563 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset); 564 565 if (i == 0) 566 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 567 ring->doorbell_index, 568 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances); 569 570 if (amdgpu_sriov_vf(adev)) 571 sdma_v6_0_ring_set_wptr(ring); 572 573 /* set minor_ptr_update to 0 after wptr programed */ 574 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0); 575 576 /* Set up sdma hang watchdog */ 577 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL)); 578 /* 100ms per unit */ 579 temp = REG_SET_FIELD(temp, SDMA0_WATCHDOG_CNTL, QUEUE_HANG_COUNT, 580 max(adev->usec_timeout/100000, 1)); 581 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), temp); 582 583 /* Set up RESP_MODE to non-copy addresses */ 584 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL)); 585 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 586 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 587 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp); 588 589 /* program default cache read and write policy */ 590 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE)); 591 /* clean read policy and write policy bits */ 592 temp &= 0xFF0FFF; 593 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | 594 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | 595 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK); 596 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp); 597 598 if (!amdgpu_sriov_vf(adev)) { 599 /* unhalt engine */ 600 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 601 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 602 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0); 603 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp); 604 } 605 606 /* enable DMA RB */ 607 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1); 608 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 609 610 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 611 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1); 612 #ifdef __BIG_ENDIAN 613 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1); 614 #endif 615 /* enable DMA IBs */ 616 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 617 618 if (amdgpu_sriov_vf(adev)) 619 sdma_v6_0_enable(adev, true); 620 621 return amdgpu_ring_test_helper(ring); 622 } 623 624 /** 625 * sdma_v6_0_gfx_resume - setup and start the async dma engines 626 * 627 * @adev: amdgpu_device pointer 628 * 629 * Set up the gfx DMA ring buffers and enable them. 630 * Returns 0 for success, error for failure. 631 */ 632 static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev) 633 { 634 int i, r; 635 636 for (i = 0; i < adev->sdma.num_instances; i++) { 637 r = sdma_v6_0_gfx_resume_instance(adev, i, false); 638 if (r) 639 return r; 640 } 641 642 return 0; 643 } 644 645 /** 646 * sdma_v6_0_rlc_resume - setup and start the async dma engines 647 * 648 * @adev: amdgpu_device pointer 649 * 650 * Set up the compute DMA queues and enable them. 651 * Returns 0 for success, error for failure. 652 */ 653 static int sdma_v6_0_rlc_resume(struct amdgpu_device *adev) 654 { 655 return 0; 656 } 657 658 /** 659 * sdma_v6_0_load_microcode - load the sDMA ME ucode 660 * 661 * @adev: amdgpu_device pointer 662 * 663 * Loads the sDMA0/1 ucode. 664 * Returns 0 for success, -EINVAL if the ucode is not available. 665 */ 666 static int sdma_v6_0_load_microcode(struct amdgpu_device *adev) 667 { 668 const struct sdma_firmware_header_v2_0 *hdr; 669 const __le32 *fw_data; 670 u32 fw_size; 671 int i, j; 672 bool use_broadcast; 673 674 /* halt the MEs */ 675 sdma_v6_0_enable(adev, false); 676 677 if (!adev->sdma.instance[0].fw) 678 return -EINVAL; 679 680 /* use broadcast mode to load SDMA microcode by default */ 681 use_broadcast = true; 682 683 if (use_broadcast) { 684 dev_info(adev->dev, "Use broadcast method to load SDMA firmware\n"); 685 /* load Control Thread microcode */ 686 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data; 687 amdgpu_ucode_print_sdma_hdr(&hdr->header); 688 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4; 689 690 fw_data = (const __le32 *) 691 (adev->sdma.instance[0].fw->data + 692 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 693 694 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0); 695 696 for (j = 0; j < fw_size; j++) { 697 if (amdgpu_emu_mode == 1 && j % 500 == 0) 698 msleep(1); 699 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++)); 700 } 701 702 /* load Context Switch microcode */ 703 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4; 704 705 fw_data = (const __le32 *) 706 (adev->sdma.instance[0].fw->data + 707 le32_to_cpu(hdr->ctl_ucode_offset)); 708 709 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0x8000); 710 711 for (j = 0; j < fw_size; j++) { 712 if (amdgpu_emu_mode == 1 && j % 500 == 0) 713 msleep(1); 714 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++)); 715 } 716 } else { 717 dev_info(adev->dev, "Use legacy method to load SDMA firmware\n"); 718 for (i = 0; i < adev->sdma.num_instances; i++) { 719 /* load Control Thread microcode */ 720 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data; 721 amdgpu_ucode_print_sdma_hdr(&hdr->header); 722 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4; 723 724 fw_data = (const __le32 *) 725 (adev->sdma.instance[0].fw->data + 726 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 727 728 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0); 729 730 for (j = 0; j < fw_size; j++) { 731 if (amdgpu_emu_mode == 1 && j % 500 == 0) 732 msleep(1); 733 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 734 } 735 736 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version); 737 738 /* load Context Switch microcode */ 739 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4; 740 741 fw_data = (const __le32 *) 742 (adev->sdma.instance[0].fw->data + 743 le32_to_cpu(hdr->ctl_ucode_offset)); 744 745 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0x8000); 746 747 for (j = 0; j < fw_size; j++) { 748 if (amdgpu_emu_mode == 1 && j % 500 == 0) 749 msleep(1); 750 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 751 } 752 753 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version); 754 } 755 } 756 757 return 0; 758 } 759 760 static int sdma_v6_0_soft_reset(struct amdgpu_ip_block *ip_block) 761 { 762 struct amdgpu_device *adev = ip_block->adev; 763 u32 tmp; 764 int i; 765 766 sdma_v6_0_gfx_stop(adev); 767 768 for (i = 0; i < adev->sdma.num_instances; i++) { 769 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE)); 770 tmp |= SDMA0_FREEZE__FREEZE_MASK; 771 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp); 772 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 773 tmp |= SDMA0_F32_CNTL__HALT_MASK; 774 tmp |= SDMA0_F32_CNTL__TH1_RESET_MASK; 775 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp); 776 777 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0); 778 779 udelay(100); 780 781 tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i; 782 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); 783 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 784 785 udelay(100); 786 787 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0); 788 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 789 790 udelay(100); 791 } 792 793 return sdma_v6_0_start(adev); 794 } 795 796 /** 797 * sdma_v6_0_start - setup and start the async dma engines 798 * 799 * @adev: amdgpu_device pointer 800 * 801 * Set up the DMA engines and enable them. 802 * Returns 0 for success, error for failure. 803 */ 804 static int sdma_v6_0_start(struct amdgpu_device *adev) 805 { 806 int r = 0; 807 808 if (amdgpu_sriov_vf(adev)) { 809 sdma_v6_0_enable(adev, false); 810 811 /* set RB registers */ 812 r = sdma_v6_0_gfx_resume(adev); 813 return r; 814 } 815 816 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 817 r = sdma_v6_0_load_microcode(adev); 818 if (r) 819 return r; 820 821 /* The value of regSDMA_F32_CNTL is invalid the moment after loading fw */ 822 if (amdgpu_emu_mode == 1) 823 msleep(1000); 824 } 825 826 /* unhalt the MEs */ 827 sdma_v6_0_enable(adev, true); 828 /* enable sdma ring preemption */ 829 sdma_v6_0_ctxempty_int_enable(adev, true); 830 831 /* start the gfx rings and rlc compute queues */ 832 r = sdma_v6_0_gfx_resume(adev); 833 if (r) 834 return r; 835 r = sdma_v6_0_rlc_resume(adev); 836 837 return r; 838 } 839 840 static int sdma_v6_0_mqd_init(struct amdgpu_device *adev, void *mqd, 841 struct amdgpu_mqd_prop *prop) 842 { 843 struct v11_sdma_mqd *m = mqd; 844 uint64_t wb_gpu_addr; 845 846 m->sdmax_rlcx_rb_cntl = 847 order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT | 848 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 849 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | 850 1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT; 851 852 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8); 853 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); 854 855 wb_gpu_addr = prop->wptr_gpu_addr; 856 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); 857 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); 858 859 wb_gpu_addr = prop->rptr_gpu_addr; 860 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); 861 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); 862 863 m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 0, 864 regSDMA0_QUEUE0_IB_CNTL)); 865 866 m->sdmax_rlcx_doorbell_offset = 867 prop->doorbell_index << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 868 869 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 870 871 m->sdmax_rlcx_skip_cntl = 0; 872 m->sdmax_rlcx_context_status = 0; 873 m->sdmax_rlcx_doorbell_log = 0; 874 875 m->sdmax_rlcx_rb_aql_cntl = regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT; 876 m->sdmax_rlcx_dummy_reg = regSDMA0_QUEUE0_DUMMY_REG_DEFAULT; 877 878 m->sdmax_rlcx_csa_addr_lo = lower_32_bits(prop->csa_addr); 879 m->sdmax_rlcx_csa_addr_hi = upper_32_bits(prop->csa_addr); 880 881 m->sdmax_rlcx_f32_dbg0 = lower_32_bits(prop->fence_address); 882 m->sdmax_rlcx_f32_dbg1 = upper_32_bits(prop->fence_address); 883 884 return 0; 885 } 886 887 static void sdma_v6_0_set_mqd_funcs(struct amdgpu_device *adev) 888 { 889 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v11_sdma_mqd); 890 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v6_0_mqd_init; 891 } 892 893 /** 894 * sdma_v6_0_ring_test_ring - simple async dma engine test 895 * 896 * @ring: amdgpu_ring structure holding ring information 897 * 898 * Test the DMA engine by writing using it to write an 899 * value to memory. 900 * Returns 0 for success, error for failure. 901 */ 902 static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring) 903 { 904 struct amdgpu_device *adev = ring->adev; 905 unsigned i; 906 unsigned index; 907 int r; 908 u32 tmp; 909 u64 gpu_addr; 910 911 tmp = 0xCAFEDEAD; 912 913 r = amdgpu_wb_get(adev, &index); 914 if (r) { 915 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 916 return r; 917 } 918 919 gpu_addr = adev->wb.gpu_addr + (index * 4); 920 adev->wb.wb[index] = cpu_to_le32(tmp); 921 922 r = amdgpu_ring_alloc(ring, 5); 923 if (r) { 924 drm_err(adev_to_drm(adev), "dma failed to lock ring %d (%d).\n", ring->idx, r); 925 amdgpu_wb_free(adev, index); 926 return r; 927 } 928 929 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 930 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 931 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 932 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 933 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 934 amdgpu_ring_write(ring, 0xDEADBEEF); 935 amdgpu_ring_commit(ring); 936 937 for (i = 0; i < adev->usec_timeout; i++) { 938 tmp = le32_to_cpu(adev->wb.wb[index]); 939 if (tmp == 0xDEADBEEF) 940 break; 941 if (amdgpu_emu_mode == 1) 942 msleep(1); 943 else 944 udelay(1); 945 } 946 947 if (i >= adev->usec_timeout) 948 r = -ETIMEDOUT; 949 950 amdgpu_wb_free(adev, index); 951 952 return r; 953 } 954 955 /* 956 * sdma_v6_0_ring_test_ib - test an IB on the DMA engine 957 * 958 * @ring: amdgpu_ring structure holding ring information 959 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 960 * 961 * Test a simple IB in the DMA ring. 962 * Returns 0 on success, error on failure. 963 */ 964 static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 965 { 966 struct amdgpu_device *adev = ring->adev; 967 struct amdgpu_ib ib; 968 struct dma_fence *f = NULL; 969 unsigned index; 970 long r; 971 u32 tmp = 0; 972 u64 gpu_addr; 973 974 tmp = 0xCAFEDEAD; 975 memset(&ib, 0, sizeof(ib)); 976 977 r = amdgpu_wb_get(adev, &index); 978 if (r) { 979 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 980 return r; 981 } 982 983 gpu_addr = adev->wb.gpu_addr + (index * 4); 984 adev->wb.wb[index] = cpu_to_le32(tmp); 985 986 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 987 if (r) { 988 drm_err(adev_to_drm(adev), "failed to get ib (%ld).\n", r); 989 goto err0; 990 } 991 992 ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 993 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 994 ib.ptr[1] = lower_32_bits(gpu_addr); 995 ib.ptr[2] = upper_32_bits(gpu_addr); 996 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 997 ib.ptr[4] = 0xDEADBEEF; 998 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 999 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1000 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1001 ib.length_dw = 8; 1002 1003 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1004 if (r) 1005 goto err1; 1006 1007 r = dma_fence_wait_timeout(f, false, timeout); 1008 if (r == 0) { 1009 drm_err(adev_to_drm(adev), "IB test timed out\n"); 1010 r = -ETIMEDOUT; 1011 goto err1; 1012 } else if (r < 0) { 1013 drm_err(adev_to_drm(adev), "fence wait failed (%ld).\n", r); 1014 goto err1; 1015 } 1016 1017 tmp = le32_to_cpu(adev->wb.wb[index]); 1018 1019 if (tmp == 0xDEADBEEF) 1020 r = 0; 1021 else 1022 r = -EINVAL; 1023 1024 err1: 1025 amdgpu_ib_free(&ib, NULL); 1026 dma_fence_put(f); 1027 err0: 1028 amdgpu_wb_free(adev, index); 1029 return r; 1030 } 1031 1032 1033 /** 1034 * sdma_v6_0_vm_copy_pte - update PTEs by copying them from the GART 1035 * 1036 * @ib: indirect buffer to fill with commands 1037 * @pe: addr of the page entry 1038 * @src: src addr to copy from 1039 * @count: number of page entries to update 1040 * 1041 * Update PTEs by copying them from the GART using sDMA. 1042 */ 1043 static void sdma_v6_0_vm_copy_pte(struct amdgpu_ib *ib, 1044 uint64_t pe, uint64_t src, 1045 unsigned count) 1046 { 1047 unsigned bytes = count * 8; 1048 1049 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1050 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1051 ib->ptr[ib->length_dw++] = bytes - 1; 1052 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1053 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1054 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1055 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1056 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1057 1058 } 1059 1060 /** 1061 * sdma_v6_0_vm_write_pte - update PTEs by writing them manually 1062 * 1063 * @ib: indirect buffer to fill with commands 1064 * @pe: addr of the page entry 1065 * @value: dst addr to write into pe 1066 * @count: number of page entries to update 1067 * @incr: increase next addr by incr bytes 1068 * 1069 * Update PTEs by writing them manually using sDMA. 1070 */ 1071 static void sdma_v6_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1072 uint64_t value, unsigned count, 1073 uint32_t incr) 1074 { 1075 unsigned ndw = count * 2; 1076 1077 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 1078 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1079 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1080 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1081 ib->ptr[ib->length_dw++] = ndw - 1; 1082 for (; ndw > 0; ndw -= 2) { 1083 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1084 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1085 value += incr; 1086 } 1087 } 1088 1089 /** 1090 * sdma_v6_0_vm_set_pte_pde - update the page tables using sDMA 1091 * 1092 * @ib: indirect buffer to fill with commands 1093 * @pe: addr of the page entry 1094 * @addr: dst addr to write into pe 1095 * @count: number of page entries to update 1096 * @incr: increase next addr by incr bytes 1097 * @flags: access flags 1098 * 1099 * Update the page tables using sDMA. 1100 */ 1101 static void sdma_v6_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1102 uint64_t pe, 1103 uint64_t addr, unsigned count, 1104 uint32_t incr, uint64_t flags) 1105 { 1106 /* for physically contiguous pages (vram) */ 1107 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE); 1108 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1109 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1110 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1111 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1112 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1113 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1114 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1115 ib->ptr[ib->length_dw++] = 0; 1116 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1117 } 1118 1119 /* 1120 * sdma_v6_0_ring_pad_ib - pad the IB 1121 * @ib: indirect buffer to fill with padding 1122 * @ring: amdgpu ring pointer 1123 * 1124 * Pad the IB with NOPs to a boundary multiple of 8. 1125 */ 1126 static void sdma_v6_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1127 { 1128 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1129 u32 pad_count; 1130 int i; 1131 1132 pad_count = (-ib->length_dw) & 0x7; 1133 for (i = 0; i < pad_count; i++) 1134 if (sdma && sdma->burst_nop && (i == 0)) 1135 ib->ptr[ib->length_dw++] = 1136 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) | 1137 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1138 else 1139 ib->ptr[ib->length_dw++] = 1140 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP); 1141 } 1142 1143 /** 1144 * sdma_v6_0_ring_emit_pipeline_sync - sync the pipeline 1145 * 1146 * @ring: amdgpu_ring pointer 1147 * 1148 * Make sure all previous operations are completed (CIK). 1149 */ 1150 static void sdma_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1151 { 1152 uint32_t seq = ring->fence_drv.sync_seq; 1153 uint64_t addr = ring->fence_drv.gpu_addr; 1154 1155 /* wait for idle */ 1156 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1157 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1158 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1159 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1160 amdgpu_ring_write(ring, addr & 0xfffffffc); 1161 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1162 amdgpu_ring_write(ring, seq); /* reference */ 1163 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1164 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1165 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1166 } 1167 1168 /* 1169 * sdma_v6_0_ring_emit_vm_flush - vm flush using sDMA 1170 * 1171 * @ring: amdgpu_ring pointer 1172 * @vmid: vmid number to use 1173 * @pd_addr: address 1174 * 1175 * Update the page table base and flush the VM TLB 1176 * using sDMA. 1177 */ 1178 static void sdma_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1179 unsigned vmid, uint64_t pd_addr) 1180 { 1181 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1182 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 1183 1184 /* Update the PD address for this VMID. */ 1185 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 1186 (hub->ctx_addr_distance * vmid), 1187 lower_32_bits(pd_addr)); 1188 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 1189 (hub->ctx_addr_distance * vmid), 1190 upper_32_bits(pd_addr)); 1191 1192 /* Trigger invalidation. */ 1193 amdgpu_ring_write(ring, 1194 SDMA_PKT_VM_INVALIDATION_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1195 SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(SDMA_SUBOP_VM_INVALIDATION) | 1196 SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(ring->vm_inv_eng) | 1197 SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(0x1f)); 1198 amdgpu_ring_write(ring, req); 1199 amdgpu_ring_write(ring, 0xFFFFFFFF); 1200 amdgpu_ring_write(ring, 1201 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(1 << vmid) | 1202 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(0x1F)); 1203 } 1204 1205 static void sdma_v6_0_ring_emit_wreg(struct amdgpu_ring *ring, 1206 uint32_t reg, uint32_t val) 1207 { 1208 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1209 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1210 amdgpu_ring_write(ring, reg); 1211 amdgpu_ring_write(ring, val); 1212 } 1213 1214 static void sdma_v6_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1215 uint32_t val, uint32_t mask) 1216 { 1217 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1218 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1219 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1220 amdgpu_ring_write(ring, reg << 2); 1221 amdgpu_ring_write(ring, 0); 1222 amdgpu_ring_write(ring, val); /* reference */ 1223 amdgpu_ring_write(ring, mask); /* mask */ 1224 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1225 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1226 } 1227 1228 static void sdma_v6_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1229 uint32_t reg0, uint32_t reg1, 1230 uint32_t ref, uint32_t mask) 1231 { 1232 amdgpu_ring_emit_wreg(ring, reg0, ref); 1233 /* wait for a cycle to reset vm_inv_eng*_ack */ 1234 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1235 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1236 } 1237 1238 static struct amdgpu_sdma_ras sdma_v6_0_3_ras = { 1239 .ras_block = { 1240 .ras_late_init = amdgpu_ras_block_late_init, 1241 }, 1242 }; 1243 1244 static void sdma_v6_0_set_ras_funcs(struct amdgpu_device *adev) 1245 { 1246 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1247 case IP_VERSION(6, 0, 3): 1248 adev->sdma.ras = &sdma_v6_0_3_ras; 1249 break; 1250 default: 1251 break; 1252 } 1253 } 1254 1255 /* all sizes are in bytes */ 1256 #define SDMA6_CSA_SIZE 32 1257 #define SDMA6_CSA_ALIGNMENT 4 1258 1259 static void sdma_v6_0_get_csa_info(struct amdgpu_device *adev, 1260 struct amdgpu_sdma_csa_info *csa_info) 1261 { 1262 csa_info->size = SDMA6_CSA_SIZE; 1263 csa_info->alignment = SDMA6_CSA_ALIGNMENT; 1264 } 1265 1266 static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = { 1267 .copy_pte_num_dw = 7, 1268 .copy_pte = sdma_v6_0_vm_copy_pte, 1269 .write_pte = sdma_v6_0_vm_write_pte, 1270 .set_pte_pde = sdma_v6_0_vm_set_pte_pde, 1271 }; 1272 1273 static int sdma_v6_0_early_init(struct amdgpu_ip_block *ip_block) 1274 { 1275 struct amdgpu_device *adev = ip_block->adev; 1276 int r; 1277 1278 switch (amdgpu_user_queue) { 1279 case -1: 1280 case 0: 1281 default: 1282 adev->sdma.no_user_submission = false; 1283 adev->sdma.disable_uq = true; 1284 break; 1285 case 1: 1286 adev->sdma.no_user_submission = false; 1287 adev->sdma.disable_uq = false; 1288 break; 1289 case 2: 1290 adev->sdma.no_user_submission = true; 1291 adev->sdma.disable_uq = false; 1292 break; 1293 } 1294 1295 r = amdgpu_sdma_init_microcode(adev, 0, true); 1296 if (r) 1297 return r; 1298 1299 sdma_v6_0_set_ring_funcs(adev); 1300 amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v6_0_vm_pte_funcs); 1301 sdma_v6_0_set_irq_funcs(adev); 1302 sdma_v6_0_set_mqd_funcs(adev); 1303 sdma_v6_0_set_ras_funcs(adev); 1304 adev->sdma.get_csa_info = &sdma_v6_0_get_csa_info; 1305 1306 return 0; 1307 } 1308 1309 static int sdma_v6_0_sw_init(struct amdgpu_ip_block *ip_block) 1310 { 1311 struct amdgpu_ring *ring; 1312 int r, i; 1313 struct amdgpu_device *adev = ip_block->adev; 1314 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0); 1315 uint32_t *ptr; 1316 1317 /* SDMA trap event */ 1318 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1319 GFX_11_0_0__SRCID__SDMA_TRAP, 1320 &adev->sdma.trap_irq); 1321 if (r) 1322 return r; 1323 1324 /* SDMA user fence event */ 1325 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1326 GFX_11_0_0__SRCID__SDMA_FENCE, 1327 &adev->sdma.fence_irq); 1328 if (r) 1329 return r; 1330 1331 for (i = 0; i < adev->sdma.num_instances; i++) { 1332 ring = &adev->sdma.instance[i].ring; 1333 ring->ring_obj = NULL; 1334 ring->use_doorbell = true; 1335 ring->me = i; 1336 ring->no_user_submission = adev->sdma.no_user_submission; 1337 1338 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1339 ring->use_doorbell?"true":"false"); 1340 1341 ring->doorbell_index = 1342 (adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset 1343 1344 ring->vm_hub = AMDGPU_GFXHUB(0); 1345 sprintf(ring->name, "sdma%d", i); 1346 r = amdgpu_ring_init(adev, ring, 1024, 1347 &adev->sdma.trap_irq, 1348 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1349 AMDGPU_RING_PRIO_DEFAULT, NULL); 1350 if (r) 1351 return r; 1352 } 1353 1354 adev->sdma.supported_reset = 1355 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); 1356 if (!amdgpu_sriov_vf(adev) && 1357 !adev->debug_disable_gpu_ring_reset) 1358 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1359 1360 if (amdgpu_sdma_ras_sw_init(adev)) { 1361 dev_err(adev->dev, "Failed to initialize sdma ras block!\n"); 1362 return -EINVAL; 1363 } 1364 1365 /* Allocate memory for SDMA IP Dump buffer */ 1366 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); 1367 if (ptr) 1368 adev->sdma.ip_dump = ptr; 1369 else 1370 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n"); 1371 1372 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1373 case IP_VERSION(6, 0, 0): 1374 if ((adev->sdma.instance[0].fw_version >= 27) && !adev->sdma.disable_uq) 1375 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1376 break; 1377 case IP_VERSION(6, 0, 1): 1378 if ((adev->sdma.instance[0].fw_version >= 18) && !adev->sdma.disable_uq) 1379 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1380 break; 1381 case IP_VERSION(6, 0, 2): 1382 if ((adev->sdma.instance[0].fw_version >= 23) && !adev->sdma.disable_uq) 1383 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1384 break; 1385 case IP_VERSION(6, 0, 3): 1386 if (adev->sdma.instance[0].fw_version >= 29 && !adev->sdma.disable_uq) 1387 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1388 break; 1389 case IP_VERSION(6, 1, 0): 1390 if ((adev->sdma.instance[0].fw_version >= 14) && !adev->sdma.disable_uq) 1391 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1392 break; 1393 case IP_VERSION(6, 1, 1): 1394 if ((adev->sdma.instance[0].fw_version >= 17) && !adev->sdma.disable_uq) 1395 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1396 break; 1397 case IP_VERSION(6, 1, 2): 1398 if ((adev->sdma.instance[0].fw_version >= 15) && !adev->sdma.disable_uq) 1399 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1400 break; 1401 case IP_VERSION(6, 1, 3): 1402 if ((adev->sdma.instance[0].fw_version >= 10) && !adev->sdma.disable_uq) 1403 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1404 break; 1405 default: 1406 break; 1407 } 1408 1409 r = amdgpu_sdma_sysfs_reset_mask_init(adev); 1410 if (r) 1411 return r; 1412 1413 return r; 1414 } 1415 1416 static int sdma_v6_0_sw_fini(struct amdgpu_ip_block *ip_block) 1417 { 1418 struct amdgpu_device *adev = ip_block->adev; 1419 int i; 1420 1421 for (i = 0; i < adev->sdma.num_instances; i++) 1422 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1423 1424 amdgpu_sdma_sysfs_reset_mask_fini(adev); 1425 amdgpu_sdma_destroy_inst_ctx(adev, true); 1426 1427 kfree(adev->sdma.ip_dump); 1428 1429 return 0; 1430 } 1431 1432 static int sdma_v6_0_set_userq_trap_interrupts(struct amdgpu_device *adev, 1433 bool enable) 1434 { 1435 unsigned int irq_type; 1436 int i, r; 1437 1438 if (adev->userq_funcs[AMDGPU_HW_IP_DMA]) { 1439 for (i = 0; i < adev->sdma.num_instances; i++) { 1440 irq_type = AMDGPU_SDMA_IRQ_INSTANCE0 + i; 1441 if (enable) 1442 r = amdgpu_irq_get(adev, &adev->sdma.trap_irq, 1443 irq_type); 1444 else 1445 r = amdgpu_irq_put(adev, &adev->sdma.trap_irq, 1446 irq_type); 1447 if (r) 1448 return r; 1449 } 1450 } 1451 1452 return 0; 1453 } 1454 1455 static int sdma_v6_0_hw_init(struct amdgpu_ip_block *ip_block) 1456 { 1457 struct amdgpu_device *adev = ip_block->adev; 1458 int r; 1459 1460 r = sdma_v6_0_start(adev); 1461 if (r) 1462 return r; 1463 sdma_v6_0_set_buffer_funcs(adev); 1464 1465 return sdma_v6_0_set_userq_trap_interrupts(adev, true); 1466 } 1467 1468 static int sdma_v6_0_hw_fini(struct amdgpu_ip_block *ip_block) 1469 { 1470 struct amdgpu_device *adev = ip_block->adev; 1471 1472 if (amdgpu_sriov_vf(adev)) 1473 return 0; 1474 1475 sdma_v6_0_ctxempty_int_enable(adev, false); 1476 sdma_v6_0_enable(adev, false); 1477 sdma_v6_0_set_userq_trap_interrupts(adev, false); 1478 1479 return 0; 1480 } 1481 1482 static int sdma_v6_0_suspend(struct amdgpu_ip_block *ip_block) 1483 { 1484 return sdma_v6_0_hw_fini(ip_block); 1485 } 1486 1487 static int sdma_v6_0_resume(struct amdgpu_ip_block *ip_block) 1488 { 1489 return sdma_v6_0_hw_init(ip_block); 1490 } 1491 1492 static bool sdma_v6_0_is_idle(struct amdgpu_ip_block *ip_block) 1493 { 1494 struct amdgpu_device *adev = ip_block->adev; 1495 u32 i; 1496 1497 for (i = 0; i < adev->sdma.num_instances; i++) { 1498 u32 tmp = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG)); 1499 1500 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1501 return false; 1502 } 1503 1504 return true; 1505 } 1506 1507 static int sdma_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1508 { 1509 unsigned i; 1510 u32 sdma0, sdma1; 1511 struct amdgpu_device *adev = ip_block->adev; 1512 1513 for (i = 0; i < adev->usec_timeout; i++) { 1514 sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG)); 1515 sdma1 = RREG32(sdma_v6_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG)); 1516 1517 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1518 return 0; 1519 udelay(1); 1520 } 1521 return -ETIMEDOUT; 1522 } 1523 1524 static int sdma_v6_0_ring_preempt_ib(struct amdgpu_ring *ring) 1525 { 1526 int i, r = 0; 1527 struct amdgpu_device *adev = ring->adev; 1528 u32 index = 0; 1529 u64 sdma_gfx_preempt; 1530 1531 amdgpu_sdma_get_index_from_ring(ring, &index); 1532 sdma_gfx_preempt = 1533 sdma_v6_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT); 1534 1535 /* assert preemption condition */ 1536 amdgpu_ring_set_preempt_cond_exec(ring, false); 1537 1538 /* emit the trailing fence */ 1539 ring->trail_seq += 1; 1540 amdgpu_ring_alloc(ring, 10); 1541 sdma_v6_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1542 ring->trail_seq, 0); 1543 amdgpu_ring_commit(ring); 1544 1545 /* assert IB preemption */ 1546 WREG32(sdma_gfx_preempt, 1); 1547 1548 /* poll the trailing fence */ 1549 for (i = 0; i < adev->usec_timeout; i++) { 1550 if (ring->trail_seq == 1551 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1552 break; 1553 udelay(1); 1554 } 1555 1556 if (i >= adev->usec_timeout) { 1557 r = -EINVAL; 1558 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1559 } 1560 1561 /* deassert IB preemption */ 1562 WREG32(sdma_gfx_preempt, 0); 1563 1564 /* deassert the preemption condition */ 1565 amdgpu_ring_set_preempt_cond_exec(ring, true); 1566 return r; 1567 } 1568 1569 static int sdma_v6_0_reset_queue(struct amdgpu_ring *ring, 1570 unsigned int vmid, 1571 struct amdgpu_fence *timedout_fence) 1572 { 1573 struct amdgpu_device *adev = ring->adev; 1574 int r; 1575 1576 if (ring->me >= adev->sdma.num_instances) { 1577 dev_err(adev->dev, "sdma instance not found\n"); 1578 return -EINVAL; 1579 } 1580 1581 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 1582 1583 r = amdgpu_mes_reset_legacy_queue(adev, ring, vmid, true, 0); 1584 if (r) 1585 return r; 1586 1587 r = sdma_v6_0_gfx_resume_instance(adev, ring->me, true); 1588 if (r) 1589 return r; 1590 1591 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 1592 } 1593 1594 static int sdma_v6_0_set_trap_irq_state(struct amdgpu_device *adev, 1595 struct amdgpu_irq_src *source, 1596 unsigned type, 1597 enum amdgpu_interrupt_state state) 1598 { 1599 u32 sdma_cntl; 1600 1601 u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL); 1602 1603 if (!amdgpu_sriov_vf(adev)) { 1604 sdma_cntl = RREG32(reg_offset); 1605 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1606 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1607 WREG32(reg_offset, sdma_cntl); 1608 } 1609 1610 return 0; 1611 } 1612 1613 static int sdma_v6_0_process_trap_irq(struct amdgpu_device *adev, 1614 struct amdgpu_irq_src *source, 1615 struct amdgpu_iv_entry *entry) 1616 { 1617 int instances, queue; 1618 1619 DRM_DEBUG("IH: SDMA trap\n"); 1620 1621 queue = entry->ring_id & 0xf; 1622 instances = (entry->ring_id & 0xf0) >> 4; 1623 if (instances > 1) { 1624 DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n"); 1625 return -EINVAL; 1626 } 1627 1628 switch (entry->client_id) { 1629 case SOC21_IH_CLIENTID_GFX: 1630 switch (queue) { 1631 case 0: 1632 amdgpu_fence_process(&adev->sdma.instance[instances].ring); 1633 break; 1634 default: 1635 break; 1636 } 1637 break; 1638 } 1639 return 0; 1640 } 1641 1642 static int sdma_v6_0_process_fence_irq(struct amdgpu_device *adev, 1643 struct amdgpu_irq_src *source, 1644 struct amdgpu_iv_entry *entry) 1645 { 1646 u32 doorbell_offset = entry->src_data[0]; 1647 1648 if (adev->enable_mes && doorbell_offset) { 1649 doorbell_offset >>= SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 1650 amdgpu_userq_process_fence_irq(adev, doorbell_offset); 1651 } 1652 1653 return 0; 1654 } 1655 1656 static int sdma_v6_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1657 struct amdgpu_irq_src *source, 1658 struct amdgpu_iv_entry *entry) 1659 { 1660 return 0; 1661 } 1662 1663 static int sdma_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1664 enum amd_clockgating_state state) 1665 { 1666 return 0; 1667 } 1668 1669 static int sdma_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 1670 enum amd_powergating_state state) 1671 { 1672 return 0; 1673 } 1674 1675 static void sdma_v6_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1676 { 1677 } 1678 1679 static void sdma_v6_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 1680 { 1681 struct amdgpu_device *adev = ip_block->adev; 1682 int i, j; 1683 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0); 1684 uint32_t instance_offset; 1685 1686 if (!adev->sdma.ip_dump) 1687 return; 1688 1689 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances); 1690 for (i = 0; i < adev->sdma.num_instances; i++) { 1691 instance_offset = i * reg_count; 1692 drm_printf(p, "\nInstance:%d\n", i); 1693 1694 for (j = 0; j < reg_count; j++) 1695 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_6_0[j].reg_name, 1696 adev->sdma.ip_dump[instance_offset + j]); 1697 } 1698 } 1699 1700 static void sdma_v6_0_dump_ip_state(struct amdgpu_ip_block *ip_block) 1701 { 1702 struct amdgpu_device *adev = ip_block->adev; 1703 int i, j; 1704 uint32_t instance_offset; 1705 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0); 1706 1707 if (!adev->sdma.ip_dump) 1708 return; 1709 1710 amdgpu_gfx_off_ctrl(adev, false); 1711 for (i = 0; i < adev->sdma.num_instances; i++) { 1712 instance_offset = i * reg_count; 1713 for (j = 0; j < reg_count; j++) 1714 adev->sdma.ip_dump[instance_offset + j] = 1715 RREG32(sdma_v6_0_get_reg_offset(adev, i, 1716 sdma_reg_list_6_0[j].reg_offset)); 1717 } 1718 amdgpu_gfx_off_ctrl(adev, true); 1719 } 1720 1721 const struct amd_ip_funcs sdma_v6_0_ip_funcs = { 1722 .name = "sdma_v6_0", 1723 .early_init = sdma_v6_0_early_init, 1724 .sw_init = sdma_v6_0_sw_init, 1725 .sw_fini = sdma_v6_0_sw_fini, 1726 .hw_init = sdma_v6_0_hw_init, 1727 .hw_fini = sdma_v6_0_hw_fini, 1728 .suspend = sdma_v6_0_suspend, 1729 .resume = sdma_v6_0_resume, 1730 .is_idle = sdma_v6_0_is_idle, 1731 .wait_for_idle = sdma_v6_0_wait_for_idle, 1732 .soft_reset = sdma_v6_0_soft_reset, 1733 .set_clockgating_state = sdma_v6_0_set_clockgating_state, 1734 .set_powergating_state = sdma_v6_0_set_powergating_state, 1735 .get_clockgating_state = sdma_v6_0_get_clockgating_state, 1736 .dump_ip_state = sdma_v6_0_dump_ip_state, 1737 .print_ip_state = sdma_v6_0_print_ip_state, 1738 }; 1739 1740 static const struct amdgpu_ring_funcs sdma_v6_0_ring_funcs = { 1741 .type = AMDGPU_RING_TYPE_SDMA, 1742 .align_mask = 0xf, 1743 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1744 .support_64bit_ptrs = true, 1745 .secure_submission_supported = true, 1746 .get_rptr = sdma_v6_0_ring_get_rptr, 1747 .get_wptr = sdma_v6_0_ring_get_wptr, 1748 .set_wptr = sdma_v6_0_ring_set_wptr, 1749 .emit_frame_size = 1750 5 + /* sdma_v6_0_ring_init_cond_exec */ 1751 6 + /* sdma_v6_0_ring_emit_hdp_flush */ 1752 6 + /* sdma_v6_0_ring_emit_pipeline_sync */ 1753 /* sdma_v6_0_ring_emit_vm_flush */ 1754 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1755 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1756 10 + 10 + 10, /* sdma_v6_0_ring_emit_fence x3 for user fence, vm fence */ 1757 .emit_ib_size = 5 + 7 + 6, /* sdma_v6_0_ring_emit_ib */ 1758 .emit_ib = sdma_v6_0_ring_emit_ib, 1759 .emit_mem_sync = sdma_v6_0_ring_emit_mem_sync, 1760 .emit_fence = sdma_v6_0_ring_emit_fence, 1761 .emit_pipeline_sync = sdma_v6_0_ring_emit_pipeline_sync, 1762 .emit_vm_flush = sdma_v6_0_ring_emit_vm_flush, 1763 .emit_hdp_flush = sdma_v6_0_ring_emit_hdp_flush, 1764 .test_ring = sdma_v6_0_ring_test_ring, 1765 .test_ib = sdma_v6_0_ring_test_ib, 1766 .insert_nop = sdma_v6_0_ring_insert_nop, 1767 .pad_ib = sdma_v6_0_ring_pad_ib, 1768 .emit_wreg = sdma_v6_0_ring_emit_wreg, 1769 .emit_reg_wait = sdma_v6_0_ring_emit_reg_wait, 1770 .emit_reg_write_reg_wait = sdma_v6_0_ring_emit_reg_write_reg_wait, 1771 .init_cond_exec = sdma_v6_0_ring_init_cond_exec, 1772 .preempt_ib = sdma_v6_0_ring_preempt_ib, 1773 .reset = sdma_v6_0_reset_queue, 1774 }; 1775 1776 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev) 1777 { 1778 int i; 1779 1780 for (i = 0; i < adev->sdma.num_instances; i++) { 1781 adev->sdma.instance[i].ring.funcs = &sdma_v6_0_ring_funcs; 1782 adev->sdma.instance[i].ring.me = i; 1783 } 1784 } 1785 1786 static const struct amdgpu_irq_src_funcs sdma_v6_0_trap_irq_funcs = { 1787 .set = sdma_v6_0_set_trap_irq_state, 1788 .process = sdma_v6_0_process_trap_irq, 1789 }; 1790 1791 static const struct amdgpu_irq_src_funcs sdma_v6_0_fence_irq_funcs = { 1792 .process = sdma_v6_0_process_fence_irq, 1793 }; 1794 1795 static const struct amdgpu_irq_src_funcs sdma_v6_0_illegal_inst_irq_funcs = { 1796 .process = sdma_v6_0_process_illegal_inst_irq, 1797 }; 1798 1799 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev) 1800 { 1801 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1802 adev->sdma.num_instances; 1803 adev->sdma.trap_irq.funcs = &sdma_v6_0_trap_irq_funcs; 1804 adev->sdma.fence_irq.funcs = &sdma_v6_0_fence_irq_funcs; 1805 adev->sdma.illegal_inst_irq.funcs = &sdma_v6_0_illegal_inst_irq_funcs; 1806 } 1807 1808 /** 1809 * sdma_v6_0_emit_copy_buffer - copy buffer using the sDMA engine 1810 * 1811 * @ib: indirect buffer to fill with commands 1812 * @src_offset: src GPU address 1813 * @dst_offset: dst GPU address 1814 * @byte_count: number of bytes to xfer 1815 * @copy_flags: copy flags for the buffers 1816 * 1817 * Copy GPU buffers using the DMA engine. 1818 * Used by the amdgpu ttm implementation to move pages if 1819 * registered as the asic copy callback. 1820 */ 1821 static void sdma_v6_0_emit_copy_buffer(struct amdgpu_ib *ib, 1822 uint64_t src_offset, 1823 uint64_t dst_offset, 1824 uint32_t byte_count, 1825 uint32_t copy_flags) 1826 { 1827 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1828 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1829 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0); 1830 ib->ptr[ib->length_dw++] = byte_count - 1; 1831 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1832 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1833 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1834 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1835 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1836 } 1837 1838 /** 1839 * sdma_v6_0_emit_fill_buffer - fill buffer using the sDMA engine 1840 * 1841 * @ib: indirect buffer to fill 1842 * @src_data: value to write to buffer 1843 * @dst_offset: dst GPU address 1844 * @byte_count: number of bytes to xfer 1845 * 1846 * Fill GPU buffers using the DMA engine. 1847 */ 1848 static void sdma_v6_0_emit_fill_buffer(struct amdgpu_ib *ib, 1849 uint32_t src_data, 1850 uint64_t dst_offset, 1851 uint32_t byte_count) 1852 { 1853 ib->ptr[ib->length_dw++] = SDMA_PKT_CONSTANT_FILL_HEADER_OP(SDMA_OP_CONST_FILL); 1854 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1855 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1856 ib->ptr[ib->length_dw++] = src_data; 1857 ib->ptr[ib->length_dw++] = byte_count - 1; 1858 } 1859 1860 static const struct amdgpu_buffer_funcs sdma_v6_0_buffer_funcs = { 1861 .copy_max_bytes = 1 << 30, 1862 .copy_num_dw = 7, 1863 .emit_copy_buffer = sdma_v6_0_emit_copy_buffer, 1864 1865 .fill_max_bytes = 1 << 30, 1866 .fill_num_dw = 5, 1867 .emit_fill_buffer = sdma_v6_0_emit_fill_buffer, 1868 }; 1869 1870 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev) 1871 { 1872 amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v6_0_buffer_funcs); 1873 } 1874 1875 const struct amdgpu_ip_block_version sdma_v6_0_ip_block = { 1876 .type = AMD_IP_BLOCK_TYPE_SDMA, 1877 .major = 6, 1878 .minor = 0, 1879 .rev = 0, 1880 .funcs = &sdma_v6_0_ip_funcs, 1881 }; 1882