1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_11_0_0_offset.h" 34 #include "gc/gc_11_0_0_sh_mask.h" 35 #include "gc/gc_11_0_0_default.h" 36 #include "hdp/hdp_6_0_0_offset.h" 37 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 38 39 #include "soc15_common.h" 40 #include "soc15.h" 41 #include "sdma_v6_0_0_pkt_open.h" 42 #include "nbio_v4_3.h" 43 #include "sdma_common.h" 44 #include "sdma_v6_0.h" 45 #include "v11_structs.h" 46 #include "mes_userqueue.h" 47 #include "amdgpu_userq_fence.h" 48 49 MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin"); 50 MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin"); 51 MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin"); 52 MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin"); 53 MODULE_FIRMWARE("amdgpu/sdma_6_1_0.bin"); 54 MODULE_FIRMWARE("amdgpu/sdma_6_1_1.bin"); 55 MODULE_FIRMWARE("amdgpu/sdma_6_1_2.bin"); 56 MODULE_FIRMWARE("amdgpu/sdma_6_1_3.bin"); 57 58 #define SDMA1_REG_OFFSET 0x600 59 #define SDMA0_HYP_DEC_REG_START 0x5880 60 #define SDMA0_HYP_DEC_REG_END 0x589a 61 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 62 63 static const struct amdgpu_hwip_reg_entry sdma_reg_list_6_0[] = { 64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS_REG), 65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS1_REG), 66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS2_REG), 67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS3_REG), 68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS4_REG), 69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS5_REG), 70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS6_REG), 71 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UCODE_CHECKSUM), 72 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH_HI), 73 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH), 74 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_STATUS), 75 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_STATUS), 76 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK0), 77 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK1), 78 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK0), 79 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK1), 80 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_CNTL), 81 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR), 82 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR_HI), 83 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR), 84 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR_HI), 85 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_OFFSET), 86 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_LO), 87 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_HI), 88 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_CNTL), 89 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_RPTR), 90 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_SUB_REMAIN), 91 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_DUMMY_REG), 92 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE_STATUS0), 93 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_CNTL), 94 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR), 95 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR_HI), 96 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR), 97 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR_HI), 98 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_OFFSET), 99 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_LO), 100 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_HI), 101 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_RPTR), 102 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_SUB_REMAIN), 103 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_DUMMY_REG), 104 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_CNTL), 105 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR), 106 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR_HI), 107 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR), 108 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR_HI), 109 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_OFFSET), 110 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_LO), 111 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_HI), 112 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_RPTR), 113 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_SUB_REMAIN), 114 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_DUMMY_REG), 115 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_INT_STATUS), 116 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 117 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_CHICKEN_BITS), 118 }; 119 120 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev); 121 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev); 122 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev); 123 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev); 124 static int sdma_v6_0_start(struct amdgpu_device *adev); 125 126 static u32 sdma_v6_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 127 { 128 u32 base; 129 130 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 131 internal_offset <= SDMA0_HYP_DEC_REG_END) { 132 base = adev->reg_offset[GC_HWIP][0][1]; 133 if (instance != 0) 134 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance; 135 } else { 136 base = adev->reg_offset[GC_HWIP][0][0]; 137 if (instance == 1) 138 internal_offset += SDMA1_REG_OFFSET; 139 } 140 141 return base + internal_offset; 142 } 143 144 static unsigned sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring *ring, 145 uint64_t addr) 146 { 147 unsigned ret; 148 149 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE)); 150 amdgpu_ring_write(ring, lower_32_bits(addr)); 151 amdgpu_ring_write(ring, upper_32_bits(addr)); 152 amdgpu_ring_write(ring, 1); 153 /* this is the offset we need patch later */ 154 ret = ring->wptr & ring->buf_mask; 155 /* insert dummy here and patch it later */ 156 amdgpu_ring_write(ring, 0); 157 158 return ret; 159 } 160 161 /** 162 * sdma_v6_0_ring_get_rptr - get the current read pointer 163 * 164 * @ring: amdgpu ring pointer 165 * 166 * Get the current rptr from the hardware. 167 */ 168 static uint64_t sdma_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 169 { 170 u64 *rptr; 171 172 /* XXX check if swapping is necessary on BE */ 173 rptr = (u64 *)ring->rptr_cpu_addr; 174 175 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 176 return ((*rptr) >> 2); 177 } 178 179 /** 180 * sdma_v6_0_ring_get_wptr - get the current write pointer 181 * 182 * @ring: amdgpu ring pointer 183 * 184 * Get the current wptr from the hardware. 185 */ 186 static uint64_t sdma_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 187 { 188 u64 wptr = 0; 189 190 if (ring->use_doorbell) { 191 /* XXX check if swapping is necessary on BE */ 192 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 193 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 194 } 195 196 return wptr >> 2; 197 } 198 199 /** 200 * sdma_v6_0_ring_set_wptr - commit the write pointer 201 * 202 * @ring: amdgpu ring pointer 203 * 204 * Write the wptr back to the hardware. 205 */ 206 static void sdma_v6_0_ring_set_wptr(struct amdgpu_ring *ring) 207 { 208 struct amdgpu_device *adev = ring->adev; 209 210 if (ring->use_doorbell) { 211 DRM_DEBUG("Using doorbell -- " 212 "wptr_offs == 0x%08x " 213 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 214 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 215 ring->wptr_offs, 216 lower_32_bits(ring->wptr << 2), 217 upper_32_bits(ring->wptr << 2)); 218 /* XXX check if swapping is necessary on BE */ 219 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 220 ring->wptr << 2); 221 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 222 ring->doorbell_index, ring->wptr << 2); 223 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 224 } else { 225 DRM_DEBUG("Not using doorbell -- " 226 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 227 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 228 ring->me, 229 lower_32_bits(ring->wptr << 2), 230 ring->me, 231 upper_32_bits(ring->wptr << 2)); 232 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 233 ring->me, regSDMA0_QUEUE0_RB_WPTR), 234 lower_32_bits(ring->wptr << 2)); 235 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 236 ring->me, regSDMA0_QUEUE0_RB_WPTR_HI), 237 upper_32_bits(ring->wptr << 2)); 238 } 239 } 240 241 static void sdma_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 242 { 243 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 244 int i; 245 246 for (i = 0; i < count; i++) 247 if (sdma && sdma->burst_nop && (i == 0)) 248 amdgpu_ring_write(ring, ring->funcs->nop | 249 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 250 else 251 amdgpu_ring_write(ring, ring->funcs->nop); 252 } 253 254 /* 255 * sdma_v6_0_ring_emit_ib - Schedule an IB on the DMA engine 256 * 257 * @ring: amdgpu ring pointer 258 * @ib: IB object to schedule 259 * @flags: unused 260 * @job: job to retrieve vmid from 261 * 262 * Schedule an IB in the DMA ring. 263 */ 264 static void sdma_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 265 struct amdgpu_job *job, 266 struct amdgpu_ib *ib, 267 uint32_t flags) 268 { 269 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 270 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 271 272 /* An IB packet must end on a 8 DW boundary--the next dword 273 * must be on a 8-dword boundary. Our IB packet below is 6 274 * dwords long, thus add x number of NOPs, such that, in 275 * modular arithmetic, 276 * wptr + 6 + x = 8k, k >= 0, which in C is, 277 * (wptr + 6 + x) % 8 = 0. 278 * The expression below, is a solution of x. 279 */ 280 sdma_v6_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 281 282 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) | 283 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 284 /* base must be 32 byte aligned */ 285 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 286 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 287 amdgpu_ring_write(ring, ib->length_dw); 288 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 289 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 290 } 291 292 /** 293 * sdma_v6_0_ring_emit_mem_sync - flush the IB by graphics cache rinse 294 * 295 * @ring: amdgpu ring pointer 296 * 297 * flush the IB by graphics cache rinse. 298 */ 299 static void sdma_v6_0_ring_emit_mem_sync(struct amdgpu_ring *ring) 300 { 301 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV | 302 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 303 SDMA_GCR_GLI_INV(1); 304 305 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 306 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ)); 307 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 308 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 309 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 310 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 311 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 312 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 313 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 314 } 315 316 317 /** 318 * sdma_v6_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 319 * 320 * @ring: amdgpu ring pointer 321 * 322 * Emit an hdp flush packet on the requested DMA ring. 323 */ 324 static void sdma_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 325 { 326 struct amdgpu_device *adev = ring->adev; 327 u32 ref_and_mask = 0; 328 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 329 330 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 331 332 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 333 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 334 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 335 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 336 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 337 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 338 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 339 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 340 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 341 } 342 343 /** 344 * sdma_v6_0_ring_emit_fence - emit a fence on the DMA ring 345 * 346 * @ring: amdgpu ring pointer 347 * @addr: address 348 * @seq: fence seq number 349 * @flags: fence flags 350 * 351 * Add a DMA fence packet to the ring to write 352 * the fence seq number and DMA trap packet to generate 353 * an interrupt if needed. 354 */ 355 static void sdma_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 356 unsigned flags) 357 { 358 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 359 /* write the fence */ 360 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 361 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 362 /* zero in first two bits */ 363 BUG_ON(addr & 0x3); 364 amdgpu_ring_write(ring, lower_32_bits(addr)); 365 amdgpu_ring_write(ring, upper_32_bits(addr)); 366 amdgpu_ring_write(ring, lower_32_bits(seq)); 367 368 /* optionally write high bits as well */ 369 if (write64bit) { 370 addr += 4; 371 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 372 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 373 /* zero in first two bits */ 374 BUG_ON(addr & 0x3); 375 amdgpu_ring_write(ring, lower_32_bits(addr)); 376 amdgpu_ring_write(ring, upper_32_bits(addr)); 377 amdgpu_ring_write(ring, upper_32_bits(seq)); 378 } 379 380 if (flags & AMDGPU_FENCE_FLAG_INT) { 381 /* generate an interrupt */ 382 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP)); 383 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 384 } 385 } 386 387 /** 388 * sdma_v6_0_gfx_stop - stop the gfx async dma engines 389 * 390 * @adev: amdgpu_device pointer 391 * 392 * Stop the gfx async dma ring buffers. 393 */ 394 static void sdma_v6_0_gfx_stop(struct amdgpu_device *adev) 395 { 396 u32 rb_cntl, ib_cntl; 397 int i; 398 399 for (i = 0; i < adev->sdma.num_instances; i++) { 400 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 401 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0); 402 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 403 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 404 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0); 405 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 406 } 407 } 408 409 /** 410 * sdma_v6_0_rlc_stop - stop the compute async dma engines 411 * 412 * @adev: amdgpu_device pointer 413 * 414 * Stop the compute async dma queues. 415 */ 416 static void sdma_v6_0_rlc_stop(struct amdgpu_device *adev) 417 { 418 /* XXX todo */ 419 } 420 421 /** 422 * sdma_v6_0_ctxempty_int_enable - enable or disable context empty interrupts 423 * 424 * @adev: amdgpu_device pointer 425 * @enable: enable/disable context switching due to queue empty conditions 426 * 427 * Enable or disable the async dma engines queue empty context switch. 428 */ 429 static void sdma_v6_0_ctxempty_int_enable(struct amdgpu_device *adev, bool enable) 430 { 431 u32 f32_cntl; 432 int i; 433 434 if (!amdgpu_sriov_vf(adev)) { 435 for (i = 0; i < adev->sdma.num_instances; i++) { 436 f32_cntl = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL)); 437 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 438 CTXEMPTY_INT_ENABLE, enable ? 1 : 0); 439 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL), f32_cntl); 440 } 441 } 442 } 443 444 /** 445 * sdma_v6_0_enable - stop the async dma engines 446 * 447 * @adev: amdgpu_device pointer 448 * @enable: enable/disable the DMA MEs. 449 * 450 * Halt or unhalt the async dma engines. 451 */ 452 static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable) 453 { 454 u32 f32_cntl; 455 int i; 456 457 if (!enable) { 458 sdma_v6_0_gfx_stop(adev); 459 sdma_v6_0_rlc_stop(adev); 460 } 461 462 if (amdgpu_sriov_vf(adev)) 463 return; 464 465 for (i = 0; i < adev->sdma.num_instances; i++) { 466 f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 467 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 468 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl); 469 } 470 } 471 472 /** 473 * sdma_v6_0_gfx_resume_instance - start/restart a certain sdma engine 474 * 475 * @adev: amdgpu_device pointer 476 * @i: instance 477 * @restore: used to restore wptr when restart 478 * 479 * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr. 480 * Return 0 for success. 481 */ 482 static int sdma_v6_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore) 483 { 484 struct amdgpu_ring *ring; 485 u32 rb_cntl, ib_cntl; 486 u32 rb_bufsz; 487 u32 doorbell; 488 u32 doorbell_offset; 489 u32 temp; 490 u64 wptr_gpu_addr; 491 492 ring = &adev->sdma.instance[i].ring; 493 if (!amdgpu_sriov_vf(adev)) 494 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 495 496 /* Set ring buffer size in dwords */ 497 rb_bufsz = order_base_2(ring->ring_size / 4); 498 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 499 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); 500 #ifdef __BIG_ENDIAN 501 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1); 502 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, 503 RPTR_WRITEBACK_SWAP_ENABLE, 1); 504 #endif 505 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1); 506 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 507 508 /* Initialize the ring buffer's read and write pointers */ 509 if (restore) { 510 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2)); 511 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2)); 512 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2)); 513 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); 514 } else { 515 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0); 516 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0); 517 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0); 518 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0); 519 } 520 /* setup the wptr shadow polling */ 521 wptr_gpu_addr = ring->wptr_gpu_addr; 522 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO), 523 lower_32_bits(wptr_gpu_addr)); 524 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI), 525 upper_32_bits(wptr_gpu_addr)); 526 527 /* set the wb address whether it's enabled or not */ 528 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI), 529 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 530 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO), 531 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 532 533 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 534 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0); 535 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1); 536 537 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8); 538 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40); 539 540 if (!restore) 541 ring->wptr = 0; 542 543 /* before programing wptr to a less value, need set minor_ptr_update first */ 544 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1); 545 546 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 547 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2); 548 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 549 } 550 551 doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL)); 552 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET)); 553 554 if (ring->use_doorbell) { 555 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 556 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET, 557 OFFSET, ring->doorbell_index); 558 } else { 559 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0); 560 } 561 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell); 562 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset); 563 564 if (i == 0) 565 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 566 ring->doorbell_index, 567 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances); 568 569 if (amdgpu_sriov_vf(adev)) 570 sdma_v6_0_ring_set_wptr(ring); 571 572 /* set minor_ptr_update to 0 after wptr programed */ 573 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0); 574 575 /* Set up sdma hang watchdog */ 576 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL)); 577 /* 100ms per unit */ 578 temp = REG_SET_FIELD(temp, SDMA0_WATCHDOG_CNTL, QUEUE_HANG_COUNT, 579 max(adev->usec_timeout/100000, 1)); 580 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), temp); 581 582 /* Set up RESP_MODE to non-copy addresses */ 583 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL)); 584 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 585 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 586 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp); 587 588 /* program default cache read and write policy */ 589 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE)); 590 /* clean read policy and write policy bits */ 591 temp &= 0xFF0FFF; 592 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | 593 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | 594 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK); 595 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp); 596 597 if (!amdgpu_sriov_vf(adev)) { 598 /* unhalt engine */ 599 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 600 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 601 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0); 602 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp); 603 } 604 605 /* enable DMA RB */ 606 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1); 607 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 608 609 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 610 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1); 611 #ifdef __BIG_ENDIAN 612 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1); 613 #endif 614 /* enable DMA IBs */ 615 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 616 617 if (amdgpu_sriov_vf(adev)) 618 sdma_v6_0_enable(adev, true); 619 620 return amdgpu_ring_test_helper(ring); 621 } 622 623 /** 624 * sdma_v6_0_gfx_resume - setup and start the async dma engines 625 * 626 * @adev: amdgpu_device pointer 627 * 628 * Set up the gfx DMA ring buffers and enable them. 629 * Returns 0 for success, error for failure. 630 */ 631 static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev) 632 { 633 int i, r; 634 635 for (i = 0; i < adev->sdma.num_instances; i++) { 636 r = sdma_v6_0_gfx_resume_instance(adev, i, false); 637 if (r) 638 return r; 639 } 640 641 return 0; 642 } 643 644 /** 645 * sdma_v6_0_rlc_resume - setup and start the async dma engines 646 * 647 * @adev: amdgpu_device pointer 648 * 649 * Set up the compute DMA queues and enable them. 650 * Returns 0 for success, error for failure. 651 */ 652 static int sdma_v6_0_rlc_resume(struct amdgpu_device *adev) 653 { 654 return 0; 655 } 656 657 /** 658 * sdma_v6_0_load_microcode - load the sDMA ME ucode 659 * 660 * @adev: amdgpu_device pointer 661 * 662 * Loads the sDMA0/1 ucode. 663 * Returns 0 for success, -EINVAL if the ucode is not available. 664 */ 665 static int sdma_v6_0_load_microcode(struct amdgpu_device *adev) 666 { 667 const struct sdma_firmware_header_v2_0 *hdr; 668 const __le32 *fw_data; 669 u32 fw_size; 670 int i, j; 671 bool use_broadcast; 672 673 /* halt the MEs */ 674 sdma_v6_0_enable(adev, false); 675 676 if (!adev->sdma.instance[0].fw) 677 return -EINVAL; 678 679 /* use broadcast mode to load SDMA microcode by default */ 680 use_broadcast = true; 681 682 if (use_broadcast) { 683 dev_info(adev->dev, "Use broadcast method to load SDMA firmware\n"); 684 /* load Control Thread microcode */ 685 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data; 686 amdgpu_ucode_print_sdma_hdr(&hdr->header); 687 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4; 688 689 fw_data = (const __le32 *) 690 (adev->sdma.instance[0].fw->data + 691 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 692 693 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0); 694 695 for (j = 0; j < fw_size; j++) { 696 if (amdgpu_emu_mode == 1 && j % 500 == 0) 697 msleep(1); 698 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++)); 699 } 700 701 /* load Context Switch microcode */ 702 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4; 703 704 fw_data = (const __le32 *) 705 (adev->sdma.instance[0].fw->data + 706 le32_to_cpu(hdr->ctl_ucode_offset)); 707 708 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0x8000); 709 710 for (j = 0; j < fw_size; j++) { 711 if (amdgpu_emu_mode == 1 && j % 500 == 0) 712 msleep(1); 713 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++)); 714 } 715 } else { 716 dev_info(adev->dev, "Use legacy method to load SDMA firmware\n"); 717 for (i = 0; i < adev->sdma.num_instances; i++) { 718 /* load Control Thread microcode */ 719 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data; 720 amdgpu_ucode_print_sdma_hdr(&hdr->header); 721 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4; 722 723 fw_data = (const __le32 *) 724 (adev->sdma.instance[0].fw->data + 725 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 726 727 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0); 728 729 for (j = 0; j < fw_size; j++) { 730 if (amdgpu_emu_mode == 1 && j % 500 == 0) 731 msleep(1); 732 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 733 } 734 735 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version); 736 737 /* load Context Switch microcode */ 738 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4; 739 740 fw_data = (const __le32 *) 741 (adev->sdma.instance[0].fw->data + 742 le32_to_cpu(hdr->ctl_ucode_offset)); 743 744 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0x8000); 745 746 for (j = 0; j < fw_size; j++) { 747 if (amdgpu_emu_mode == 1 && j % 500 == 0) 748 msleep(1); 749 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 750 } 751 752 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version); 753 } 754 } 755 756 return 0; 757 } 758 759 static int sdma_v6_0_soft_reset(struct amdgpu_ip_block *ip_block) 760 { 761 struct amdgpu_device *adev = ip_block->adev; 762 u32 tmp; 763 int i; 764 765 sdma_v6_0_gfx_stop(adev); 766 767 for (i = 0; i < adev->sdma.num_instances; i++) { 768 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE)); 769 tmp |= SDMA0_FREEZE__FREEZE_MASK; 770 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp); 771 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 772 tmp |= SDMA0_F32_CNTL__HALT_MASK; 773 tmp |= SDMA0_F32_CNTL__TH1_RESET_MASK; 774 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp); 775 776 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0); 777 778 udelay(100); 779 780 tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i; 781 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); 782 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 783 784 udelay(100); 785 786 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0); 787 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 788 789 udelay(100); 790 } 791 792 return sdma_v6_0_start(adev); 793 } 794 795 static bool sdma_v6_0_check_soft_reset(struct amdgpu_ip_block *ip_block) 796 { 797 struct amdgpu_device *adev = ip_block->adev; 798 struct amdgpu_ring *ring; 799 int i, r; 800 long tmo = msecs_to_jiffies(1000); 801 802 for (i = 0; i < adev->sdma.num_instances; i++) { 803 ring = &adev->sdma.instance[i].ring; 804 r = amdgpu_ring_test_ib(ring, tmo); 805 if (r) 806 return true; 807 } 808 809 return false; 810 } 811 812 /** 813 * sdma_v6_0_start - setup and start the async dma engines 814 * 815 * @adev: amdgpu_device pointer 816 * 817 * Set up the DMA engines and enable them. 818 * Returns 0 for success, error for failure. 819 */ 820 static int sdma_v6_0_start(struct amdgpu_device *adev) 821 { 822 int r = 0; 823 824 if (amdgpu_sriov_vf(adev)) { 825 sdma_v6_0_enable(adev, false); 826 827 /* set RB registers */ 828 r = sdma_v6_0_gfx_resume(adev); 829 return r; 830 } 831 832 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 833 r = sdma_v6_0_load_microcode(adev); 834 if (r) 835 return r; 836 837 /* The value of regSDMA_F32_CNTL is invalid the moment after loading fw */ 838 if (amdgpu_emu_mode == 1) 839 msleep(1000); 840 } 841 842 /* unhalt the MEs */ 843 sdma_v6_0_enable(adev, true); 844 /* enable sdma ring preemption */ 845 sdma_v6_0_ctxempty_int_enable(adev, true); 846 847 /* start the gfx rings and rlc compute queues */ 848 r = sdma_v6_0_gfx_resume(adev); 849 if (r) 850 return r; 851 r = sdma_v6_0_rlc_resume(adev); 852 853 return r; 854 } 855 856 static int sdma_v6_0_mqd_init(struct amdgpu_device *adev, void *mqd, 857 struct amdgpu_mqd_prop *prop) 858 { 859 struct v11_sdma_mqd *m = mqd; 860 uint64_t wb_gpu_addr; 861 862 m->sdmax_rlcx_rb_cntl = 863 order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT | 864 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 865 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | 866 1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT; 867 868 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8); 869 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); 870 871 wb_gpu_addr = prop->wptr_gpu_addr; 872 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); 873 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); 874 875 wb_gpu_addr = prop->rptr_gpu_addr; 876 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); 877 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); 878 879 m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 0, 880 regSDMA0_QUEUE0_IB_CNTL)); 881 882 m->sdmax_rlcx_doorbell_offset = 883 prop->doorbell_index << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 884 885 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 886 887 m->sdmax_rlcx_skip_cntl = 0; 888 m->sdmax_rlcx_context_status = 0; 889 m->sdmax_rlcx_doorbell_log = 0; 890 891 m->sdmax_rlcx_rb_aql_cntl = regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT; 892 m->sdmax_rlcx_dummy_reg = regSDMA0_QUEUE0_DUMMY_REG_DEFAULT; 893 894 m->sdmax_rlcx_csa_addr_lo = lower_32_bits(prop->csa_addr); 895 m->sdmax_rlcx_csa_addr_hi = upper_32_bits(prop->csa_addr); 896 897 m->sdmax_rlcx_f32_dbg0 = lower_32_bits(prop->fence_address); 898 m->sdmax_rlcx_f32_dbg1 = upper_32_bits(prop->fence_address); 899 900 return 0; 901 } 902 903 static void sdma_v6_0_set_mqd_funcs(struct amdgpu_device *adev) 904 { 905 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v11_sdma_mqd); 906 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v6_0_mqd_init; 907 } 908 909 /** 910 * sdma_v6_0_ring_test_ring - simple async dma engine test 911 * 912 * @ring: amdgpu_ring structure holding ring information 913 * 914 * Test the DMA engine by writing using it to write an 915 * value to memory. 916 * Returns 0 for success, error for failure. 917 */ 918 static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring) 919 { 920 struct amdgpu_device *adev = ring->adev; 921 unsigned i; 922 unsigned index; 923 int r; 924 u32 tmp; 925 u64 gpu_addr; 926 927 tmp = 0xCAFEDEAD; 928 929 r = amdgpu_device_wb_get(adev, &index); 930 if (r) { 931 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 932 return r; 933 } 934 935 gpu_addr = adev->wb.gpu_addr + (index * 4); 936 adev->wb.wb[index] = cpu_to_le32(tmp); 937 938 r = amdgpu_ring_alloc(ring, 5); 939 if (r) { 940 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 941 amdgpu_device_wb_free(adev, index); 942 return r; 943 } 944 945 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 946 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 947 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 948 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 949 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 950 amdgpu_ring_write(ring, 0xDEADBEEF); 951 amdgpu_ring_commit(ring); 952 953 for (i = 0; i < adev->usec_timeout; i++) { 954 tmp = le32_to_cpu(adev->wb.wb[index]); 955 if (tmp == 0xDEADBEEF) 956 break; 957 if (amdgpu_emu_mode == 1) 958 msleep(1); 959 else 960 udelay(1); 961 } 962 963 if (i >= adev->usec_timeout) 964 r = -ETIMEDOUT; 965 966 amdgpu_device_wb_free(adev, index); 967 968 return r; 969 } 970 971 /* 972 * sdma_v6_0_ring_test_ib - test an IB on the DMA engine 973 * 974 * @ring: amdgpu_ring structure holding ring information 975 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 976 * 977 * Test a simple IB in the DMA ring. 978 * Returns 0 on success, error on failure. 979 */ 980 static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 981 { 982 struct amdgpu_device *adev = ring->adev; 983 struct amdgpu_ib ib; 984 struct dma_fence *f = NULL; 985 unsigned index; 986 long r; 987 u32 tmp = 0; 988 u64 gpu_addr; 989 990 tmp = 0xCAFEDEAD; 991 memset(&ib, 0, sizeof(ib)); 992 993 r = amdgpu_device_wb_get(adev, &index); 994 if (r) { 995 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 996 return r; 997 } 998 999 gpu_addr = adev->wb.gpu_addr + (index * 4); 1000 adev->wb.wb[index] = cpu_to_le32(tmp); 1001 1002 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 1003 if (r) { 1004 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 1005 goto err0; 1006 } 1007 1008 ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 1009 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1010 ib.ptr[1] = lower_32_bits(gpu_addr); 1011 ib.ptr[2] = upper_32_bits(gpu_addr); 1012 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1013 ib.ptr[4] = 0xDEADBEEF; 1014 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1015 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1016 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1017 ib.length_dw = 8; 1018 1019 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1020 if (r) 1021 goto err1; 1022 1023 r = dma_fence_wait_timeout(f, false, timeout); 1024 if (r == 0) { 1025 DRM_ERROR("amdgpu: IB test timed out\n"); 1026 r = -ETIMEDOUT; 1027 goto err1; 1028 } else if (r < 0) { 1029 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1030 goto err1; 1031 } 1032 1033 tmp = le32_to_cpu(adev->wb.wb[index]); 1034 1035 if (tmp == 0xDEADBEEF) 1036 r = 0; 1037 else 1038 r = -EINVAL; 1039 1040 err1: 1041 amdgpu_ib_free(&ib, NULL); 1042 dma_fence_put(f); 1043 err0: 1044 amdgpu_device_wb_free(adev, index); 1045 return r; 1046 } 1047 1048 1049 /** 1050 * sdma_v6_0_vm_copy_pte - update PTEs by copying them from the GART 1051 * 1052 * @ib: indirect buffer to fill with commands 1053 * @pe: addr of the page entry 1054 * @src: src addr to copy from 1055 * @count: number of page entries to update 1056 * 1057 * Update PTEs by copying them from the GART using sDMA. 1058 */ 1059 static void sdma_v6_0_vm_copy_pte(struct amdgpu_ib *ib, 1060 uint64_t pe, uint64_t src, 1061 unsigned count) 1062 { 1063 unsigned bytes = count * 8; 1064 1065 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1066 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1067 ib->ptr[ib->length_dw++] = bytes - 1; 1068 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1069 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1070 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1071 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1072 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1073 1074 } 1075 1076 /** 1077 * sdma_v6_0_vm_write_pte - update PTEs by writing them manually 1078 * 1079 * @ib: indirect buffer to fill with commands 1080 * @pe: addr of the page entry 1081 * @value: dst addr to write into pe 1082 * @count: number of page entries to update 1083 * @incr: increase next addr by incr bytes 1084 * 1085 * Update PTEs by writing them manually using sDMA. 1086 */ 1087 static void sdma_v6_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1088 uint64_t value, unsigned count, 1089 uint32_t incr) 1090 { 1091 unsigned ndw = count * 2; 1092 1093 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 1094 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1095 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1096 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1097 ib->ptr[ib->length_dw++] = ndw - 1; 1098 for (; ndw > 0; ndw -= 2) { 1099 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1100 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1101 value += incr; 1102 } 1103 } 1104 1105 /** 1106 * sdma_v6_0_vm_set_pte_pde - update the page tables using sDMA 1107 * 1108 * @ib: indirect buffer to fill with commands 1109 * @pe: addr of the page entry 1110 * @addr: dst addr to write into pe 1111 * @count: number of page entries to update 1112 * @incr: increase next addr by incr bytes 1113 * @flags: access flags 1114 * 1115 * Update the page tables using sDMA. 1116 */ 1117 static void sdma_v6_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1118 uint64_t pe, 1119 uint64_t addr, unsigned count, 1120 uint32_t incr, uint64_t flags) 1121 { 1122 /* for physically contiguous pages (vram) */ 1123 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE); 1124 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1125 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1126 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1127 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1128 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1129 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1130 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1131 ib->ptr[ib->length_dw++] = 0; 1132 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1133 } 1134 1135 /* 1136 * sdma_v6_0_ring_pad_ib - pad the IB 1137 * @ib: indirect buffer to fill with padding 1138 * @ring: amdgpu ring pointer 1139 * 1140 * Pad the IB with NOPs to a boundary multiple of 8. 1141 */ 1142 static void sdma_v6_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1143 { 1144 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1145 u32 pad_count; 1146 int i; 1147 1148 pad_count = (-ib->length_dw) & 0x7; 1149 for (i = 0; i < pad_count; i++) 1150 if (sdma && sdma->burst_nop && (i == 0)) 1151 ib->ptr[ib->length_dw++] = 1152 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) | 1153 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1154 else 1155 ib->ptr[ib->length_dw++] = 1156 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP); 1157 } 1158 1159 /** 1160 * sdma_v6_0_ring_emit_pipeline_sync - sync the pipeline 1161 * 1162 * @ring: amdgpu_ring pointer 1163 * 1164 * Make sure all previous operations are completed (CIK). 1165 */ 1166 static void sdma_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1167 { 1168 uint32_t seq = ring->fence_drv.sync_seq; 1169 uint64_t addr = ring->fence_drv.gpu_addr; 1170 1171 /* wait for idle */ 1172 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1173 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1174 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1175 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1176 amdgpu_ring_write(ring, addr & 0xfffffffc); 1177 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1178 amdgpu_ring_write(ring, seq); /* reference */ 1179 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1180 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1181 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1182 } 1183 1184 /* 1185 * sdma_v6_0_ring_emit_vm_flush - vm flush using sDMA 1186 * 1187 * @ring: amdgpu_ring pointer 1188 * @vmid: vmid number to use 1189 * @pd_addr: address 1190 * 1191 * Update the page table base and flush the VM TLB 1192 * using sDMA. 1193 */ 1194 static void sdma_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1195 unsigned vmid, uint64_t pd_addr) 1196 { 1197 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1198 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 1199 1200 /* Update the PD address for this VMID. */ 1201 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 1202 (hub->ctx_addr_distance * vmid), 1203 lower_32_bits(pd_addr)); 1204 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 1205 (hub->ctx_addr_distance * vmid), 1206 upper_32_bits(pd_addr)); 1207 1208 /* Trigger invalidation. */ 1209 amdgpu_ring_write(ring, 1210 SDMA_PKT_VM_INVALIDATION_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1211 SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(SDMA_SUBOP_VM_INVALIDATION) | 1212 SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(ring->vm_inv_eng) | 1213 SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(0x1f)); 1214 amdgpu_ring_write(ring, req); 1215 amdgpu_ring_write(ring, 0xFFFFFFFF); 1216 amdgpu_ring_write(ring, 1217 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(1 << vmid) | 1218 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(0x1F)); 1219 } 1220 1221 static void sdma_v6_0_ring_emit_wreg(struct amdgpu_ring *ring, 1222 uint32_t reg, uint32_t val) 1223 { 1224 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1225 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1226 amdgpu_ring_write(ring, reg); 1227 amdgpu_ring_write(ring, val); 1228 } 1229 1230 static void sdma_v6_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1231 uint32_t val, uint32_t mask) 1232 { 1233 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1234 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1235 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1236 amdgpu_ring_write(ring, reg << 2); 1237 amdgpu_ring_write(ring, 0); 1238 amdgpu_ring_write(ring, val); /* reference */ 1239 amdgpu_ring_write(ring, mask); /* mask */ 1240 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1241 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1242 } 1243 1244 static void sdma_v6_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1245 uint32_t reg0, uint32_t reg1, 1246 uint32_t ref, uint32_t mask) 1247 { 1248 amdgpu_ring_emit_wreg(ring, reg0, ref); 1249 /* wait for a cycle to reset vm_inv_eng*_ack */ 1250 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1251 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1252 } 1253 1254 static struct amdgpu_sdma_ras sdma_v6_0_3_ras = { 1255 .ras_block = { 1256 .ras_late_init = amdgpu_ras_block_late_init, 1257 }, 1258 }; 1259 1260 static void sdma_v6_0_set_ras_funcs(struct amdgpu_device *adev) 1261 { 1262 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1263 case IP_VERSION(6, 0, 3): 1264 adev->sdma.ras = &sdma_v6_0_3_ras; 1265 break; 1266 default: 1267 break; 1268 } 1269 } 1270 1271 static int sdma_v6_0_early_init(struct amdgpu_ip_block *ip_block) 1272 { 1273 struct amdgpu_device *adev = ip_block->adev; 1274 int r; 1275 1276 switch (amdgpu_user_queue) { 1277 case -1: 1278 case 0: 1279 default: 1280 adev->sdma.no_user_submission = false; 1281 adev->sdma.disable_uq = true; 1282 break; 1283 case 1: 1284 adev->sdma.no_user_submission = false; 1285 adev->sdma.disable_uq = false; 1286 break; 1287 case 2: 1288 adev->sdma.no_user_submission = true; 1289 adev->sdma.disable_uq = false; 1290 break; 1291 } 1292 1293 r = amdgpu_sdma_init_microcode(adev, 0, true); 1294 if (r) 1295 return r; 1296 1297 sdma_v6_0_set_ring_funcs(adev); 1298 sdma_v6_0_set_buffer_funcs(adev); 1299 sdma_v6_0_set_vm_pte_funcs(adev); 1300 sdma_v6_0_set_irq_funcs(adev); 1301 sdma_v6_0_set_mqd_funcs(adev); 1302 sdma_v6_0_set_ras_funcs(adev); 1303 1304 return 0; 1305 } 1306 1307 static int sdma_v6_0_sw_init(struct amdgpu_ip_block *ip_block) 1308 { 1309 struct amdgpu_ring *ring; 1310 int r, i; 1311 struct amdgpu_device *adev = ip_block->adev; 1312 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0); 1313 uint32_t *ptr; 1314 1315 /* SDMA trap event */ 1316 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1317 GFX_11_0_0__SRCID__SDMA_TRAP, 1318 &adev->sdma.trap_irq); 1319 if (r) 1320 return r; 1321 1322 /* SDMA user fence event */ 1323 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1324 GFX_11_0_0__SRCID__SDMA_FENCE, 1325 &adev->sdma.fence_irq); 1326 if (r) 1327 return r; 1328 1329 for (i = 0; i < adev->sdma.num_instances; i++) { 1330 ring = &adev->sdma.instance[i].ring; 1331 ring->ring_obj = NULL; 1332 ring->use_doorbell = true; 1333 ring->me = i; 1334 ring->no_user_submission = adev->sdma.no_user_submission; 1335 1336 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1337 ring->use_doorbell?"true":"false"); 1338 1339 ring->doorbell_index = 1340 (adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset 1341 1342 ring->vm_hub = AMDGPU_GFXHUB(0); 1343 sprintf(ring->name, "sdma%d", i); 1344 r = amdgpu_ring_init(adev, ring, 1024, 1345 &adev->sdma.trap_irq, 1346 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1347 AMDGPU_RING_PRIO_DEFAULT, NULL); 1348 if (r) 1349 return r; 1350 } 1351 1352 adev->sdma.supported_reset = 1353 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); 1354 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1355 case IP_VERSION(6, 0, 0): 1356 case IP_VERSION(6, 0, 2): 1357 case IP_VERSION(6, 0, 3): 1358 if ((adev->sdma.instance[0].fw_version >= 21) && 1359 !amdgpu_sriov_vf(adev)) 1360 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1361 break; 1362 default: 1363 break; 1364 } 1365 1366 if (amdgpu_sdma_ras_sw_init(adev)) { 1367 dev_err(adev->dev, "Failed to initialize sdma ras block!\n"); 1368 return -EINVAL; 1369 } 1370 1371 /* Allocate memory for SDMA IP Dump buffer */ 1372 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); 1373 if (ptr) 1374 adev->sdma.ip_dump = ptr; 1375 else 1376 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n"); 1377 1378 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1379 case IP_VERSION(6, 0, 0): 1380 if ((adev->sdma.instance[0].fw_version >= 24) && !adev->sdma.disable_uq) 1381 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1382 break; 1383 case IP_VERSION(6, 0, 1): 1384 if ((adev->sdma.instance[0].fw_version >= 18) && !adev->sdma.disable_uq) 1385 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1386 break; 1387 case IP_VERSION(6, 0, 2): 1388 if ((adev->sdma.instance[0].fw_version >= 21) && !adev->sdma.disable_uq) 1389 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1390 break; 1391 case IP_VERSION(6, 0, 3): 1392 if ((adev->sdma.instance[0].fw_version >= 25) && !adev->sdma.disable_uq) 1393 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1394 break; 1395 case IP_VERSION(6, 1, 0): 1396 if ((adev->sdma.instance[0].fw_version >= 14) && !adev->sdma.disable_uq) 1397 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1398 break; 1399 case IP_VERSION(6, 1, 1): 1400 if ((adev->sdma.instance[0].fw_version >= 17) && !adev->sdma.disable_uq) 1401 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1402 break; 1403 case IP_VERSION(6, 1, 2): 1404 if ((adev->sdma.instance[0].fw_version >= 15) && !adev->sdma.disable_uq) 1405 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1406 break; 1407 case IP_VERSION(6, 1, 3): 1408 if ((adev->sdma.instance[0].fw_version >= 10) && !adev->sdma.disable_uq) 1409 adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; 1410 break; 1411 default: 1412 break; 1413 } 1414 1415 r = amdgpu_sdma_sysfs_reset_mask_init(adev); 1416 if (r) 1417 return r; 1418 1419 return r; 1420 } 1421 1422 static int sdma_v6_0_sw_fini(struct amdgpu_ip_block *ip_block) 1423 { 1424 struct amdgpu_device *adev = ip_block->adev; 1425 int i; 1426 1427 for (i = 0; i < adev->sdma.num_instances; i++) 1428 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1429 1430 amdgpu_sdma_sysfs_reset_mask_fini(adev); 1431 amdgpu_sdma_destroy_inst_ctx(adev, true); 1432 1433 kfree(adev->sdma.ip_dump); 1434 1435 return 0; 1436 } 1437 1438 static int sdma_v6_0_set_userq_trap_interrupts(struct amdgpu_device *adev, 1439 bool enable) 1440 { 1441 unsigned int irq_type; 1442 int i, r; 1443 1444 if (adev->userq_funcs[AMDGPU_HW_IP_DMA]) { 1445 for (i = 0; i < adev->sdma.num_instances; i++) { 1446 irq_type = AMDGPU_SDMA_IRQ_INSTANCE0 + i; 1447 if (enable) 1448 r = amdgpu_irq_get(adev, &adev->sdma.trap_irq, 1449 irq_type); 1450 else 1451 r = amdgpu_irq_put(adev, &adev->sdma.trap_irq, 1452 irq_type); 1453 if (r) 1454 return r; 1455 } 1456 } 1457 1458 return 0; 1459 } 1460 1461 static int sdma_v6_0_hw_init(struct amdgpu_ip_block *ip_block) 1462 { 1463 struct amdgpu_device *adev = ip_block->adev; 1464 int r; 1465 1466 r = sdma_v6_0_start(adev); 1467 if (r) 1468 return r; 1469 1470 return sdma_v6_0_set_userq_trap_interrupts(adev, true); 1471 } 1472 1473 static int sdma_v6_0_hw_fini(struct amdgpu_ip_block *ip_block) 1474 { 1475 struct amdgpu_device *adev = ip_block->adev; 1476 1477 if (amdgpu_sriov_vf(adev)) 1478 return 0; 1479 1480 sdma_v6_0_ctxempty_int_enable(adev, false); 1481 sdma_v6_0_enable(adev, false); 1482 sdma_v6_0_set_userq_trap_interrupts(adev, false); 1483 1484 return 0; 1485 } 1486 1487 static int sdma_v6_0_suspend(struct amdgpu_ip_block *ip_block) 1488 { 1489 return sdma_v6_0_hw_fini(ip_block); 1490 } 1491 1492 static int sdma_v6_0_resume(struct amdgpu_ip_block *ip_block) 1493 { 1494 return sdma_v6_0_hw_init(ip_block); 1495 } 1496 1497 static bool sdma_v6_0_is_idle(struct amdgpu_ip_block *ip_block) 1498 { 1499 struct amdgpu_device *adev = ip_block->adev; 1500 u32 i; 1501 1502 for (i = 0; i < adev->sdma.num_instances; i++) { 1503 u32 tmp = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG)); 1504 1505 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1506 return false; 1507 } 1508 1509 return true; 1510 } 1511 1512 static int sdma_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1513 { 1514 unsigned i; 1515 u32 sdma0, sdma1; 1516 struct amdgpu_device *adev = ip_block->adev; 1517 1518 for (i = 0; i < adev->usec_timeout; i++) { 1519 sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG)); 1520 sdma1 = RREG32(sdma_v6_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG)); 1521 1522 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1523 return 0; 1524 udelay(1); 1525 } 1526 return -ETIMEDOUT; 1527 } 1528 1529 static int sdma_v6_0_ring_preempt_ib(struct amdgpu_ring *ring) 1530 { 1531 int i, r = 0; 1532 struct amdgpu_device *adev = ring->adev; 1533 u32 index = 0; 1534 u64 sdma_gfx_preempt; 1535 1536 amdgpu_sdma_get_index_from_ring(ring, &index); 1537 sdma_gfx_preempt = 1538 sdma_v6_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT); 1539 1540 /* assert preemption condition */ 1541 amdgpu_ring_set_preempt_cond_exec(ring, false); 1542 1543 /* emit the trailing fence */ 1544 ring->trail_seq += 1; 1545 amdgpu_ring_alloc(ring, 10); 1546 sdma_v6_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1547 ring->trail_seq, 0); 1548 amdgpu_ring_commit(ring); 1549 1550 /* assert IB preemption */ 1551 WREG32(sdma_gfx_preempt, 1); 1552 1553 /* poll the trailing fence */ 1554 for (i = 0; i < adev->usec_timeout; i++) { 1555 if (ring->trail_seq == 1556 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1557 break; 1558 udelay(1); 1559 } 1560 1561 if (i >= adev->usec_timeout) { 1562 r = -EINVAL; 1563 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1564 } 1565 1566 /* deassert IB preemption */ 1567 WREG32(sdma_gfx_preempt, 0); 1568 1569 /* deassert the preemption condition */ 1570 amdgpu_ring_set_preempt_cond_exec(ring, true); 1571 return r; 1572 } 1573 1574 static int sdma_v6_0_reset_queue(struct amdgpu_ring *ring, 1575 unsigned int vmid, 1576 struct amdgpu_fence *timedout_fence) 1577 { 1578 struct amdgpu_device *adev = ring->adev; 1579 int r; 1580 1581 if (ring->me >= adev->sdma.num_instances) { 1582 dev_err(adev->dev, "sdma instance not found\n"); 1583 return -EINVAL; 1584 } 1585 1586 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 1587 1588 r = amdgpu_mes_reset_legacy_queue(adev, ring, vmid, true); 1589 if (r) 1590 return r; 1591 1592 r = sdma_v6_0_gfx_resume_instance(adev, ring->me, true); 1593 if (r) 1594 return r; 1595 1596 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 1597 } 1598 1599 static int sdma_v6_0_set_trap_irq_state(struct amdgpu_device *adev, 1600 struct amdgpu_irq_src *source, 1601 unsigned type, 1602 enum amdgpu_interrupt_state state) 1603 { 1604 u32 sdma_cntl; 1605 1606 u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL); 1607 1608 if (!amdgpu_sriov_vf(adev)) { 1609 sdma_cntl = RREG32(reg_offset); 1610 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1611 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1612 WREG32(reg_offset, sdma_cntl); 1613 } 1614 1615 return 0; 1616 } 1617 1618 static int sdma_v6_0_process_trap_irq(struct amdgpu_device *adev, 1619 struct amdgpu_irq_src *source, 1620 struct amdgpu_iv_entry *entry) 1621 { 1622 int instances, queue; 1623 1624 DRM_DEBUG("IH: SDMA trap\n"); 1625 1626 queue = entry->ring_id & 0xf; 1627 instances = (entry->ring_id & 0xf0) >> 4; 1628 if (instances > 1) { 1629 DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n"); 1630 return -EINVAL; 1631 } 1632 1633 switch (entry->client_id) { 1634 case SOC21_IH_CLIENTID_GFX: 1635 switch (queue) { 1636 case 0: 1637 amdgpu_fence_process(&adev->sdma.instance[instances].ring); 1638 break; 1639 default: 1640 break; 1641 } 1642 break; 1643 } 1644 return 0; 1645 } 1646 1647 static int sdma_v6_0_process_fence_irq(struct amdgpu_device *adev, 1648 struct amdgpu_irq_src *source, 1649 struct amdgpu_iv_entry *entry) 1650 { 1651 u32 doorbell_offset = entry->src_data[0]; 1652 1653 if (adev->enable_mes && doorbell_offset) { 1654 struct amdgpu_userq_fence_driver *fence_drv = NULL; 1655 struct xarray *xa = &adev->userq_xa; 1656 unsigned long flags; 1657 1658 doorbell_offset >>= SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 1659 1660 xa_lock_irqsave(xa, flags); 1661 fence_drv = xa_load(xa, doorbell_offset); 1662 if (fence_drv) 1663 amdgpu_userq_fence_driver_process(fence_drv); 1664 xa_unlock_irqrestore(xa, flags); 1665 } 1666 1667 return 0; 1668 } 1669 1670 static int sdma_v6_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1671 struct amdgpu_irq_src *source, 1672 struct amdgpu_iv_entry *entry) 1673 { 1674 return 0; 1675 } 1676 1677 static int sdma_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1678 enum amd_clockgating_state state) 1679 { 1680 return 0; 1681 } 1682 1683 static int sdma_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 1684 enum amd_powergating_state state) 1685 { 1686 return 0; 1687 } 1688 1689 static void sdma_v6_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1690 { 1691 } 1692 1693 static void sdma_v6_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 1694 { 1695 struct amdgpu_device *adev = ip_block->adev; 1696 int i, j; 1697 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0); 1698 uint32_t instance_offset; 1699 1700 if (!adev->sdma.ip_dump) 1701 return; 1702 1703 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances); 1704 for (i = 0; i < adev->sdma.num_instances; i++) { 1705 instance_offset = i * reg_count; 1706 drm_printf(p, "\nInstance:%d\n", i); 1707 1708 for (j = 0; j < reg_count; j++) 1709 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_6_0[j].reg_name, 1710 adev->sdma.ip_dump[instance_offset + j]); 1711 } 1712 } 1713 1714 static void sdma_v6_0_dump_ip_state(struct amdgpu_ip_block *ip_block) 1715 { 1716 struct amdgpu_device *adev = ip_block->adev; 1717 int i, j; 1718 uint32_t instance_offset; 1719 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0); 1720 1721 if (!adev->sdma.ip_dump) 1722 return; 1723 1724 amdgpu_gfx_off_ctrl(adev, false); 1725 for (i = 0; i < adev->sdma.num_instances; i++) { 1726 instance_offset = i * reg_count; 1727 for (j = 0; j < reg_count; j++) 1728 adev->sdma.ip_dump[instance_offset + j] = 1729 RREG32(sdma_v6_0_get_reg_offset(adev, i, 1730 sdma_reg_list_6_0[j].reg_offset)); 1731 } 1732 amdgpu_gfx_off_ctrl(adev, true); 1733 } 1734 1735 const struct amd_ip_funcs sdma_v6_0_ip_funcs = { 1736 .name = "sdma_v6_0", 1737 .early_init = sdma_v6_0_early_init, 1738 .sw_init = sdma_v6_0_sw_init, 1739 .sw_fini = sdma_v6_0_sw_fini, 1740 .hw_init = sdma_v6_0_hw_init, 1741 .hw_fini = sdma_v6_0_hw_fini, 1742 .suspend = sdma_v6_0_suspend, 1743 .resume = sdma_v6_0_resume, 1744 .is_idle = sdma_v6_0_is_idle, 1745 .wait_for_idle = sdma_v6_0_wait_for_idle, 1746 .soft_reset = sdma_v6_0_soft_reset, 1747 .check_soft_reset = sdma_v6_0_check_soft_reset, 1748 .set_clockgating_state = sdma_v6_0_set_clockgating_state, 1749 .set_powergating_state = sdma_v6_0_set_powergating_state, 1750 .get_clockgating_state = sdma_v6_0_get_clockgating_state, 1751 .dump_ip_state = sdma_v6_0_dump_ip_state, 1752 .print_ip_state = sdma_v6_0_print_ip_state, 1753 }; 1754 1755 static const struct amdgpu_ring_funcs sdma_v6_0_ring_funcs = { 1756 .type = AMDGPU_RING_TYPE_SDMA, 1757 .align_mask = 0xf, 1758 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1759 .support_64bit_ptrs = true, 1760 .secure_submission_supported = true, 1761 .get_rptr = sdma_v6_0_ring_get_rptr, 1762 .get_wptr = sdma_v6_0_ring_get_wptr, 1763 .set_wptr = sdma_v6_0_ring_set_wptr, 1764 .emit_frame_size = 1765 5 + /* sdma_v6_0_ring_init_cond_exec */ 1766 6 + /* sdma_v6_0_ring_emit_hdp_flush */ 1767 6 + /* sdma_v6_0_ring_emit_pipeline_sync */ 1768 /* sdma_v6_0_ring_emit_vm_flush */ 1769 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1770 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1771 10 + 10 + 10, /* sdma_v6_0_ring_emit_fence x3 for user fence, vm fence */ 1772 .emit_ib_size = 5 + 7 + 6, /* sdma_v6_0_ring_emit_ib */ 1773 .emit_ib = sdma_v6_0_ring_emit_ib, 1774 .emit_mem_sync = sdma_v6_0_ring_emit_mem_sync, 1775 .emit_fence = sdma_v6_0_ring_emit_fence, 1776 .emit_pipeline_sync = sdma_v6_0_ring_emit_pipeline_sync, 1777 .emit_vm_flush = sdma_v6_0_ring_emit_vm_flush, 1778 .emit_hdp_flush = sdma_v6_0_ring_emit_hdp_flush, 1779 .test_ring = sdma_v6_0_ring_test_ring, 1780 .test_ib = sdma_v6_0_ring_test_ib, 1781 .insert_nop = sdma_v6_0_ring_insert_nop, 1782 .pad_ib = sdma_v6_0_ring_pad_ib, 1783 .emit_wreg = sdma_v6_0_ring_emit_wreg, 1784 .emit_reg_wait = sdma_v6_0_ring_emit_reg_wait, 1785 .emit_reg_write_reg_wait = sdma_v6_0_ring_emit_reg_write_reg_wait, 1786 .init_cond_exec = sdma_v6_0_ring_init_cond_exec, 1787 .preempt_ib = sdma_v6_0_ring_preempt_ib, 1788 .reset = sdma_v6_0_reset_queue, 1789 }; 1790 1791 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev) 1792 { 1793 int i; 1794 1795 for (i = 0; i < adev->sdma.num_instances; i++) { 1796 adev->sdma.instance[i].ring.funcs = &sdma_v6_0_ring_funcs; 1797 adev->sdma.instance[i].ring.me = i; 1798 } 1799 } 1800 1801 static const struct amdgpu_irq_src_funcs sdma_v6_0_trap_irq_funcs = { 1802 .set = sdma_v6_0_set_trap_irq_state, 1803 .process = sdma_v6_0_process_trap_irq, 1804 }; 1805 1806 static const struct amdgpu_irq_src_funcs sdma_v6_0_fence_irq_funcs = { 1807 .process = sdma_v6_0_process_fence_irq, 1808 }; 1809 1810 static const struct amdgpu_irq_src_funcs sdma_v6_0_illegal_inst_irq_funcs = { 1811 .process = sdma_v6_0_process_illegal_inst_irq, 1812 }; 1813 1814 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev) 1815 { 1816 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1817 adev->sdma.num_instances; 1818 adev->sdma.trap_irq.funcs = &sdma_v6_0_trap_irq_funcs; 1819 adev->sdma.fence_irq.funcs = &sdma_v6_0_fence_irq_funcs; 1820 adev->sdma.illegal_inst_irq.funcs = &sdma_v6_0_illegal_inst_irq_funcs; 1821 } 1822 1823 /** 1824 * sdma_v6_0_emit_copy_buffer - copy buffer using the sDMA engine 1825 * 1826 * @ib: indirect buffer to fill with commands 1827 * @src_offset: src GPU address 1828 * @dst_offset: dst GPU address 1829 * @byte_count: number of bytes to xfer 1830 * @copy_flags: copy flags for the buffers 1831 * 1832 * Copy GPU buffers using the DMA engine. 1833 * Used by the amdgpu ttm implementation to move pages if 1834 * registered as the asic copy callback. 1835 */ 1836 static void sdma_v6_0_emit_copy_buffer(struct amdgpu_ib *ib, 1837 uint64_t src_offset, 1838 uint64_t dst_offset, 1839 uint32_t byte_count, 1840 uint32_t copy_flags) 1841 { 1842 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1843 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1844 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0); 1845 ib->ptr[ib->length_dw++] = byte_count - 1; 1846 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1847 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1848 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1849 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1850 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1851 } 1852 1853 /** 1854 * sdma_v6_0_emit_fill_buffer - fill buffer using the sDMA engine 1855 * 1856 * @ib: indirect buffer to fill 1857 * @src_data: value to write to buffer 1858 * @dst_offset: dst GPU address 1859 * @byte_count: number of bytes to xfer 1860 * 1861 * Fill GPU buffers using the DMA engine. 1862 */ 1863 static void sdma_v6_0_emit_fill_buffer(struct amdgpu_ib *ib, 1864 uint32_t src_data, 1865 uint64_t dst_offset, 1866 uint32_t byte_count) 1867 { 1868 ib->ptr[ib->length_dw++] = SDMA_PKT_CONSTANT_FILL_HEADER_OP(SDMA_OP_CONST_FILL); 1869 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1870 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1871 ib->ptr[ib->length_dw++] = src_data; 1872 ib->ptr[ib->length_dw++] = byte_count - 1; 1873 } 1874 1875 static const struct amdgpu_buffer_funcs sdma_v6_0_buffer_funcs = { 1876 .copy_max_bytes = 0x400000, 1877 .copy_num_dw = 7, 1878 .emit_copy_buffer = sdma_v6_0_emit_copy_buffer, 1879 1880 .fill_max_bytes = 0x400000, 1881 .fill_num_dw = 5, 1882 .emit_fill_buffer = sdma_v6_0_emit_fill_buffer, 1883 }; 1884 1885 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev) 1886 { 1887 adev->mman.buffer_funcs = &sdma_v6_0_buffer_funcs; 1888 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1889 } 1890 1891 static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = { 1892 .copy_pte_num_dw = 7, 1893 .copy_pte = sdma_v6_0_vm_copy_pte, 1894 .write_pte = sdma_v6_0_vm_write_pte, 1895 .set_pte_pde = sdma_v6_0_vm_set_pte_pde, 1896 }; 1897 1898 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1899 { 1900 unsigned i; 1901 1902 adev->vm_manager.vm_pte_funcs = &sdma_v6_0_vm_pte_funcs; 1903 for (i = 0; i < adev->sdma.num_instances; i++) { 1904 adev->vm_manager.vm_pte_scheds[i] = 1905 &adev->sdma.instance[i].ring.sched; 1906 } 1907 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1908 } 1909 1910 const struct amdgpu_ip_block_version sdma_v6_0_ip_block = { 1911 .type = AMD_IP_BLOCK_TYPE_SDMA, 1912 .major = 6, 1913 .minor = 0, 1914 .rev = 0, 1915 .funcs = &sdma_v6_0_ip_funcs, 1916 }; 1917