1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_10_3_0_offset.h" 34 #include "gc/gc_10_3_0_sh_mask.h" 35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h" 36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h" 37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h" 38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h" 39 40 #include "soc15_common.h" 41 #include "soc15.h" 42 #include "navi10_sdma_pkt_open.h" 43 #include "nbio_v2_3.h" 44 #include "sdma_common.h" 45 #include "sdma_v5_2.h" 46 47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin"); 48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin"); 49 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin"); 50 MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin"); 51 52 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin"); 53 MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin"); 54 MODULE_FIRMWARE("amdgpu/sdma_5_2_6.bin"); 55 MODULE_FIRMWARE("amdgpu/sdma_5_2_7.bin"); 56 57 #define SDMA1_REG_OFFSET 0x600 58 #define SDMA3_REG_OFFSET 0x400 59 #define SDMA0_HYP_DEC_REG_START 0x5880 60 #define SDMA0_HYP_DEC_REG_END 0x5893 61 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 62 63 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev); 64 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev); 65 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev); 66 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev); 67 68 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 69 { 70 u32 base; 71 72 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 73 internal_offset <= SDMA0_HYP_DEC_REG_END) { 74 base = adev->reg_offset[GC_HWIP][0][1]; 75 if (instance != 0) 76 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance; 77 } else { 78 if (instance < 2) { 79 base = adev->reg_offset[GC_HWIP][0][0]; 80 if (instance == 1) 81 internal_offset += SDMA1_REG_OFFSET; 82 } else { 83 base = adev->reg_offset[GC_HWIP][0][2]; 84 if (instance == 3) 85 internal_offset += SDMA3_REG_OFFSET; 86 } 87 } 88 89 return base + internal_offset; 90 } 91 92 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring) 93 { 94 unsigned ret; 95 96 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); 97 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 98 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 99 amdgpu_ring_write(ring, 1); 100 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ 101 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ 102 103 return ret; 104 } 105 106 static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring, 107 unsigned offset) 108 { 109 unsigned cur; 110 111 BUG_ON(offset > ring->buf_mask); 112 BUG_ON(ring->ring[offset] != 0x55aa55aa); 113 114 cur = (ring->wptr - 1) & ring->buf_mask; 115 if (cur > offset) 116 ring->ring[offset] = cur - offset; 117 else 118 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 119 } 120 121 /** 122 * sdma_v5_2_ring_get_rptr - get the current read pointer 123 * 124 * @ring: amdgpu ring pointer 125 * 126 * Get the current rptr from the hardware (NAVI10+). 127 */ 128 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring) 129 { 130 u64 *rptr; 131 132 /* XXX check if swapping is necessary on BE */ 133 rptr = (u64 *)ring->rptr_cpu_addr; 134 135 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 136 return ((*rptr) >> 2); 137 } 138 139 /** 140 * sdma_v5_2_ring_get_wptr - get the current write pointer 141 * 142 * @ring: amdgpu ring pointer 143 * 144 * Get the current wptr from the hardware (NAVI10+). 145 */ 146 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring) 147 { 148 struct amdgpu_device *adev = ring->adev; 149 u64 wptr; 150 151 if (ring->use_doorbell) { 152 /* XXX check if swapping is necessary on BE */ 153 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 154 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 155 } else { 156 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); 157 wptr = wptr << 32; 158 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); 159 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr); 160 } 161 162 return wptr >> 2; 163 } 164 165 /** 166 * sdma_v5_2_ring_set_wptr - commit the write pointer 167 * 168 * @ring: amdgpu ring pointer 169 * 170 * Write the wptr back to the hardware (NAVI10+). 171 */ 172 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring) 173 { 174 struct amdgpu_device *adev = ring->adev; 175 176 DRM_DEBUG("Setting write pointer\n"); 177 if (ring->use_doorbell) { 178 DRM_DEBUG("Using doorbell -- " 179 "wptr_offs == 0x%08x " 180 "lower_32_bits(ring->wptr << 2) == 0x%08x " 181 "upper_32_bits(ring->wptr << 2) == 0x%08x\n", 182 ring->wptr_offs, 183 lower_32_bits(ring->wptr << 2), 184 upper_32_bits(ring->wptr << 2)); 185 /* XXX check if swapping is necessary on BE */ 186 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 187 ring->wptr << 2); 188 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 189 ring->doorbell_index, ring->wptr << 2); 190 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 191 } else { 192 DRM_DEBUG("Not using doorbell -- " 193 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 194 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 195 ring->me, 196 lower_32_bits(ring->wptr << 2), 197 ring->me, 198 upper_32_bits(ring->wptr << 2)); 199 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), 200 lower_32_bits(ring->wptr << 2)); 201 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), 202 upper_32_bits(ring->wptr << 2)); 203 } 204 } 205 206 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 207 { 208 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 209 int i; 210 211 for (i = 0; i < count; i++) 212 if (sdma && sdma->burst_nop && (i == 0)) 213 amdgpu_ring_write(ring, ring->funcs->nop | 214 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 215 else 216 amdgpu_ring_write(ring, ring->funcs->nop); 217 } 218 219 /** 220 * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine 221 * 222 * @ring: amdgpu ring pointer 223 * @job: job to retrieve vmid from 224 * @ib: IB object to schedule 225 * @flags: unused 226 * 227 * Schedule an IB in the DMA ring. 228 */ 229 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring, 230 struct amdgpu_job *job, 231 struct amdgpu_ib *ib, 232 uint32_t flags) 233 { 234 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 235 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 236 237 /* An IB packet must end on a 8 DW boundary--the next dword 238 * must be on a 8-dword boundary. Our IB packet below is 6 239 * dwords long, thus add x number of NOPs, such that, in 240 * modular arithmetic, 241 * wptr + 6 + x = 8k, k >= 0, which in C is, 242 * (wptr + 6 + x) % 8 = 0. 243 * The expression below, is a solution of x. 244 */ 245 sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 246 247 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 248 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 249 /* base must be 32 byte aligned */ 250 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 251 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 252 amdgpu_ring_write(ring, ib->length_dw); 253 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 254 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 255 } 256 257 /** 258 * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse 259 * 260 * @ring: amdgpu ring pointer 261 * 262 * flush the IB by graphics cache rinse. 263 */ 264 static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring) 265 { 266 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | 267 SDMA_GCR_GLM_INV | SDMA_GCR_GL1_INV | 268 SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 269 SDMA_GCR_GLI_INV(1); 270 271 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 272 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ)); 273 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 274 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 275 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 276 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 277 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 278 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 279 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 280 } 281 282 /** 283 * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 284 * 285 * @ring: amdgpu ring pointer 286 * 287 * Emit an hdp flush packet on the requested DMA ring. 288 */ 289 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 290 { 291 struct amdgpu_device *adev = ring->adev; 292 u32 ref_and_mask = 0; 293 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 294 295 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 296 297 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 298 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 299 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 300 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 301 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 302 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 303 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 304 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 305 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 306 } 307 308 /** 309 * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring 310 * 311 * @ring: amdgpu ring pointer 312 * @addr: address 313 * @seq: sequence number 314 * @flags: fence related flags 315 * 316 * Add a DMA fence packet to the ring to write 317 * the fence seq number and DMA trap packet to generate 318 * an interrupt if needed. 319 */ 320 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 321 unsigned flags) 322 { 323 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 324 /* write the fence */ 325 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 326 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 327 /* zero in first two bits */ 328 BUG_ON(addr & 0x3); 329 amdgpu_ring_write(ring, lower_32_bits(addr)); 330 amdgpu_ring_write(ring, upper_32_bits(addr)); 331 amdgpu_ring_write(ring, lower_32_bits(seq)); 332 333 /* optionally write high bits as well */ 334 if (write64bit) { 335 addr += 4; 336 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 337 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 338 /* zero in first two bits */ 339 BUG_ON(addr & 0x3); 340 amdgpu_ring_write(ring, lower_32_bits(addr)); 341 amdgpu_ring_write(ring, upper_32_bits(addr)); 342 amdgpu_ring_write(ring, upper_32_bits(seq)); 343 } 344 345 if ((flags & AMDGPU_FENCE_FLAG_INT)) { 346 uint32_t ctx = ring->is_mes_queue ? 347 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0; 348 /* generate an interrupt */ 349 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 350 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx)); 351 } 352 } 353 354 355 /** 356 * sdma_v5_2_gfx_stop - stop the gfx async dma engines 357 * 358 * @adev: amdgpu_device pointer 359 * 360 * Stop the gfx async dma ring buffers. 361 */ 362 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev) 363 { 364 u32 rb_cntl, ib_cntl; 365 int i; 366 367 for (i = 0; i < adev->sdma.num_instances; i++) { 368 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 369 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 370 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 371 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 372 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 373 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 374 } 375 } 376 377 /** 378 * sdma_v5_2_rlc_stop - stop the compute async dma engines 379 * 380 * @adev: amdgpu_device pointer 381 * 382 * Stop the compute async dma queues. 383 */ 384 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev) 385 { 386 /* XXX todo */ 387 } 388 389 /** 390 * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch 391 * 392 * @adev: amdgpu_device pointer 393 * @enable: enable/disable the DMA MEs context switch. 394 * 395 * Halt or unhalt the async dma engines context switch. 396 */ 397 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 398 { 399 u32 f32_cntl, phase_quantum = 0; 400 int i; 401 402 if (amdgpu_sdma_phase_quantum) { 403 unsigned value = amdgpu_sdma_phase_quantum; 404 unsigned unit = 0; 405 406 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 407 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 408 value = (value + 1) >> 1; 409 unit++; 410 } 411 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 412 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 413 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 414 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 415 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 416 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 417 WARN_ONCE(1, 418 "clamping sdma_phase_quantum to %uK clock cycles\n", 419 value << unit); 420 } 421 phase_quantum = 422 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 423 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 424 } 425 426 for (i = 0; i < adev->sdma.num_instances; i++) { 427 if (enable && amdgpu_sdma_phase_quantum) { 428 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 429 phase_quantum); 430 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 431 phase_quantum); 432 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 433 phase_quantum); 434 } 435 436 if (!amdgpu_sriov_vf(adev)) { 437 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); 438 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 439 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 440 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 441 } 442 } 443 444 } 445 446 /** 447 * sdma_v5_2_enable - stop the async dma engines 448 * 449 * @adev: amdgpu_device pointer 450 * @enable: enable/disable the DMA MEs. 451 * 452 * Halt or unhalt the async dma engines. 453 */ 454 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable) 455 { 456 u32 f32_cntl; 457 int i; 458 459 if (!enable) { 460 sdma_v5_2_gfx_stop(adev); 461 sdma_v5_2_rlc_stop(adev); 462 } 463 464 if (!amdgpu_sriov_vf(adev)) { 465 for (i = 0; i < adev->sdma.num_instances; i++) { 466 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 467 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 468 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 469 } 470 } 471 } 472 473 /** 474 * sdma_v5_2_gfx_resume - setup and start the async dma engines 475 * 476 * @adev: amdgpu_device pointer 477 * 478 * Set up the gfx DMA ring buffers and enable them. 479 * Returns 0 for success, error for failure. 480 */ 481 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) 482 { 483 struct amdgpu_ring *ring; 484 u32 rb_cntl, ib_cntl; 485 u32 rb_bufsz; 486 u32 doorbell; 487 u32 doorbell_offset; 488 u32 temp; 489 u32 wptr_poll_cntl; 490 u64 wptr_gpu_addr; 491 int i, r; 492 493 for (i = 0; i < adev->sdma.num_instances; i++) { 494 ring = &adev->sdma.instance[i].ring; 495 496 if (!amdgpu_sriov_vf(adev)) 497 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 498 499 /* Set ring buffer size in dwords */ 500 rb_bufsz = order_base_2(ring->ring_size / 4); 501 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 502 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 503 #ifdef __BIG_ENDIAN 504 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 505 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 506 RPTR_WRITEBACK_SWAP_ENABLE, 1); 507 #endif 508 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 509 510 /* Initialize the ring buffer's read and write pointers */ 511 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 512 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 513 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 514 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 515 516 /* setup the wptr shadow polling */ 517 wptr_gpu_addr = ring->wptr_gpu_addr; 518 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 519 lower_32_bits(wptr_gpu_addr)); 520 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 521 upper_32_bits(wptr_gpu_addr)); 522 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 523 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 524 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 525 SDMA0_GFX_RB_WPTR_POLL_CNTL, 526 F32_POLL_ENABLE, 1); 527 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 528 wptr_poll_cntl); 529 530 /* set the wb address whether it's enabled or not */ 531 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 532 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 533 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 534 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 535 536 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 537 538 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 539 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 540 541 ring->wptr = 0; 542 543 /* before programing wptr to a less value, need set minor_ptr_update first */ 544 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 545 546 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 547 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); 548 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); 549 } 550 551 doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 552 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); 553 554 if (ring->use_doorbell) { 555 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 556 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 557 OFFSET, ring->doorbell_index); 558 } else { 559 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 560 } 561 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 562 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 563 564 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 565 ring->doorbell_index, 566 adev->doorbell_index.sdma_doorbell_range); 567 568 if (amdgpu_sriov_vf(adev)) 569 sdma_v5_2_ring_set_wptr(ring); 570 571 /* set minor_ptr_update to 0 after wptr programed */ 572 573 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 574 575 /* SRIOV VF has no control of any of registers below */ 576 if (!amdgpu_sriov_vf(adev)) { 577 /* set utc l1 enable flag always to 1 */ 578 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); 579 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 580 581 /* enable MCBP */ 582 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); 583 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 584 585 /* Set up RESP_MODE to non-copy addresses */ 586 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); 587 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 588 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 589 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); 590 591 /* program default cache read and write policy */ 592 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); 593 /* clean read policy and write policy bits */ 594 temp &= 0xFF0FFF; 595 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | 596 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | 597 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK); 598 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); 599 600 /* unhalt engine */ 601 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 602 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 603 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 604 } 605 606 /* enable DMA RB */ 607 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 608 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 609 610 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 611 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 612 #ifdef __BIG_ENDIAN 613 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 614 #endif 615 /* enable DMA IBs */ 616 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 617 618 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 619 sdma_v5_2_ctx_switch_enable(adev, true); 620 sdma_v5_2_enable(adev, true); 621 } 622 623 r = amdgpu_ring_test_helper(ring); 624 if (r) 625 return r; 626 } 627 628 return 0; 629 } 630 631 /** 632 * sdma_v5_2_rlc_resume - setup and start the async dma engines 633 * 634 * @adev: amdgpu_device pointer 635 * 636 * Set up the compute DMA queues and enable them. 637 * Returns 0 for success, error for failure. 638 */ 639 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev) 640 { 641 return 0; 642 } 643 644 /** 645 * sdma_v5_2_load_microcode - load the sDMA ME ucode 646 * 647 * @adev: amdgpu_device pointer 648 * 649 * Loads the sDMA0/1/2/3 ucode. 650 * Returns 0 for success, -EINVAL if the ucode is not available. 651 */ 652 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev) 653 { 654 const struct sdma_firmware_header_v1_0 *hdr; 655 const __le32 *fw_data; 656 u32 fw_size; 657 int i, j; 658 659 /* halt the MEs */ 660 sdma_v5_2_enable(adev, false); 661 662 for (i = 0; i < adev->sdma.num_instances; i++) { 663 if (!adev->sdma.instance[i].fw) 664 return -EINVAL; 665 666 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 667 amdgpu_ucode_print_sdma_hdr(&hdr->header); 668 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 669 670 fw_data = (const __le32 *) 671 (adev->sdma.instance[i].fw->data + 672 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 673 674 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 675 676 for (j = 0; j < fw_size; j++) { 677 if (amdgpu_emu_mode == 1 && j % 500 == 0) 678 msleep(1); 679 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 680 } 681 682 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 683 } 684 685 return 0; 686 } 687 688 static int sdma_v5_2_soft_reset(void *handle) 689 { 690 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 691 u32 grbm_soft_reset; 692 u32 tmp; 693 int i; 694 695 for (i = 0; i < adev->sdma.num_instances; i++) { 696 grbm_soft_reset = REG_SET_FIELD(0, 697 GRBM_SOFT_RESET, SOFT_RESET_SDMA0, 698 1); 699 grbm_soft_reset <<= i; 700 701 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 702 tmp |= grbm_soft_reset; 703 DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp); 704 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 705 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 706 707 udelay(50); 708 709 tmp &= ~grbm_soft_reset; 710 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 711 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 712 713 udelay(50); 714 } 715 716 return 0; 717 } 718 719 /** 720 * sdma_v5_2_start - setup and start the async dma engines 721 * 722 * @adev: amdgpu_device pointer 723 * 724 * Set up the DMA engines and enable them. 725 * Returns 0 for success, error for failure. 726 */ 727 static int sdma_v5_2_start(struct amdgpu_device *adev) 728 { 729 int r = 0; 730 731 if (amdgpu_sriov_vf(adev)) { 732 sdma_v5_2_ctx_switch_enable(adev, false); 733 sdma_v5_2_enable(adev, false); 734 735 /* set RB registers */ 736 r = sdma_v5_2_gfx_resume(adev); 737 return r; 738 } 739 740 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 741 r = sdma_v5_2_load_microcode(adev); 742 if (r) 743 return r; 744 745 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */ 746 if (amdgpu_emu_mode == 1) 747 msleep(1000); 748 } 749 750 sdma_v5_2_soft_reset(adev); 751 /* unhalt the MEs */ 752 sdma_v5_2_enable(adev, true); 753 /* enable sdma ring preemption */ 754 sdma_v5_2_ctx_switch_enable(adev, true); 755 756 /* start the gfx rings and rlc compute queues */ 757 r = sdma_v5_2_gfx_resume(adev); 758 if (r) 759 return r; 760 r = sdma_v5_2_rlc_resume(adev); 761 762 return r; 763 } 764 765 static int sdma_v5_2_mqd_init(struct amdgpu_device *adev, void *mqd, 766 struct amdgpu_mqd_prop *prop) 767 { 768 struct v10_sdma_mqd *m = mqd; 769 uint64_t wb_gpu_addr; 770 771 m->sdmax_rlcx_rb_cntl = 772 order_base_2(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 773 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 774 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | 775 1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT; 776 777 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8); 778 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); 779 780 m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0, 781 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 782 783 wb_gpu_addr = prop->wptr_gpu_addr; 784 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); 785 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); 786 787 wb_gpu_addr = prop->rptr_gpu_addr; 788 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); 789 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); 790 791 m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0, 792 mmSDMA0_GFX_IB_CNTL)); 793 794 m->sdmax_rlcx_doorbell_offset = 795 prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 796 797 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1); 798 799 return 0; 800 } 801 802 static void sdma_v5_2_set_mqd_funcs(struct amdgpu_device *adev) 803 { 804 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v10_sdma_mqd); 805 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v5_2_mqd_init; 806 } 807 808 /** 809 * sdma_v5_2_ring_test_ring - simple async dma engine test 810 * 811 * @ring: amdgpu_ring structure holding ring information 812 * 813 * Test the DMA engine by writing using it to write an 814 * value to memory. 815 * Returns 0 for success, error for failure. 816 */ 817 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring) 818 { 819 struct amdgpu_device *adev = ring->adev; 820 unsigned i; 821 unsigned index; 822 int r; 823 u32 tmp; 824 u64 gpu_addr; 825 volatile uint32_t *cpu_ptr = NULL; 826 827 tmp = 0xCAFEDEAD; 828 829 if (ring->is_mes_queue) { 830 uint32_t offset = 0; 831 offset = amdgpu_mes_ctx_get_offs(ring, 832 AMDGPU_MES_CTX_PADDING_OFFS); 833 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 834 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 835 *cpu_ptr = tmp; 836 } else { 837 r = amdgpu_device_wb_get(adev, &index); 838 if (r) { 839 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 840 return r; 841 } 842 843 gpu_addr = adev->wb.gpu_addr + (index * 4); 844 adev->wb.wb[index] = cpu_to_le32(tmp); 845 } 846 847 r = amdgpu_ring_alloc(ring, 20); 848 if (r) { 849 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 850 amdgpu_device_wb_free(adev, index); 851 return r; 852 } 853 854 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 855 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 856 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 857 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 858 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 859 amdgpu_ring_write(ring, 0xDEADBEEF); 860 amdgpu_ring_commit(ring); 861 862 for (i = 0; i < adev->usec_timeout; i++) { 863 if (ring->is_mes_queue) 864 tmp = le32_to_cpu(*cpu_ptr); 865 else 866 tmp = le32_to_cpu(adev->wb.wb[index]); 867 if (tmp == 0xDEADBEEF) 868 break; 869 if (amdgpu_emu_mode == 1) 870 msleep(1); 871 else 872 udelay(1); 873 } 874 875 if (i >= adev->usec_timeout) 876 r = -ETIMEDOUT; 877 878 if (!ring->is_mes_queue) 879 amdgpu_device_wb_free(adev, index); 880 881 return r; 882 } 883 884 /** 885 * sdma_v5_2_ring_test_ib - test an IB on the DMA engine 886 * 887 * @ring: amdgpu_ring structure holding ring information 888 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 889 * 890 * Test a simple IB in the DMA ring. 891 * Returns 0 on success, error on failure. 892 */ 893 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) 894 { 895 struct amdgpu_device *adev = ring->adev; 896 struct amdgpu_ib ib; 897 struct dma_fence *f = NULL; 898 unsigned index; 899 long r; 900 u32 tmp = 0; 901 u64 gpu_addr; 902 volatile uint32_t *cpu_ptr = NULL; 903 904 tmp = 0xCAFEDEAD; 905 memset(&ib, 0, sizeof(ib)); 906 907 if (ring->is_mes_queue) { 908 uint32_t offset = 0; 909 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 910 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 911 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 912 913 offset = amdgpu_mes_ctx_get_offs(ring, 914 AMDGPU_MES_CTX_PADDING_OFFS); 915 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 916 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 917 *cpu_ptr = tmp; 918 } else { 919 r = amdgpu_device_wb_get(adev, &index); 920 if (r) { 921 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 922 return r; 923 } 924 925 gpu_addr = adev->wb.gpu_addr + (index * 4); 926 adev->wb.wb[index] = cpu_to_le32(tmp); 927 928 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 929 if (r) { 930 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 931 goto err0; 932 } 933 } 934 935 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 936 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 937 ib.ptr[1] = lower_32_bits(gpu_addr); 938 ib.ptr[2] = upper_32_bits(gpu_addr); 939 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 940 ib.ptr[4] = 0xDEADBEEF; 941 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 942 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 943 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 944 ib.length_dw = 8; 945 946 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 947 if (r) 948 goto err1; 949 950 r = dma_fence_wait_timeout(f, false, timeout); 951 if (r == 0) { 952 DRM_ERROR("amdgpu: IB test timed out\n"); 953 r = -ETIMEDOUT; 954 goto err1; 955 } else if (r < 0) { 956 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 957 goto err1; 958 } 959 960 if (ring->is_mes_queue) 961 tmp = le32_to_cpu(*cpu_ptr); 962 else 963 tmp = le32_to_cpu(adev->wb.wb[index]); 964 965 if (tmp == 0xDEADBEEF) 966 r = 0; 967 else 968 r = -EINVAL; 969 970 err1: 971 amdgpu_ib_free(adev, &ib, NULL); 972 dma_fence_put(f); 973 err0: 974 if (!ring->is_mes_queue) 975 amdgpu_device_wb_free(adev, index); 976 return r; 977 } 978 979 980 /** 981 * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART 982 * 983 * @ib: indirect buffer to fill with commands 984 * @pe: addr of the page entry 985 * @src: src addr to copy from 986 * @count: number of page entries to update 987 * 988 * Update PTEs by copying them from the GART using sDMA. 989 */ 990 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib, 991 uint64_t pe, uint64_t src, 992 unsigned count) 993 { 994 unsigned bytes = count * 8; 995 996 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 997 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 998 ib->ptr[ib->length_dw++] = bytes - 1; 999 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1000 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1001 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1002 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1003 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1004 1005 } 1006 1007 /** 1008 * sdma_v5_2_vm_write_pte - update PTEs by writing them manually 1009 * 1010 * @ib: indirect buffer to fill with commands 1011 * @pe: addr of the page entry 1012 * @value: dst addr to write into pe 1013 * @count: number of page entries to update 1014 * @incr: increase next addr by incr bytes 1015 * 1016 * Update PTEs by writing them manually using sDMA. 1017 */ 1018 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1019 uint64_t value, unsigned count, 1020 uint32_t incr) 1021 { 1022 unsigned ndw = count * 2; 1023 1024 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1025 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1026 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1027 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1028 ib->ptr[ib->length_dw++] = ndw - 1; 1029 for (; ndw > 0; ndw -= 2) { 1030 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1031 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1032 value += incr; 1033 } 1034 } 1035 1036 /** 1037 * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA 1038 * 1039 * @ib: indirect buffer to fill with commands 1040 * @pe: addr of the page entry 1041 * @addr: dst addr to write into pe 1042 * @count: number of page entries to update 1043 * @incr: increase next addr by incr bytes 1044 * @flags: access flags 1045 * 1046 * Update the page tables using sDMA. 1047 */ 1048 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib, 1049 uint64_t pe, 1050 uint64_t addr, unsigned count, 1051 uint32_t incr, uint64_t flags) 1052 { 1053 /* for physically contiguous pages (vram) */ 1054 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1055 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1056 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1057 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1058 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1059 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1060 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1061 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1062 ib->ptr[ib->length_dw++] = 0; 1063 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1064 } 1065 1066 /** 1067 * sdma_v5_2_ring_pad_ib - pad the IB 1068 * 1069 * @ib: indirect buffer to fill with padding 1070 * @ring: amdgpu_ring structure holding ring information 1071 * 1072 * Pad the IB with NOPs to a boundary multiple of 8. 1073 */ 1074 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1075 { 1076 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1077 u32 pad_count; 1078 int i; 1079 1080 pad_count = (-ib->length_dw) & 0x7; 1081 for (i = 0; i < pad_count; i++) 1082 if (sdma && sdma->burst_nop && (i == 0)) 1083 ib->ptr[ib->length_dw++] = 1084 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1085 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1086 else 1087 ib->ptr[ib->length_dw++] = 1088 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1089 } 1090 1091 1092 /** 1093 * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline 1094 * 1095 * @ring: amdgpu_ring pointer 1096 * 1097 * Make sure all previous operations are completed (CIK). 1098 */ 1099 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1100 { 1101 uint32_t seq = ring->fence_drv.sync_seq; 1102 uint64_t addr = ring->fence_drv.gpu_addr; 1103 1104 /* wait for idle */ 1105 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1106 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1107 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1108 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1109 amdgpu_ring_write(ring, addr & 0xfffffffc); 1110 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1111 amdgpu_ring_write(ring, seq); /* reference */ 1112 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1113 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1114 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1115 } 1116 1117 1118 /** 1119 * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA 1120 * 1121 * @ring: amdgpu_ring pointer 1122 * @vmid: vmid number to use 1123 * @pd_addr: address 1124 * 1125 * Update the page table base and flush the VM TLB 1126 * using sDMA. 1127 */ 1128 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring, 1129 unsigned vmid, uint64_t pd_addr) 1130 { 1131 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1132 } 1133 1134 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring, 1135 uint32_t reg, uint32_t val) 1136 { 1137 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1138 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1139 amdgpu_ring_write(ring, reg); 1140 amdgpu_ring_write(ring, val); 1141 } 1142 1143 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1144 uint32_t val, uint32_t mask) 1145 { 1146 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1147 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1148 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1149 amdgpu_ring_write(ring, reg << 2); 1150 amdgpu_ring_write(ring, 0); 1151 amdgpu_ring_write(ring, val); /* reference */ 1152 amdgpu_ring_write(ring, mask); /* mask */ 1153 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1154 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1155 } 1156 1157 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1158 uint32_t reg0, uint32_t reg1, 1159 uint32_t ref, uint32_t mask) 1160 { 1161 amdgpu_ring_emit_wreg(ring, reg0, ref); 1162 /* wait for a cycle to reset vm_inv_eng*_ack */ 1163 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1164 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1165 } 1166 1167 static int sdma_v5_2_early_init(void *handle) 1168 { 1169 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1170 int r; 1171 1172 r = amdgpu_sdma_init_microcode(adev, 0, true); 1173 if (r) 1174 return r; 1175 1176 sdma_v5_2_set_ring_funcs(adev); 1177 sdma_v5_2_set_buffer_funcs(adev); 1178 sdma_v5_2_set_vm_pte_funcs(adev); 1179 sdma_v5_2_set_irq_funcs(adev); 1180 sdma_v5_2_set_mqd_funcs(adev); 1181 1182 return 0; 1183 } 1184 1185 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num) 1186 { 1187 switch (seq_num) { 1188 case 0: 1189 return SOC15_IH_CLIENTID_SDMA0; 1190 case 1: 1191 return SOC15_IH_CLIENTID_SDMA1; 1192 case 2: 1193 return SOC15_IH_CLIENTID_SDMA2; 1194 case 3: 1195 return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid; 1196 default: 1197 break; 1198 } 1199 return -EINVAL; 1200 } 1201 1202 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num) 1203 { 1204 switch (seq_num) { 1205 case 0: 1206 return SDMA0_5_0__SRCID__SDMA_TRAP; 1207 case 1: 1208 return SDMA1_5_0__SRCID__SDMA_TRAP; 1209 case 2: 1210 return SDMA2_5_0__SRCID__SDMA_TRAP; 1211 case 3: 1212 return SDMA3_5_0__SRCID__SDMA_TRAP; 1213 default: 1214 break; 1215 } 1216 return -EINVAL; 1217 } 1218 1219 static int sdma_v5_2_sw_init(void *handle) 1220 { 1221 struct amdgpu_ring *ring; 1222 int r, i; 1223 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1224 1225 /* SDMA trap event */ 1226 for (i = 0; i < adev->sdma.num_instances; i++) { 1227 r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i), 1228 sdma_v5_2_seq_to_trap_id(i), 1229 &adev->sdma.trap_irq); 1230 if (r) 1231 return r; 1232 } 1233 1234 for (i = 0; i < adev->sdma.num_instances; i++) { 1235 ring = &adev->sdma.instance[i].ring; 1236 ring->ring_obj = NULL; 1237 ring->use_doorbell = true; 1238 ring->me = i; 1239 1240 DRM_INFO("use_doorbell being set to: [%s]\n", 1241 ring->use_doorbell?"true":"false"); 1242 1243 ring->doorbell_index = 1244 (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset 1245 1246 ring->vm_hub = AMDGPU_GFXHUB(0); 1247 sprintf(ring->name, "sdma%d", i); 1248 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1249 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1250 AMDGPU_RING_PRIO_DEFAULT, NULL); 1251 if (r) 1252 return r; 1253 } 1254 1255 return r; 1256 } 1257 1258 static int sdma_v5_2_sw_fini(void *handle) 1259 { 1260 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1261 int i; 1262 1263 for (i = 0; i < adev->sdma.num_instances; i++) 1264 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1265 1266 amdgpu_sdma_destroy_inst_ctx(adev, true); 1267 1268 return 0; 1269 } 1270 1271 static int sdma_v5_2_hw_init(void *handle) 1272 { 1273 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1274 1275 return sdma_v5_2_start(adev); 1276 } 1277 1278 static int sdma_v5_2_hw_fini(void *handle) 1279 { 1280 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1281 1282 if (amdgpu_sriov_vf(adev)) 1283 return 0; 1284 1285 sdma_v5_2_ctx_switch_enable(adev, false); 1286 sdma_v5_2_enable(adev, false); 1287 1288 return 0; 1289 } 1290 1291 static int sdma_v5_2_suspend(void *handle) 1292 { 1293 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1294 1295 return sdma_v5_2_hw_fini(adev); 1296 } 1297 1298 static int sdma_v5_2_resume(void *handle) 1299 { 1300 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1301 1302 return sdma_v5_2_hw_init(adev); 1303 } 1304 1305 static bool sdma_v5_2_is_idle(void *handle) 1306 { 1307 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1308 u32 i; 1309 1310 for (i = 0; i < adev->sdma.num_instances; i++) { 1311 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1312 1313 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1314 return false; 1315 } 1316 1317 return true; 1318 } 1319 1320 static int sdma_v5_2_wait_for_idle(void *handle) 1321 { 1322 unsigned i; 1323 u32 sdma0, sdma1, sdma2, sdma3; 1324 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1325 1326 for (i = 0; i < adev->usec_timeout; i++) { 1327 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1328 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1329 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG)); 1330 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG)); 1331 1332 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK) 1333 return 0; 1334 udelay(1); 1335 } 1336 return -ETIMEDOUT; 1337 } 1338 1339 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring) 1340 { 1341 int i, r = 0; 1342 struct amdgpu_device *adev = ring->adev; 1343 u32 index = 0; 1344 u64 sdma_gfx_preempt; 1345 1346 amdgpu_sdma_get_index_from_ring(ring, &index); 1347 sdma_gfx_preempt = 1348 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT); 1349 1350 /* assert preemption condition */ 1351 amdgpu_ring_set_preempt_cond_exec(ring, false); 1352 1353 /* emit the trailing fence */ 1354 ring->trail_seq += 1; 1355 amdgpu_ring_alloc(ring, 10); 1356 sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1357 ring->trail_seq, 0); 1358 amdgpu_ring_commit(ring); 1359 1360 /* assert IB preemption */ 1361 WREG32(sdma_gfx_preempt, 1); 1362 1363 /* poll the trailing fence */ 1364 for (i = 0; i < adev->usec_timeout; i++) { 1365 if (ring->trail_seq == 1366 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1367 break; 1368 udelay(1); 1369 } 1370 1371 if (i >= adev->usec_timeout) { 1372 r = -EINVAL; 1373 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1374 } 1375 1376 /* deassert IB preemption */ 1377 WREG32(sdma_gfx_preempt, 0); 1378 1379 /* deassert the preemption condition */ 1380 amdgpu_ring_set_preempt_cond_exec(ring, true); 1381 return r; 1382 } 1383 1384 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev, 1385 struct amdgpu_irq_src *source, 1386 unsigned type, 1387 enum amdgpu_interrupt_state state) 1388 { 1389 u32 sdma_cntl; 1390 u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL); 1391 1392 if (!amdgpu_sriov_vf(adev)) { 1393 sdma_cntl = RREG32(reg_offset); 1394 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1395 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1396 WREG32(reg_offset, sdma_cntl); 1397 } 1398 1399 return 0; 1400 } 1401 1402 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev, 1403 struct amdgpu_irq_src *source, 1404 struct amdgpu_iv_entry *entry) 1405 { 1406 uint32_t mes_queue_id = entry->src_data[0]; 1407 1408 DRM_DEBUG("IH: SDMA trap\n"); 1409 1410 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 1411 struct amdgpu_mes_queue *queue; 1412 1413 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 1414 1415 spin_lock(&adev->mes.queue_id_lock); 1416 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 1417 if (queue) { 1418 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); 1419 amdgpu_fence_process(queue->ring); 1420 } 1421 spin_unlock(&adev->mes.queue_id_lock); 1422 return 0; 1423 } 1424 1425 switch (entry->client_id) { 1426 case SOC15_IH_CLIENTID_SDMA0: 1427 switch (entry->ring_id) { 1428 case 0: 1429 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1430 break; 1431 case 1: 1432 /* XXX compute */ 1433 break; 1434 case 2: 1435 /* XXX compute */ 1436 break; 1437 case 3: 1438 /* XXX page queue*/ 1439 break; 1440 } 1441 break; 1442 case SOC15_IH_CLIENTID_SDMA1: 1443 switch (entry->ring_id) { 1444 case 0: 1445 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1446 break; 1447 case 1: 1448 /* XXX compute */ 1449 break; 1450 case 2: 1451 /* XXX compute */ 1452 break; 1453 case 3: 1454 /* XXX page queue*/ 1455 break; 1456 } 1457 break; 1458 case SOC15_IH_CLIENTID_SDMA2: 1459 switch (entry->ring_id) { 1460 case 0: 1461 amdgpu_fence_process(&adev->sdma.instance[2].ring); 1462 break; 1463 case 1: 1464 /* XXX compute */ 1465 break; 1466 case 2: 1467 /* XXX compute */ 1468 break; 1469 case 3: 1470 /* XXX page queue*/ 1471 break; 1472 } 1473 break; 1474 case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid: 1475 switch (entry->ring_id) { 1476 case 0: 1477 amdgpu_fence_process(&adev->sdma.instance[3].ring); 1478 break; 1479 case 1: 1480 /* XXX compute */ 1481 break; 1482 case 2: 1483 /* XXX compute */ 1484 break; 1485 case 3: 1486 /* XXX page queue*/ 1487 break; 1488 } 1489 break; 1490 } 1491 return 0; 1492 } 1493 1494 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev, 1495 struct amdgpu_irq_src *source, 1496 struct amdgpu_iv_entry *entry) 1497 { 1498 return 0; 1499 } 1500 1501 static bool sdma_v5_2_firmware_mgcg_support(struct amdgpu_device *adev, 1502 int i) 1503 { 1504 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1505 case IP_VERSION(5, 2, 1): 1506 if (adev->sdma.instance[i].fw_version < 70) 1507 return false; 1508 break; 1509 case IP_VERSION(5, 2, 3): 1510 if (adev->sdma.instance[i].fw_version < 47) 1511 return false; 1512 break; 1513 case IP_VERSION(5, 2, 7): 1514 if (adev->sdma.instance[i].fw_version < 9) 1515 return false; 1516 break; 1517 default: 1518 return true; 1519 } 1520 1521 return true; 1522 1523 } 1524 1525 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev, 1526 bool enable) 1527 { 1528 uint32_t data, def; 1529 int i; 1530 1531 for (i = 0; i < adev->sdma.num_instances; i++) { 1532 1533 if (!sdma_v5_2_firmware_mgcg_support(adev, i)) 1534 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG; 1535 1536 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1537 /* Enable sdma clock gating */ 1538 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1539 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1540 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1541 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1542 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1543 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK | 1544 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK); 1545 if (def != data) 1546 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1547 } else { 1548 /* Disable sdma clock gating */ 1549 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1550 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1551 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1552 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1553 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1554 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK | 1555 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK); 1556 if (def != data) 1557 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1558 } 1559 } 1560 } 1561 1562 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev, 1563 bool enable) 1564 { 1565 uint32_t data, def; 1566 int i; 1567 1568 for (i = 0; i < adev->sdma.num_instances; i++) { 1569 if (adev->sdma.instance[i].fw_version < 70 && 1570 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == 1571 IP_VERSION(5, 2, 1)) 1572 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS; 1573 1574 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1575 /* Enable sdma mem light sleep */ 1576 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1577 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1578 if (def != data) 1579 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1580 1581 } else { 1582 /* Disable sdma mem light sleep */ 1583 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1584 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1585 if (def != data) 1586 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1587 1588 } 1589 } 1590 } 1591 1592 static int sdma_v5_2_set_clockgating_state(void *handle, 1593 enum amd_clockgating_state state) 1594 { 1595 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1596 1597 if (amdgpu_sriov_vf(adev)) 1598 return 0; 1599 1600 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1601 case IP_VERSION(5, 2, 0): 1602 case IP_VERSION(5, 2, 2): 1603 case IP_VERSION(5, 2, 1): 1604 case IP_VERSION(5, 2, 4): 1605 case IP_VERSION(5, 2, 5): 1606 case IP_VERSION(5, 2, 6): 1607 case IP_VERSION(5, 2, 3): 1608 case IP_VERSION(5, 2, 7): 1609 sdma_v5_2_update_medium_grain_clock_gating(adev, 1610 state == AMD_CG_STATE_GATE); 1611 sdma_v5_2_update_medium_grain_light_sleep(adev, 1612 state == AMD_CG_STATE_GATE); 1613 break; 1614 default: 1615 break; 1616 } 1617 1618 return 0; 1619 } 1620 1621 static int sdma_v5_2_set_powergating_state(void *handle, 1622 enum amd_powergating_state state) 1623 { 1624 return 0; 1625 } 1626 1627 static void sdma_v5_2_get_clockgating_state(void *handle, u64 *flags) 1628 { 1629 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1630 int data; 1631 1632 if (amdgpu_sriov_vf(adev)) 1633 *flags = 0; 1634 1635 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1636 data = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL)); 1637 if (!(data & SDMA0_CLK_CTRL__CGCG_EN_OVERRIDE_MASK)) 1638 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1639 1640 /* AMD_CG_SUPPORT_SDMA_LS */ 1641 data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); 1642 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1643 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1644 } 1645 1646 static void sdma_v5_2_ring_begin_use(struct amdgpu_ring *ring) 1647 { 1648 struct amdgpu_device *adev = ring->adev; 1649 1650 /* SDMA 5.2.3 (RMB) FW doesn't seem to properly 1651 * disallow GFXOFF in some cases leading to 1652 * hangs in SDMA. Disallow GFXOFF while SDMA is active. 1653 * We can probably just limit this to 5.2.3, 1654 * but it shouldn't hurt for other parts since 1655 * this GFXOFF will be disallowed anyway when SDMA is 1656 * active, this just makes it explicit. 1657 */ 1658 amdgpu_gfx_off_ctrl(adev, false); 1659 } 1660 1661 static void sdma_v5_2_ring_end_use(struct amdgpu_ring *ring) 1662 { 1663 struct amdgpu_device *adev = ring->adev; 1664 1665 /* SDMA 5.2.3 (RMB) FW doesn't seem to properly 1666 * disallow GFXOFF in some cases leading to 1667 * hangs in SDMA. Allow GFXOFF when SDMA is complete. 1668 */ 1669 amdgpu_gfx_off_ctrl(adev, true); 1670 } 1671 1672 const struct amd_ip_funcs sdma_v5_2_ip_funcs = { 1673 .name = "sdma_v5_2", 1674 .early_init = sdma_v5_2_early_init, 1675 .late_init = NULL, 1676 .sw_init = sdma_v5_2_sw_init, 1677 .sw_fini = sdma_v5_2_sw_fini, 1678 .hw_init = sdma_v5_2_hw_init, 1679 .hw_fini = sdma_v5_2_hw_fini, 1680 .suspend = sdma_v5_2_suspend, 1681 .resume = sdma_v5_2_resume, 1682 .is_idle = sdma_v5_2_is_idle, 1683 .wait_for_idle = sdma_v5_2_wait_for_idle, 1684 .soft_reset = sdma_v5_2_soft_reset, 1685 .set_clockgating_state = sdma_v5_2_set_clockgating_state, 1686 .set_powergating_state = sdma_v5_2_set_powergating_state, 1687 .get_clockgating_state = sdma_v5_2_get_clockgating_state, 1688 }; 1689 1690 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = { 1691 .type = AMDGPU_RING_TYPE_SDMA, 1692 .align_mask = 0xf, 1693 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1694 .support_64bit_ptrs = true, 1695 .secure_submission_supported = true, 1696 .get_rptr = sdma_v5_2_ring_get_rptr, 1697 .get_wptr = sdma_v5_2_ring_get_wptr, 1698 .set_wptr = sdma_v5_2_ring_set_wptr, 1699 .emit_frame_size = 1700 5 + /* sdma_v5_2_ring_init_cond_exec */ 1701 6 + /* sdma_v5_2_ring_emit_hdp_flush */ 1702 3 + /* hdp_invalidate */ 1703 6 + /* sdma_v5_2_ring_emit_pipeline_sync */ 1704 /* sdma_v5_2_ring_emit_vm_flush */ 1705 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1706 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1707 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */ 1708 .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */ 1709 .emit_ib = sdma_v5_2_ring_emit_ib, 1710 .emit_mem_sync = sdma_v5_2_ring_emit_mem_sync, 1711 .emit_fence = sdma_v5_2_ring_emit_fence, 1712 .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync, 1713 .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush, 1714 .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush, 1715 .test_ring = sdma_v5_2_ring_test_ring, 1716 .test_ib = sdma_v5_2_ring_test_ib, 1717 .insert_nop = sdma_v5_2_ring_insert_nop, 1718 .pad_ib = sdma_v5_2_ring_pad_ib, 1719 .begin_use = sdma_v5_2_ring_begin_use, 1720 .end_use = sdma_v5_2_ring_end_use, 1721 .emit_wreg = sdma_v5_2_ring_emit_wreg, 1722 .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait, 1723 .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait, 1724 .init_cond_exec = sdma_v5_2_ring_init_cond_exec, 1725 .patch_cond_exec = sdma_v5_2_ring_patch_cond_exec, 1726 .preempt_ib = sdma_v5_2_ring_preempt_ib, 1727 }; 1728 1729 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev) 1730 { 1731 int i; 1732 1733 for (i = 0; i < adev->sdma.num_instances; i++) { 1734 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs; 1735 adev->sdma.instance[i].ring.me = i; 1736 } 1737 } 1738 1739 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = { 1740 .set = sdma_v5_2_set_trap_irq_state, 1741 .process = sdma_v5_2_process_trap_irq, 1742 }; 1743 1744 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = { 1745 .process = sdma_v5_2_process_illegal_inst_irq, 1746 }; 1747 1748 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev) 1749 { 1750 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1751 adev->sdma.num_instances; 1752 adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs; 1753 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs; 1754 } 1755 1756 /** 1757 * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine 1758 * 1759 * @ib: indirect buffer to copy to 1760 * @src_offset: src GPU address 1761 * @dst_offset: dst GPU address 1762 * @byte_count: number of bytes to xfer 1763 * @tmz: if a secure copy should be used 1764 * 1765 * Copy GPU buffers using the DMA engine. 1766 * Used by the amdgpu ttm implementation to move pages if 1767 * registered as the asic copy callback. 1768 */ 1769 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib, 1770 uint64_t src_offset, 1771 uint64_t dst_offset, 1772 uint32_t byte_count, 1773 bool tmz) 1774 { 1775 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1776 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1777 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 1778 ib->ptr[ib->length_dw++] = byte_count - 1; 1779 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1780 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1781 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1782 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1783 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1784 } 1785 1786 /** 1787 * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine 1788 * 1789 * @ib: indirect buffer to fill 1790 * @src_data: value to write to buffer 1791 * @dst_offset: dst GPU address 1792 * @byte_count: number of bytes to xfer 1793 * 1794 * Fill GPU buffers using the DMA engine. 1795 */ 1796 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib, 1797 uint32_t src_data, 1798 uint64_t dst_offset, 1799 uint32_t byte_count) 1800 { 1801 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1802 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1803 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1804 ib->ptr[ib->length_dw++] = src_data; 1805 ib->ptr[ib->length_dw++] = byte_count - 1; 1806 } 1807 1808 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = { 1809 .copy_max_bytes = 0x400000, 1810 .copy_num_dw = 7, 1811 .emit_copy_buffer = sdma_v5_2_emit_copy_buffer, 1812 1813 .fill_max_bytes = 0x400000, 1814 .fill_num_dw = 5, 1815 .emit_fill_buffer = sdma_v5_2_emit_fill_buffer, 1816 }; 1817 1818 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev) 1819 { 1820 if (adev->mman.buffer_funcs == NULL) { 1821 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs; 1822 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1823 } 1824 } 1825 1826 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = { 1827 .copy_pte_num_dw = 7, 1828 .copy_pte = sdma_v5_2_vm_copy_pte, 1829 .write_pte = sdma_v5_2_vm_write_pte, 1830 .set_pte_pde = sdma_v5_2_vm_set_pte_pde, 1831 }; 1832 1833 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev) 1834 { 1835 unsigned i; 1836 1837 if (adev->vm_manager.vm_pte_funcs == NULL) { 1838 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs; 1839 for (i = 0; i < adev->sdma.num_instances; i++) { 1840 adev->vm_manager.vm_pte_scheds[i] = 1841 &adev->sdma.instance[i].ring.sched; 1842 } 1843 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1844 } 1845 } 1846 1847 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = { 1848 .type = AMD_IP_BLOCK_TYPE_SDMA, 1849 .major = 5, 1850 .minor = 2, 1851 .rev = 0, 1852 .funcs = &sdma_v5_2_ip_funcs, 1853 }; 1854