1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_10_3_0_offset.h" 34 #include "gc/gc_10_3_0_sh_mask.h" 35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h" 36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h" 37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h" 38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h" 39 40 #include "soc15_common.h" 41 #include "soc15.h" 42 #include "navi10_sdma_pkt_open.h" 43 #include "nbio_v2_3.h" 44 #include "sdma_common.h" 45 #include "sdma_v5_2.h" 46 47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin"); 48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin"); 49 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin"); 50 MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin"); 51 52 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin"); 53 MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin"); 54 MODULE_FIRMWARE("amdgpu/sdma_5_2_6.bin"); 55 MODULE_FIRMWARE("amdgpu/sdma_5_2_7.bin"); 56 57 #define SDMA1_REG_OFFSET 0x600 58 #define SDMA3_REG_OFFSET 0x400 59 #define SDMA0_HYP_DEC_REG_START 0x5880 60 #define SDMA0_HYP_DEC_REG_END 0x5893 61 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 62 63 static const struct amdgpu_hwip_reg_entry sdma_reg_list_5_2[] = { 64 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG), 65 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG), 66 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG), 67 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG), 68 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UCODE_CHECKSUM), 69 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH_HI), 70 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH), 71 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_STATUS), 72 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_STATUS), 73 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK0), 74 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK1), 75 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK0), 76 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK1), 77 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_CNTL), 78 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR), 79 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR_HI), 80 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR), 81 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR_HI), 82 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_OFFSET), 83 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_LO), 84 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_HI), 85 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_CNTL), 86 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_RPTR), 87 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_SUB_REMAIN), 88 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_DUMMY_REG), 89 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_CNTL), 90 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR), 91 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR_HI), 92 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR), 93 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR_HI), 94 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_OFFSET), 95 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_LO), 96 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_HI), 97 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_DUMMY_REG), 98 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_CNTL), 99 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR), 100 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR_HI), 101 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR), 102 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR_HI), 103 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_OFFSET), 104 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_LO), 105 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_HI), 106 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_DUMMY_REG), 107 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_INT_STATUS), 108 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_VM_CNTL), 109 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2) 110 }; 111 112 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev); 113 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev); 114 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev); 115 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev); 116 117 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 118 { 119 u32 base; 120 121 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 122 internal_offset <= SDMA0_HYP_DEC_REG_END) { 123 base = adev->reg_offset[GC_HWIP][0][1]; 124 if (instance != 0) 125 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance; 126 } else { 127 if (instance < 2) { 128 base = adev->reg_offset[GC_HWIP][0][0]; 129 if (instance == 1) 130 internal_offset += SDMA1_REG_OFFSET; 131 } else { 132 base = adev->reg_offset[GC_HWIP][0][2]; 133 if (instance == 3) 134 internal_offset += SDMA3_REG_OFFSET; 135 } 136 } 137 138 return base + internal_offset; 139 } 140 141 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring, 142 uint64_t addr) 143 { 144 unsigned ret; 145 146 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); 147 amdgpu_ring_write(ring, lower_32_bits(addr)); 148 amdgpu_ring_write(ring, upper_32_bits(addr)); 149 amdgpu_ring_write(ring, 1); 150 /* this is the offset we need patch later */ 151 ret = ring->wptr & ring->buf_mask; 152 /* insert dummy here and patch it later */ 153 amdgpu_ring_write(ring, 0); 154 155 return ret; 156 } 157 158 /** 159 * sdma_v5_2_ring_get_rptr - get the current read pointer 160 * 161 * @ring: amdgpu ring pointer 162 * 163 * Get the current rptr from the hardware (NAVI10+). 164 */ 165 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring) 166 { 167 u64 *rptr; 168 169 /* XXX check if swapping is necessary on BE */ 170 rptr = (u64 *)ring->rptr_cpu_addr; 171 172 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 173 return ((*rptr) >> 2); 174 } 175 176 /** 177 * sdma_v5_2_ring_get_wptr - get the current write pointer 178 * 179 * @ring: amdgpu ring pointer 180 * 181 * Get the current wptr from the hardware (NAVI10+). 182 */ 183 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring) 184 { 185 struct amdgpu_device *adev = ring->adev; 186 u64 wptr; 187 188 if (ring->use_doorbell) { 189 /* XXX check if swapping is necessary on BE */ 190 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 191 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 192 } else { 193 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); 194 wptr = wptr << 32; 195 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); 196 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr); 197 } 198 199 return wptr >> 2; 200 } 201 202 /** 203 * sdma_v5_2_ring_set_wptr - commit the write pointer 204 * 205 * @ring: amdgpu ring pointer 206 * 207 * Write the wptr back to the hardware (NAVI10+). 208 */ 209 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring) 210 { 211 struct amdgpu_device *adev = ring->adev; 212 213 DRM_DEBUG("Setting write pointer\n"); 214 if (ring->use_doorbell) { 215 DRM_DEBUG("Using doorbell -- " 216 "wptr_offs == 0x%08x " 217 "lower_32_bits(ring->wptr << 2) == 0x%08x " 218 "upper_32_bits(ring->wptr << 2) == 0x%08x\n", 219 ring->wptr_offs, 220 lower_32_bits(ring->wptr << 2), 221 upper_32_bits(ring->wptr << 2)); 222 /* XXX check if swapping is necessary on BE */ 223 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 224 ring->wptr << 2); 225 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 226 ring->doorbell_index, ring->wptr << 2); 227 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 228 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(5, 2, 1)) { 229 /* SDMA seems to miss doorbells sometimes when powergating kicks in. 230 * Updating the wptr directly will wake it. This is only safe because 231 * we disallow gfxoff in begin_use() and then allow it again in end_use(). 232 */ 233 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), 234 lower_32_bits(ring->wptr << 2)); 235 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), 236 upper_32_bits(ring->wptr << 2)); 237 } 238 } else { 239 DRM_DEBUG("Not using doorbell -- " 240 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 241 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 242 ring->me, 243 lower_32_bits(ring->wptr << 2), 244 ring->me, 245 upper_32_bits(ring->wptr << 2)); 246 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), 247 lower_32_bits(ring->wptr << 2)); 248 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), 249 upper_32_bits(ring->wptr << 2)); 250 } 251 } 252 253 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 254 { 255 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 256 int i; 257 258 for (i = 0; i < count; i++) 259 if (sdma && sdma->burst_nop && (i == 0)) 260 amdgpu_ring_write(ring, ring->funcs->nop | 261 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 262 else 263 amdgpu_ring_write(ring, ring->funcs->nop); 264 } 265 266 /** 267 * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine 268 * 269 * @ring: amdgpu ring pointer 270 * @job: job to retrieve vmid from 271 * @ib: IB object to schedule 272 * @flags: unused 273 * 274 * Schedule an IB in the DMA ring. 275 */ 276 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring, 277 struct amdgpu_job *job, 278 struct amdgpu_ib *ib, 279 uint32_t flags) 280 { 281 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 282 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 283 284 /* An IB packet must end on a 8 DW boundary--the next dword 285 * must be on a 8-dword boundary. Our IB packet below is 6 286 * dwords long, thus add x number of NOPs, such that, in 287 * modular arithmetic, 288 * wptr + 6 + x = 8k, k >= 0, which in C is, 289 * (wptr + 6 + x) % 8 = 0. 290 * The expression below, is a solution of x. 291 */ 292 sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 293 294 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 295 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 296 /* base must be 32 byte aligned */ 297 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 298 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 299 amdgpu_ring_write(ring, ib->length_dw); 300 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 301 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 302 } 303 304 /** 305 * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse 306 * 307 * @ring: amdgpu ring pointer 308 * 309 * flush the IB by graphics cache rinse. 310 */ 311 static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring) 312 { 313 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | 314 SDMA_GCR_GLM_INV | SDMA_GCR_GL1_INV | 315 SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 316 SDMA_GCR_GLI_INV(1); 317 318 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 319 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ)); 320 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 321 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 322 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 323 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 324 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 325 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 326 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 327 } 328 329 /** 330 * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 331 * 332 * @ring: amdgpu ring pointer 333 * 334 * Emit an hdp flush packet on the requested DMA ring. 335 */ 336 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 337 { 338 struct amdgpu_device *adev = ring->adev; 339 u32 ref_and_mask = 0; 340 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 341 342 if (ring->me > 1) { 343 amdgpu_asic_flush_hdp(adev, ring); 344 } else { 345 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 346 347 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 348 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 349 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 350 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 351 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 352 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 353 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 354 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 355 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 356 } 357 } 358 359 /** 360 * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring 361 * 362 * @ring: amdgpu ring pointer 363 * @addr: address 364 * @seq: sequence number 365 * @flags: fence related flags 366 * 367 * Add a DMA fence packet to the ring to write 368 * the fence seq number and DMA trap packet to generate 369 * an interrupt if needed. 370 */ 371 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 372 unsigned flags) 373 { 374 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 375 /* write the fence */ 376 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 377 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 378 /* zero in first two bits */ 379 BUG_ON(addr & 0x3); 380 amdgpu_ring_write(ring, lower_32_bits(addr)); 381 amdgpu_ring_write(ring, upper_32_bits(addr)); 382 amdgpu_ring_write(ring, lower_32_bits(seq)); 383 384 /* optionally write high bits as well */ 385 if (write64bit) { 386 addr += 4; 387 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 388 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 389 /* zero in first two bits */ 390 BUG_ON(addr & 0x3); 391 amdgpu_ring_write(ring, lower_32_bits(addr)); 392 amdgpu_ring_write(ring, upper_32_bits(addr)); 393 amdgpu_ring_write(ring, upper_32_bits(seq)); 394 } 395 396 if ((flags & AMDGPU_FENCE_FLAG_INT)) { 397 /* generate an interrupt */ 398 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 399 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 400 } 401 } 402 403 404 /** 405 * sdma_v5_2_gfx_stop - stop the gfx async dma engines 406 * 407 * @adev: amdgpu_device pointer 408 * 409 * Stop the gfx async dma ring buffers. 410 */ 411 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev) 412 { 413 u32 rb_cntl, ib_cntl; 414 int i; 415 416 for (i = 0; i < adev->sdma.num_instances; i++) { 417 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 418 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 419 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 420 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 421 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 422 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 423 } 424 } 425 426 /** 427 * sdma_v5_2_rlc_stop - stop the compute async dma engines 428 * 429 * @adev: amdgpu_device pointer 430 * 431 * Stop the compute async dma queues. 432 */ 433 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev) 434 { 435 /* XXX todo */ 436 } 437 438 /** 439 * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch 440 * 441 * @adev: amdgpu_device pointer 442 * @enable: enable/disable the DMA MEs context switch. 443 * 444 * Halt or unhalt the async dma engines context switch. 445 */ 446 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 447 { 448 u32 f32_cntl, phase_quantum = 0; 449 int i; 450 451 if (amdgpu_sdma_phase_quantum) { 452 unsigned value = amdgpu_sdma_phase_quantum; 453 unsigned unit = 0; 454 455 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 456 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 457 value = (value + 1) >> 1; 458 unit++; 459 } 460 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 461 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 462 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 463 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 464 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 465 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 466 WARN_ONCE(1, 467 "clamping sdma_phase_quantum to %uK clock cycles\n", 468 value << unit); 469 } 470 phase_quantum = 471 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 472 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 473 } 474 475 for (i = 0; i < adev->sdma.num_instances; i++) { 476 if (enable && amdgpu_sdma_phase_quantum) { 477 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 478 phase_quantum); 479 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 480 phase_quantum); 481 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 482 phase_quantum); 483 } 484 485 if (!amdgpu_sriov_vf(adev)) { 486 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); 487 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 488 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 489 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 490 } 491 } 492 493 } 494 495 /** 496 * sdma_v5_2_enable - stop the async dma engines 497 * 498 * @adev: amdgpu_device pointer 499 * @enable: enable/disable the DMA MEs. 500 * 501 * Halt or unhalt the async dma engines. 502 */ 503 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable) 504 { 505 u32 f32_cntl; 506 int i; 507 508 if (!enable) { 509 sdma_v5_2_gfx_stop(adev); 510 sdma_v5_2_rlc_stop(adev); 511 } 512 513 if (!amdgpu_sriov_vf(adev)) { 514 for (i = 0; i < adev->sdma.num_instances; i++) { 515 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 516 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 517 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 518 } 519 } 520 } 521 522 /** 523 * sdma_v5_2_gfx_resume_instance - start/restart a certain sdma engine 524 * 525 * @adev: amdgpu_device pointer 526 * @i: instance 527 * @restore: used to restore wptr when restart 528 * 529 * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr. 530 * Return 0 for success. 531 */ 532 533 static int sdma_v5_2_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore) 534 { 535 struct amdgpu_ring *ring; 536 u32 rb_cntl, ib_cntl; 537 u32 rb_bufsz; 538 u32 doorbell; 539 u32 doorbell_offset; 540 u32 temp; 541 u32 wptr_poll_cntl; 542 u64 wptr_gpu_addr; 543 544 ring = &adev->sdma.instance[i].ring; 545 546 if (!amdgpu_sriov_vf(adev)) 547 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 548 549 /* Set ring buffer size in dwords */ 550 rb_bufsz = order_base_2(ring->ring_size / 4); 551 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 552 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 553 #ifdef __BIG_ENDIAN 554 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 555 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 556 RPTR_WRITEBACK_SWAP_ENABLE, 1); 557 #endif 558 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 559 560 /* Initialize the ring buffer's read and write pointers */ 561 if (restore) { 562 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), lower_32_bits(ring->wptr << 2)); 563 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring->wptr << 2)); 564 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); 565 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); 566 } else { 567 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 568 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 569 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 570 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 571 } 572 573 /* setup the wptr shadow polling */ 574 wptr_gpu_addr = ring->wptr_gpu_addr; 575 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 576 lower_32_bits(wptr_gpu_addr)); 577 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 578 upper_32_bits(wptr_gpu_addr)); 579 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 580 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 581 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 582 SDMA0_GFX_RB_WPTR_POLL_CNTL, 583 F32_POLL_ENABLE, 1); 584 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 585 wptr_poll_cntl); 586 587 /* set the wb address whether it's enabled or not */ 588 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 589 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 590 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 591 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 592 593 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 594 595 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 596 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 597 598 if (!restore) 599 ring->wptr = 0; 600 601 /* before programing wptr to a less value, need set minor_ptr_update first */ 602 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 603 604 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 605 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); 606 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); 607 } 608 609 doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 610 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); 611 612 if (ring->use_doorbell) { 613 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 614 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 615 OFFSET, ring->doorbell_index); 616 } else { 617 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 618 } 619 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 620 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 621 622 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 623 ring->doorbell_index, 624 adev->doorbell_index.sdma_doorbell_range); 625 626 if (amdgpu_sriov_vf(adev)) 627 sdma_v5_2_ring_set_wptr(ring); 628 629 /* set minor_ptr_update to 0 after wptr programed */ 630 631 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 632 633 /* SRIOV VF has no control of any of registers below */ 634 if (!amdgpu_sriov_vf(adev)) { 635 /* set utc l1 enable flag always to 1 */ 636 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); 637 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 638 639 /* enable MCBP */ 640 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); 641 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 642 643 /* Set up RESP_MODE to non-copy addresses */ 644 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); 645 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 646 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 647 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); 648 649 /* program default cache read and write policy */ 650 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); 651 /* clean read policy and write policy bits */ 652 temp &= 0xFF0FFF; 653 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | 654 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | 655 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK); 656 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); 657 658 /* unhalt engine */ 659 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 660 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 661 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 662 } 663 664 /* enable DMA RB */ 665 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 666 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 667 668 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 669 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 670 #ifdef __BIG_ENDIAN 671 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 672 #endif 673 /* enable DMA IBs */ 674 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 675 676 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 677 sdma_v5_2_ctx_switch_enable(adev, true); 678 sdma_v5_2_enable(adev, true); 679 } 680 681 return amdgpu_ring_test_helper(ring); 682 } 683 684 /** 685 * sdma_v5_2_gfx_resume - setup and start the async dma engines 686 * 687 * @adev: amdgpu_device pointer 688 * 689 * Set up the gfx DMA ring buffers and enable them. 690 * Returns 0 for success, error for failure. 691 */ 692 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) 693 { 694 int i, r; 695 696 for (i = 0; i < adev->sdma.num_instances; i++) { 697 r = sdma_v5_2_gfx_resume_instance(adev, i, false); 698 if (r) 699 return r; 700 } 701 702 return 0; 703 } 704 705 /** 706 * sdma_v5_2_rlc_resume - setup and start the async dma engines 707 * 708 * @adev: amdgpu_device pointer 709 * 710 * Set up the compute DMA queues and enable them. 711 * Returns 0 for success, error for failure. 712 */ 713 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev) 714 { 715 return 0; 716 } 717 718 /** 719 * sdma_v5_2_load_microcode - load the sDMA ME ucode 720 * 721 * @adev: amdgpu_device pointer 722 * 723 * Loads the sDMA0/1/2/3 ucode. 724 * Returns 0 for success, -EINVAL if the ucode is not available. 725 */ 726 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev) 727 { 728 const struct sdma_firmware_header_v1_0 *hdr; 729 const __le32 *fw_data; 730 u32 fw_size; 731 int i, j; 732 733 /* halt the MEs */ 734 sdma_v5_2_enable(adev, false); 735 736 for (i = 0; i < adev->sdma.num_instances; i++) { 737 if (!adev->sdma.instance[i].fw) 738 return -EINVAL; 739 740 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 741 amdgpu_ucode_print_sdma_hdr(&hdr->header); 742 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 743 744 fw_data = (const __le32 *) 745 (adev->sdma.instance[i].fw->data + 746 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 747 748 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 749 750 for (j = 0; j < fw_size; j++) { 751 if (amdgpu_emu_mode == 1 && j % 500 == 0) 752 msleep(1); 753 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 754 } 755 756 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 757 } 758 759 return 0; 760 } 761 762 static int sdma_v5_2_soft_reset(struct amdgpu_ip_block *ip_block) 763 { 764 struct amdgpu_device *adev = ip_block->adev; 765 u32 grbm_soft_reset; 766 u32 tmp; 767 int i; 768 769 for (i = 0; i < adev->sdma.num_instances; i++) { 770 grbm_soft_reset = REG_SET_FIELD(0, 771 GRBM_SOFT_RESET, SOFT_RESET_SDMA0, 772 1); 773 grbm_soft_reset <<= i; 774 775 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 776 tmp |= grbm_soft_reset; 777 DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp); 778 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 779 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 780 781 udelay(50); 782 783 tmp &= ~grbm_soft_reset; 784 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 785 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 786 787 udelay(50); 788 } 789 790 return 0; 791 } 792 793 /** 794 * sdma_v5_2_start - setup and start the async dma engines 795 * 796 * @adev: amdgpu_device pointer 797 * 798 * Set up the DMA engines and enable them. 799 * Returns 0 for success, error for failure. 800 */ 801 static int sdma_v5_2_start(struct amdgpu_device *adev) 802 { 803 int r = 0; 804 struct amdgpu_ip_block *ip_block; 805 806 if (amdgpu_sriov_vf(adev)) { 807 sdma_v5_2_ctx_switch_enable(adev, false); 808 sdma_v5_2_enable(adev, false); 809 810 /* set RB registers */ 811 r = sdma_v5_2_gfx_resume(adev); 812 return r; 813 } 814 815 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 816 r = sdma_v5_2_load_microcode(adev); 817 if (r) 818 return r; 819 820 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */ 821 if (amdgpu_emu_mode == 1) 822 msleep(1000); 823 } 824 825 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SDMA); 826 if (!ip_block) 827 return -EINVAL; 828 829 sdma_v5_2_soft_reset(ip_block); 830 /* unhalt the MEs */ 831 sdma_v5_2_enable(adev, true); 832 /* enable sdma ring preemption */ 833 sdma_v5_2_ctx_switch_enable(adev, true); 834 835 /* start the gfx rings and rlc compute queues */ 836 r = sdma_v5_2_gfx_resume(adev); 837 if (r) 838 return r; 839 r = sdma_v5_2_rlc_resume(adev); 840 841 return r; 842 } 843 844 static int sdma_v5_2_mqd_init(struct amdgpu_device *adev, void *mqd, 845 struct amdgpu_mqd_prop *prop) 846 { 847 struct v10_sdma_mqd *m = mqd; 848 uint64_t wb_gpu_addr; 849 850 m->sdmax_rlcx_rb_cntl = 851 order_base_2(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 852 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 853 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | 854 1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT; 855 856 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8); 857 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); 858 859 m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0, 860 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 861 862 wb_gpu_addr = prop->wptr_gpu_addr; 863 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); 864 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); 865 866 wb_gpu_addr = prop->rptr_gpu_addr; 867 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); 868 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); 869 870 m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0, 871 mmSDMA0_GFX_IB_CNTL)); 872 873 m->sdmax_rlcx_doorbell_offset = 874 prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 875 876 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1); 877 878 return 0; 879 } 880 881 static void sdma_v5_2_set_mqd_funcs(struct amdgpu_device *adev) 882 { 883 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v10_sdma_mqd); 884 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v5_2_mqd_init; 885 } 886 887 /** 888 * sdma_v5_2_ring_test_ring - simple async dma engine test 889 * 890 * @ring: amdgpu_ring structure holding ring information 891 * 892 * Test the DMA engine by writing using it to write an 893 * value to memory. 894 * Returns 0 for success, error for failure. 895 */ 896 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring) 897 { 898 struct amdgpu_device *adev = ring->adev; 899 unsigned i; 900 unsigned index; 901 int r; 902 u32 tmp; 903 u64 gpu_addr; 904 905 tmp = 0xCAFEDEAD; 906 907 r = amdgpu_device_wb_get(adev, &index); 908 if (r) { 909 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 910 return r; 911 } 912 913 gpu_addr = adev->wb.gpu_addr + (index * 4); 914 adev->wb.wb[index] = cpu_to_le32(tmp); 915 916 r = amdgpu_ring_alloc(ring, 20); 917 if (r) { 918 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 919 amdgpu_device_wb_free(adev, index); 920 return r; 921 } 922 923 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 924 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 925 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 926 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 927 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 928 amdgpu_ring_write(ring, 0xDEADBEEF); 929 amdgpu_ring_commit(ring); 930 931 for (i = 0; i < adev->usec_timeout; i++) { 932 tmp = le32_to_cpu(adev->wb.wb[index]); 933 if (tmp == 0xDEADBEEF) 934 break; 935 if (amdgpu_emu_mode == 1) 936 msleep(1); 937 else 938 udelay(1); 939 } 940 941 if (i >= adev->usec_timeout) 942 r = -ETIMEDOUT; 943 944 amdgpu_device_wb_free(adev, index); 945 946 return r; 947 } 948 949 /** 950 * sdma_v5_2_ring_test_ib - test an IB on the DMA engine 951 * 952 * @ring: amdgpu_ring structure holding ring information 953 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 954 * 955 * Test a simple IB in the DMA ring. 956 * Returns 0 on success, error on failure. 957 */ 958 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) 959 { 960 struct amdgpu_device *adev = ring->adev; 961 struct amdgpu_ib ib; 962 struct dma_fence *f = NULL; 963 unsigned index; 964 long r; 965 u32 tmp = 0; 966 u64 gpu_addr; 967 968 tmp = 0xCAFEDEAD; 969 memset(&ib, 0, sizeof(ib)); 970 971 r = amdgpu_device_wb_get(adev, &index); 972 if (r) { 973 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 974 return r; 975 } 976 977 gpu_addr = adev->wb.gpu_addr + (index * 4); 978 adev->wb.wb[index] = cpu_to_le32(tmp); 979 980 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 981 if (r) { 982 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 983 goto err0; 984 } 985 986 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 987 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 988 ib.ptr[1] = lower_32_bits(gpu_addr); 989 ib.ptr[2] = upper_32_bits(gpu_addr); 990 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 991 ib.ptr[4] = 0xDEADBEEF; 992 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 993 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 994 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 995 ib.length_dw = 8; 996 997 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 998 if (r) 999 goto err1; 1000 1001 r = dma_fence_wait_timeout(f, false, timeout); 1002 if (r == 0) { 1003 DRM_ERROR("amdgpu: IB test timed out\n"); 1004 r = -ETIMEDOUT; 1005 goto err1; 1006 } else if (r < 0) { 1007 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1008 goto err1; 1009 } 1010 1011 tmp = le32_to_cpu(adev->wb.wb[index]); 1012 1013 if (tmp == 0xDEADBEEF) 1014 r = 0; 1015 else 1016 r = -EINVAL; 1017 1018 err1: 1019 amdgpu_ib_free(&ib, NULL); 1020 dma_fence_put(f); 1021 err0: 1022 amdgpu_device_wb_free(adev, index); 1023 return r; 1024 } 1025 1026 1027 /** 1028 * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART 1029 * 1030 * @ib: indirect buffer to fill with commands 1031 * @pe: addr of the page entry 1032 * @src: src addr to copy from 1033 * @count: number of page entries to update 1034 * 1035 * Update PTEs by copying them from the GART using sDMA. 1036 */ 1037 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib, 1038 uint64_t pe, uint64_t src, 1039 unsigned count) 1040 { 1041 unsigned bytes = count * 8; 1042 1043 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1044 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1045 ib->ptr[ib->length_dw++] = bytes - 1; 1046 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1047 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1048 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1049 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1050 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1051 1052 } 1053 1054 /** 1055 * sdma_v5_2_vm_write_pte - update PTEs by writing them manually 1056 * 1057 * @ib: indirect buffer to fill with commands 1058 * @pe: addr of the page entry 1059 * @value: dst addr to write into pe 1060 * @count: number of page entries to update 1061 * @incr: increase next addr by incr bytes 1062 * 1063 * Update PTEs by writing them manually using sDMA. 1064 */ 1065 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1066 uint64_t value, unsigned count, 1067 uint32_t incr) 1068 { 1069 unsigned ndw = count * 2; 1070 1071 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1072 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1073 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1074 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1075 ib->ptr[ib->length_dw++] = ndw - 1; 1076 for (; ndw > 0; ndw -= 2) { 1077 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1078 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1079 value += incr; 1080 } 1081 } 1082 1083 /** 1084 * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA 1085 * 1086 * @ib: indirect buffer to fill with commands 1087 * @pe: addr of the page entry 1088 * @addr: dst addr to write into pe 1089 * @count: number of page entries to update 1090 * @incr: increase next addr by incr bytes 1091 * @flags: access flags 1092 * 1093 * Update the page tables using sDMA. 1094 */ 1095 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib, 1096 uint64_t pe, 1097 uint64_t addr, unsigned count, 1098 uint32_t incr, uint64_t flags) 1099 { 1100 /* for physically contiguous pages (vram) */ 1101 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1102 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1103 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1104 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1105 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1106 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1107 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1108 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1109 ib->ptr[ib->length_dw++] = 0; 1110 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1111 } 1112 1113 /** 1114 * sdma_v5_2_ring_pad_ib - pad the IB 1115 * 1116 * @ib: indirect buffer to fill with padding 1117 * @ring: amdgpu_ring structure holding ring information 1118 * 1119 * Pad the IB with NOPs to a boundary multiple of 8. 1120 */ 1121 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1122 { 1123 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1124 u32 pad_count; 1125 int i; 1126 1127 pad_count = (-ib->length_dw) & 0x7; 1128 for (i = 0; i < pad_count; i++) 1129 if (sdma && sdma->burst_nop && (i == 0)) 1130 ib->ptr[ib->length_dw++] = 1131 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1132 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1133 else 1134 ib->ptr[ib->length_dw++] = 1135 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1136 } 1137 1138 1139 /** 1140 * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline 1141 * 1142 * @ring: amdgpu_ring pointer 1143 * 1144 * Make sure all previous operations are completed (CIK). 1145 */ 1146 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1147 { 1148 uint32_t seq = ring->fence_drv.sync_seq; 1149 uint64_t addr = ring->fence_drv.gpu_addr; 1150 1151 /* wait for idle */ 1152 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1153 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1154 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1155 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1156 amdgpu_ring_write(ring, addr & 0xfffffffc); 1157 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1158 amdgpu_ring_write(ring, seq); /* reference */ 1159 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1160 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1161 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1162 } 1163 1164 1165 /** 1166 * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA 1167 * 1168 * @ring: amdgpu_ring pointer 1169 * @vmid: vmid number to use 1170 * @pd_addr: address 1171 * 1172 * Update the page table base and flush the VM TLB 1173 * using sDMA. 1174 */ 1175 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring, 1176 unsigned vmid, uint64_t pd_addr) 1177 { 1178 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1179 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 1180 1181 /* Update the PD address for this VMID. */ 1182 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 1183 (hub->ctx_addr_distance * vmid), 1184 lower_32_bits(pd_addr)); 1185 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 1186 (hub->ctx_addr_distance * vmid), 1187 upper_32_bits(pd_addr)); 1188 1189 /* Trigger invalidation. */ 1190 amdgpu_ring_write(ring, 1191 SDMA_PKT_VM_INVALIDATION_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1192 SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(SDMA_SUBOP_VM_INVALIDATION) | 1193 SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(ring->vm_inv_eng) | 1194 SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(0x1f)); 1195 amdgpu_ring_write(ring, req); 1196 amdgpu_ring_write(ring, 0xFFFFFFFF); 1197 amdgpu_ring_write(ring, 1198 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(1 << vmid) | 1199 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(0x1F)); 1200 } 1201 1202 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring, 1203 uint32_t reg, uint32_t val) 1204 { 1205 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1206 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1207 amdgpu_ring_write(ring, reg); 1208 amdgpu_ring_write(ring, val); 1209 } 1210 1211 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1212 uint32_t val, uint32_t mask) 1213 { 1214 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1215 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1216 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1217 amdgpu_ring_write(ring, reg << 2); 1218 amdgpu_ring_write(ring, 0); 1219 amdgpu_ring_write(ring, val); /* reference */ 1220 amdgpu_ring_write(ring, mask); /* mask */ 1221 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1222 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1223 } 1224 1225 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1226 uint32_t reg0, uint32_t reg1, 1227 uint32_t ref, uint32_t mask) 1228 { 1229 amdgpu_ring_emit_wreg(ring, reg0, ref); 1230 /* wait for a cycle to reset vm_inv_eng*_ack */ 1231 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1232 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1233 } 1234 1235 static int sdma_v5_2_early_init(struct amdgpu_ip_block *ip_block) 1236 { 1237 struct amdgpu_device *adev = ip_block->adev; 1238 int r; 1239 1240 r = amdgpu_sdma_init_microcode(adev, 0, true); 1241 if (r) 1242 return r; 1243 1244 sdma_v5_2_set_ring_funcs(adev); 1245 sdma_v5_2_set_buffer_funcs(adev); 1246 sdma_v5_2_set_vm_pte_funcs(adev); 1247 sdma_v5_2_set_irq_funcs(adev); 1248 sdma_v5_2_set_mqd_funcs(adev); 1249 1250 return 0; 1251 } 1252 1253 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num) 1254 { 1255 switch (seq_num) { 1256 case 0: 1257 return SOC15_IH_CLIENTID_SDMA0; 1258 case 1: 1259 return SOC15_IH_CLIENTID_SDMA1; 1260 case 2: 1261 return SOC15_IH_CLIENTID_SDMA2; 1262 case 3: 1263 return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid; 1264 default: 1265 break; 1266 } 1267 return -EINVAL; 1268 } 1269 1270 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num) 1271 { 1272 switch (seq_num) { 1273 case 0: 1274 return SDMA0_5_0__SRCID__SDMA_TRAP; 1275 case 1: 1276 return SDMA1_5_0__SRCID__SDMA_TRAP; 1277 case 2: 1278 return SDMA2_5_0__SRCID__SDMA_TRAP; 1279 case 3: 1280 return SDMA3_5_0__SRCID__SDMA_TRAP; 1281 default: 1282 break; 1283 } 1284 return -EINVAL; 1285 } 1286 1287 static int sdma_v5_2_sw_init(struct amdgpu_ip_block *ip_block) 1288 { 1289 struct amdgpu_ring *ring; 1290 int r, i; 1291 struct amdgpu_device *adev = ip_block->adev; 1292 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2); 1293 uint32_t *ptr; 1294 1295 /* SDMA trap event */ 1296 for (i = 0; i < adev->sdma.num_instances; i++) { 1297 r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i), 1298 sdma_v5_2_seq_to_trap_id(i), 1299 &adev->sdma.trap_irq); 1300 if (r) 1301 return r; 1302 } 1303 1304 for (i = 0; i < adev->sdma.num_instances; i++) { 1305 ring = &adev->sdma.instance[i].ring; 1306 ring->ring_obj = NULL; 1307 ring->use_doorbell = true; 1308 ring->me = i; 1309 1310 DRM_INFO("use_doorbell being set to: [%s]\n", 1311 ring->use_doorbell?"true":"false"); 1312 1313 ring->doorbell_index = 1314 (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset 1315 1316 ring->vm_hub = AMDGPU_GFXHUB(0); 1317 sprintf(ring->name, "sdma%d", i); 1318 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1319 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1320 AMDGPU_RING_PRIO_DEFAULT, NULL); 1321 if (r) 1322 return r; 1323 } 1324 1325 adev->sdma.supported_reset = 1326 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); 1327 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1328 case IP_VERSION(5, 2, 0): 1329 case IP_VERSION(5, 2, 2): 1330 case IP_VERSION(5, 2, 3): 1331 case IP_VERSION(5, 2, 4): 1332 if (adev->sdma.instance[0].fw_version >= 76) 1333 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1334 break; 1335 case IP_VERSION(5, 2, 5): 1336 if (adev->sdma.instance[0].fw_version >= 34) 1337 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1338 break; 1339 default: 1340 break; 1341 } 1342 1343 /* Allocate memory for SDMA IP Dump buffer */ 1344 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); 1345 if (ptr) 1346 adev->sdma.ip_dump = ptr; 1347 else 1348 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n"); 1349 1350 r = amdgpu_sdma_sysfs_reset_mask_init(adev); 1351 if (r) 1352 return r; 1353 1354 return r; 1355 } 1356 1357 static int sdma_v5_2_sw_fini(struct amdgpu_ip_block *ip_block) 1358 { 1359 struct amdgpu_device *adev = ip_block->adev; 1360 int i; 1361 1362 for (i = 0; i < adev->sdma.num_instances; i++) 1363 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1364 1365 amdgpu_sdma_sysfs_reset_mask_fini(adev); 1366 amdgpu_sdma_destroy_inst_ctx(adev, true); 1367 1368 kfree(adev->sdma.ip_dump); 1369 1370 return 0; 1371 } 1372 1373 static int sdma_v5_2_hw_init(struct amdgpu_ip_block *ip_block) 1374 { 1375 struct amdgpu_device *adev = ip_block->adev; 1376 1377 return sdma_v5_2_start(adev); 1378 } 1379 1380 static int sdma_v5_2_hw_fini(struct amdgpu_ip_block *ip_block) 1381 { 1382 struct amdgpu_device *adev = ip_block->adev; 1383 1384 if (amdgpu_sriov_vf(adev)) 1385 return 0; 1386 1387 sdma_v5_2_ctx_switch_enable(adev, false); 1388 sdma_v5_2_enable(adev, false); 1389 1390 return 0; 1391 } 1392 1393 static int sdma_v5_2_suspend(struct amdgpu_ip_block *ip_block) 1394 { 1395 return sdma_v5_2_hw_fini(ip_block); 1396 } 1397 1398 static int sdma_v5_2_resume(struct amdgpu_ip_block *ip_block) 1399 { 1400 return sdma_v5_2_hw_init(ip_block); 1401 } 1402 1403 static bool sdma_v5_2_is_idle(struct amdgpu_ip_block *ip_block) 1404 { 1405 struct amdgpu_device *adev = ip_block->adev; 1406 u32 i; 1407 1408 for (i = 0; i < adev->sdma.num_instances; i++) { 1409 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1410 1411 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1412 return false; 1413 } 1414 1415 return true; 1416 } 1417 1418 static int sdma_v5_2_wait_for_idle(struct amdgpu_ip_block *ip_block) 1419 { 1420 unsigned i; 1421 u32 sdma0, sdma1, sdma2, sdma3; 1422 struct amdgpu_device *adev = ip_block->adev; 1423 1424 for (i = 0; i < adev->usec_timeout; i++) { 1425 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1426 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1427 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG)); 1428 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG)); 1429 1430 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK) 1431 return 0; 1432 udelay(1); 1433 } 1434 return -ETIMEDOUT; 1435 } 1436 1437 static int sdma_v5_2_reset_queue(struct amdgpu_ring *ring, unsigned int vmid) 1438 { 1439 struct amdgpu_device *adev = ring->adev; 1440 int i, j, r; 1441 u32 rb_cntl, ib_cntl, f32_cntl, freeze, cntl, preempt, soft_reset, stat1_reg; 1442 1443 if (amdgpu_sriov_vf(adev)) 1444 return -EINVAL; 1445 1446 for (i = 0; i < adev->sdma.num_instances; i++) { 1447 if (ring == &adev->sdma.instance[i].ring) 1448 break; 1449 } 1450 1451 if (i == adev->sdma.num_instances) { 1452 DRM_ERROR("sdma instance not found\n"); 1453 return -EINVAL; 1454 } 1455 1456 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 1457 1458 /* stop queue */ 1459 ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 1460 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 1461 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 1462 1463 rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 1464 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 1465 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 1466 1467 /*engine stop SDMA1_F32_CNTL.HALT to 1 and SDMAx_FREEZE freeze bit to 1 */ 1468 freeze = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE)); 1469 freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 1); 1470 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE), freeze); 1471 1472 for (j = 0; j < adev->usec_timeout; j++) { 1473 freeze = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE)); 1474 1475 if (REG_GET_FIELD(freeze, SDMA0_FREEZE, FROZEN) & 1) 1476 break; 1477 udelay(1); 1478 } 1479 1480 1481 if (j == adev->usec_timeout) { 1482 stat1_reg = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS1_REG)); 1483 if ((stat1_reg & 0x3FF) != 0x3FF) { 1484 DRM_ERROR("cannot soft reset as sdma not idle\n"); 1485 r = -ETIMEDOUT; 1486 goto err0; 1487 } 1488 } 1489 1490 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 1491 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 1492 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 1493 1494 cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); 1495 cntl = REG_SET_FIELD(cntl, SDMA0_CNTL, UTC_L1_ENABLE, 0); 1496 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), cntl); 1497 1498 /* soft reset SDMA_GFX_PREEMPT.IB_PREEMPT = 0 mmGRBM_SOFT_RESET.SOFT_RESET_SDMA0/1 = 1 */ 1499 preempt = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_PREEMPT)); 1500 preempt = REG_SET_FIELD(preempt, SDMA0_GFX_PREEMPT, IB_PREEMPT, 0); 1501 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_PREEMPT), preempt); 1502 1503 soft_reset = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 1504 soft_reset |= 1 << GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT << i; 1505 1506 1507 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, soft_reset); 1508 1509 udelay(50); 1510 1511 soft_reset &= ~(1 << GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT << i); 1512 1513 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, soft_reset); 1514 1515 /* unfreeze and unhalt */ 1516 freeze = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE)); 1517 freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 0); 1518 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE), freeze); 1519 1520 r = sdma_v5_2_gfx_resume_instance(adev, i, true); 1521 1522 err0: 1523 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 1524 return r; 1525 } 1526 1527 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring) 1528 { 1529 int i, r = 0; 1530 struct amdgpu_device *adev = ring->adev; 1531 u32 index = 0; 1532 u64 sdma_gfx_preempt; 1533 1534 amdgpu_sdma_get_index_from_ring(ring, &index); 1535 sdma_gfx_preempt = 1536 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT); 1537 1538 /* assert preemption condition */ 1539 amdgpu_ring_set_preempt_cond_exec(ring, false); 1540 1541 /* emit the trailing fence */ 1542 ring->trail_seq += 1; 1543 amdgpu_ring_alloc(ring, 10); 1544 sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1545 ring->trail_seq, 0); 1546 amdgpu_ring_commit(ring); 1547 1548 /* assert IB preemption */ 1549 WREG32(sdma_gfx_preempt, 1); 1550 1551 /* poll the trailing fence */ 1552 for (i = 0; i < adev->usec_timeout; i++) { 1553 if (ring->trail_seq == 1554 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1555 break; 1556 udelay(1); 1557 } 1558 1559 if (i >= adev->usec_timeout) { 1560 r = -EINVAL; 1561 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1562 } 1563 1564 /* deassert IB preemption */ 1565 WREG32(sdma_gfx_preempt, 0); 1566 1567 /* deassert the preemption condition */ 1568 amdgpu_ring_set_preempt_cond_exec(ring, true); 1569 return r; 1570 } 1571 1572 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev, 1573 struct amdgpu_irq_src *source, 1574 unsigned type, 1575 enum amdgpu_interrupt_state state) 1576 { 1577 u32 sdma_cntl; 1578 u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL); 1579 1580 if (!amdgpu_sriov_vf(adev)) { 1581 sdma_cntl = RREG32(reg_offset); 1582 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1583 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1584 WREG32(reg_offset, sdma_cntl); 1585 } 1586 1587 return 0; 1588 } 1589 1590 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev, 1591 struct amdgpu_irq_src *source, 1592 struct amdgpu_iv_entry *entry) 1593 { 1594 uint32_t mes_queue_id = entry->src_data[0]; 1595 1596 DRM_DEBUG("IH: SDMA trap\n"); 1597 1598 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 1599 struct amdgpu_mes_queue *queue; 1600 1601 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 1602 1603 spin_lock(&adev->mes.queue_id_lock); 1604 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 1605 if (queue) { 1606 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); 1607 amdgpu_fence_process(queue->ring); 1608 } 1609 spin_unlock(&adev->mes.queue_id_lock); 1610 return 0; 1611 } 1612 1613 switch (entry->client_id) { 1614 case SOC15_IH_CLIENTID_SDMA0: 1615 switch (entry->ring_id) { 1616 case 0: 1617 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1618 break; 1619 case 1: 1620 /* XXX compute */ 1621 break; 1622 case 2: 1623 /* XXX compute */ 1624 break; 1625 case 3: 1626 /* XXX page queue*/ 1627 break; 1628 } 1629 break; 1630 case SOC15_IH_CLIENTID_SDMA1: 1631 switch (entry->ring_id) { 1632 case 0: 1633 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1634 break; 1635 case 1: 1636 /* XXX compute */ 1637 break; 1638 case 2: 1639 /* XXX compute */ 1640 break; 1641 case 3: 1642 /* XXX page queue*/ 1643 break; 1644 } 1645 break; 1646 case SOC15_IH_CLIENTID_SDMA2: 1647 switch (entry->ring_id) { 1648 case 0: 1649 amdgpu_fence_process(&adev->sdma.instance[2].ring); 1650 break; 1651 case 1: 1652 /* XXX compute */ 1653 break; 1654 case 2: 1655 /* XXX compute */ 1656 break; 1657 case 3: 1658 /* XXX page queue*/ 1659 break; 1660 } 1661 break; 1662 case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid: 1663 switch (entry->ring_id) { 1664 case 0: 1665 amdgpu_fence_process(&adev->sdma.instance[3].ring); 1666 break; 1667 case 1: 1668 /* XXX compute */ 1669 break; 1670 case 2: 1671 /* XXX compute */ 1672 break; 1673 case 3: 1674 /* XXX page queue*/ 1675 break; 1676 } 1677 break; 1678 } 1679 return 0; 1680 } 1681 1682 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev, 1683 struct amdgpu_irq_src *source, 1684 struct amdgpu_iv_entry *entry) 1685 { 1686 return 0; 1687 } 1688 1689 static bool sdma_v5_2_firmware_mgcg_support(struct amdgpu_device *adev, 1690 int i) 1691 { 1692 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1693 case IP_VERSION(5, 2, 1): 1694 if (adev->sdma.instance[i].fw_version < 70) 1695 return false; 1696 break; 1697 case IP_VERSION(5, 2, 3): 1698 if (adev->sdma.instance[i].fw_version < 47) 1699 return false; 1700 break; 1701 case IP_VERSION(5, 2, 7): 1702 if (adev->sdma.instance[i].fw_version < 9) 1703 return false; 1704 break; 1705 default: 1706 return true; 1707 } 1708 1709 return true; 1710 1711 } 1712 1713 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev, 1714 bool enable) 1715 { 1716 uint32_t data, def; 1717 int i; 1718 1719 for (i = 0; i < adev->sdma.num_instances; i++) { 1720 1721 if (!sdma_v5_2_firmware_mgcg_support(adev, i)) 1722 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG; 1723 1724 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1725 /* Enable sdma clock gating */ 1726 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1727 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1728 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1729 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1730 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1731 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK | 1732 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK); 1733 if (def != data) 1734 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1735 } else { 1736 /* Disable sdma clock gating */ 1737 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1738 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1739 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1740 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1741 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1742 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK | 1743 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK); 1744 if (def != data) 1745 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1746 } 1747 } 1748 } 1749 1750 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev, 1751 bool enable) 1752 { 1753 uint32_t data, def; 1754 int i; 1755 1756 for (i = 0; i < adev->sdma.num_instances; i++) { 1757 if (adev->sdma.instance[i].fw_version < 70 && 1758 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == 1759 IP_VERSION(5, 2, 1)) 1760 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS; 1761 1762 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1763 /* Enable sdma mem light sleep */ 1764 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1765 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1766 if (def != data) 1767 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1768 1769 } else { 1770 /* Disable sdma mem light sleep */ 1771 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1772 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1773 if (def != data) 1774 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1775 1776 } 1777 } 1778 } 1779 1780 static int sdma_v5_2_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1781 enum amd_clockgating_state state) 1782 { 1783 struct amdgpu_device *adev = ip_block->adev; 1784 1785 if (amdgpu_sriov_vf(adev)) 1786 return 0; 1787 1788 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1789 case IP_VERSION(5, 2, 0): 1790 case IP_VERSION(5, 2, 2): 1791 case IP_VERSION(5, 2, 1): 1792 case IP_VERSION(5, 2, 4): 1793 case IP_VERSION(5, 2, 5): 1794 case IP_VERSION(5, 2, 6): 1795 case IP_VERSION(5, 2, 3): 1796 case IP_VERSION(5, 2, 7): 1797 sdma_v5_2_update_medium_grain_clock_gating(adev, 1798 state == AMD_CG_STATE_GATE); 1799 sdma_v5_2_update_medium_grain_light_sleep(adev, 1800 state == AMD_CG_STATE_GATE); 1801 break; 1802 default: 1803 break; 1804 } 1805 1806 return 0; 1807 } 1808 1809 static int sdma_v5_2_set_powergating_state(struct amdgpu_ip_block *ip_block, 1810 enum amd_powergating_state state) 1811 { 1812 return 0; 1813 } 1814 1815 static void sdma_v5_2_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1816 { 1817 struct amdgpu_device *adev = ip_block->adev; 1818 int data; 1819 1820 if (amdgpu_sriov_vf(adev)) 1821 *flags = 0; 1822 1823 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1824 data = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL)); 1825 if (!(data & SDMA0_CLK_CTRL__CGCG_EN_OVERRIDE_MASK)) 1826 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1827 1828 /* AMD_CG_SUPPORT_SDMA_LS */ 1829 data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); 1830 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1831 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1832 } 1833 1834 static void sdma_v5_2_ring_begin_use(struct amdgpu_ring *ring) 1835 { 1836 struct amdgpu_device *adev = ring->adev; 1837 1838 /* SDMA 5.2.3 (RMB) FW doesn't seem to properly 1839 * disallow GFXOFF in some cases leading to 1840 * hangs in SDMA. Disallow GFXOFF while SDMA is active. 1841 * We can probably just limit this to 5.2.3, 1842 * but it shouldn't hurt for other parts since 1843 * this GFXOFF will be disallowed anyway when SDMA is 1844 * active, this just makes it explicit. 1845 * sdma_v5_2_ring_set_wptr() takes advantage of this 1846 * to update the wptr because sometimes SDMA seems to miss 1847 * doorbells when entering PG. If you remove this, update 1848 * sdma_v5_2_ring_set_wptr() as well! 1849 */ 1850 amdgpu_gfx_off_ctrl(adev, false); 1851 } 1852 1853 static void sdma_v5_2_ring_end_use(struct amdgpu_ring *ring) 1854 { 1855 struct amdgpu_device *adev = ring->adev; 1856 1857 /* SDMA 5.2.3 (RMB) FW doesn't seem to properly 1858 * disallow GFXOFF in some cases leading to 1859 * hangs in SDMA. Allow GFXOFF when SDMA is complete. 1860 */ 1861 amdgpu_gfx_off_ctrl(adev, true); 1862 } 1863 1864 static void sdma_v5_2_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 1865 { 1866 struct amdgpu_device *adev = ip_block->adev; 1867 int i, j; 1868 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2); 1869 uint32_t instance_offset; 1870 1871 if (!adev->sdma.ip_dump) 1872 return; 1873 1874 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances); 1875 for (i = 0; i < adev->sdma.num_instances; i++) { 1876 instance_offset = i * reg_count; 1877 drm_printf(p, "\nInstance:%d\n", i); 1878 1879 for (j = 0; j < reg_count; j++) 1880 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_5_2[j].reg_name, 1881 adev->sdma.ip_dump[instance_offset + j]); 1882 } 1883 } 1884 1885 static void sdma_v5_2_dump_ip_state(struct amdgpu_ip_block *ip_block) 1886 { 1887 struct amdgpu_device *adev = ip_block->adev; 1888 int i, j; 1889 uint32_t instance_offset; 1890 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2); 1891 1892 if (!adev->sdma.ip_dump) 1893 return; 1894 1895 amdgpu_gfx_off_ctrl(adev, false); 1896 for (i = 0; i < adev->sdma.num_instances; i++) { 1897 instance_offset = i * reg_count; 1898 for (j = 0; j < reg_count; j++) 1899 adev->sdma.ip_dump[instance_offset + j] = 1900 RREG32(sdma_v5_2_get_reg_offset(adev, i, 1901 sdma_reg_list_5_2[j].reg_offset)); 1902 } 1903 amdgpu_gfx_off_ctrl(adev, true); 1904 } 1905 1906 static const struct amd_ip_funcs sdma_v5_2_ip_funcs = { 1907 .name = "sdma_v5_2", 1908 .early_init = sdma_v5_2_early_init, 1909 .sw_init = sdma_v5_2_sw_init, 1910 .sw_fini = sdma_v5_2_sw_fini, 1911 .hw_init = sdma_v5_2_hw_init, 1912 .hw_fini = sdma_v5_2_hw_fini, 1913 .suspend = sdma_v5_2_suspend, 1914 .resume = sdma_v5_2_resume, 1915 .is_idle = sdma_v5_2_is_idle, 1916 .wait_for_idle = sdma_v5_2_wait_for_idle, 1917 .soft_reset = sdma_v5_2_soft_reset, 1918 .set_clockgating_state = sdma_v5_2_set_clockgating_state, 1919 .set_powergating_state = sdma_v5_2_set_powergating_state, 1920 .get_clockgating_state = sdma_v5_2_get_clockgating_state, 1921 .dump_ip_state = sdma_v5_2_dump_ip_state, 1922 .print_ip_state = sdma_v5_2_print_ip_state, 1923 }; 1924 1925 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = { 1926 .type = AMDGPU_RING_TYPE_SDMA, 1927 .align_mask = 0xf, 1928 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1929 .support_64bit_ptrs = true, 1930 .secure_submission_supported = true, 1931 .get_rptr = sdma_v5_2_ring_get_rptr, 1932 .get_wptr = sdma_v5_2_ring_get_wptr, 1933 .set_wptr = sdma_v5_2_ring_set_wptr, 1934 .emit_frame_size = 1935 5 + /* sdma_v5_2_ring_init_cond_exec */ 1936 6 + /* sdma_v5_2_ring_emit_hdp_flush */ 1937 3 + /* hdp_invalidate */ 1938 6 + /* sdma_v5_2_ring_emit_pipeline_sync */ 1939 /* sdma_v5_2_ring_emit_vm_flush */ 1940 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1941 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1942 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */ 1943 .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */ 1944 .emit_ib = sdma_v5_2_ring_emit_ib, 1945 .emit_mem_sync = sdma_v5_2_ring_emit_mem_sync, 1946 .emit_fence = sdma_v5_2_ring_emit_fence, 1947 .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync, 1948 .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush, 1949 .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush, 1950 .test_ring = sdma_v5_2_ring_test_ring, 1951 .test_ib = sdma_v5_2_ring_test_ib, 1952 .insert_nop = sdma_v5_2_ring_insert_nop, 1953 .pad_ib = sdma_v5_2_ring_pad_ib, 1954 .begin_use = sdma_v5_2_ring_begin_use, 1955 .end_use = sdma_v5_2_ring_end_use, 1956 .emit_wreg = sdma_v5_2_ring_emit_wreg, 1957 .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait, 1958 .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait, 1959 .init_cond_exec = sdma_v5_2_ring_init_cond_exec, 1960 .preempt_ib = sdma_v5_2_ring_preempt_ib, 1961 .reset = sdma_v5_2_reset_queue, 1962 }; 1963 1964 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev) 1965 { 1966 int i; 1967 1968 for (i = 0; i < adev->sdma.num_instances; i++) { 1969 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs; 1970 adev->sdma.instance[i].ring.me = i; 1971 } 1972 } 1973 1974 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = { 1975 .set = sdma_v5_2_set_trap_irq_state, 1976 .process = sdma_v5_2_process_trap_irq, 1977 }; 1978 1979 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = { 1980 .process = sdma_v5_2_process_illegal_inst_irq, 1981 }; 1982 1983 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev) 1984 { 1985 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1986 adev->sdma.num_instances; 1987 adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs; 1988 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs; 1989 } 1990 1991 /** 1992 * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine 1993 * 1994 * @ib: indirect buffer to copy to 1995 * @src_offset: src GPU address 1996 * @dst_offset: dst GPU address 1997 * @byte_count: number of bytes to xfer 1998 * @copy_flags: copy flags for the buffers 1999 * 2000 * Copy GPU buffers using the DMA engine. 2001 * Used by the amdgpu ttm implementation to move pages if 2002 * registered as the asic copy callback. 2003 */ 2004 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib, 2005 uint64_t src_offset, 2006 uint64_t dst_offset, 2007 uint32_t byte_count, 2008 uint32_t copy_flags) 2009 { 2010 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 2011 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 2012 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0); 2013 ib->ptr[ib->length_dw++] = byte_count - 1; 2014 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 2015 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 2016 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 2017 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2018 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2019 } 2020 2021 /** 2022 * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine 2023 * 2024 * @ib: indirect buffer to fill 2025 * @src_data: value to write to buffer 2026 * @dst_offset: dst GPU address 2027 * @byte_count: number of bytes to xfer 2028 * 2029 * Fill GPU buffers using the DMA engine. 2030 */ 2031 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib, 2032 uint32_t src_data, 2033 uint64_t dst_offset, 2034 uint32_t byte_count) 2035 { 2036 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2037 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2038 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2039 ib->ptr[ib->length_dw++] = src_data; 2040 ib->ptr[ib->length_dw++] = byte_count - 1; 2041 } 2042 2043 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = { 2044 .copy_max_bytes = 0x400000, 2045 .copy_num_dw = 7, 2046 .emit_copy_buffer = sdma_v5_2_emit_copy_buffer, 2047 2048 .fill_max_bytes = 0x400000, 2049 .fill_num_dw = 5, 2050 .emit_fill_buffer = sdma_v5_2_emit_fill_buffer, 2051 }; 2052 2053 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev) 2054 { 2055 if (adev->mman.buffer_funcs == NULL) { 2056 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs; 2057 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2058 } 2059 } 2060 2061 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = { 2062 .copy_pte_num_dw = 7, 2063 .copy_pte = sdma_v5_2_vm_copy_pte, 2064 .write_pte = sdma_v5_2_vm_write_pte, 2065 .set_pte_pde = sdma_v5_2_vm_set_pte_pde, 2066 }; 2067 2068 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev) 2069 { 2070 unsigned i; 2071 2072 if (adev->vm_manager.vm_pte_funcs == NULL) { 2073 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs; 2074 for (i = 0; i < adev->sdma.num_instances; i++) { 2075 adev->vm_manager.vm_pte_scheds[i] = 2076 &adev->sdma.instance[i].ring.sched; 2077 } 2078 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 2079 } 2080 } 2081 2082 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = { 2083 .type = AMD_IP_BLOCK_TYPE_SDMA, 2084 .major = 5, 2085 .minor = 2, 2086 .rev = 0, 2087 .funcs = &sdma_v5_2_ip_funcs, 2088 }; 2089