1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_10_3_0_offset.h" 34 #include "gc/gc_10_3_0_sh_mask.h" 35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h" 36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h" 37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h" 38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h" 39 40 #include "soc15_common.h" 41 #include "soc15.h" 42 #include "navi10_sdma_pkt_open.h" 43 #include "nbio_v2_3.h" 44 #include "sdma_common.h" 45 #include "sdma_v5_2.h" 46 47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin"); 48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin"); 49 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin"); 50 MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin"); 51 52 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin"); 53 MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin"); 54 MODULE_FIRMWARE("amdgpu/sdma_5_2_6.bin"); 55 MODULE_FIRMWARE("amdgpu/sdma_5_2_7.bin"); 56 57 #define SDMA1_REG_OFFSET 0x600 58 #define SDMA3_REG_OFFSET 0x400 59 #define SDMA0_HYP_DEC_REG_START 0x5880 60 #define SDMA0_HYP_DEC_REG_END 0x5893 61 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 62 63 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev); 64 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev); 65 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev); 66 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev); 67 68 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 69 { 70 u32 base; 71 72 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 73 internal_offset <= SDMA0_HYP_DEC_REG_END) { 74 base = adev->reg_offset[GC_HWIP][0][1]; 75 if (instance != 0) 76 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance; 77 } else { 78 if (instance < 2) { 79 base = adev->reg_offset[GC_HWIP][0][0]; 80 if (instance == 1) 81 internal_offset += SDMA1_REG_OFFSET; 82 } else { 83 base = adev->reg_offset[GC_HWIP][0][2]; 84 if (instance == 3) 85 internal_offset += SDMA3_REG_OFFSET; 86 } 87 } 88 89 return base + internal_offset; 90 } 91 92 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring, 93 uint64_t addr) 94 { 95 unsigned ret; 96 97 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); 98 amdgpu_ring_write(ring, lower_32_bits(addr)); 99 amdgpu_ring_write(ring, upper_32_bits(addr)); 100 amdgpu_ring_write(ring, 1); 101 /* this is the offset we need patch later */ 102 ret = ring->wptr & ring->buf_mask; 103 /* insert dummy here and patch it later */ 104 amdgpu_ring_write(ring, 0); 105 106 return ret; 107 } 108 109 /** 110 * sdma_v5_2_ring_get_rptr - get the current read pointer 111 * 112 * @ring: amdgpu ring pointer 113 * 114 * Get the current rptr from the hardware (NAVI10+). 115 */ 116 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring) 117 { 118 u64 *rptr; 119 120 /* XXX check if swapping is necessary on BE */ 121 rptr = (u64 *)ring->rptr_cpu_addr; 122 123 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 124 return ((*rptr) >> 2); 125 } 126 127 /** 128 * sdma_v5_2_ring_get_wptr - get the current write pointer 129 * 130 * @ring: amdgpu ring pointer 131 * 132 * Get the current wptr from the hardware (NAVI10+). 133 */ 134 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring) 135 { 136 struct amdgpu_device *adev = ring->adev; 137 u64 wptr; 138 139 if (ring->use_doorbell) { 140 /* XXX check if swapping is necessary on BE */ 141 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 142 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 143 } else { 144 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); 145 wptr = wptr << 32; 146 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); 147 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr); 148 } 149 150 return wptr >> 2; 151 } 152 153 /** 154 * sdma_v5_2_ring_set_wptr - commit the write pointer 155 * 156 * @ring: amdgpu ring pointer 157 * 158 * Write the wptr back to the hardware (NAVI10+). 159 */ 160 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring) 161 { 162 struct amdgpu_device *adev = ring->adev; 163 164 DRM_DEBUG("Setting write pointer\n"); 165 if (ring->use_doorbell) { 166 DRM_DEBUG("Using doorbell -- " 167 "wptr_offs == 0x%08x " 168 "lower_32_bits(ring->wptr << 2) == 0x%08x " 169 "upper_32_bits(ring->wptr << 2) == 0x%08x\n", 170 ring->wptr_offs, 171 lower_32_bits(ring->wptr << 2), 172 upper_32_bits(ring->wptr << 2)); 173 /* XXX check if swapping is necessary on BE */ 174 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 175 ring->wptr << 2); 176 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 177 ring->doorbell_index, ring->wptr << 2); 178 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 179 /* SDMA seems to miss doorbells sometimes when powergating kicks in. 180 * Updating the wptr directly will wake it. This is only safe because 181 * we disallow gfxoff in begin_use() and then allow it again in end_use(). 182 */ 183 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), 184 lower_32_bits(ring->wptr << 2)); 185 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), 186 upper_32_bits(ring->wptr << 2)); 187 } else { 188 DRM_DEBUG("Not using doorbell -- " 189 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 190 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 191 ring->me, 192 lower_32_bits(ring->wptr << 2), 193 ring->me, 194 upper_32_bits(ring->wptr << 2)); 195 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), 196 lower_32_bits(ring->wptr << 2)); 197 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), 198 upper_32_bits(ring->wptr << 2)); 199 } 200 } 201 202 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 203 { 204 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 205 int i; 206 207 for (i = 0; i < count; i++) 208 if (sdma && sdma->burst_nop && (i == 0)) 209 amdgpu_ring_write(ring, ring->funcs->nop | 210 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 211 else 212 amdgpu_ring_write(ring, ring->funcs->nop); 213 } 214 215 /** 216 * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine 217 * 218 * @ring: amdgpu ring pointer 219 * @job: job to retrieve vmid from 220 * @ib: IB object to schedule 221 * @flags: unused 222 * 223 * Schedule an IB in the DMA ring. 224 */ 225 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring, 226 struct amdgpu_job *job, 227 struct amdgpu_ib *ib, 228 uint32_t flags) 229 { 230 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 231 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 232 233 /* An IB packet must end on a 8 DW boundary--the next dword 234 * must be on a 8-dword boundary. Our IB packet below is 6 235 * dwords long, thus add x number of NOPs, such that, in 236 * modular arithmetic, 237 * wptr + 6 + x = 8k, k >= 0, which in C is, 238 * (wptr + 6 + x) % 8 = 0. 239 * The expression below, is a solution of x. 240 */ 241 sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 242 243 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 244 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 245 /* base must be 32 byte aligned */ 246 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 247 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 248 amdgpu_ring_write(ring, ib->length_dw); 249 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 250 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 251 } 252 253 /** 254 * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse 255 * 256 * @ring: amdgpu ring pointer 257 * 258 * flush the IB by graphics cache rinse. 259 */ 260 static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring) 261 { 262 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | 263 SDMA_GCR_GLM_INV | SDMA_GCR_GL1_INV | 264 SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 265 SDMA_GCR_GLI_INV(1); 266 267 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 268 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ)); 269 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 270 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 271 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 272 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 273 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 274 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 275 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 276 } 277 278 /** 279 * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 280 * 281 * @ring: amdgpu ring pointer 282 * 283 * Emit an hdp flush packet on the requested DMA ring. 284 */ 285 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 286 { 287 struct amdgpu_device *adev = ring->adev; 288 u32 ref_and_mask = 0; 289 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 290 291 if (ring->me > 1) { 292 amdgpu_asic_flush_hdp(adev, ring); 293 } else { 294 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 295 296 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 297 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 298 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 299 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 300 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 301 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 302 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 303 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 304 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 305 } 306 } 307 308 /** 309 * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring 310 * 311 * @ring: amdgpu ring pointer 312 * @addr: address 313 * @seq: sequence number 314 * @flags: fence related flags 315 * 316 * Add a DMA fence packet to the ring to write 317 * the fence seq number and DMA trap packet to generate 318 * an interrupt if needed. 319 */ 320 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 321 unsigned flags) 322 { 323 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 324 /* write the fence */ 325 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 326 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 327 /* zero in first two bits */ 328 BUG_ON(addr & 0x3); 329 amdgpu_ring_write(ring, lower_32_bits(addr)); 330 amdgpu_ring_write(ring, upper_32_bits(addr)); 331 amdgpu_ring_write(ring, lower_32_bits(seq)); 332 333 /* optionally write high bits as well */ 334 if (write64bit) { 335 addr += 4; 336 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 337 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 338 /* zero in first two bits */ 339 BUG_ON(addr & 0x3); 340 amdgpu_ring_write(ring, lower_32_bits(addr)); 341 amdgpu_ring_write(ring, upper_32_bits(addr)); 342 amdgpu_ring_write(ring, upper_32_bits(seq)); 343 } 344 345 if ((flags & AMDGPU_FENCE_FLAG_INT)) { 346 uint32_t ctx = ring->is_mes_queue ? 347 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0; 348 /* generate an interrupt */ 349 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 350 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx)); 351 } 352 } 353 354 355 /** 356 * sdma_v5_2_gfx_stop - stop the gfx async dma engines 357 * 358 * @adev: amdgpu_device pointer 359 * 360 * Stop the gfx async dma ring buffers. 361 */ 362 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev) 363 { 364 u32 rb_cntl, ib_cntl; 365 int i; 366 367 for (i = 0; i < adev->sdma.num_instances; i++) { 368 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 369 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 370 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 371 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 372 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 373 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 374 } 375 } 376 377 /** 378 * sdma_v5_2_rlc_stop - stop the compute async dma engines 379 * 380 * @adev: amdgpu_device pointer 381 * 382 * Stop the compute async dma queues. 383 */ 384 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev) 385 { 386 /* XXX todo */ 387 } 388 389 /** 390 * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch 391 * 392 * @adev: amdgpu_device pointer 393 * @enable: enable/disable the DMA MEs context switch. 394 * 395 * Halt or unhalt the async dma engines context switch. 396 */ 397 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 398 { 399 u32 f32_cntl, phase_quantum = 0; 400 int i; 401 402 if (amdgpu_sdma_phase_quantum) { 403 unsigned value = amdgpu_sdma_phase_quantum; 404 unsigned unit = 0; 405 406 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 407 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 408 value = (value + 1) >> 1; 409 unit++; 410 } 411 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 412 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 413 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 414 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 415 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 416 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 417 WARN_ONCE(1, 418 "clamping sdma_phase_quantum to %uK clock cycles\n", 419 value << unit); 420 } 421 phase_quantum = 422 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 423 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 424 } 425 426 for (i = 0; i < adev->sdma.num_instances; i++) { 427 if (enable && amdgpu_sdma_phase_quantum) { 428 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 429 phase_quantum); 430 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 431 phase_quantum); 432 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 433 phase_quantum); 434 } 435 436 if (!amdgpu_sriov_vf(adev)) { 437 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); 438 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 439 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 440 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 441 } 442 } 443 444 } 445 446 /** 447 * sdma_v5_2_enable - stop the async dma engines 448 * 449 * @adev: amdgpu_device pointer 450 * @enable: enable/disable the DMA MEs. 451 * 452 * Halt or unhalt the async dma engines. 453 */ 454 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable) 455 { 456 u32 f32_cntl; 457 int i; 458 459 if (!enable) { 460 sdma_v5_2_gfx_stop(adev); 461 sdma_v5_2_rlc_stop(adev); 462 } 463 464 if (!amdgpu_sriov_vf(adev)) { 465 for (i = 0; i < adev->sdma.num_instances; i++) { 466 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 467 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 468 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 469 } 470 } 471 } 472 473 /** 474 * sdma_v5_2_gfx_resume - setup and start the async dma engines 475 * 476 * @adev: amdgpu_device pointer 477 * 478 * Set up the gfx DMA ring buffers and enable them. 479 * Returns 0 for success, error for failure. 480 */ 481 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) 482 { 483 struct amdgpu_ring *ring; 484 u32 rb_cntl, ib_cntl; 485 u32 rb_bufsz; 486 u32 doorbell; 487 u32 doorbell_offset; 488 u32 temp; 489 u32 wptr_poll_cntl; 490 u64 wptr_gpu_addr; 491 int i, r; 492 493 for (i = 0; i < adev->sdma.num_instances; i++) { 494 ring = &adev->sdma.instance[i].ring; 495 496 if (!amdgpu_sriov_vf(adev)) 497 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 498 499 /* Set ring buffer size in dwords */ 500 rb_bufsz = order_base_2(ring->ring_size / 4); 501 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 502 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 503 #ifdef __BIG_ENDIAN 504 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 505 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 506 RPTR_WRITEBACK_SWAP_ENABLE, 1); 507 #endif 508 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 509 510 /* Initialize the ring buffer's read and write pointers */ 511 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 512 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 513 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 514 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 515 516 /* setup the wptr shadow polling */ 517 wptr_gpu_addr = ring->wptr_gpu_addr; 518 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 519 lower_32_bits(wptr_gpu_addr)); 520 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 521 upper_32_bits(wptr_gpu_addr)); 522 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 523 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 524 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 525 SDMA0_GFX_RB_WPTR_POLL_CNTL, 526 F32_POLL_ENABLE, 1); 527 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 528 wptr_poll_cntl); 529 530 /* set the wb address whether it's enabled or not */ 531 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 532 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 533 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 534 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 535 536 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 537 538 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 539 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 540 541 ring->wptr = 0; 542 543 /* before programing wptr to a less value, need set minor_ptr_update first */ 544 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 545 546 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 547 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); 548 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); 549 } 550 551 doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 552 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); 553 554 if (ring->use_doorbell) { 555 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 556 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 557 OFFSET, ring->doorbell_index); 558 } else { 559 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 560 } 561 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 562 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 563 564 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 565 ring->doorbell_index, 566 adev->doorbell_index.sdma_doorbell_range); 567 568 if (amdgpu_sriov_vf(adev)) 569 sdma_v5_2_ring_set_wptr(ring); 570 571 /* set minor_ptr_update to 0 after wptr programed */ 572 573 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 574 575 /* SRIOV VF has no control of any of registers below */ 576 if (!amdgpu_sriov_vf(adev)) { 577 /* set utc l1 enable flag always to 1 */ 578 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); 579 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 580 581 /* enable MCBP */ 582 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); 583 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 584 585 /* Set up RESP_MODE to non-copy addresses */ 586 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); 587 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 588 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 589 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); 590 591 /* program default cache read and write policy */ 592 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); 593 /* clean read policy and write policy bits */ 594 temp &= 0xFF0FFF; 595 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | 596 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | 597 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK); 598 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); 599 600 /* unhalt engine */ 601 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 602 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 603 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 604 } 605 606 /* enable DMA RB */ 607 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 608 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 609 610 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 611 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 612 #ifdef __BIG_ENDIAN 613 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 614 #endif 615 /* enable DMA IBs */ 616 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 617 618 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 619 sdma_v5_2_ctx_switch_enable(adev, true); 620 sdma_v5_2_enable(adev, true); 621 } 622 623 r = amdgpu_ring_test_helper(ring); 624 if (r) 625 return r; 626 } 627 628 return 0; 629 } 630 631 /** 632 * sdma_v5_2_rlc_resume - setup and start the async dma engines 633 * 634 * @adev: amdgpu_device pointer 635 * 636 * Set up the compute DMA queues and enable them. 637 * Returns 0 for success, error for failure. 638 */ 639 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev) 640 { 641 return 0; 642 } 643 644 /** 645 * sdma_v5_2_load_microcode - load the sDMA ME ucode 646 * 647 * @adev: amdgpu_device pointer 648 * 649 * Loads the sDMA0/1/2/3 ucode. 650 * Returns 0 for success, -EINVAL if the ucode is not available. 651 */ 652 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev) 653 { 654 const struct sdma_firmware_header_v1_0 *hdr; 655 const __le32 *fw_data; 656 u32 fw_size; 657 int i, j; 658 659 /* halt the MEs */ 660 sdma_v5_2_enable(adev, false); 661 662 for (i = 0; i < adev->sdma.num_instances; i++) { 663 if (!adev->sdma.instance[i].fw) 664 return -EINVAL; 665 666 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 667 amdgpu_ucode_print_sdma_hdr(&hdr->header); 668 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 669 670 fw_data = (const __le32 *) 671 (adev->sdma.instance[i].fw->data + 672 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 673 674 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 675 676 for (j = 0; j < fw_size; j++) { 677 if (amdgpu_emu_mode == 1 && j % 500 == 0) 678 msleep(1); 679 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 680 } 681 682 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 683 } 684 685 return 0; 686 } 687 688 static int sdma_v5_2_soft_reset(void *handle) 689 { 690 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 691 u32 grbm_soft_reset; 692 u32 tmp; 693 int i; 694 695 for (i = 0; i < adev->sdma.num_instances; i++) { 696 grbm_soft_reset = REG_SET_FIELD(0, 697 GRBM_SOFT_RESET, SOFT_RESET_SDMA0, 698 1); 699 grbm_soft_reset <<= i; 700 701 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 702 tmp |= grbm_soft_reset; 703 DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp); 704 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 705 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 706 707 udelay(50); 708 709 tmp &= ~grbm_soft_reset; 710 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 711 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 712 713 udelay(50); 714 } 715 716 return 0; 717 } 718 719 /** 720 * sdma_v5_2_start - setup and start the async dma engines 721 * 722 * @adev: amdgpu_device pointer 723 * 724 * Set up the DMA engines and enable them. 725 * Returns 0 for success, error for failure. 726 */ 727 static int sdma_v5_2_start(struct amdgpu_device *adev) 728 { 729 int r = 0; 730 731 if (amdgpu_sriov_vf(adev)) { 732 sdma_v5_2_ctx_switch_enable(adev, false); 733 sdma_v5_2_enable(adev, false); 734 735 /* set RB registers */ 736 r = sdma_v5_2_gfx_resume(adev); 737 return r; 738 } 739 740 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 741 r = sdma_v5_2_load_microcode(adev); 742 if (r) 743 return r; 744 745 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */ 746 if (amdgpu_emu_mode == 1) 747 msleep(1000); 748 } 749 750 sdma_v5_2_soft_reset(adev); 751 /* unhalt the MEs */ 752 sdma_v5_2_enable(adev, true); 753 /* enable sdma ring preemption */ 754 sdma_v5_2_ctx_switch_enable(adev, true); 755 756 /* start the gfx rings and rlc compute queues */ 757 r = sdma_v5_2_gfx_resume(adev); 758 if (r) 759 return r; 760 r = sdma_v5_2_rlc_resume(adev); 761 762 return r; 763 } 764 765 static int sdma_v5_2_mqd_init(struct amdgpu_device *adev, void *mqd, 766 struct amdgpu_mqd_prop *prop) 767 { 768 struct v10_sdma_mqd *m = mqd; 769 uint64_t wb_gpu_addr; 770 771 m->sdmax_rlcx_rb_cntl = 772 order_base_2(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 773 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 774 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | 775 1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT; 776 777 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8); 778 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); 779 780 m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0, 781 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 782 783 wb_gpu_addr = prop->wptr_gpu_addr; 784 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); 785 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); 786 787 wb_gpu_addr = prop->rptr_gpu_addr; 788 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); 789 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); 790 791 m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0, 792 mmSDMA0_GFX_IB_CNTL)); 793 794 m->sdmax_rlcx_doorbell_offset = 795 prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 796 797 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1); 798 799 return 0; 800 } 801 802 static void sdma_v5_2_set_mqd_funcs(struct amdgpu_device *adev) 803 { 804 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v10_sdma_mqd); 805 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v5_2_mqd_init; 806 } 807 808 /** 809 * sdma_v5_2_ring_test_ring - simple async dma engine test 810 * 811 * @ring: amdgpu_ring structure holding ring information 812 * 813 * Test the DMA engine by writing using it to write an 814 * value to memory. 815 * Returns 0 for success, error for failure. 816 */ 817 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring) 818 { 819 struct amdgpu_device *adev = ring->adev; 820 unsigned i; 821 unsigned index; 822 int r; 823 u32 tmp; 824 u64 gpu_addr; 825 volatile uint32_t *cpu_ptr = NULL; 826 827 tmp = 0xCAFEDEAD; 828 829 if (ring->is_mes_queue) { 830 uint32_t offset = 0; 831 offset = amdgpu_mes_ctx_get_offs(ring, 832 AMDGPU_MES_CTX_PADDING_OFFS); 833 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 834 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 835 *cpu_ptr = tmp; 836 } else { 837 r = amdgpu_device_wb_get(adev, &index); 838 if (r) { 839 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 840 return r; 841 } 842 843 gpu_addr = adev->wb.gpu_addr + (index * 4); 844 adev->wb.wb[index] = cpu_to_le32(tmp); 845 } 846 847 r = amdgpu_ring_alloc(ring, 20); 848 if (r) { 849 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 850 if (!ring->is_mes_queue) 851 amdgpu_device_wb_free(adev, index); 852 return r; 853 } 854 855 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 856 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 857 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 858 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 859 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 860 amdgpu_ring_write(ring, 0xDEADBEEF); 861 amdgpu_ring_commit(ring); 862 863 for (i = 0; i < adev->usec_timeout; i++) { 864 if (ring->is_mes_queue) 865 tmp = le32_to_cpu(*cpu_ptr); 866 else 867 tmp = le32_to_cpu(adev->wb.wb[index]); 868 if (tmp == 0xDEADBEEF) 869 break; 870 if (amdgpu_emu_mode == 1) 871 msleep(1); 872 else 873 udelay(1); 874 } 875 876 if (i >= adev->usec_timeout) 877 r = -ETIMEDOUT; 878 879 if (!ring->is_mes_queue) 880 amdgpu_device_wb_free(adev, index); 881 882 return r; 883 } 884 885 /** 886 * sdma_v5_2_ring_test_ib - test an IB on the DMA engine 887 * 888 * @ring: amdgpu_ring structure holding ring information 889 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 890 * 891 * Test a simple IB in the DMA ring. 892 * Returns 0 on success, error on failure. 893 */ 894 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) 895 { 896 struct amdgpu_device *adev = ring->adev; 897 struct amdgpu_ib ib; 898 struct dma_fence *f = NULL; 899 unsigned index; 900 long r; 901 u32 tmp = 0; 902 u64 gpu_addr; 903 volatile uint32_t *cpu_ptr = NULL; 904 905 tmp = 0xCAFEDEAD; 906 memset(&ib, 0, sizeof(ib)); 907 908 if (ring->is_mes_queue) { 909 uint32_t offset = 0; 910 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 911 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 912 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 913 914 offset = amdgpu_mes_ctx_get_offs(ring, 915 AMDGPU_MES_CTX_PADDING_OFFS); 916 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 917 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 918 *cpu_ptr = tmp; 919 } else { 920 r = amdgpu_device_wb_get(adev, &index); 921 if (r) { 922 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 923 return r; 924 } 925 926 gpu_addr = adev->wb.gpu_addr + (index * 4); 927 adev->wb.wb[index] = cpu_to_le32(tmp); 928 929 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 930 if (r) { 931 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 932 goto err0; 933 } 934 } 935 936 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 937 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 938 ib.ptr[1] = lower_32_bits(gpu_addr); 939 ib.ptr[2] = upper_32_bits(gpu_addr); 940 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 941 ib.ptr[4] = 0xDEADBEEF; 942 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 943 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 944 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 945 ib.length_dw = 8; 946 947 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 948 if (r) 949 goto err1; 950 951 r = dma_fence_wait_timeout(f, false, timeout); 952 if (r == 0) { 953 DRM_ERROR("amdgpu: IB test timed out\n"); 954 r = -ETIMEDOUT; 955 goto err1; 956 } else if (r < 0) { 957 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 958 goto err1; 959 } 960 961 if (ring->is_mes_queue) 962 tmp = le32_to_cpu(*cpu_ptr); 963 else 964 tmp = le32_to_cpu(adev->wb.wb[index]); 965 966 if (tmp == 0xDEADBEEF) 967 r = 0; 968 else 969 r = -EINVAL; 970 971 err1: 972 amdgpu_ib_free(adev, &ib, NULL); 973 dma_fence_put(f); 974 err0: 975 if (!ring->is_mes_queue) 976 amdgpu_device_wb_free(adev, index); 977 return r; 978 } 979 980 981 /** 982 * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART 983 * 984 * @ib: indirect buffer to fill with commands 985 * @pe: addr of the page entry 986 * @src: src addr to copy from 987 * @count: number of page entries to update 988 * 989 * Update PTEs by copying them from the GART using sDMA. 990 */ 991 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib, 992 uint64_t pe, uint64_t src, 993 unsigned count) 994 { 995 unsigned bytes = count * 8; 996 997 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 998 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 999 ib->ptr[ib->length_dw++] = bytes - 1; 1000 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1001 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1002 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1003 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1004 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1005 1006 } 1007 1008 /** 1009 * sdma_v5_2_vm_write_pte - update PTEs by writing them manually 1010 * 1011 * @ib: indirect buffer to fill with commands 1012 * @pe: addr of the page entry 1013 * @value: dst addr to write into pe 1014 * @count: number of page entries to update 1015 * @incr: increase next addr by incr bytes 1016 * 1017 * Update PTEs by writing them manually using sDMA. 1018 */ 1019 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1020 uint64_t value, unsigned count, 1021 uint32_t incr) 1022 { 1023 unsigned ndw = count * 2; 1024 1025 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1026 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1027 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1028 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1029 ib->ptr[ib->length_dw++] = ndw - 1; 1030 for (; ndw > 0; ndw -= 2) { 1031 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1032 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1033 value += incr; 1034 } 1035 } 1036 1037 /** 1038 * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA 1039 * 1040 * @ib: indirect buffer to fill with commands 1041 * @pe: addr of the page entry 1042 * @addr: dst addr to write into pe 1043 * @count: number of page entries to update 1044 * @incr: increase next addr by incr bytes 1045 * @flags: access flags 1046 * 1047 * Update the page tables using sDMA. 1048 */ 1049 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib, 1050 uint64_t pe, 1051 uint64_t addr, unsigned count, 1052 uint32_t incr, uint64_t flags) 1053 { 1054 /* for physically contiguous pages (vram) */ 1055 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1056 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1057 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1058 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1059 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1060 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1061 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1062 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1063 ib->ptr[ib->length_dw++] = 0; 1064 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1065 } 1066 1067 /** 1068 * sdma_v5_2_ring_pad_ib - pad the IB 1069 * 1070 * @ib: indirect buffer to fill with padding 1071 * @ring: amdgpu_ring structure holding ring information 1072 * 1073 * Pad the IB with NOPs to a boundary multiple of 8. 1074 */ 1075 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1076 { 1077 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1078 u32 pad_count; 1079 int i; 1080 1081 pad_count = (-ib->length_dw) & 0x7; 1082 for (i = 0; i < pad_count; i++) 1083 if (sdma && sdma->burst_nop && (i == 0)) 1084 ib->ptr[ib->length_dw++] = 1085 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1086 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1087 else 1088 ib->ptr[ib->length_dw++] = 1089 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1090 } 1091 1092 1093 /** 1094 * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline 1095 * 1096 * @ring: amdgpu_ring pointer 1097 * 1098 * Make sure all previous operations are completed (CIK). 1099 */ 1100 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1101 { 1102 uint32_t seq = ring->fence_drv.sync_seq; 1103 uint64_t addr = ring->fence_drv.gpu_addr; 1104 1105 /* wait for idle */ 1106 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1107 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1108 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1109 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1110 amdgpu_ring_write(ring, addr & 0xfffffffc); 1111 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1112 amdgpu_ring_write(ring, seq); /* reference */ 1113 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1114 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1115 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1116 } 1117 1118 1119 /** 1120 * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA 1121 * 1122 * @ring: amdgpu_ring pointer 1123 * @vmid: vmid number to use 1124 * @pd_addr: address 1125 * 1126 * Update the page table base and flush the VM TLB 1127 * using sDMA. 1128 */ 1129 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring, 1130 unsigned vmid, uint64_t pd_addr) 1131 { 1132 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1133 } 1134 1135 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring, 1136 uint32_t reg, uint32_t val) 1137 { 1138 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1139 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1140 amdgpu_ring_write(ring, reg); 1141 amdgpu_ring_write(ring, val); 1142 } 1143 1144 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1145 uint32_t val, uint32_t mask) 1146 { 1147 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1148 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1149 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1150 amdgpu_ring_write(ring, reg << 2); 1151 amdgpu_ring_write(ring, 0); 1152 amdgpu_ring_write(ring, val); /* reference */ 1153 amdgpu_ring_write(ring, mask); /* mask */ 1154 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1155 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1156 } 1157 1158 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1159 uint32_t reg0, uint32_t reg1, 1160 uint32_t ref, uint32_t mask) 1161 { 1162 amdgpu_ring_emit_wreg(ring, reg0, ref); 1163 /* wait for a cycle to reset vm_inv_eng*_ack */ 1164 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1165 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1166 } 1167 1168 static int sdma_v5_2_early_init(void *handle) 1169 { 1170 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1171 int r; 1172 1173 r = amdgpu_sdma_init_microcode(adev, 0, true); 1174 if (r) 1175 return r; 1176 1177 sdma_v5_2_set_ring_funcs(adev); 1178 sdma_v5_2_set_buffer_funcs(adev); 1179 sdma_v5_2_set_vm_pte_funcs(adev); 1180 sdma_v5_2_set_irq_funcs(adev); 1181 sdma_v5_2_set_mqd_funcs(adev); 1182 1183 return 0; 1184 } 1185 1186 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num) 1187 { 1188 switch (seq_num) { 1189 case 0: 1190 return SOC15_IH_CLIENTID_SDMA0; 1191 case 1: 1192 return SOC15_IH_CLIENTID_SDMA1; 1193 case 2: 1194 return SOC15_IH_CLIENTID_SDMA2; 1195 case 3: 1196 return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid; 1197 default: 1198 break; 1199 } 1200 return -EINVAL; 1201 } 1202 1203 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num) 1204 { 1205 switch (seq_num) { 1206 case 0: 1207 return SDMA0_5_0__SRCID__SDMA_TRAP; 1208 case 1: 1209 return SDMA1_5_0__SRCID__SDMA_TRAP; 1210 case 2: 1211 return SDMA2_5_0__SRCID__SDMA_TRAP; 1212 case 3: 1213 return SDMA3_5_0__SRCID__SDMA_TRAP; 1214 default: 1215 break; 1216 } 1217 return -EINVAL; 1218 } 1219 1220 static int sdma_v5_2_sw_init(void *handle) 1221 { 1222 struct amdgpu_ring *ring; 1223 int r, i; 1224 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1225 1226 /* SDMA trap event */ 1227 for (i = 0; i < adev->sdma.num_instances; i++) { 1228 r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i), 1229 sdma_v5_2_seq_to_trap_id(i), 1230 &adev->sdma.trap_irq); 1231 if (r) 1232 return r; 1233 } 1234 1235 for (i = 0; i < adev->sdma.num_instances; i++) { 1236 ring = &adev->sdma.instance[i].ring; 1237 ring->ring_obj = NULL; 1238 ring->use_doorbell = true; 1239 ring->me = i; 1240 1241 DRM_INFO("use_doorbell being set to: [%s]\n", 1242 ring->use_doorbell?"true":"false"); 1243 1244 ring->doorbell_index = 1245 (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset 1246 1247 ring->vm_hub = AMDGPU_GFXHUB(0); 1248 sprintf(ring->name, "sdma%d", i); 1249 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1250 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1251 AMDGPU_RING_PRIO_DEFAULT, NULL); 1252 if (r) 1253 return r; 1254 } 1255 1256 return r; 1257 } 1258 1259 static int sdma_v5_2_sw_fini(void *handle) 1260 { 1261 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1262 int i; 1263 1264 for (i = 0; i < adev->sdma.num_instances; i++) 1265 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1266 1267 amdgpu_sdma_destroy_inst_ctx(adev, true); 1268 1269 return 0; 1270 } 1271 1272 static int sdma_v5_2_hw_init(void *handle) 1273 { 1274 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1275 1276 return sdma_v5_2_start(adev); 1277 } 1278 1279 static int sdma_v5_2_hw_fini(void *handle) 1280 { 1281 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1282 1283 if (amdgpu_sriov_vf(adev)) 1284 return 0; 1285 1286 sdma_v5_2_ctx_switch_enable(adev, false); 1287 sdma_v5_2_enable(adev, false); 1288 1289 return 0; 1290 } 1291 1292 static int sdma_v5_2_suspend(void *handle) 1293 { 1294 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1295 1296 return sdma_v5_2_hw_fini(adev); 1297 } 1298 1299 static int sdma_v5_2_resume(void *handle) 1300 { 1301 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1302 1303 return sdma_v5_2_hw_init(adev); 1304 } 1305 1306 static bool sdma_v5_2_is_idle(void *handle) 1307 { 1308 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1309 u32 i; 1310 1311 for (i = 0; i < adev->sdma.num_instances; i++) { 1312 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1313 1314 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1315 return false; 1316 } 1317 1318 return true; 1319 } 1320 1321 static int sdma_v5_2_wait_for_idle(void *handle) 1322 { 1323 unsigned i; 1324 u32 sdma0, sdma1, sdma2, sdma3; 1325 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1326 1327 for (i = 0; i < adev->usec_timeout; i++) { 1328 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1329 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1330 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG)); 1331 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG)); 1332 1333 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK) 1334 return 0; 1335 udelay(1); 1336 } 1337 return -ETIMEDOUT; 1338 } 1339 1340 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring) 1341 { 1342 int i, r = 0; 1343 struct amdgpu_device *adev = ring->adev; 1344 u32 index = 0; 1345 u64 sdma_gfx_preempt; 1346 1347 amdgpu_sdma_get_index_from_ring(ring, &index); 1348 sdma_gfx_preempt = 1349 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT); 1350 1351 /* assert preemption condition */ 1352 amdgpu_ring_set_preempt_cond_exec(ring, false); 1353 1354 /* emit the trailing fence */ 1355 ring->trail_seq += 1; 1356 amdgpu_ring_alloc(ring, 10); 1357 sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1358 ring->trail_seq, 0); 1359 amdgpu_ring_commit(ring); 1360 1361 /* assert IB preemption */ 1362 WREG32(sdma_gfx_preempt, 1); 1363 1364 /* poll the trailing fence */ 1365 for (i = 0; i < adev->usec_timeout; i++) { 1366 if (ring->trail_seq == 1367 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1368 break; 1369 udelay(1); 1370 } 1371 1372 if (i >= adev->usec_timeout) { 1373 r = -EINVAL; 1374 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1375 } 1376 1377 /* deassert IB preemption */ 1378 WREG32(sdma_gfx_preempt, 0); 1379 1380 /* deassert the preemption condition */ 1381 amdgpu_ring_set_preempt_cond_exec(ring, true); 1382 return r; 1383 } 1384 1385 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev, 1386 struct amdgpu_irq_src *source, 1387 unsigned type, 1388 enum amdgpu_interrupt_state state) 1389 { 1390 u32 sdma_cntl; 1391 u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL); 1392 1393 if (!amdgpu_sriov_vf(adev)) { 1394 sdma_cntl = RREG32(reg_offset); 1395 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1396 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1397 WREG32(reg_offset, sdma_cntl); 1398 } 1399 1400 return 0; 1401 } 1402 1403 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev, 1404 struct amdgpu_irq_src *source, 1405 struct amdgpu_iv_entry *entry) 1406 { 1407 uint32_t mes_queue_id = entry->src_data[0]; 1408 1409 DRM_DEBUG("IH: SDMA trap\n"); 1410 1411 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 1412 struct amdgpu_mes_queue *queue; 1413 1414 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 1415 1416 spin_lock(&adev->mes.queue_id_lock); 1417 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 1418 if (queue) { 1419 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); 1420 amdgpu_fence_process(queue->ring); 1421 } 1422 spin_unlock(&adev->mes.queue_id_lock); 1423 return 0; 1424 } 1425 1426 switch (entry->client_id) { 1427 case SOC15_IH_CLIENTID_SDMA0: 1428 switch (entry->ring_id) { 1429 case 0: 1430 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1431 break; 1432 case 1: 1433 /* XXX compute */ 1434 break; 1435 case 2: 1436 /* XXX compute */ 1437 break; 1438 case 3: 1439 /* XXX page queue*/ 1440 break; 1441 } 1442 break; 1443 case SOC15_IH_CLIENTID_SDMA1: 1444 switch (entry->ring_id) { 1445 case 0: 1446 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1447 break; 1448 case 1: 1449 /* XXX compute */ 1450 break; 1451 case 2: 1452 /* XXX compute */ 1453 break; 1454 case 3: 1455 /* XXX page queue*/ 1456 break; 1457 } 1458 break; 1459 case SOC15_IH_CLIENTID_SDMA2: 1460 switch (entry->ring_id) { 1461 case 0: 1462 amdgpu_fence_process(&adev->sdma.instance[2].ring); 1463 break; 1464 case 1: 1465 /* XXX compute */ 1466 break; 1467 case 2: 1468 /* XXX compute */ 1469 break; 1470 case 3: 1471 /* XXX page queue*/ 1472 break; 1473 } 1474 break; 1475 case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid: 1476 switch (entry->ring_id) { 1477 case 0: 1478 amdgpu_fence_process(&adev->sdma.instance[3].ring); 1479 break; 1480 case 1: 1481 /* XXX compute */ 1482 break; 1483 case 2: 1484 /* XXX compute */ 1485 break; 1486 case 3: 1487 /* XXX page queue*/ 1488 break; 1489 } 1490 break; 1491 } 1492 return 0; 1493 } 1494 1495 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev, 1496 struct amdgpu_irq_src *source, 1497 struct amdgpu_iv_entry *entry) 1498 { 1499 return 0; 1500 } 1501 1502 static bool sdma_v5_2_firmware_mgcg_support(struct amdgpu_device *adev, 1503 int i) 1504 { 1505 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1506 case IP_VERSION(5, 2, 1): 1507 if (adev->sdma.instance[i].fw_version < 70) 1508 return false; 1509 break; 1510 case IP_VERSION(5, 2, 3): 1511 if (adev->sdma.instance[i].fw_version < 47) 1512 return false; 1513 break; 1514 case IP_VERSION(5, 2, 7): 1515 if (adev->sdma.instance[i].fw_version < 9) 1516 return false; 1517 break; 1518 default: 1519 return true; 1520 } 1521 1522 return true; 1523 1524 } 1525 1526 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev, 1527 bool enable) 1528 { 1529 uint32_t data, def; 1530 int i; 1531 1532 for (i = 0; i < adev->sdma.num_instances; i++) { 1533 1534 if (!sdma_v5_2_firmware_mgcg_support(adev, i)) 1535 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG; 1536 1537 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1538 /* Enable sdma clock gating */ 1539 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1540 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1541 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1542 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1543 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1544 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK | 1545 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK); 1546 if (def != data) 1547 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1548 } else { 1549 /* Disable sdma clock gating */ 1550 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1551 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1552 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1553 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1554 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1555 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK | 1556 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK); 1557 if (def != data) 1558 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1559 } 1560 } 1561 } 1562 1563 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev, 1564 bool enable) 1565 { 1566 uint32_t data, def; 1567 int i; 1568 1569 for (i = 0; i < adev->sdma.num_instances; i++) { 1570 if (adev->sdma.instance[i].fw_version < 70 && 1571 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == 1572 IP_VERSION(5, 2, 1)) 1573 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS; 1574 1575 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1576 /* Enable sdma mem light sleep */ 1577 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1578 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1579 if (def != data) 1580 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1581 1582 } else { 1583 /* Disable sdma mem light sleep */ 1584 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1585 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1586 if (def != data) 1587 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1588 1589 } 1590 } 1591 } 1592 1593 static int sdma_v5_2_set_clockgating_state(void *handle, 1594 enum amd_clockgating_state state) 1595 { 1596 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1597 1598 if (amdgpu_sriov_vf(adev)) 1599 return 0; 1600 1601 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1602 case IP_VERSION(5, 2, 0): 1603 case IP_VERSION(5, 2, 2): 1604 case IP_VERSION(5, 2, 1): 1605 case IP_VERSION(5, 2, 4): 1606 case IP_VERSION(5, 2, 5): 1607 case IP_VERSION(5, 2, 6): 1608 case IP_VERSION(5, 2, 3): 1609 case IP_VERSION(5, 2, 7): 1610 sdma_v5_2_update_medium_grain_clock_gating(adev, 1611 state == AMD_CG_STATE_GATE); 1612 sdma_v5_2_update_medium_grain_light_sleep(adev, 1613 state == AMD_CG_STATE_GATE); 1614 break; 1615 default: 1616 break; 1617 } 1618 1619 return 0; 1620 } 1621 1622 static int sdma_v5_2_set_powergating_state(void *handle, 1623 enum amd_powergating_state state) 1624 { 1625 return 0; 1626 } 1627 1628 static void sdma_v5_2_get_clockgating_state(void *handle, u64 *flags) 1629 { 1630 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1631 int data; 1632 1633 if (amdgpu_sriov_vf(adev)) 1634 *flags = 0; 1635 1636 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1637 data = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL)); 1638 if (!(data & SDMA0_CLK_CTRL__CGCG_EN_OVERRIDE_MASK)) 1639 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1640 1641 /* AMD_CG_SUPPORT_SDMA_LS */ 1642 data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); 1643 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1644 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1645 } 1646 1647 static void sdma_v5_2_ring_begin_use(struct amdgpu_ring *ring) 1648 { 1649 struct amdgpu_device *adev = ring->adev; 1650 1651 /* SDMA 5.2.3 (RMB) FW doesn't seem to properly 1652 * disallow GFXOFF in some cases leading to 1653 * hangs in SDMA. Disallow GFXOFF while SDMA is active. 1654 * We can probably just limit this to 5.2.3, 1655 * but it shouldn't hurt for other parts since 1656 * this GFXOFF will be disallowed anyway when SDMA is 1657 * active, this just makes it explicit. 1658 * sdma_v5_2_ring_set_wptr() takes advantage of this 1659 * to update the wptr because sometimes SDMA seems to miss 1660 * doorbells when entering PG. If you remove this, update 1661 * sdma_v5_2_ring_set_wptr() as well! 1662 */ 1663 amdgpu_gfx_off_ctrl(adev, false); 1664 } 1665 1666 static void sdma_v5_2_ring_end_use(struct amdgpu_ring *ring) 1667 { 1668 struct amdgpu_device *adev = ring->adev; 1669 1670 /* SDMA 5.2.3 (RMB) FW doesn't seem to properly 1671 * disallow GFXOFF in some cases leading to 1672 * hangs in SDMA. Allow GFXOFF when SDMA is complete. 1673 */ 1674 amdgpu_gfx_off_ctrl(adev, true); 1675 } 1676 1677 const struct amd_ip_funcs sdma_v5_2_ip_funcs = { 1678 .name = "sdma_v5_2", 1679 .early_init = sdma_v5_2_early_init, 1680 .late_init = NULL, 1681 .sw_init = sdma_v5_2_sw_init, 1682 .sw_fini = sdma_v5_2_sw_fini, 1683 .hw_init = sdma_v5_2_hw_init, 1684 .hw_fini = sdma_v5_2_hw_fini, 1685 .suspend = sdma_v5_2_suspend, 1686 .resume = sdma_v5_2_resume, 1687 .is_idle = sdma_v5_2_is_idle, 1688 .wait_for_idle = sdma_v5_2_wait_for_idle, 1689 .soft_reset = sdma_v5_2_soft_reset, 1690 .set_clockgating_state = sdma_v5_2_set_clockgating_state, 1691 .set_powergating_state = sdma_v5_2_set_powergating_state, 1692 .get_clockgating_state = sdma_v5_2_get_clockgating_state, 1693 }; 1694 1695 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = { 1696 .type = AMDGPU_RING_TYPE_SDMA, 1697 .align_mask = 0xf, 1698 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1699 .support_64bit_ptrs = true, 1700 .secure_submission_supported = true, 1701 .get_rptr = sdma_v5_2_ring_get_rptr, 1702 .get_wptr = sdma_v5_2_ring_get_wptr, 1703 .set_wptr = sdma_v5_2_ring_set_wptr, 1704 .emit_frame_size = 1705 5 + /* sdma_v5_2_ring_init_cond_exec */ 1706 6 + /* sdma_v5_2_ring_emit_hdp_flush */ 1707 3 + /* hdp_invalidate */ 1708 6 + /* sdma_v5_2_ring_emit_pipeline_sync */ 1709 /* sdma_v5_2_ring_emit_vm_flush */ 1710 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1711 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1712 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */ 1713 .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */ 1714 .emit_ib = sdma_v5_2_ring_emit_ib, 1715 .emit_mem_sync = sdma_v5_2_ring_emit_mem_sync, 1716 .emit_fence = sdma_v5_2_ring_emit_fence, 1717 .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync, 1718 .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush, 1719 .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush, 1720 .test_ring = sdma_v5_2_ring_test_ring, 1721 .test_ib = sdma_v5_2_ring_test_ib, 1722 .insert_nop = sdma_v5_2_ring_insert_nop, 1723 .pad_ib = sdma_v5_2_ring_pad_ib, 1724 .begin_use = sdma_v5_2_ring_begin_use, 1725 .end_use = sdma_v5_2_ring_end_use, 1726 .emit_wreg = sdma_v5_2_ring_emit_wreg, 1727 .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait, 1728 .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait, 1729 .init_cond_exec = sdma_v5_2_ring_init_cond_exec, 1730 .preempt_ib = sdma_v5_2_ring_preempt_ib, 1731 }; 1732 1733 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev) 1734 { 1735 int i; 1736 1737 for (i = 0; i < adev->sdma.num_instances; i++) { 1738 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs; 1739 adev->sdma.instance[i].ring.me = i; 1740 } 1741 } 1742 1743 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = { 1744 .set = sdma_v5_2_set_trap_irq_state, 1745 .process = sdma_v5_2_process_trap_irq, 1746 }; 1747 1748 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = { 1749 .process = sdma_v5_2_process_illegal_inst_irq, 1750 }; 1751 1752 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev) 1753 { 1754 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1755 adev->sdma.num_instances; 1756 adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs; 1757 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs; 1758 } 1759 1760 /** 1761 * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine 1762 * 1763 * @ib: indirect buffer to copy to 1764 * @src_offset: src GPU address 1765 * @dst_offset: dst GPU address 1766 * @byte_count: number of bytes to xfer 1767 * @copy_flags: copy flags for the buffers 1768 * 1769 * Copy GPU buffers using the DMA engine. 1770 * Used by the amdgpu ttm implementation to move pages if 1771 * registered as the asic copy callback. 1772 */ 1773 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib, 1774 uint64_t src_offset, 1775 uint64_t dst_offset, 1776 uint32_t byte_count, 1777 uint32_t copy_flags) 1778 { 1779 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1780 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1781 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0); 1782 ib->ptr[ib->length_dw++] = byte_count - 1; 1783 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1784 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1785 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1786 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1787 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1788 } 1789 1790 /** 1791 * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine 1792 * 1793 * @ib: indirect buffer to fill 1794 * @src_data: value to write to buffer 1795 * @dst_offset: dst GPU address 1796 * @byte_count: number of bytes to xfer 1797 * 1798 * Fill GPU buffers using the DMA engine. 1799 */ 1800 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib, 1801 uint32_t src_data, 1802 uint64_t dst_offset, 1803 uint32_t byte_count) 1804 { 1805 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1806 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1807 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1808 ib->ptr[ib->length_dw++] = src_data; 1809 ib->ptr[ib->length_dw++] = byte_count - 1; 1810 } 1811 1812 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = { 1813 .copy_max_bytes = 0x400000, 1814 .copy_num_dw = 7, 1815 .emit_copy_buffer = sdma_v5_2_emit_copy_buffer, 1816 1817 .fill_max_bytes = 0x400000, 1818 .fill_num_dw = 5, 1819 .emit_fill_buffer = sdma_v5_2_emit_fill_buffer, 1820 }; 1821 1822 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev) 1823 { 1824 if (adev->mman.buffer_funcs == NULL) { 1825 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs; 1826 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1827 } 1828 } 1829 1830 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = { 1831 .copy_pte_num_dw = 7, 1832 .copy_pte = sdma_v5_2_vm_copy_pte, 1833 .write_pte = sdma_v5_2_vm_write_pte, 1834 .set_pte_pde = sdma_v5_2_vm_set_pte_pde, 1835 }; 1836 1837 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev) 1838 { 1839 unsigned i; 1840 1841 if (adev->vm_manager.vm_pte_funcs == NULL) { 1842 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs; 1843 for (i = 0; i < adev->sdma.num_instances; i++) { 1844 adev->vm_manager.vm_pte_scheds[i] = 1845 &adev->sdma.instance[i].ring.sched; 1846 } 1847 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1848 } 1849 } 1850 1851 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = { 1852 .type = AMD_IP_BLOCK_TYPE_SDMA, 1853 .major = 5, 1854 .minor = 2, 1855 .rev = 0, 1856 .funcs = &sdma_v5_2_ip_funcs, 1857 }; 1858