1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_10_3_0_offset.h" 34 #include "gc/gc_10_3_0_sh_mask.h" 35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h" 36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h" 37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h" 38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h" 39 40 #include "soc15_common.h" 41 #include "soc15.h" 42 #include "navi10_sdma_pkt_open.h" 43 #include "nbio_v2_3.h" 44 #include "sdma_common.h" 45 #include "sdma_v5_2.h" 46 47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin"); 48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin"); 49 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin"); 50 MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin"); 51 52 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin"); 53 MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin"); 54 MODULE_FIRMWARE("amdgpu/sdma_5_2_7.bin"); 55 56 #define SDMA1_REG_OFFSET 0x600 57 #define SDMA3_REG_OFFSET 0x400 58 #define SDMA0_HYP_DEC_REG_START 0x5880 59 #define SDMA0_HYP_DEC_REG_END 0x5893 60 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 61 62 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev); 63 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev); 64 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev); 65 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev); 66 67 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 68 { 69 u32 base; 70 71 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 72 internal_offset <= SDMA0_HYP_DEC_REG_END) { 73 base = adev->reg_offset[GC_HWIP][0][1]; 74 if (instance != 0) 75 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance; 76 } else { 77 if (instance < 2) { 78 base = adev->reg_offset[GC_HWIP][0][0]; 79 if (instance == 1) 80 internal_offset += SDMA1_REG_OFFSET; 81 } else { 82 base = adev->reg_offset[GC_HWIP][0][2]; 83 if (instance == 3) 84 internal_offset += SDMA3_REG_OFFSET; 85 } 86 } 87 88 return base + internal_offset; 89 } 90 91 static int sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst) 92 { 93 int err = 0; 94 const struct sdma_firmware_header_v1_0 *hdr; 95 96 err = amdgpu_ucode_validate(sdma_inst->fw); 97 if (err) 98 return err; 99 100 hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data; 101 sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version); 102 sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version); 103 104 if (sdma_inst->feature_version >= 20) 105 sdma_inst->burst_nop = true; 106 107 return 0; 108 } 109 110 static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev) 111 { 112 release_firmware(adev->sdma.instance[0].fw); 113 114 memset((void *)adev->sdma.instance, 0, 115 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES); 116 } 117 118 /** 119 * sdma_v5_2_init_microcode - load ucode images from disk 120 * 121 * @adev: amdgpu_device pointer 122 * 123 * Use the firmware interface to load the ucode images into 124 * the driver (not loaded into hw). 125 * Returns 0 on success, error on failure. 126 */ 127 128 // emulation only, won't work on real chip 129 // navi10 real chip need to use PSP to load firmware 130 static int sdma_v5_2_init_microcode(struct amdgpu_device *adev) 131 { 132 const char *chip_name; 133 char fw_name[40]; 134 int err = 0, i; 135 struct amdgpu_firmware_info *info = NULL; 136 const struct common_firmware_header *header = NULL; 137 138 DRM_DEBUG("\n"); 139 140 switch (adev->ip_versions[SDMA0_HWIP][0]) { 141 case IP_VERSION(5, 2, 0): 142 chip_name = "sienna_cichlid_sdma"; 143 break; 144 case IP_VERSION(5, 2, 2): 145 chip_name = "navy_flounder_sdma"; 146 break; 147 case IP_VERSION(5, 2, 1): 148 chip_name = "vangogh_sdma"; 149 break; 150 case IP_VERSION(5, 2, 4): 151 chip_name = "dimgrey_cavefish_sdma"; 152 break; 153 case IP_VERSION(5, 2, 5): 154 chip_name = "beige_goby_sdma"; 155 break; 156 case IP_VERSION(5, 2, 3): 157 chip_name = "yellow_carp_sdma"; 158 break; 159 case IP_VERSION(5, 2, 7): 160 chip_name = "sdma_5_2_7"; 161 break; 162 163 default: 164 BUG(); 165 } 166 167 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name); 168 169 err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev); 170 if (err) 171 goto out; 172 173 err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]); 174 if (err) 175 goto out; 176 177 for (i = 1; i < adev->sdma.num_instances; i++) 178 memcpy((void *)&adev->sdma.instance[i], 179 (void *)&adev->sdma.instance[0], 180 sizeof(struct amdgpu_sdma_instance)); 181 182 if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 0))) 183 return 0; 184 185 DRM_DEBUG("psp_load == '%s'\n", 186 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 187 188 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 189 for (i = 0; i < adev->sdma.num_instances; i++) { 190 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 191 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 192 info->fw = adev->sdma.instance[i].fw; 193 header = (const struct common_firmware_header *)info->fw->data; 194 adev->firmware.fw_size += 195 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 196 } 197 } 198 199 out: 200 if (err) { 201 DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name); 202 sdma_v5_2_destroy_inst_ctx(adev); 203 } 204 return err; 205 } 206 207 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring) 208 { 209 unsigned ret; 210 211 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); 212 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 213 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 214 amdgpu_ring_write(ring, 1); 215 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ 216 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ 217 218 return ret; 219 } 220 221 static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring, 222 unsigned offset) 223 { 224 unsigned cur; 225 226 BUG_ON(offset > ring->buf_mask); 227 BUG_ON(ring->ring[offset] != 0x55aa55aa); 228 229 cur = (ring->wptr - 1) & ring->buf_mask; 230 if (cur > offset) 231 ring->ring[offset] = cur - offset; 232 else 233 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 234 } 235 236 /** 237 * sdma_v5_2_ring_get_rptr - get the current read pointer 238 * 239 * @ring: amdgpu ring pointer 240 * 241 * Get the current rptr from the hardware (NAVI10+). 242 */ 243 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring) 244 { 245 u64 *rptr; 246 247 /* XXX check if swapping is necessary on BE */ 248 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 249 250 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 251 return ((*rptr) >> 2); 252 } 253 254 /** 255 * sdma_v5_2_ring_get_wptr - get the current write pointer 256 * 257 * @ring: amdgpu ring pointer 258 * 259 * Get the current wptr from the hardware (NAVI10+). 260 */ 261 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring) 262 { 263 struct amdgpu_device *adev = ring->adev; 264 u64 wptr; 265 266 if (ring->use_doorbell) { 267 /* XXX check if swapping is necessary on BE */ 268 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 269 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 270 } else { 271 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); 272 wptr = wptr << 32; 273 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); 274 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr); 275 } 276 277 return wptr >> 2; 278 } 279 280 /** 281 * sdma_v5_2_ring_set_wptr - commit the write pointer 282 * 283 * @ring: amdgpu ring pointer 284 * 285 * Write the wptr back to the hardware (NAVI10+). 286 */ 287 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring) 288 { 289 struct amdgpu_device *adev = ring->adev; 290 291 DRM_DEBUG("Setting write pointer\n"); 292 if (ring->use_doorbell) { 293 DRM_DEBUG("Using doorbell -- " 294 "wptr_offs == 0x%08x " 295 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 296 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 297 ring->wptr_offs, 298 lower_32_bits(ring->wptr << 2), 299 upper_32_bits(ring->wptr << 2)); 300 /* XXX check if swapping is necessary on BE */ 301 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); 302 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); 303 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 304 ring->doorbell_index, ring->wptr << 2); 305 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 306 } else { 307 DRM_DEBUG("Not using doorbell -- " 308 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 309 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 310 ring->me, 311 lower_32_bits(ring->wptr << 2), 312 ring->me, 313 upper_32_bits(ring->wptr << 2)); 314 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), 315 lower_32_bits(ring->wptr << 2)); 316 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), 317 upper_32_bits(ring->wptr << 2)); 318 } 319 } 320 321 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 322 { 323 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 324 int i; 325 326 for (i = 0; i < count; i++) 327 if (sdma && sdma->burst_nop && (i == 0)) 328 amdgpu_ring_write(ring, ring->funcs->nop | 329 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 330 else 331 amdgpu_ring_write(ring, ring->funcs->nop); 332 } 333 334 /** 335 * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine 336 * 337 * @ring: amdgpu ring pointer 338 * @job: job to retrieve vmid from 339 * @ib: IB object to schedule 340 * @flags: unused 341 * 342 * Schedule an IB in the DMA ring. 343 */ 344 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring, 345 struct amdgpu_job *job, 346 struct amdgpu_ib *ib, 347 uint32_t flags) 348 { 349 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 350 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 351 352 /* An IB packet must end on a 8 DW boundary--the next dword 353 * must be on a 8-dword boundary. Our IB packet below is 6 354 * dwords long, thus add x number of NOPs, such that, in 355 * modular arithmetic, 356 * wptr + 6 + x = 8k, k >= 0, which in C is, 357 * (wptr + 6 + x) % 8 = 0. 358 * The expression below, is a solution of x. 359 */ 360 sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 361 362 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 363 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 364 /* base must be 32 byte aligned */ 365 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 366 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 367 amdgpu_ring_write(ring, ib->length_dw); 368 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 369 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 370 } 371 372 /** 373 * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse 374 * 375 * @ring: amdgpu ring pointer 376 * 377 * flush the IB by graphics cache rinse. 378 */ 379 static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring) 380 { 381 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | 382 SDMA_GCR_GLM_INV | SDMA_GCR_GL1_INV | 383 SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 384 SDMA_GCR_GLI_INV(1); 385 386 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 387 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ)); 388 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 389 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 390 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 391 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 392 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 393 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 394 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 395 } 396 397 /** 398 * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 399 * 400 * @ring: amdgpu ring pointer 401 * 402 * Emit an hdp flush packet on the requested DMA ring. 403 */ 404 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 405 { 406 struct amdgpu_device *adev = ring->adev; 407 u32 ref_and_mask = 0; 408 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 409 410 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 411 412 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 413 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 414 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 415 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 416 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 417 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 418 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 419 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 420 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 421 } 422 423 /** 424 * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring 425 * 426 * @ring: amdgpu ring pointer 427 * @addr: address 428 * @seq: sequence number 429 * @flags: fence related flags 430 * 431 * Add a DMA fence packet to the ring to write 432 * the fence seq number and DMA trap packet to generate 433 * an interrupt if needed. 434 */ 435 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 436 unsigned flags) 437 { 438 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 439 /* write the fence */ 440 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 441 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 442 /* zero in first two bits */ 443 BUG_ON(addr & 0x3); 444 amdgpu_ring_write(ring, lower_32_bits(addr)); 445 amdgpu_ring_write(ring, upper_32_bits(addr)); 446 amdgpu_ring_write(ring, lower_32_bits(seq)); 447 448 /* optionally write high bits as well */ 449 if (write64bit) { 450 addr += 4; 451 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 452 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 453 /* zero in first two bits */ 454 BUG_ON(addr & 0x3); 455 amdgpu_ring_write(ring, lower_32_bits(addr)); 456 amdgpu_ring_write(ring, upper_32_bits(addr)); 457 amdgpu_ring_write(ring, upper_32_bits(seq)); 458 } 459 460 if (flags & AMDGPU_FENCE_FLAG_INT) { 461 /* generate an interrupt */ 462 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 463 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 464 } 465 } 466 467 468 /** 469 * sdma_v5_2_gfx_stop - stop the gfx async dma engines 470 * 471 * @adev: amdgpu_device pointer 472 * 473 * Stop the gfx async dma ring buffers. 474 */ 475 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev) 476 { 477 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 478 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 479 struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring; 480 struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring; 481 u32 rb_cntl, ib_cntl; 482 int i; 483 484 if ((adev->mman.buffer_funcs_ring == sdma0) || 485 (adev->mman.buffer_funcs_ring == sdma1) || 486 (adev->mman.buffer_funcs_ring == sdma2) || 487 (adev->mman.buffer_funcs_ring == sdma3)) 488 amdgpu_ttm_set_buffer_funcs_status(adev, false); 489 490 for (i = 0; i < adev->sdma.num_instances; i++) { 491 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 492 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 493 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 494 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 495 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 496 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 497 } 498 } 499 500 /** 501 * sdma_v5_2_rlc_stop - stop the compute async dma engines 502 * 503 * @adev: amdgpu_device pointer 504 * 505 * Stop the compute async dma queues. 506 */ 507 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev) 508 { 509 /* XXX todo */ 510 } 511 512 /** 513 * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch 514 * 515 * @adev: amdgpu_device pointer 516 * @enable: enable/disable the DMA MEs context switch. 517 * 518 * Halt or unhalt the async dma engines context switch. 519 */ 520 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 521 { 522 u32 f32_cntl, phase_quantum = 0; 523 int i; 524 525 if (amdgpu_sdma_phase_quantum) { 526 unsigned value = amdgpu_sdma_phase_quantum; 527 unsigned unit = 0; 528 529 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 530 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 531 value = (value + 1) >> 1; 532 unit++; 533 } 534 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 535 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 536 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 537 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 538 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 539 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 540 WARN_ONCE(1, 541 "clamping sdma_phase_quantum to %uK clock cycles\n", 542 value << unit); 543 } 544 phase_quantum = 545 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 546 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 547 } 548 549 for (i = 0; i < adev->sdma.num_instances; i++) { 550 if (enable && amdgpu_sdma_phase_quantum) { 551 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 552 phase_quantum); 553 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 554 phase_quantum); 555 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 556 phase_quantum); 557 } 558 559 if (!amdgpu_sriov_vf(adev)) { 560 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); 561 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 562 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 563 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 564 } 565 } 566 567 } 568 569 /** 570 * sdma_v5_2_enable - stop the async dma engines 571 * 572 * @adev: amdgpu_device pointer 573 * @enable: enable/disable the DMA MEs. 574 * 575 * Halt or unhalt the async dma engines. 576 */ 577 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable) 578 { 579 u32 f32_cntl; 580 int i; 581 582 if (!enable) { 583 sdma_v5_2_gfx_stop(adev); 584 sdma_v5_2_rlc_stop(adev); 585 } 586 587 if (!amdgpu_sriov_vf(adev)) { 588 for (i = 0; i < adev->sdma.num_instances; i++) { 589 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 590 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 591 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 592 } 593 } 594 } 595 596 /** 597 * sdma_v5_2_gfx_resume - setup and start the async dma engines 598 * 599 * @adev: amdgpu_device pointer 600 * 601 * Set up the gfx DMA ring buffers and enable them. 602 * Returns 0 for success, error for failure. 603 */ 604 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) 605 { 606 struct amdgpu_ring *ring; 607 u32 rb_cntl, ib_cntl; 608 u32 rb_bufsz; 609 u32 wb_offset; 610 u32 doorbell; 611 u32 doorbell_offset; 612 u32 temp; 613 u32 wptr_poll_cntl; 614 u64 wptr_gpu_addr; 615 int i, r; 616 617 for (i = 0; i < adev->sdma.num_instances; i++) { 618 ring = &adev->sdma.instance[i].ring; 619 wb_offset = (ring->rptr_offs * 4); 620 621 if (!amdgpu_sriov_vf(adev)) 622 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 623 624 /* Set ring buffer size in dwords */ 625 rb_bufsz = order_base_2(ring->ring_size / 4); 626 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 627 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 628 #ifdef __BIG_ENDIAN 629 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 630 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 631 RPTR_WRITEBACK_SWAP_ENABLE, 1); 632 #endif 633 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 634 635 /* Initialize the ring buffer's read and write pointers */ 636 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 637 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 638 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 639 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 640 641 /* setup the wptr shadow polling */ 642 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 643 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 644 lower_32_bits(wptr_gpu_addr)); 645 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 646 upper_32_bits(wptr_gpu_addr)); 647 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 648 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 649 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 650 SDMA0_GFX_RB_WPTR_POLL_CNTL, 651 F32_POLL_ENABLE, 1); 652 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 653 wptr_poll_cntl); 654 655 /* set the wb address whether it's enabled or not */ 656 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 657 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 658 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 659 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 660 661 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 662 663 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 664 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 665 666 ring->wptr = 0; 667 668 /* before programing wptr to a less value, need set minor_ptr_update first */ 669 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 670 671 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 672 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); 673 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 674 } 675 676 doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 677 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); 678 679 if (ring->use_doorbell) { 680 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 681 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 682 OFFSET, ring->doorbell_index); 683 } else { 684 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 685 } 686 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 687 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 688 689 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 690 ring->doorbell_index, 691 adev->doorbell_index.sdma_doorbell_range); 692 693 if (amdgpu_sriov_vf(adev)) 694 sdma_v5_2_ring_set_wptr(ring); 695 696 /* set minor_ptr_update to 0 after wptr programed */ 697 698 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 699 700 /* SRIOV VF has no control of any of registers below */ 701 if (!amdgpu_sriov_vf(adev)) { 702 /* set utc l1 enable flag always to 1 */ 703 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); 704 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 705 706 /* enable MCBP */ 707 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); 708 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 709 710 /* Set up RESP_MODE to non-copy addresses */ 711 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); 712 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 713 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 714 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); 715 716 /* program default cache read and write policy */ 717 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); 718 /* clean read policy and write policy bits */ 719 temp &= 0xFF0FFF; 720 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | 721 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | 722 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK); 723 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); 724 725 /* unhalt engine */ 726 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 727 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 728 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 729 } 730 731 /* enable DMA RB */ 732 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 733 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 734 735 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 736 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 737 #ifdef __BIG_ENDIAN 738 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 739 #endif 740 /* enable DMA IBs */ 741 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 742 743 ring->sched.ready = true; 744 745 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 746 sdma_v5_2_ctx_switch_enable(adev, true); 747 sdma_v5_2_enable(adev, true); 748 } 749 750 r = amdgpu_ring_test_ring(ring); 751 if (r) { 752 ring->sched.ready = false; 753 return r; 754 } 755 756 if (adev->mman.buffer_funcs_ring == ring) 757 amdgpu_ttm_set_buffer_funcs_status(adev, true); 758 } 759 760 return 0; 761 } 762 763 /** 764 * sdma_v5_2_rlc_resume - setup and start the async dma engines 765 * 766 * @adev: amdgpu_device pointer 767 * 768 * Set up the compute DMA queues and enable them. 769 * Returns 0 for success, error for failure. 770 */ 771 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev) 772 { 773 return 0; 774 } 775 776 /** 777 * sdma_v5_2_load_microcode - load the sDMA ME ucode 778 * 779 * @adev: amdgpu_device pointer 780 * 781 * Loads the sDMA0/1/2/3 ucode. 782 * Returns 0 for success, -EINVAL if the ucode is not available. 783 */ 784 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev) 785 { 786 const struct sdma_firmware_header_v1_0 *hdr; 787 const __le32 *fw_data; 788 u32 fw_size; 789 int i, j; 790 791 /* halt the MEs */ 792 sdma_v5_2_enable(adev, false); 793 794 for (i = 0; i < adev->sdma.num_instances; i++) { 795 if (!adev->sdma.instance[i].fw) 796 return -EINVAL; 797 798 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 799 amdgpu_ucode_print_sdma_hdr(&hdr->header); 800 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 801 802 fw_data = (const __le32 *) 803 (adev->sdma.instance[i].fw->data + 804 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 805 806 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 807 808 for (j = 0; j < fw_size; j++) { 809 if (amdgpu_emu_mode == 1 && j % 500 == 0) 810 msleep(1); 811 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 812 } 813 814 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 815 } 816 817 return 0; 818 } 819 820 static int sdma_v5_2_soft_reset(void *handle) 821 { 822 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 823 u32 grbm_soft_reset; 824 u32 tmp; 825 int i; 826 827 for (i = 0; i < adev->sdma.num_instances; i++) { 828 grbm_soft_reset = REG_SET_FIELD(0, 829 GRBM_SOFT_RESET, SOFT_RESET_SDMA0, 830 1); 831 grbm_soft_reset <<= i; 832 833 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 834 tmp |= grbm_soft_reset; 835 DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp); 836 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 837 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 838 839 udelay(50); 840 841 tmp &= ~grbm_soft_reset; 842 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 843 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 844 845 udelay(50); 846 } 847 848 return 0; 849 } 850 851 /** 852 * sdma_v5_2_start - setup and start the async dma engines 853 * 854 * @adev: amdgpu_device pointer 855 * 856 * Set up the DMA engines and enable them. 857 * Returns 0 for success, error for failure. 858 */ 859 static int sdma_v5_2_start(struct amdgpu_device *adev) 860 { 861 int r = 0; 862 863 if (amdgpu_sriov_vf(adev)) { 864 sdma_v5_2_ctx_switch_enable(adev, false); 865 sdma_v5_2_enable(adev, false); 866 867 /* set RB registers */ 868 r = sdma_v5_2_gfx_resume(adev); 869 return r; 870 } 871 872 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 873 r = sdma_v5_2_load_microcode(adev); 874 if (r) 875 return r; 876 877 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */ 878 if (amdgpu_emu_mode == 1) 879 msleep(1000); 880 } 881 882 /* TODO: check whether can submit a doorbell request to raise 883 * a doorbell fence to exit gfxoff. 884 */ 885 if (adev->in_s0ix) 886 amdgpu_gfx_off_ctrl(adev, false); 887 888 sdma_v5_2_soft_reset(adev); 889 /* unhalt the MEs */ 890 sdma_v5_2_enable(adev, true); 891 /* enable sdma ring preemption */ 892 sdma_v5_2_ctx_switch_enable(adev, true); 893 894 /* start the gfx rings and rlc compute queues */ 895 r = sdma_v5_2_gfx_resume(adev); 896 if (adev->in_s0ix) 897 amdgpu_gfx_off_ctrl(adev, true); 898 if (r) 899 return r; 900 r = sdma_v5_2_rlc_resume(adev); 901 902 return r; 903 } 904 905 /** 906 * sdma_v5_2_ring_test_ring - simple async dma engine test 907 * 908 * @ring: amdgpu_ring structure holding ring information 909 * 910 * Test the DMA engine by writing using it to write an 911 * value to memory. 912 * Returns 0 for success, error for failure. 913 */ 914 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring) 915 { 916 struct amdgpu_device *adev = ring->adev; 917 unsigned i; 918 unsigned index; 919 int r; 920 u32 tmp; 921 u64 gpu_addr; 922 923 r = amdgpu_device_wb_get(adev, &index); 924 if (r) { 925 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 926 return r; 927 } 928 929 gpu_addr = adev->wb.gpu_addr + (index * 4); 930 tmp = 0xCAFEDEAD; 931 adev->wb.wb[index] = cpu_to_le32(tmp); 932 933 r = amdgpu_ring_alloc(ring, 5); 934 if (r) { 935 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 936 amdgpu_device_wb_free(adev, index); 937 return r; 938 } 939 940 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 941 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 942 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 943 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 944 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 945 amdgpu_ring_write(ring, 0xDEADBEEF); 946 amdgpu_ring_commit(ring); 947 948 for (i = 0; i < adev->usec_timeout; i++) { 949 tmp = le32_to_cpu(adev->wb.wb[index]); 950 if (tmp == 0xDEADBEEF) 951 break; 952 if (amdgpu_emu_mode == 1) 953 msleep(1); 954 else 955 udelay(1); 956 } 957 958 if (i >= adev->usec_timeout) 959 r = -ETIMEDOUT; 960 961 amdgpu_device_wb_free(adev, index); 962 963 return r; 964 } 965 966 /** 967 * sdma_v5_2_ring_test_ib - test an IB on the DMA engine 968 * 969 * @ring: amdgpu_ring structure holding ring information 970 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 971 * 972 * Test a simple IB in the DMA ring. 973 * Returns 0 on success, error on failure. 974 */ 975 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) 976 { 977 struct amdgpu_device *adev = ring->adev; 978 struct amdgpu_ib ib; 979 struct dma_fence *f = NULL; 980 unsigned index; 981 long r; 982 u32 tmp = 0; 983 u64 gpu_addr; 984 985 r = amdgpu_device_wb_get(adev, &index); 986 if (r) { 987 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 988 return r; 989 } 990 991 gpu_addr = adev->wb.gpu_addr + (index * 4); 992 tmp = 0xCAFEDEAD; 993 adev->wb.wb[index] = cpu_to_le32(tmp); 994 memset(&ib, 0, sizeof(ib)); 995 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 996 if (r) { 997 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 998 goto err0; 999 } 1000 1001 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1002 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1003 ib.ptr[1] = lower_32_bits(gpu_addr); 1004 ib.ptr[2] = upper_32_bits(gpu_addr); 1005 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1006 ib.ptr[4] = 0xDEADBEEF; 1007 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1008 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1009 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1010 ib.length_dw = 8; 1011 1012 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1013 if (r) 1014 goto err1; 1015 1016 r = dma_fence_wait_timeout(f, false, timeout); 1017 if (r == 0) { 1018 DRM_ERROR("amdgpu: IB test timed out\n"); 1019 r = -ETIMEDOUT; 1020 goto err1; 1021 } else if (r < 0) { 1022 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1023 goto err1; 1024 } 1025 tmp = le32_to_cpu(adev->wb.wb[index]); 1026 if (tmp == 0xDEADBEEF) 1027 r = 0; 1028 else 1029 r = -EINVAL; 1030 1031 err1: 1032 amdgpu_ib_free(adev, &ib, NULL); 1033 dma_fence_put(f); 1034 err0: 1035 amdgpu_device_wb_free(adev, index); 1036 return r; 1037 } 1038 1039 1040 /** 1041 * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART 1042 * 1043 * @ib: indirect buffer to fill with commands 1044 * @pe: addr of the page entry 1045 * @src: src addr to copy from 1046 * @count: number of page entries to update 1047 * 1048 * Update PTEs by copying them from the GART using sDMA. 1049 */ 1050 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib, 1051 uint64_t pe, uint64_t src, 1052 unsigned count) 1053 { 1054 unsigned bytes = count * 8; 1055 1056 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1057 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1058 ib->ptr[ib->length_dw++] = bytes - 1; 1059 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1060 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1061 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1062 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1063 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1064 1065 } 1066 1067 /** 1068 * sdma_v5_2_vm_write_pte - update PTEs by writing them manually 1069 * 1070 * @ib: indirect buffer to fill with commands 1071 * @pe: addr of the page entry 1072 * @value: dst addr to write into pe 1073 * @count: number of page entries to update 1074 * @incr: increase next addr by incr bytes 1075 * 1076 * Update PTEs by writing them manually using sDMA. 1077 */ 1078 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1079 uint64_t value, unsigned count, 1080 uint32_t incr) 1081 { 1082 unsigned ndw = count * 2; 1083 1084 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1085 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1086 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1087 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1088 ib->ptr[ib->length_dw++] = ndw - 1; 1089 for (; ndw > 0; ndw -= 2) { 1090 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1091 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1092 value += incr; 1093 } 1094 } 1095 1096 /** 1097 * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA 1098 * 1099 * @ib: indirect buffer to fill with commands 1100 * @pe: addr of the page entry 1101 * @addr: dst addr to write into pe 1102 * @count: number of page entries to update 1103 * @incr: increase next addr by incr bytes 1104 * @flags: access flags 1105 * 1106 * Update the page tables using sDMA. 1107 */ 1108 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib, 1109 uint64_t pe, 1110 uint64_t addr, unsigned count, 1111 uint32_t incr, uint64_t flags) 1112 { 1113 /* for physically contiguous pages (vram) */ 1114 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1115 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1116 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1117 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1118 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1119 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1120 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1121 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1122 ib->ptr[ib->length_dw++] = 0; 1123 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1124 } 1125 1126 /** 1127 * sdma_v5_2_ring_pad_ib - pad the IB 1128 * 1129 * @ib: indirect buffer to fill with padding 1130 * @ring: amdgpu_ring structure holding ring information 1131 * 1132 * Pad the IB with NOPs to a boundary multiple of 8. 1133 */ 1134 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1135 { 1136 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1137 u32 pad_count; 1138 int i; 1139 1140 pad_count = (-ib->length_dw) & 0x7; 1141 for (i = 0; i < pad_count; i++) 1142 if (sdma && sdma->burst_nop && (i == 0)) 1143 ib->ptr[ib->length_dw++] = 1144 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1145 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1146 else 1147 ib->ptr[ib->length_dw++] = 1148 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1149 } 1150 1151 1152 /** 1153 * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline 1154 * 1155 * @ring: amdgpu_ring pointer 1156 * 1157 * Make sure all previous operations are completed (CIK). 1158 */ 1159 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1160 { 1161 uint32_t seq = ring->fence_drv.sync_seq; 1162 uint64_t addr = ring->fence_drv.gpu_addr; 1163 1164 /* wait for idle */ 1165 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1166 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1167 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1168 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1169 amdgpu_ring_write(ring, addr & 0xfffffffc); 1170 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1171 amdgpu_ring_write(ring, seq); /* reference */ 1172 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1173 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1174 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1175 } 1176 1177 1178 /** 1179 * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA 1180 * 1181 * @ring: amdgpu_ring pointer 1182 * @vmid: vmid number to use 1183 * @pd_addr: address 1184 * 1185 * Update the page table base and flush the VM TLB 1186 * using sDMA. 1187 */ 1188 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring, 1189 unsigned vmid, uint64_t pd_addr) 1190 { 1191 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1192 } 1193 1194 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring, 1195 uint32_t reg, uint32_t val) 1196 { 1197 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1198 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1199 amdgpu_ring_write(ring, reg); 1200 amdgpu_ring_write(ring, val); 1201 } 1202 1203 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1204 uint32_t val, uint32_t mask) 1205 { 1206 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1207 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1208 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1209 amdgpu_ring_write(ring, reg << 2); 1210 amdgpu_ring_write(ring, 0); 1211 amdgpu_ring_write(ring, val); /* reference */ 1212 amdgpu_ring_write(ring, mask); /* mask */ 1213 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1214 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1215 } 1216 1217 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1218 uint32_t reg0, uint32_t reg1, 1219 uint32_t ref, uint32_t mask) 1220 { 1221 amdgpu_ring_emit_wreg(ring, reg0, ref); 1222 /* wait for a cycle to reset vm_inv_eng*_ack */ 1223 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1224 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1225 } 1226 1227 static int sdma_v5_2_early_init(void *handle) 1228 { 1229 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1230 1231 sdma_v5_2_set_ring_funcs(adev); 1232 sdma_v5_2_set_buffer_funcs(adev); 1233 sdma_v5_2_set_vm_pte_funcs(adev); 1234 sdma_v5_2_set_irq_funcs(adev); 1235 1236 return 0; 1237 } 1238 1239 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num) 1240 { 1241 switch (seq_num) { 1242 case 0: 1243 return SOC15_IH_CLIENTID_SDMA0; 1244 case 1: 1245 return SOC15_IH_CLIENTID_SDMA1; 1246 case 2: 1247 return SOC15_IH_CLIENTID_SDMA2; 1248 case 3: 1249 return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid; 1250 default: 1251 break; 1252 } 1253 return -EINVAL; 1254 } 1255 1256 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num) 1257 { 1258 switch (seq_num) { 1259 case 0: 1260 return SDMA0_5_0__SRCID__SDMA_TRAP; 1261 case 1: 1262 return SDMA1_5_0__SRCID__SDMA_TRAP; 1263 case 2: 1264 return SDMA2_5_0__SRCID__SDMA_TRAP; 1265 case 3: 1266 return SDMA3_5_0__SRCID__SDMA_TRAP; 1267 default: 1268 break; 1269 } 1270 return -EINVAL; 1271 } 1272 1273 static int sdma_v5_2_sw_init(void *handle) 1274 { 1275 struct amdgpu_ring *ring; 1276 int r, i; 1277 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1278 1279 /* SDMA trap event */ 1280 for (i = 0; i < adev->sdma.num_instances; i++) { 1281 r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i), 1282 sdma_v5_2_seq_to_trap_id(i), 1283 &adev->sdma.trap_irq); 1284 if (r) 1285 return r; 1286 } 1287 1288 r = sdma_v5_2_init_microcode(adev); 1289 if (r) { 1290 DRM_ERROR("Failed to load sdma firmware!\n"); 1291 return r; 1292 } 1293 1294 for (i = 0; i < adev->sdma.num_instances; i++) { 1295 ring = &adev->sdma.instance[i].ring; 1296 ring->ring_obj = NULL; 1297 ring->use_doorbell = true; 1298 ring->me = i; 1299 1300 DRM_INFO("use_doorbell being set to: [%s]\n", 1301 ring->use_doorbell?"true":"false"); 1302 1303 ring->doorbell_index = 1304 (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset 1305 1306 sprintf(ring->name, "sdma%d", i); 1307 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1308 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1309 AMDGPU_RING_PRIO_DEFAULT, NULL); 1310 if (r) 1311 return r; 1312 } 1313 1314 return r; 1315 } 1316 1317 static int sdma_v5_2_sw_fini(void *handle) 1318 { 1319 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1320 int i; 1321 1322 for (i = 0; i < adev->sdma.num_instances; i++) 1323 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1324 1325 sdma_v5_2_destroy_inst_ctx(adev); 1326 1327 return 0; 1328 } 1329 1330 static int sdma_v5_2_hw_init(void *handle) 1331 { 1332 int r; 1333 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1334 1335 r = sdma_v5_2_start(adev); 1336 1337 return r; 1338 } 1339 1340 static int sdma_v5_2_hw_fini(void *handle) 1341 { 1342 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1343 1344 if (amdgpu_sriov_vf(adev)) 1345 return 0; 1346 1347 sdma_v5_2_ctx_switch_enable(adev, false); 1348 sdma_v5_2_enable(adev, false); 1349 1350 return 0; 1351 } 1352 1353 static int sdma_v5_2_suspend(void *handle) 1354 { 1355 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1356 1357 return sdma_v5_2_hw_fini(adev); 1358 } 1359 1360 static int sdma_v5_2_resume(void *handle) 1361 { 1362 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1363 1364 return sdma_v5_2_hw_init(adev); 1365 } 1366 1367 static bool sdma_v5_2_is_idle(void *handle) 1368 { 1369 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1370 u32 i; 1371 1372 for (i = 0; i < adev->sdma.num_instances; i++) { 1373 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1374 1375 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1376 return false; 1377 } 1378 1379 return true; 1380 } 1381 1382 static int sdma_v5_2_wait_for_idle(void *handle) 1383 { 1384 unsigned i; 1385 u32 sdma0, sdma1, sdma2, sdma3; 1386 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1387 1388 for (i = 0; i < adev->usec_timeout; i++) { 1389 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1390 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1391 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG)); 1392 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG)); 1393 1394 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK) 1395 return 0; 1396 udelay(1); 1397 } 1398 return -ETIMEDOUT; 1399 } 1400 1401 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring) 1402 { 1403 int i, r = 0; 1404 struct amdgpu_device *adev = ring->adev; 1405 u32 index = 0; 1406 u64 sdma_gfx_preempt; 1407 1408 amdgpu_sdma_get_index_from_ring(ring, &index); 1409 sdma_gfx_preempt = 1410 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT); 1411 1412 /* assert preemption condition */ 1413 amdgpu_ring_set_preempt_cond_exec(ring, false); 1414 1415 /* emit the trailing fence */ 1416 ring->trail_seq += 1; 1417 amdgpu_ring_alloc(ring, 10); 1418 sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1419 ring->trail_seq, 0); 1420 amdgpu_ring_commit(ring); 1421 1422 /* assert IB preemption */ 1423 WREG32(sdma_gfx_preempt, 1); 1424 1425 /* poll the trailing fence */ 1426 for (i = 0; i < adev->usec_timeout; i++) { 1427 if (ring->trail_seq == 1428 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1429 break; 1430 udelay(1); 1431 } 1432 1433 if (i >= adev->usec_timeout) { 1434 r = -EINVAL; 1435 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1436 } 1437 1438 /* deassert IB preemption */ 1439 WREG32(sdma_gfx_preempt, 0); 1440 1441 /* deassert the preemption condition */ 1442 amdgpu_ring_set_preempt_cond_exec(ring, true); 1443 return r; 1444 } 1445 1446 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev, 1447 struct amdgpu_irq_src *source, 1448 unsigned type, 1449 enum amdgpu_interrupt_state state) 1450 { 1451 u32 sdma_cntl; 1452 u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL); 1453 1454 if (!amdgpu_sriov_vf(adev)) { 1455 sdma_cntl = RREG32(reg_offset); 1456 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1457 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1458 WREG32(reg_offset, sdma_cntl); 1459 } 1460 1461 return 0; 1462 } 1463 1464 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev, 1465 struct amdgpu_irq_src *source, 1466 struct amdgpu_iv_entry *entry) 1467 { 1468 DRM_DEBUG("IH: SDMA trap\n"); 1469 switch (entry->client_id) { 1470 case SOC15_IH_CLIENTID_SDMA0: 1471 switch (entry->ring_id) { 1472 case 0: 1473 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1474 break; 1475 case 1: 1476 /* XXX compute */ 1477 break; 1478 case 2: 1479 /* XXX compute */ 1480 break; 1481 case 3: 1482 /* XXX page queue*/ 1483 break; 1484 } 1485 break; 1486 case SOC15_IH_CLIENTID_SDMA1: 1487 switch (entry->ring_id) { 1488 case 0: 1489 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1490 break; 1491 case 1: 1492 /* XXX compute */ 1493 break; 1494 case 2: 1495 /* XXX compute */ 1496 break; 1497 case 3: 1498 /* XXX page queue*/ 1499 break; 1500 } 1501 break; 1502 case SOC15_IH_CLIENTID_SDMA2: 1503 switch (entry->ring_id) { 1504 case 0: 1505 amdgpu_fence_process(&adev->sdma.instance[2].ring); 1506 break; 1507 case 1: 1508 /* XXX compute */ 1509 break; 1510 case 2: 1511 /* XXX compute */ 1512 break; 1513 case 3: 1514 /* XXX page queue*/ 1515 break; 1516 } 1517 break; 1518 case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid: 1519 switch (entry->ring_id) { 1520 case 0: 1521 amdgpu_fence_process(&adev->sdma.instance[3].ring); 1522 break; 1523 case 1: 1524 /* XXX compute */ 1525 break; 1526 case 2: 1527 /* XXX compute */ 1528 break; 1529 case 3: 1530 /* XXX page queue*/ 1531 break; 1532 } 1533 break; 1534 } 1535 return 0; 1536 } 1537 1538 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev, 1539 struct amdgpu_irq_src *source, 1540 struct amdgpu_iv_entry *entry) 1541 { 1542 return 0; 1543 } 1544 1545 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev, 1546 bool enable) 1547 { 1548 uint32_t data, def; 1549 int i; 1550 1551 for (i = 0; i < adev->sdma.num_instances; i++) { 1552 1553 if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1)) 1554 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG; 1555 1556 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1557 /* Enable sdma clock gating */ 1558 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1559 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1560 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1561 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1562 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1563 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK | 1564 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK); 1565 if (def != data) 1566 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1567 } else { 1568 /* Disable sdma clock gating */ 1569 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1570 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1571 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1572 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1573 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1574 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK | 1575 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK); 1576 if (def != data) 1577 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1578 } 1579 } 1580 } 1581 1582 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev, 1583 bool enable) 1584 { 1585 uint32_t data, def; 1586 int i; 1587 1588 for (i = 0; i < adev->sdma.num_instances; i++) { 1589 1590 if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1)) 1591 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS; 1592 1593 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1594 /* Enable sdma mem light sleep */ 1595 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1596 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1597 if (def != data) 1598 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1599 1600 } else { 1601 /* Disable sdma mem light sleep */ 1602 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1603 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1604 if (def != data) 1605 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1606 1607 } 1608 } 1609 } 1610 1611 static int sdma_v5_2_set_clockgating_state(void *handle, 1612 enum amd_clockgating_state state) 1613 { 1614 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1615 1616 if (amdgpu_sriov_vf(adev)) 1617 return 0; 1618 1619 switch (adev->ip_versions[SDMA0_HWIP][0]) { 1620 case IP_VERSION(5, 2, 0): 1621 case IP_VERSION(5, 2, 2): 1622 case IP_VERSION(5, 2, 1): 1623 case IP_VERSION(5, 2, 4): 1624 case IP_VERSION(5, 2, 5): 1625 case IP_VERSION(5, 2, 3): 1626 sdma_v5_2_update_medium_grain_clock_gating(adev, 1627 state == AMD_CG_STATE_GATE); 1628 sdma_v5_2_update_medium_grain_light_sleep(adev, 1629 state == AMD_CG_STATE_GATE); 1630 break; 1631 default: 1632 break; 1633 } 1634 1635 return 0; 1636 } 1637 1638 static int sdma_v5_2_set_powergating_state(void *handle, 1639 enum amd_powergating_state state) 1640 { 1641 return 0; 1642 } 1643 1644 static void sdma_v5_2_get_clockgating_state(void *handle, u32 *flags) 1645 { 1646 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1647 int data; 1648 1649 if (amdgpu_sriov_vf(adev)) 1650 *flags = 0; 1651 1652 /* AMD_CG_SUPPORT_SDMA_LS */ 1653 data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); 1654 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1655 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1656 } 1657 1658 const struct amd_ip_funcs sdma_v5_2_ip_funcs = { 1659 .name = "sdma_v5_2", 1660 .early_init = sdma_v5_2_early_init, 1661 .late_init = NULL, 1662 .sw_init = sdma_v5_2_sw_init, 1663 .sw_fini = sdma_v5_2_sw_fini, 1664 .hw_init = sdma_v5_2_hw_init, 1665 .hw_fini = sdma_v5_2_hw_fini, 1666 .suspend = sdma_v5_2_suspend, 1667 .resume = sdma_v5_2_resume, 1668 .is_idle = sdma_v5_2_is_idle, 1669 .wait_for_idle = sdma_v5_2_wait_for_idle, 1670 .soft_reset = sdma_v5_2_soft_reset, 1671 .set_clockgating_state = sdma_v5_2_set_clockgating_state, 1672 .set_powergating_state = sdma_v5_2_set_powergating_state, 1673 .get_clockgating_state = sdma_v5_2_get_clockgating_state, 1674 }; 1675 1676 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = { 1677 .type = AMDGPU_RING_TYPE_SDMA, 1678 .align_mask = 0xf, 1679 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1680 .support_64bit_ptrs = true, 1681 .vmhub = AMDGPU_GFXHUB_0, 1682 .get_rptr = sdma_v5_2_ring_get_rptr, 1683 .get_wptr = sdma_v5_2_ring_get_wptr, 1684 .set_wptr = sdma_v5_2_ring_set_wptr, 1685 .emit_frame_size = 1686 5 + /* sdma_v5_2_ring_init_cond_exec */ 1687 6 + /* sdma_v5_2_ring_emit_hdp_flush */ 1688 3 + /* hdp_invalidate */ 1689 6 + /* sdma_v5_2_ring_emit_pipeline_sync */ 1690 /* sdma_v5_2_ring_emit_vm_flush */ 1691 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1692 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1693 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */ 1694 .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */ 1695 .emit_ib = sdma_v5_2_ring_emit_ib, 1696 .emit_mem_sync = sdma_v5_2_ring_emit_mem_sync, 1697 .emit_fence = sdma_v5_2_ring_emit_fence, 1698 .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync, 1699 .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush, 1700 .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush, 1701 .test_ring = sdma_v5_2_ring_test_ring, 1702 .test_ib = sdma_v5_2_ring_test_ib, 1703 .insert_nop = sdma_v5_2_ring_insert_nop, 1704 .pad_ib = sdma_v5_2_ring_pad_ib, 1705 .emit_wreg = sdma_v5_2_ring_emit_wreg, 1706 .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait, 1707 .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait, 1708 .init_cond_exec = sdma_v5_2_ring_init_cond_exec, 1709 .patch_cond_exec = sdma_v5_2_ring_patch_cond_exec, 1710 .preempt_ib = sdma_v5_2_ring_preempt_ib, 1711 }; 1712 1713 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev) 1714 { 1715 int i; 1716 1717 for (i = 0; i < adev->sdma.num_instances; i++) { 1718 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs; 1719 adev->sdma.instance[i].ring.me = i; 1720 } 1721 } 1722 1723 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = { 1724 .set = sdma_v5_2_set_trap_irq_state, 1725 .process = sdma_v5_2_process_trap_irq, 1726 }; 1727 1728 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = { 1729 .process = sdma_v5_2_process_illegal_inst_irq, 1730 }; 1731 1732 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev) 1733 { 1734 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1735 adev->sdma.num_instances; 1736 adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs; 1737 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs; 1738 } 1739 1740 /** 1741 * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine 1742 * 1743 * @ib: indirect buffer to copy to 1744 * @src_offset: src GPU address 1745 * @dst_offset: dst GPU address 1746 * @byte_count: number of bytes to xfer 1747 * @tmz: if a secure copy should be used 1748 * 1749 * Copy GPU buffers using the DMA engine. 1750 * Used by the amdgpu ttm implementation to move pages if 1751 * registered as the asic copy callback. 1752 */ 1753 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib, 1754 uint64_t src_offset, 1755 uint64_t dst_offset, 1756 uint32_t byte_count, 1757 bool tmz) 1758 { 1759 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1760 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1761 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 1762 ib->ptr[ib->length_dw++] = byte_count - 1; 1763 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1764 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1765 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1766 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1767 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1768 } 1769 1770 /** 1771 * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine 1772 * 1773 * @ib: indirect buffer to fill 1774 * @src_data: value to write to buffer 1775 * @dst_offset: dst GPU address 1776 * @byte_count: number of bytes to xfer 1777 * 1778 * Fill GPU buffers using the DMA engine. 1779 */ 1780 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib, 1781 uint32_t src_data, 1782 uint64_t dst_offset, 1783 uint32_t byte_count) 1784 { 1785 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1786 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1787 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1788 ib->ptr[ib->length_dw++] = src_data; 1789 ib->ptr[ib->length_dw++] = byte_count - 1; 1790 } 1791 1792 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = { 1793 .copy_max_bytes = 0x400000, 1794 .copy_num_dw = 7, 1795 .emit_copy_buffer = sdma_v5_2_emit_copy_buffer, 1796 1797 .fill_max_bytes = 0x400000, 1798 .fill_num_dw = 5, 1799 .emit_fill_buffer = sdma_v5_2_emit_fill_buffer, 1800 }; 1801 1802 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev) 1803 { 1804 if (adev->mman.buffer_funcs == NULL) { 1805 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs; 1806 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1807 } 1808 } 1809 1810 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = { 1811 .copy_pte_num_dw = 7, 1812 .copy_pte = sdma_v5_2_vm_copy_pte, 1813 .write_pte = sdma_v5_2_vm_write_pte, 1814 .set_pte_pde = sdma_v5_2_vm_set_pte_pde, 1815 }; 1816 1817 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev) 1818 { 1819 unsigned i; 1820 1821 if (adev->vm_manager.vm_pte_funcs == NULL) { 1822 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs; 1823 for (i = 0; i < adev->sdma.num_instances; i++) { 1824 adev->vm_manager.vm_pte_scheds[i] = 1825 &adev->sdma.instance[i].ring.sched; 1826 } 1827 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1828 } 1829 } 1830 1831 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = { 1832 .type = AMD_IP_BLOCK_TYPE_SDMA, 1833 .major = 5, 1834 .minor = 2, 1835 .rev = 0, 1836 .funcs = &sdma_v5_2_ip_funcs, 1837 }; 1838