1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_10_3_0_offset.h" 34 #include "gc/gc_10_3_0_sh_mask.h" 35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h" 36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h" 37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h" 38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h" 39 40 #include "soc15_common.h" 41 #include "soc15.h" 42 #include "navi10_sdma_pkt_open.h" 43 #include "nbio_v2_3.h" 44 #include "sdma_common.h" 45 #include "sdma_v5_2.h" 46 47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin"); 48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin"); 49 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin"); 50 MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin"); 51 52 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin"); 53 MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin"); 54 MODULE_FIRMWARE("amdgpu/sdma_5_2_6.bin"); 55 MODULE_FIRMWARE("amdgpu/sdma_5_2_7.bin"); 56 57 #define SDMA1_REG_OFFSET 0x600 58 #define SDMA3_REG_OFFSET 0x400 59 #define SDMA0_HYP_DEC_REG_START 0x5880 60 #define SDMA0_HYP_DEC_REG_END 0x5893 61 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 62 63 static const struct amdgpu_hwip_reg_entry sdma_reg_list_5_2[] = { 64 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG), 65 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG), 66 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG), 67 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG), 68 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UCODE_CHECKSUM), 69 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH_HI), 70 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH), 71 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_STATUS), 72 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_STATUS), 73 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK0), 74 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK1), 75 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK0), 76 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK1), 77 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_CNTL), 78 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR), 79 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR_HI), 80 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR), 81 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR_HI), 82 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_OFFSET), 83 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_LO), 84 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_HI), 85 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_CNTL), 86 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_RPTR), 87 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_SUB_REMAIN), 88 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_DUMMY_REG), 89 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_CNTL), 90 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR), 91 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR_HI), 92 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR), 93 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR_HI), 94 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_OFFSET), 95 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_LO), 96 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_HI), 97 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_DUMMY_REG), 98 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_CNTL), 99 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR), 100 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR_HI), 101 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR), 102 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR_HI), 103 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_OFFSET), 104 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_LO), 105 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_HI), 106 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_DUMMY_REG), 107 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_INT_STATUS), 108 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_VM_CNTL), 109 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2) 110 }; 111 112 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev); 113 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev); 114 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev); 115 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev); 116 117 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 118 { 119 u32 base; 120 121 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 122 internal_offset <= SDMA0_HYP_DEC_REG_END) { 123 base = adev->reg_offset[GC_HWIP][0][1]; 124 if (instance != 0) 125 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance; 126 } else { 127 if (instance < 2) { 128 base = adev->reg_offset[GC_HWIP][0][0]; 129 if (instance == 1) 130 internal_offset += SDMA1_REG_OFFSET; 131 } else { 132 base = adev->reg_offset[GC_HWIP][0][2]; 133 if (instance == 3) 134 internal_offset += SDMA3_REG_OFFSET; 135 } 136 } 137 138 return base + internal_offset; 139 } 140 141 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring, 142 uint64_t addr) 143 { 144 unsigned ret; 145 146 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); 147 amdgpu_ring_write(ring, lower_32_bits(addr)); 148 amdgpu_ring_write(ring, upper_32_bits(addr)); 149 amdgpu_ring_write(ring, 1); 150 /* this is the offset we need patch later */ 151 ret = ring->wptr & ring->buf_mask; 152 /* insert dummy here and patch it later */ 153 amdgpu_ring_write(ring, 0); 154 155 return ret; 156 } 157 158 /** 159 * sdma_v5_2_ring_get_rptr - get the current read pointer 160 * 161 * @ring: amdgpu ring pointer 162 * 163 * Get the current rptr from the hardware (NAVI10+). 164 */ 165 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring) 166 { 167 u64 *rptr; 168 169 /* XXX check if swapping is necessary on BE */ 170 rptr = (u64 *)ring->rptr_cpu_addr; 171 172 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 173 return ((*rptr) >> 2); 174 } 175 176 /** 177 * sdma_v5_2_ring_get_wptr - get the current write pointer 178 * 179 * @ring: amdgpu ring pointer 180 * 181 * Get the current wptr from the hardware (NAVI10+). 182 */ 183 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring) 184 { 185 struct amdgpu_device *adev = ring->adev; 186 u64 wptr; 187 188 if (ring->use_doorbell) { 189 /* XXX check if swapping is necessary on BE */ 190 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 191 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 192 } else { 193 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); 194 wptr = wptr << 32; 195 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); 196 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr); 197 } 198 199 return wptr >> 2; 200 } 201 202 /** 203 * sdma_v5_2_ring_set_wptr - commit the write pointer 204 * 205 * @ring: amdgpu ring pointer 206 * 207 * Write the wptr back to the hardware (NAVI10+). 208 */ 209 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring) 210 { 211 struct amdgpu_device *adev = ring->adev; 212 213 DRM_DEBUG("Setting write pointer\n"); 214 if (ring->use_doorbell) { 215 DRM_DEBUG("Using doorbell -- " 216 "wptr_offs == 0x%08x " 217 "lower_32_bits(ring->wptr << 2) == 0x%08x " 218 "upper_32_bits(ring->wptr << 2) == 0x%08x\n", 219 ring->wptr_offs, 220 lower_32_bits(ring->wptr << 2), 221 upper_32_bits(ring->wptr << 2)); 222 /* XXX check if swapping is necessary on BE */ 223 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 224 ring->wptr << 2); 225 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 226 ring->doorbell_index, ring->wptr << 2); 227 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 228 /* SDMA seems to miss doorbells sometimes when powergating kicks in. 229 * Updating the wptr directly will wake it. This is only safe because 230 * we disallow gfxoff in begin_use() and then allow it again in end_use(). 231 */ 232 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), 233 lower_32_bits(ring->wptr << 2)); 234 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), 235 upper_32_bits(ring->wptr << 2)); 236 } else { 237 DRM_DEBUG("Not using doorbell -- " 238 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 239 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 240 ring->me, 241 lower_32_bits(ring->wptr << 2), 242 ring->me, 243 upper_32_bits(ring->wptr << 2)); 244 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), 245 lower_32_bits(ring->wptr << 2)); 246 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), 247 upper_32_bits(ring->wptr << 2)); 248 } 249 } 250 251 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 252 { 253 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 254 int i; 255 256 for (i = 0; i < count; i++) 257 if (sdma && sdma->burst_nop && (i == 0)) 258 amdgpu_ring_write(ring, ring->funcs->nop | 259 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 260 else 261 amdgpu_ring_write(ring, ring->funcs->nop); 262 } 263 264 /** 265 * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine 266 * 267 * @ring: amdgpu ring pointer 268 * @job: job to retrieve vmid from 269 * @ib: IB object to schedule 270 * @flags: unused 271 * 272 * Schedule an IB in the DMA ring. 273 */ 274 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring, 275 struct amdgpu_job *job, 276 struct amdgpu_ib *ib, 277 uint32_t flags) 278 { 279 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 280 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 281 282 /* An IB packet must end on a 8 DW boundary--the next dword 283 * must be on a 8-dword boundary. Our IB packet below is 6 284 * dwords long, thus add x number of NOPs, such that, in 285 * modular arithmetic, 286 * wptr + 6 + x = 8k, k >= 0, which in C is, 287 * (wptr + 6 + x) % 8 = 0. 288 * The expression below, is a solution of x. 289 */ 290 sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 291 292 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 293 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 294 /* base must be 32 byte aligned */ 295 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 296 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 297 amdgpu_ring_write(ring, ib->length_dw); 298 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 299 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 300 } 301 302 /** 303 * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse 304 * 305 * @ring: amdgpu ring pointer 306 * 307 * flush the IB by graphics cache rinse. 308 */ 309 static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring) 310 { 311 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | 312 SDMA_GCR_GLM_INV | SDMA_GCR_GL1_INV | 313 SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 314 SDMA_GCR_GLI_INV(1); 315 316 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 317 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ)); 318 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 319 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 320 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 321 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 322 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 323 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 324 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 325 } 326 327 /** 328 * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 329 * 330 * @ring: amdgpu ring pointer 331 * 332 * Emit an hdp flush packet on the requested DMA ring. 333 */ 334 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 335 { 336 struct amdgpu_device *adev = ring->adev; 337 u32 ref_and_mask = 0; 338 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 339 340 if (ring->me > 1) { 341 amdgpu_asic_flush_hdp(adev, ring); 342 } else { 343 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 344 345 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 346 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 347 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 348 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 349 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 350 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 351 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 352 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 353 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 354 } 355 } 356 357 /** 358 * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring 359 * 360 * @ring: amdgpu ring pointer 361 * @addr: address 362 * @seq: sequence number 363 * @flags: fence related flags 364 * 365 * Add a DMA fence packet to the ring to write 366 * the fence seq number and DMA trap packet to generate 367 * an interrupt if needed. 368 */ 369 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 370 unsigned flags) 371 { 372 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 373 /* write the fence */ 374 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 375 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 376 /* zero in first two bits */ 377 BUG_ON(addr & 0x3); 378 amdgpu_ring_write(ring, lower_32_bits(addr)); 379 amdgpu_ring_write(ring, upper_32_bits(addr)); 380 amdgpu_ring_write(ring, lower_32_bits(seq)); 381 382 /* optionally write high bits as well */ 383 if (write64bit) { 384 addr += 4; 385 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 386 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 387 /* zero in first two bits */ 388 BUG_ON(addr & 0x3); 389 amdgpu_ring_write(ring, lower_32_bits(addr)); 390 amdgpu_ring_write(ring, upper_32_bits(addr)); 391 amdgpu_ring_write(ring, upper_32_bits(seq)); 392 } 393 394 if ((flags & AMDGPU_FENCE_FLAG_INT)) { 395 uint32_t ctx = ring->is_mes_queue ? 396 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0; 397 /* generate an interrupt */ 398 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 399 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx)); 400 } 401 } 402 403 404 /** 405 * sdma_v5_2_gfx_stop - stop the gfx async dma engines 406 * 407 * @adev: amdgpu_device pointer 408 * 409 * Stop the gfx async dma ring buffers. 410 */ 411 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev) 412 { 413 u32 rb_cntl, ib_cntl; 414 int i; 415 416 for (i = 0; i < adev->sdma.num_instances; i++) { 417 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 418 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 419 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 420 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 421 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 422 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 423 } 424 } 425 426 /** 427 * sdma_v5_2_rlc_stop - stop the compute async dma engines 428 * 429 * @adev: amdgpu_device pointer 430 * 431 * Stop the compute async dma queues. 432 */ 433 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev) 434 { 435 /* XXX todo */ 436 } 437 438 /** 439 * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch 440 * 441 * @adev: amdgpu_device pointer 442 * @enable: enable/disable the DMA MEs context switch. 443 * 444 * Halt or unhalt the async dma engines context switch. 445 */ 446 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 447 { 448 u32 f32_cntl, phase_quantum = 0; 449 int i; 450 451 if (amdgpu_sdma_phase_quantum) { 452 unsigned value = amdgpu_sdma_phase_quantum; 453 unsigned unit = 0; 454 455 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 456 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 457 value = (value + 1) >> 1; 458 unit++; 459 } 460 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 461 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 462 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 463 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 464 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 465 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 466 WARN_ONCE(1, 467 "clamping sdma_phase_quantum to %uK clock cycles\n", 468 value << unit); 469 } 470 phase_quantum = 471 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 472 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 473 } 474 475 for (i = 0; i < adev->sdma.num_instances; i++) { 476 if (enable && amdgpu_sdma_phase_quantum) { 477 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 478 phase_quantum); 479 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 480 phase_quantum); 481 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 482 phase_quantum); 483 } 484 485 if (!amdgpu_sriov_vf(adev)) { 486 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); 487 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 488 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 489 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 490 } 491 } 492 493 } 494 495 /** 496 * sdma_v5_2_enable - stop the async dma engines 497 * 498 * @adev: amdgpu_device pointer 499 * @enable: enable/disable the DMA MEs. 500 * 501 * Halt or unhalt the async dma engines. 502 */ 503 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable) 504 { 505 u32 f32_cntl; 506 int i; 507 508 if (!enable) { 509 sdma_v5_2_gfx_stop(adev); 510 sdma_v5_2_rlc_stop(adev); 511 } 512 513 if (!amdgpu_sriov_vf(adev)) { 514 for (i = 0; i < adev->sdma.num_instances; i++) { 515 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 516 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 517 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 518 } 519 } 520 } 521 522 /** 523 * sdma_v5_2_gfx_resume - setup and start the async dma engines 524 * 525 * @adev: amdgpu_device pointer 526 * 527 * Set up the gfx DMA ring buffers and enable them. 528 * Returns 0 for success, error for failure. 529 */ 530 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) 531 { 532 struct amdgpu_ring *ring; 533 u32 rb_cntl, ib_cntl; 534 u32 rb_bufsz; 535 u32 doorbell; 536 u32 doorbell_offset; 537 u32 temp; 538 u32 wptr_poll_cntl; 539 u64 wptr_gpu_addr; 540 int i, r; 541 542 for (i = 0; i < adev->sdma.num_instances; i++) { 543 ring = &adev->sdma.instance[i].ring; 544 545 if (!amdgpu_sriov_vf(adev)) 546 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 547 548 /* Set ring buffer size in dwords */ 549 rb_bufsz = order_base_2(ring->ring_size / 4); 550 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 551 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 552 #ifdef __BIG_ENDIAN 553 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 554 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 555 RPTR_WRITEBACK_SWAP_ENABLE, 1); 556 #endif 557 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 558 559 /* Initialize the ring buffer's read and write pointers */ 560 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 561 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 562 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 563 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 564 565 /* setup the wptr shadow polling */ 566 wptr_gpu_addr = ring->wptr_gpu_addr; 567 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 568 lower_32_bits(wptr_gpu_addr)); 569 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 570 upper_32_bits(wptr_gpu_addr)); 571 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 572 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 573 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 574 SDMA0_GFX_RB_WPTR_POLL_CNTL, 575 F32_POLL_ENABLE, 1); 576 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 577 wptr_poll_cntl); 578 579 /* set the wb address whether it's enabled or not */ 580 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 581 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 582 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 583 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 584 585 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 586 587 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 588 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 589 590 ring->wptr = 0; 591 592 /* before programing wptr to a less value, need set minor_ptr_update first */ 593 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 594 595 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 596 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); 597 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); 598 } 599 600 doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 601 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); 602 603 if (ring->use_doorbell) { 604 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 605 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 606 OFFSET, ring->doorbell_index); 607 } else { 608 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 609 } 610 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 611 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 612 613 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 614 ring->doorbell_index, 615 adev->doorbell_index.sdma_doorbell_range); 616 617 if (amdgpu_sriov_vf(adev)) 618 sdma_v5_2_ring_set_wptr(ring); 619 620 /* set minor_ptr_update to 0 after wptr programed */ 621 622 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 623 624 /* SRIOV VF has no control of any of registers below */ 625 if (!amdgpu_sriov_vf(adev)) { 626 /* set utc l1 enable flag always to 1 */ 627 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); 628 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 629 630 /* enable MCBP */ 631 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); 632 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 633 634 /* Set up RESP_MODE to non-copy addresses */ 635 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); 636 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 637 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 638 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); 639 640 /* program default cache read and write policy */ 641 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); 642 /* clean read policy and write policy bits */ 643 temp &= 0xFF0FFF; 644 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | 645 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | 646 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK); 647 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); 648 649 /* unhalt engine */ 650 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 651 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 652 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 653 } 654 655 /* enable DMA RB */ 656 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 657 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 658 659 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 660 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 661 #ifdef __BIG_ENDIAN 662 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 663 #endif 664 /* enable DMA IBs */ 665 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 666 667 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 668 sdma_v5_2_ctx_switch_enable(adev, true); 669 sdma_v5_2_enable(adev, true); 670 } 671 672 r = amdgpu_ring_test_helper(ring); 673 if (r) 674 return r; 675 } 676 677 return 0; 678 } 679 680 /** 681 * sdma_v5_2_rlc_resume - setup and start the async dma engines 682 * 683 * @adev: amdgpu_device pointer 684 * 685 * Set up the compute DMA queues and enable them. 686 * Returns 0 for success, error for failure. 687 */ 688 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev) 689 { 690 return 0; 691 } 692 693 /** 694 * sdma_v5_2_load_microcode - load the sDMA ME ucode 695 * 696 * @adev: amdgpu_device pointer 697 * 698 * Loads the sDMA0/1/2/3 ucode. 699 * Returns 0 for success, -EINVAL if the ucode is not available. 700 */ 701 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev) 702 { 703 const struct sdma_firmware_header_v1_0 *hdr; 704 const __le32 *fw_data; 705 u32 fw_size; 706 int i, j; 707 708 /* halt the MEs */ 709 sdma_v5_2_enable(adev, false); 710 711 for (i = 0; i < adev->sdma.num_instances; i++) { 712 if (!adev->sdma.instance[i].fw) 713 return -EINVAL; 714 715 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 716 amdgpu_ucode_print_sdma_hdr(&hdr->header); 717 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 718 719 fw_data = (const __le32 *) 720 (adev->sdma.instance[i].fw->data + 721 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 722 723 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 724 725 for (j = 0; j < fw_size; j++) { 726 if (amdgpu_emu_mode == 1 && j % 500 == 0) 727 msleep(1); 728 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 729 } 730 731 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 732 } 733 734 return 0; 735 } 736 737 static int sdma_v5_2_soft_reset(void *handle) 738 { 739 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 740 u32 grbm_soft_reset; 741 u32 tmp; 742 int i; 743 744 for (i = 0; i < adev->sdma.num_instances; i++) { 745 grbm_soft_reset = REG_SET_FIELD(0, 746 GRBM_SOFT_RESET, SOFT_RESET_SDMA0, 747 1); 748 grbm_soft_reset <<= i; 749 750 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 751 tmp |= grbm_soft_reset; 752 DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp); 753 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 754 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 755 756 udelay(50); 757 758 tmp &= ~grbm_soft_reset; 759 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 760 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 761 762 udelay(50); 763 } 764 765 return 0; 766 } 767 768 /** 769 * sdma_v5_2_start - setup and start the async dma engines 770 * 771 * @adev: amdgpu_device pointer 772 * 773 * Set up the DMA engines and enable them. 774 * Returns 0 for success, error for failure. 775 */ 776 static int sdma_v5_2_start(struct amdgpu_device *adev) 777 { 778 int r = 0; 779 780 if (amdgpu_sriov_vf(adev)) { 781 sdma_v5_2_ctx_switch_enable(adev, false); 782 sdma_v5_2_enable(adev, false); 783 784 /* set RB registers */ 785 r = sdma_v5_2_gfx_resume(adev); 786 return r; 787 } 788 789 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 790 r = sdma_v5_2_load_microcode(adev); 791 if (r) 792 return r; 793 794 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */ 795 if (amdgpu_emu_mode == 1) 796 msleep(1000); 797 } 798 799 sdma_v5_2_soft_reset(adev); 800 /* unhalt the MEs */ 801 sdma_v5_2_enable(adev, true); 802 /* enable sdma ring preemption */ 803 sdma_v5_2_ctx_switch_enable(adev, true); 804 805 /* start the gfx rings and rlc compute queues */ 806 r = sdma_v5_2_gfx_resume(adev); 807 if (r) 808 return r; 809 r = sdma_v5_2_rlc_resume(adev); 810 811 return r; 812 } 813 814 static int sdma_v5_2_mqd_init(struct amdgpu_device *adev, void *mqd, 815 struct amdgpu_mqd_prop *prop) 816 { 817 struct v10_sdma_mqd *m = mqd; 818 uint64_t wb_gpu_addr; 819 820 m->sdmax_rlcx_rb_cntl = 821 order_base_2(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 822 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 823 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | 824 1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT; 825 826 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8); 827 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); 828 829 m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0, 830 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 831 832 wb_gpu_addr = prop->wptr_gpu_addr; 833 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); 834 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); 835 836 wb_gpu_addr = prop->rptr_gpu_addr; 837 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); 838 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); 839 840 m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0, 841 mmSDMA0_GFX_IB_CNTL)); 842 843 m->sdmax_rlcx_doorbell_offset = 844 prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 845 846 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1); 847 848 return 0; 849 } 850 851 static void sdma_v5_2_set_mqd_funcs(struct amdgpu_device *adev) 852 { 853 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v10_sdma_mqd); 854 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v5_2_mqd_init; 855 } 856 857 /** 858 * sdma_v5_2_ring_test_ring - simple async dma engine test 859 * 860 * @ring: amdgpu_ring structure holding ring information 861 * 862 * Test the DMA engine by writing using it to write an 863 * value to memory. 864 * Returns 0 for success, error for failure. 865 */ 866 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring) 867 { 868 struct amdgpu_device *adev = ring->adev; 869 unsigned i; 870 unsigned index; 871 int r; 872 u32 tmp; 873 u64 gpu_addr; 874 volatile uint32_t *cpu_ptr = NULL; 875 876 tmp = 0xCAFEDEAD; 877 878 if (ring->is_mes_queue) { 879 uint32_t offset = 0; 880 offset = amdgpu_mes_ctx_get_offs(ring, 881 AMDGPU_MES_CTX_PADDING_OFFS); 882 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 883 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 884 *cpu_ptr = tmp; 885 } else { 886 r = amdgpu_device_wb_get(adev, &index); 887 if (r) { 888 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 889 return r; 890 } 891 892 gpu_addr = adev->wb.gpu_addr + (index * 4); 893 adev->wb.wb[index] = cpu_to_le32(tmp); 894 } 895 896 r = amdgpu_ring_alloc(ring, 20); 897 if (r) { 898 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 899 if (!ring->is_mes_queue) 900 amdgpu_device_wb_free(adev, index); 901 return r; 902 } 903 904 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 905 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 906 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 907 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 908 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 909 amdgpu_ring_write(ring, 0xDEADBEEF); 910 amdgpu_ring_commit(ring); 911 912 for (i = 0; i < adev->usec_timeout; i++) { 913 if (ring->is_mes_queue) 914 tmp = le32_to_cpu(*cpu_ptr); 915 else 916 tmp = le32_to_cpu(adev->wb.wb[index]); 917 if (tmp == 0xDEADBEEF) 918 break; 919 if (amdgpu_emu_mode == 1) 920 msleep(1); 921 else 922 udelay(1); 923 } 924 925 if (i >= adev->usec_timeout) 926 r = -ETIMEDOUT; 927 928 if (!ring->is_mes_queue) 929 amdgpu_device_wb_free(adev, index); 930 931 return r; 932 } 933 934 /** 935 * sdma_v5_2_ring_test_ib - test an IB on the DMA engine 936 * 937 * @ring: amdgpu_ring structure holding ring information 938 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 939 * 940 * Test a simple IB in the DMA ring. 941 * Returns 0 on success, error on failure. 942 */ 943 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) 944 { 945 struct amdgpu_device *adev = ring->adev; 946 struct amdgpu_ib ib; 947 struct dma_fence *f = NULL; 948 unsigned index; 949 long r; 950 u32 tmp = 0; 951 u64 gpu_addr; 952 volatile uint32_t *cpu_ptr = NULL; 953 954 tmp = 0xCAFEDEAD; 955 memset(&ib, 0, sizeof(ib)); 956 957 if (ring->is_mes_queue) { 958 uint32_t offset = 0; 959 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 960 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 961 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 962 963 offset = amdgpu_mes_ctx_get_offs(ring, 964 AMDGPU_MES_CTX_PADDING_OFFS); 965 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 966 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 967 *cpu_ptr = tmp; 968 } else { 969 r = amdgpu_device_wb_get(adev, &index); 970 if (r) { 971 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 972 return r; 973 } 974 975 gpu_addr = adev->wb.gpu_addr + (index * 4); 976 adev->wb.wb[index] = cpu_to_le32(tmp); 977 978 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 979 if (r) { 980 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 981 goto err0; 982 } 983 } 984 985 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 986 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 987 ib.ptr[1] = lower_32_bits(gpu_addr); 988 ib.ptr[2] = upper_32_bits(gpu_addr); 989 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 990 ib.ptr[4] = 0xDEADBEEF; 991 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 992 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 993 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 994 ib.length_dw = 8; 995 996 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 997 if (r) 998 goto err1; 999 1000 r = dma_fence_wait_timeout(f, false, timeout); 1001 if (r == 0) { 1002 DRM_ERROR("amdgpu: IB test timed out\n"); 1003 r = -ETIMEDOUT; 1004 goto err1; 1005 } else if (r < 0) { 1006 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1007 goto err1; 1008 } 1009 1010 if (ring->is_mes_queue) 1011 tmp = le32_to_cpu(*cpu_ptr); 1012 else 1013 tmp = le32_to_cpu(adev->wb.wb[index]); 1014 1015 if (tmp == 0xDEADBEEF) 1016 r = 0; 1017 else 1018 r = -EINVAL; 1019 1020 err1: 1021 amdgpu_ib_free(adev, &ib, NULL); 1022 dma_fence_put(f); 1023 err0: 1024 if (!ring->is_mes_queue) 1025 amdgpu_device_wb_free(adev, index); 1026 return r; 1027 } 1028 1029 1030 /** 1031 * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART 1032 * 1033 * @ib: indirect buffer to fill with commands 1034 * @pe: addr of the page entry 1035 * @src: src addr to copy from 1036 * @count: number of page entries to update 1037 * 1038 * Update PTEs by copying them from the GART using sDMA. 1039 */ 1040 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib, 1041 uint64_t pe, uint64_t src, 1042 unsigned count) 1043 { 1044 unsigned bytes = count * 8; 1045 1046 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1047 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1048 ib->ptr[ib->length_dw++] = bytes - 1; 1049 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1050 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1051 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1052 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1053 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1054 1055 } 1056 1057 /** 1058 * sdma_v5_2_vm_write_pte - update PTEs by writing them manually 1059 * 1060 * @ib: indirect buffer to fill with commands 1061 * @pe: addr of the page entry 1062 * @value: dst addr to write into pe 1063 * @count: number of page entries to update 1064 * @incr: increase next addr by incr bytes 1065 * 1066 * Update PTEs by writing them manually using sDMA. 1067 */ 1068 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1069 uint64_t value, unsigned count, 1070 uint32_t incr) 1071 { 1072 unsigned ndw = count * 2; 1073 1074 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1075 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1076 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1077 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1078 ib->ptr[ib->length_dw++] = ndw - 1; 1079 for (; ndw > 0; ndw -= 2) { 1080 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1081 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1082 value += incr; 1083 } 1084 } 1085 1086 /** 1087 * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA 1088 * 1089 * @ib: indirect buffer to fill with commands 1090 * @pe: addr of the page entry 1091 * @addr: dst addr to write into pe 1092 * @count: number of page entries to update 1093 * @incr: increase next addr by incr bytes 1094 * @flags: access flags 1095 * 1096 * Update the page tables using sDMA. 1097 */ 1098 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib, 1099 uint64_t pe, 1100 uint64_t addr, unsigned count, 1101 uint32_t incr, uint64_t flags) 1102 { 1103 /* for physically contiguous pages (vram) */ 1104 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1105 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1106 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1107 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1108 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1109 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1110 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1111 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1112 ib->ptr[ib->length_dw++] = 0; 1113 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1114 } 1115 1116 /** 1117 * sdma_v5_2_ring_pad_ib - pad the IB 1118 * 1119 * @ib: indirect buffer to fill with padding 1120 * @ring: amdgpu_ring structure holding ring information 1121 * 1122 * Pad the IB with NOPs to a boundary multiple of 8. 1123 */ 1124 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1125 { 1126 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1127 u32 pad_count; 1128 int i; 1129 1130 pad_count = (-ib->length_dw) & 0x7; 1131 for (i = 0; i < pad_count; i++) 1132 if (sdma && sdma->burst_nop && (i == 0)) 1133 ib->ptr[ib->length_dw++] = 1134 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1135 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1136 else 1137 ib->ptr[ib->length_dw++] = 1138 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1139 } 1140 1141 1142 /** 1143 * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline 1144 * 1145 * @ring: amdgpu_ring pointer 1146 * 1147 * Make sure all previous operations are completed (CIK). 1148 */ 1149 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1150 { 1151 uint32_t seq = ring->fence_drv.sync_seq; 1152 uint64_t addr = ring->fence_drv.gpu_addr; 1153 1154 /* wait for idle */ 1155 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1156 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1157 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1158 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1159 amdgpu_ring_write(ring, addr & 0xfffffffc); 1160 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1161 amdgpu_ring_write(ring, seq); /* reference */ 1162 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1163 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1164 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1165 } 1166 1167 1168 /** 1169 * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA 1170 * 1171 * @ring: amdgpu_ring pointer 1172 * @vmid: vmid number to use 1173 * @pd_addr: address 1174 * 1175 * Update the page table base and flush the VM TLB 1176 * using sDMA. 1177 */ 1178 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring, 1179 unsigned vmid, uint64_t pd_addr) 1180 { 1181 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1182 } 1183 1184 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring, 1185 uint32_t reg, uint32_t val) 1186 { 1187 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1188 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1189 amdgpu_ring_write(ring, reg); 1190 amdgpu_ring_write(ring, val); 1191 } 1192 1193 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1194 uint32_t val, uint32_t mask) 1195 { 1196 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1197 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1198 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1199 amdgpu_ring_write(ring, reg << 2); 1200 amdgpu_ring_write(ring, 0); 1201 amdgpu_ring_write(ring, val); /* reference */ 1202 amdgpu_ring_write(ring, mask); /* mask */ 1203 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1204 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1205 } 1206 1207 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1208 uint32_t reg0, uint32_t reg1, 1209 uint32_t ref, uint32_t mask) 1210 { 1211 amdgpu_ring_emit_wreg(ring, reg0, ref); 1212 /* wait for a cycle to reset vm_inv_eng*_ack */ 1213 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1214 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1215 } 1216 1217 static int sdma_v5_2_early_init(void *handle) 1218 { 1219 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1220 int r; 1221 1222 r = amdgpu_sdma_init_microcode(adev, 0, true); 1223 if (r) 1224 return r; 1225 1226 sdma_v5_2_set_ring_funcs(adev); 1227 sdma_v5_2_set_buffer_funcs(adev); 1228 sdma_v5_2_set_vm_pte_funcs(adev); 1229 sdma_v5_2_set_irq_funcs(adev); 1230 sdma_v5_2_set_mqd_funcs(adev); 1231 1232 return 0; 1233 } 1234 1235 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num) 1236 { 1237 switch (seq_num) { 1238 case 0: 1239 return SOC15_IH_CLIENTID_SDMA0; 1240 case 1: 1241 return SOC15_IH_CLIENTID_SDMA1; 1242 case 2: 1243 return SOC15_IH_CLIENTID_SDMA2; 1244 case 3: 1245 return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid; 1246 default: 1247 break; 1248 } 1249 return -EINVAL; 1250 } 1251 1252 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num) 1253 { 1254 switch (seq_num) { 1255 case 0: 1256 return SDMA0_5_0__SRCID__SDMA_TRAP; 1257 case 1: 1258 return SDMA1_5_0__SRCID__SDMA_TRAP; 1259 case 2: 1260 return SDMA2_5_0__SRCID__SDMA_TRAP; 1261 case 3: 1262 return SDMA3_5_0__SRCID__SDMA_TRAP; 1263 default: 1264 break; 1265 } 1266 return -EINVAL; 1267 } 1268 1269 static int sdma_v5_2_sw_init(void *handle) 1270 { 1271 struct amdgpu_ring *ring; 1272 int r, i; 1273 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1274 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2); 1275 uint32_t *ptr; 1276 1277 /* SDMA trap event */ 1278 for (i = 0; i < adev->sdma.num_instances; i++) { 1279 r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i), 1280 sdma_v5_2_seq_to_trap_id(i), 1281 &adev->sdma.trap_irq); 1282 if (r) 1283 return r; 1284 } 1285 1286 for (i = 0; i < adev->sdma.num_instances; i++) { 1287 ring = &adev->sdma.instance[i].ring; 1288 ring->ring_obj = NULL; 1289 ring->use_doorbell = true; 1290 ring->me = i; 1291 1292 DRM_INFO("use_doorbell being set to: [%s]\n", 1293 ring->use_doorbell?"true":"false"); 1294 1295 ring->doorbell_index = 1296 (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset 1297 1298 ring->vm_hub = AMDGPU_GFXHUB(0); 1299 sprintf(ring->name, "sdma%d", i); 1300 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1301 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1302 AMDGPU_RING_PRIO_DEFAULT, NULL); 1303 if (r) 1304 return r; 1305 } 1306 1307 /* Allocate memory for SDMA IP Dump buffer */ 1308 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); 1309 if (ptr) 1310 adev->sdma.ip_dump = ptr; 1311 else 1312 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n"); 1313 1314 return r; 1315 } 1316 1317 static int sdma_v5_2_sw_fini(void *handle) 1318 { 1319 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1320 int i; 1321 1322 for (i = 0; i < adev->sdma.num_instances; i++) 1323 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1324 1325 amdgpu_sdma_destroy_inst_ctx(adev, true); 1326 1327 kfree(adev->sdma.ip_dump); 1328 1329 return 0; 1330 } 1331 1332 static int sdma_v5_2_hw_init(void *handle) 1333 { 1334 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1335 1336 return sdma_v5_2_start(adev); 1337 } 1338 1339 static int sdma_v5_2_hw_fini(void *handle) 1340 { 1341 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1342 1343 if (amdgpu_sriov_vf(adev)) 1344 return 0; 1345 1346 sdma_v5_2_ctx_switch_enable(adev, false); 1347 sdma_v5_2_enable(adev, false); 1348 1349 return 0; 1350 } 1351 1352 static int sdma_v5_2_suspend(void *handle) 1353 { 1354 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1355 1356 return sdma_v5_2_hw_fini(adev); 1357 } 1358 1359 static int sdma_v5_2_resume(void *handle) 1360 { 1361 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1362 1363 return sdma_v5_2_hw_init(adev); 1364 } 1365 1366 static bool sdma_v5_2_is_idle(void *handle) 1367 { 1368 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1369 u32 i; 1370 1371 for (i = 0; i < adev->sdma.num_instances; i++) { 1372 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1373 1374 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1375 return false; 1376 } 1377 1378 return true; 1379 } 1380 1381 static int sdma_v5_2_wait_for_idle(void *handle) 1382 { 1383 unsigned i; 1384 u32 sdma0, sdma1, sdma2, sdma3; 1385 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1386 1387 for (i = 0; i < adev->usec_timeout; i++) { 1388 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1389 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1390 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG)); 1391 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG)); 1392 1393 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK) 1394 return 0; 1395 udelay(1); 1396 } 1397 return -ETIMEDOUT; 1398 } 1399 1400 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring) 1401 { 1402 int i, r = 0; 1403 struct amdgpu_device *adev = ring->adev; 1404 u32 index = 0; 1405 u64 sdma_gfx_preempt; 1406 1407 amdgpu_sdma_get_index_from_ring(ring, &index); 1408 sdma_gfx_preempt = 1409 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT); 1410 1411 /* assert preemption condition */ 1412 amdgpu_ring_set_preempt_cond_exec(ring, false); 1413 1414 /* emit the trailing fence */ 1415 ring->trail_seq += 1; 1416 amdgpu_ring_alloc(ring, 10); 1417 sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1418 ring->trail_seq, 0); 1419 amdgpu_ring_commit(ring); 1420 1421 /* assert IB preemption */ 1422 WREG32(sdma_gfx_preempt, 1); 1423 1424 /* poll the trailing fence */ 1425 for (i = 0; i < adev->usec_timeout; i++) { 1426 if (ring->trail_seq == 1427 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1428 break; 1429 udelay(1); 1430 } 1431 1432 if (i >= adev->usec_timeout) { 1433 r = -EINVAL; 1434 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1435 } 1436 1437 /* deassert IB preemption */ 1438 WREG32(sdma_gfx_preempt, 0); 1439 1440 /* deassert the preemption condition */ 1441 amdgpu_ring_set_preempt_cond_exec(ring, true); 1442 return r; 1443 } 1444 1445 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev, 1446 struct amdgpu_irq_src *source, 1447 unsigned type, 1448 enum amdgpu_interrupt_state state) 1449 { 1450 u32 sdma_cntl; 1451 u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL); 1452 1453 if (!amdgpu_sriov_vf(adev)) { 1454 sdma_cntl = RREG32(reg_offset); 1455 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1456 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1457 WREG32(reg_offset, sdma_cntl); 1458 } 1459 1460 return 0; 1461 } 1462 1463 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev, 1464 struct amdgpu_irq_src *source, 1465 struct amdgpu_iv_entry *entry) 1466 { 1467 uint32_t mes_queue_id = entry->src_data[0]; 1468 1469 DRM_DEBUG("IH: SDMA trap\n"); 1470 1471 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 1472 struct amdgpu_mes_queue *queue; 1473 1474 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 1475 1476 spin_lock(&adev->mes.queue_id_lock); 1477 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 1478 if (queue) { 1479 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); 1480 amdgpu_fence_process(queue->ring); 1481 } 1482 spin_unlock(&adev->mes.queue_id_lock); 1483 return 0; 1484 } 1485 1486 switch (entry->client_id) { 1487 case SOC15_IH_CLIENTID_SDMA0: 1488 switch (entry->ring_id) { 1489 case 0: 1490 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1491 break; 1492 case 1: 1493 /* XXX compute */ 1494 break; 1495 case 2: 1496 /* XXX compute */ 1497 break; 1498 case 3: 1499 /* XXX page queue*/ 1500 break; 1501 } 1502 break; 1503 case SOC15_IH_CLIENTID_SDMA1: 1504 switch (entry->ring_id) { 1505 case 0: 1506 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1507 break; 1508 case 1: 1509 /* XXX compute */ 1510 break; 1511 case 2: 1512 /* XXX compute */ 1513 break; 1514 case 3: 1515 /* XXX page queue*/ 1516 break; 1517 } 1518 break; 1519 case SOC15_IH_CLIENTID_SDMA2: 1520 switch (entry->ring_id) { 1521 case 0: 1522 amdgpu_fence_process(&adev->sdma.instance[2].ring); 1523 break; 1524 case 1: 1525 /* XXX compute */ 1526 break; 1527 case 2: 1528 /* XXX compute */ 1529 break; 1530 case 3: 1531 /* XXX page queue*/ 1532 break; 1533 } 1534 break; 1535 case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid: 1536 switch (entry->ring_id) { 1537 case 0: 1538 amdgpu_fence_process(&adev->sdma.instance[3].ring); 1539 break; 1540 case 1: 1541 /* XXX compute */ 1542 break; 1543 case 2: 1544 /* XXX compute */ 1545 break; 1546 case 3: 1547 /* XXX page queue*/ 1548 break; 1549 } 1550 break; 1551 } 1552 return 0; 1553 } 1554 1555 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev, 1556 struct amdgpu_irq_src *source, 1557 struct amdgpu_iv_entry *entry) 1558 { 1559 return 0; 1560 } 1561 1562 static bool sdma_v5_2_firmware_mgcg_support(struct amdgpu_device *adev, 1563 int i) 1564 { 1565 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1566 case IP_VERSION(5, 2, 1): 1567 if (adev->sdma.instance[i].fw_version < 70) 1568 return false; 1569 break; 1570 case IP_VERSION(5, 2, 3): 1571 if (adev->sdma.instance[i].fw_version < 47) 1572 return false; 1573 break; 1574 case IP_VERSION(5, 2, 7): 1575 if (adev->sdma.instance[i].fw_version < 9) 1576 return false; 1577 break; 1578 default: 1579 return true; 1580 } 1581 1582 return true; 1583 1584 } 1585 1586 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev, 1587 bool enable) 1588 { 1589 uint32_t data, def; 1590 int i; 1591 1592 for (i = 0; i < adev->sdma.num_instances; i++) { 1593 1594 if (!sdma_v5_2_firmware_mgcg_support(adev, i)) 1595 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG; 1596 1597 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1598 /* Enable sdma clock gating */ 1599 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1600 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1601 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1602 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1603 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1604 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK | 1605 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK); 1606 if (def != data) 1607 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1608 } else { 1609 /* Disable sdma clock gating */ 1610 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1611 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1612 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1613 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1614 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1615 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK | 1616 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK); 1617 if (def != data) 1618 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1619 } 1620 } 1621 } 1622 1623 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev, 1624 bool enable) 1625 { 1626 uint32_t data, def; 1627 int i; 1628 1629 for (i = 0; i < adev->sdma.num_instances; i++) { 1630 if (adev->sdma.instance[i].fw_version < 70 && 1631 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == 1632 IP_VERSION(5, 2, 1)) 1633 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS; 1634 1635 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1636 /* Enable sdma mem light sleep */ 1637 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1638 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1639 if (def != data) 1640 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1641 1642 } else { 1643 /* Disable sdma mem light sleep */ 1644 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1645 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1646 if (def != data) 1647 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1648 1649 } 1650 } 1651 } 1652 1653 static int sdma_v5_2_set_clockgating_state(void *handle, 1654 enum amd_clockgating_state state) 1655 { 1656 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1657 1658 if (amdgpu_sriov_vf(adev)) 1659 return 0; 1660 1661 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1662 case IP_VERSION(5, 2, 0): 1663 case IP_VERSION(5, 2, 2): 1664 case IP_VERSION(5, 2, 1): 1665 case IP_VERSION(5, 2, 4): 1666 case IP_VERSION(5, 2, 5): 1667 case IP_VERSION(5, 2, 6): 1668 case IP_VERSION(5, 2, 3): 1669 case IP_VERSION(5, 2, 7): 1670 sdma_v5_2_update_medium_grain_clock_gating(adev, 1671 state == AMD_CG_STATE_GATE); 1672 sdma_v5_2_update_medium_grain_light_sleep(adev, 1673 state == AMD_CG_STATE_GATE); 1674 break; 1675 default: 1676 break; 1677 } 1678 1679 return 0; 1680 } 1681 1682 static int sdma_v5_2_set_powergating_state(void *handle, 1683 enum amd_powergating_state state) 1684 { 1685 return 0; 1686 } 1687 1688 static void sdma_v5_2_get_clockgating_state(void *handle, u64 *flags) 1689 { 1690 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1691 int data; 1692 1693 if (amdgpu_sriov_vf(adev)) 1694 *flags = 0; 1695 1696 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1697 data = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL)); 1698 if (!(data & SDMA0_CLK_CTRL__CGCG_EN_OVERRIDE_MASK)) 1699 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1700 1701 /* AMD_CG_SUPPORT_SDMA_LS */ 1702 data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); 1703 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1704 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1705 } 1706 1707 static void sdma_v5_2_ring_begin_use(struct amdgpu_ring *ring) 1708 { 1709 struct amdgpu_device *adev = ring->adev; 1710 1711 /* SDMA 5.2.3 (RMB) FW doesn't seem to properly 1712 * disallow GFXOFF in some cases leading to 1713 * hangs in SDMA. Disallow GFXOFF while SDMA is active. 1714 * We can probably just limit this to 5.2.3, 1715 * but it shouldn't hurt for other parts since 1716 * this GFXOFF will be disallowed anyway when SDMA is 1717 * active, this just makes it explicit. 1718 * sdma_v5_2_ring_set_wptr() takes advantage of this 1719 * to update the wptr because sometimes SDMA seems to miss 1720 * doorbells when entering PG. If you remove this, update 1721 * sdma_v5_2_ring_set_wptr() as well! 1722 */ 1723 amdgpu_gfx_off_ctrl(adev, false); 1724 } 1725 1726 static void sdma_v5_2_ring_end_use(struct amdgpu_ring *ring) 1727 { 1728 struct amdgpu_device *adev = ring->adev; 1729 1730 /* SDMA 5.2.3 (RMB) FW doesn't seem to properly 1731 * disallow GFXOFF in some cases leading to 1732 * hangs in SDMA. Allow GFXOFF when SDMA is complete. 1733 */ 1734 amdgpu_gfx_off_ctrl(adev, true); 1735 } 1736 1737 static void sdma_v5_2_print_ip_state(void *handle, struct drm_printer *p) 1738 { 1739 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1740 int i, j; 1741 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2); 1742 uint32_t instance_offset; 1743 1744 if (!adev->sdma.ip_dump) 1745 return; 1746 1747 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances); 1748 for (i = 0; i < adev->sdma.num_instances; i++) { 1749 instance_offset = i * reg_count; 1750 drm_printf(p, "\nInstance:%d\n", i); 1751 1752 for (j = 0; j < reg_count; j++) 1753 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_5_2[j].reg_name, 1754 adev->sdma.ip_dump[instance_offset + j]); 1755 } 1756 } 1757 1758 static void sdma_v5_2_dump_ip_state(void *handle) 1759 { 1760 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1761 int i, j; 1762 uint32_t instance_offset; 1763 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2); 1764 1765 if (!adev->sdma.ip_dump) 1766 return; 1767 1768 amdgpu_gfx_off_ctrl(adev, false); 1769 for (i = 0; i < adev->sdma.num_instances; i++) { 1770 instance_offset = i * reg_count; 1771 for (j = 0; j < reg_count; j++) 1772 adev->sdma.ip_dump[instance_offset + j] = 1773 RREG32(sdma_v5_2_get_reg_offset(adev, i, 1774 sdma_reg_list_5_2[j].reg_offset)); 1775 } 1776 amdgpu_gfx_off_ctrl(adev, true); 1777 } 1778 1779 static const struct amd_ip_funcs sdma_v5_2_ip_funcs = { 1780 .name = "sdma_v5_2", 1781 .early_init = sdma_v5_2_early_init, 1782 .late_init = NULL, 1783 .sw_init = sdma_v5_2_sw_init, 1784 .sw_fini = sdma_v5_2_sw_fini, 1785 .hw_init = sdma_v5_2_hw_init, 1786 .hw_fini = sdma_v5_2_hw_fini, 1787 .suspend = sdma_v5_2_suspend, 1788 .resume = sdma_v5_2_resume, 1789 .is_idle = sdma_v5_2_is_idle, 1790 .wait_for_idle = sdma_v5_2_wait_for_idle, 1791 .soft_reset = sdma_v5_2_soft_reset, 1792 .set_clockgating_state = sdma_v5_2_set_clockgating_state, 1793 .set_powergating_state = sdma_v5_2_set_powergating_state, 1794 .get_clockgating_state = sdma_v5_2_get_clockgating_state, 1795 .dump_ip_state = sdma_v5_2_dump_ip_state, 1796 .print_ip_state = sdma_v5_2_print_ip_state, 1797 }; 1798 1799 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = { 1800 .type = AMDGPU_RING_TYPE_SDMA, 1801 .align_mask = 0xf, 1802 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1803 .support_64bit_ptrs = true, 1804 .secure_submission_supported = true, 1805 .get_rptr = sdma_v5_2_ring_get_rptr, 1806 .get_wptr = sdma_v5_2_ring_get_wptr, 1807 .set_wptr = sdma_v5_2_ring_set_wptr, 1808 .emit_frame_size = 1809 5 + /* sdma_v5_2_ring_init_cond_exec */ 1810 6 + /* sdma_v5_2_ring_emit_hdp_flush */ 1811 3 + /* hdp_invalidate */ 1812 6 + /* sdma_v5_2_ring_emit_pipeline_sync */ 1813 /* sdma_v5_2_ring_emit_vm_flush */ 1814 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1815 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1816 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */ 1817 .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */ 1818 .emit_ib = sdma_v5_2_ring_emit_ib, 1819 .emit_mem_sync = sdma_v5_2_ring_emit_mem_sync, 1820 .emit_fence = sdma_v5_2_ring_emit_fence, 1821 .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync, 1822 .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush, 1823 .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush, 1824 .test_ring = sdma_v5_2_ring_test_ring, 1825 .test_ib = sdma_v5_2_ring_test_ib, 1826 .insert_nop = sdma_v5_2_ring_insert_nop, 1827 .pad_ib = sdma_v5_2_ring_pad_ib, 1828 .begin_use = sdma_v5_2_ring_begin_use, 1829 .end_use = sdma_v5_2_ring_end_use, 1830 .emit_wreg = sdma_v5_2_ring_emit_wreg, 1831 .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait, 1832 .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait, 1833 .init_cond_exec = sdma_v5_2_ring_init_cond_exec, 1834 .preempt_ib = sdma_v5_2_ring_preempt_ib, 1835 }; 1836 1837 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev) 1838 { 1839 int i; 1840 1841 for (i = 0; i < adev->sdma.num_instances; i++) { 1842 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs; 1843 adev->sdma.instance[i].ring.me = i; 1844 } 1845 } 1846 1847 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = { 1848 .set = sdma_v5_2_set_trap_irq_state, 1849 .process = sdma_v5_2_process_trap_irq, 1850 }; 1851 1852 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = { 1853 .process = sdma_v5_2_process_illegal_inst_irq, 1854 }; 1855 1856 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev) 1857 { 1858 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1859 adev->sdma.num_instances; 1860 adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs; 1861 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs; 1862 } 1863 1864 /** 1865 * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine 1866 * 1867 * @ib: indirect buffer to copy to 1868 * @src_offset: src GPU address 1869 * @dst_offset: dst GPU address 1870 * @byte_count: number of bytes to xfer 1871 * @copy_flags: copy flags for the buffers 1872 * 1873 * Copy GPU buffers using the DMA engine. 1874 * Used by the amdgpu ttm implementation to move pages if 1875 * registered as the asic copy callback. 1876 */ 1877 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib, 1878 uint64_t src_offset, 1879 uint64_t dst_offset, 1880 uint32_t byte_count, 1881 uint32_t copy_flags) 1882 { 1883 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1884 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1885 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0); 1886 ib->ptr[ib->length_dw++] = byte_count - 1; 1887 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1888 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1889 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1890 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1891 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1892 } 1893 1894 /** 1895 * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine 1896 * 1897 * @ib: indirect buffer to fill 1898 * @src_data: value to write to buffer 1899 * @dst_offset: dst GPU address 1900 * @byte_count: number of bytes to xfer 1901 * 1902 * Fill GPU buffers using the DMA engine. 1903 */ 1904 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib, 1905 uint32_t src_data, 1906 uint64_t dst_offset, 1907 uint32_t byte_count) 1908 { 1909 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1910 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1911 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1912 ib->ptr[ib->length_dw++] = src_data; 1913 ib->ptr[ib->length_dw++] = byte_count - 1; 1914 } 1915 1916 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = { 1917 .copy_max_bytes = 0x400000, 1918 .copy_num_dw = 7, 1919 .emit_copy_buffer = sdma_v5_2_emit_copy_buffer, 1920 1921 .fill_max_bytes = 0x400000, 1922 .fill_num_dw = 5, 1923 .emit_fill_buffer = sdma_v5_2_emit_fill_buffer, 1924 }; 1925 1926 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev) 1927 { 1928 if (adev->mman.buffer_funcs == NULL) { 1929 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs; 1930 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1931 } 1932 } 1933 1934 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = { 1935 .copy_pte_num_dw = 7, 1936 .copy_pte = sdma_v5_2_vm_copy_pte, 1937 .write_pte = sdma_v5_2_vm_write_pte, 1938 .set_pte_pde = sdma_v5_2_vm_set_pte_pde, 1939 }; 1940 1941 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev) 1942 { 1943 unsigned i; 1944 1945 if (adev->vm_manager.vm_pte_funcs == NULL) { 1946 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs; 1947 for (i = 0; i < adev->sdma.num_instances; i++) { 1948 adev->vm_manager.vm_pte_scheds[i] = 1949 &adev->sdma.instance[i].ring.sched; 1950 } 1951 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1952 } 1953 } 1954 1955 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = { 1956 .type = AMD_IP_BLOCK_TYPE_SDMA, 1957 .major = 5, 1958 .minor = 2, 1959 .rev = 0, 1960 .funcs = &sdma_v5_2_ip_funcs, 1961 }; 1962