1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_10_3_0_offset.h" 34 #include "gc/gc_10_3_0_sh_mask.h" 35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h" 36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h" 37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h" 38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h" 39 40 #include "soc15_common.h" 41 #include "soc15.h" 42 #include "navi10_sdma_pkt_open.h" 43 #include "nbio_v2_3.h" 44 #include "sdma_common.h" 45 #include "sdma_v5_2.h" 46 47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin"); 48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin"); 49 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin"); 50 MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin"); 51 52 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin"); 53 MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin"); 54 MODULE_FIRMWARE("amdgpu/sdma_5_2_6.bin"); 55 MODULE_FIRMWARE("amdgpu/sdma_5_2_7.bin"); 56 57 #define SDMA1_REG_OFFSET 0x600 58 #define SDMA3_REG_OFFSET 0x400 59 #define SDMA0_HYP_DEC_REG_START 0x5880 60 #define SDMA0_HYP_DEC_REG_END 0x5893 61 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 62 63 static const struct amdgpu_hwip_reg_entry sdma_reg_list_5_2[] = { 64 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG), 65 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG), 66 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG), 67 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG), 68 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UCODE_CHECKSUM), 69 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH_HI), 70 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH), 71 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_STATUS), 72 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_STATUS), 73 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK0), 74 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK1), 75 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK0), 76 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK1), 77 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_CNTL), 78 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR), 79 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR_HI), 80 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR), 81 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR_HI), 82 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_OFFSET), 83 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_LO), 84 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_HI), 85 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_CNTL), 86 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_RPTR), 87 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_SUB_REMAIN), 88 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_DUMMY_REG), 89 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_CNTL), 90 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR), 91 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR_HI), 92 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR), 93 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR_HI), 94 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_OFFSET), 95 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_LO), 96 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_HI), 97 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_DUMMY_REG), 98 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_CNTL), 99 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR), 100 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR_HI), 101 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR), 102 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR_HI), 103 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_OFFSET), 104 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_LO), 105 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_HI), 106 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_DUMMY_REG), 107 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_INT_STATUS), 108 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_VM_CNTL), 109 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2) 110 }; 111 112 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev); 113 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev); 114 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev); 115 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev); 116 117 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 118 { 119 u32 base; 120 121 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 122 internal_offset <= SDMA0_HYP_DEC_REG_END) { 123 base = adev->reg_offset[GC_HWIP][0][1]; 124 if (instance != 0) 125 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance; 126 } else { 127 if (instance < 2) { 128 base = adev->reg_offset[GC_HWIP][0][0]; 129 if (instance == 1) 130 internal_offset += SDMA1_REG_OFFSET; 131 } else { 132 base = adev->reg_offset[GC_HWIP][0][2]; 133 if (instance == 3) 134 internal_offset += SDMA3_REG_OFFSET; 135 } 136 } 137 138 return base + internal_offset; 139 } 140 141 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring, 142 uint64_t addr) 143 { 144 unsigned ret; 145 146 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); 147 amdgpu_ring_write(ring, lower_32_bits(addr)); 148 amdgpu_ring_write(ring, upper_32_bits(addr)); 149 amdgpu_ring_write(ring, 1); 150 /* this is the offset we need patch later */ 151 ret = ring->wptr & ring->buf_mask; 152 /* insert dummy here and patch it later */ 153 amdgpu_ring_write(ring, 0); 154 155 return ret; 156 } 157 158 /** 159 * sdma_v5_2_ring_get_rptr - get the current read pointer 160 * 161 * @ring: amdgpu ring pointer 162 * 163 * Get the current rptr from the hardware (NAVI10+). 164 */ 165 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring) 166 { 167 u64 *rptr; 168 169 /* XXX check if swapping is necessary on BE */ 170 rptr = (u64 *)ring->rptr_cpu_addr; 171 172 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 173 return ((*rptr) >> 2); 174 } 175 176 /** 177 * sdma_v5_2_ring_get_wptr - get the current write pointer 178 * 179 * @ring: amdgpu ring pointer 180 * 181 * Get the current wptr from the hardware (NAVI10+). 182 */ 183 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring) 184 { 185 struct amdgpu_device *adev = ring->adev; 186 u64 wptr; 187 188 if (ring->use_doorbell) { 189 /* XXX check if swapping is necessary on BE */ 190 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 191 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 192 } else { 193 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); 194 wptr = wptr << 32; 195 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); 196 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr); 197 } 198 199 return wptr >> 2; 200 } 201 202 /** 203 * sdma_v5_2_ring_set_wptr - commit the write pointer 204 * 205 * @ring: amdgpu ring pointer 206 * 207 * Write the wptr back to the hardware (NAVI10+). 208 */ 209 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring) 210 { 211 struct amdgpu_device *adev = ring->adev; 212 213 DRM_DEBUG("Setting write pointer\n"); 214 if (ring->use_doorbell) { 215 DRM_DEBUG("Using doorbell -- " 216 "wptr_offs == 0x%08x " 217 "lower_32_bits(ring->wptr << 2) == 0x%08x " 218 "upper_32_bits(ring->wptr << 2) == 0x%08x\n", 219 ring->wptr_offs, 220 lower_32_bits(ring->wptr << 2), 221 upper_32_bits(ring->wptr << 2)); 222 /* XXX check if swapping is necessary on BE */ 223 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 224 ring->wptr << 2); 225 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 226 ring->doorbell_index, ring->wptr << 2); 227 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 228 } else { 229 DRM_DEBUG("Not using doorbell -- " 230 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 231 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 232 ring->me, 233 lower_32_bits(ring->wptr << 2), 234 ring->me, 235 upper_32_bits(ring->wptr << 2)); 236 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), 237 lower_32_bits(ring->wptr << 2)); 238 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), 239 upper_32_bits(ring->wptr << 2)); 240 } 241 } 242 243 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 244 { 245 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 246 int i; 247 248 for (i = 0; i < count; i++) 249 if (sdma && sdma->burst_nop && (i == 0)) 250 amdgpu_ring_write(ring, ring->funcs->nop | 251 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 252 else 253 amdgpu_ring_write(ring, ring->funcs->nop); 254 } 255 256 /** 257 * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine 258 * 259 * @ring: amdgpu ring pointer 260 * @job: job to retrieve vmid from 261 * @ib: IB object to schedule 262 * @flags: unused 263 * 264 * Schedule an IB in the DMA ring. 265 */ 266 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring, 267 struct amdgpu_job *job, 268 struct amdgpu_ib *ib, 269 uint32_t flags) 270 { 271 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 272 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 273 274 /* An IB packet must end on a 8 DW boundary--the next dword 275 * must be on a 8-dword boundary. Our IB packet below is 6 276 * dwords long, thus add x number of NOPs, such that, in 277 * modular arithmetic, 278 * wptr + 6 + x = 8k, k >= 0, which in C is, 279 * (wptr + 6 + x) % 8 = 0. 280 * The expression below, is a solution of x. 281 */ 282 sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 283 284 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 285 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 286 /* base must be 32 byte aligned */ 287 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 288 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 289 amdgpu_ring_write(ring, ib->length_dw); 290 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 291 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 292 } 293 294 /** 295 * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse 296 * 297 * @ring: amdgpu ring pointer 298 * 299 * flush the IB by graphics cache rinse. 300 */ 301 static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring) 302 { 303 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | 304 SDMA_GCR_GLM_INV | SDMA_GCR_GL1_INV | 305 SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 306 SDMA_GCR_GLI_INV(1); 307 308 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 309 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ)); 310 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 311 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 312 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 313 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 314 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 315 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 316 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 317 } 318 319 /** 320 * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 321 * 322 * @ring: amdgpu ring pointer 323 * 324 * Emit an hdp flush packet on the requested DMA ring. 325 */ 326 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 327 { 328 struct amdgpu_device *adev = ring->adev; 329 u32 ref_and_mask = 0; 330 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 331 332 if (ring->me > 1) { 333 amdgpu_asic_flush_hdp(adev, ring); 334 } else { 335 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 336 337 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 338 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 339 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 340 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 341 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 342 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 343 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 344 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 345 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 346 } 347 } 348 349 /** 350 * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring 351 * 352 * @ring: amdgpu ring pointer 353 * @addr: address 354 * @seq: sequence number 355 * @flags: fence related flags 356 * 357 * Add a DMA fence packet to the ring to write 358 * the fence seq number and DMA trap packet to generate 359 * an interrupt if needed. 360 */ 361 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 362 unsigned flags) 363 { 364 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 365 /* write the fence */ 366 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 367 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 368 /* zero in first two bits */ 369 BUG_ON(addr & 0x3); 370 amdgpu_ring_write(ring, lower_32_bits(addr)); 371 amdgpu_ring_write(ring, upper_32_bits(addr)); 372 amdgpu_ring_write(ring, lower_32_bits(seq)); 373 374 /* optionally write high bits as well */ 375 if (write64bit) { 376 addr += 4; 377 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 378 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 379 /* zero in first two bits */ 380 BUG_ON(addr & 0x3); 381 amdgpu_ring_write(ring, lower_32_bits(addr)); 382 amdgpu_ring_write(ring, upper_32_bits(addr)); 383 amdgpu_ring_write(ring, upper_32_bits(seq)); 384 } 385 386 if ((flags & AMDGPU_FENCE_FLAG_INT)) { 387 uint32_t ctx = ring->is_mes_queue ? 388 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0; 389 /* generate an interrupt */ 390 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 391 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx)); 392 } 393 } 394 395 396 /** 397 * sdma_v5_2_gfx_stop - stop the gfx async dma engines 398 * 399 * @adev: amdgpu_device pointer 400 * 401 * Stop the gfx async dma ring buffers. 402 */ 403 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev) 404 { 405 u32 rb_cntl, ib_cntl; 406 int i; 407 408 for (i = 0; i < adev->sdma.num_instances; i++) { 409 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 410 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 411 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 412 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 413 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 414 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 415 } 416 } 417 418 /** 419 * sdma_v5_2_rlc_stop - stop the compute async dma engines 420 * 421 * @adev: amdgpu_device pointer 422 * 423 * Stop the compute async dma queues. 424 */ 425 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev) 426 { 427 /* XXX todo */ 428 } 429 430 /** 431 * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch 432 * 433 * @adev: amdgpu_device pointer 434 * @enable: enable/disable the DMA MEs context switch. 435 * 436 * Halt or unhalt the async dma engines context switch. 437 */ 438 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 439 { 440 u32 f32_cntl, phase_quantum = 0; 441 int i; 442 443 if (amdgpu_sdma_phase_quantum) { 444 unsigned value = amdgpu_sdma_phase_quantum; 445 unsigned unit = 0; 446 447 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 448 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 449 value = (value + 1) >> 1; 450 unit++; 451 } 452 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 453 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 454 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 455 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 456 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 457 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 458 WARN_ONCE(1, 459 "clamping sdma_phase_quantum to %uK clock cycles\n", 460 value << unit); 461 } 462 phase_quantum = 463 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 464 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 465 } 466 467 for (i = 0; i < adev->sdma.num_instances; i++) { 468 if (enable && amdgpu_sdma_phase_quantum) { 469 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 470 phase_quantum); 471 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 472 phase_quantum); 473 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 474 phase_quantum); 475 } 476 477 if (!amdgpu_sriov_vf(adev)) { 478 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); 479 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 480 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 481 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 482 } 483 } 484 485 } 486 487 /** 488 * sdma_v5_2_enable - stop the async dma engines 489 * 490 * @adev: amdgpu_device pointer 491 * @enable: enable/disable the DMA MEs. 492 * 493 * Halt or unhalt the async dma engines. 494 */ 495 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable) 496 { 497 u32 f32_cntl; 498 int i; 499 500 if (!enable) { 501 sdma_v5_2_gfx_stop(adev); 502 sdma_v5_2_rlc_stop(adev); 503 } 504 505 if (!amdgpu_sriov_vf(adev)) { 506 for (i = 0; i < adev->sdma.num_instances; i++) { 507 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 508 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 509 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 510 } 511 } 512 } 513 514 /** 515 * sdma_v5_2_gfx_resume - setup and start the async dma engines 516 * 517 * @adev: amdgpu_device pointer 518 * 519 * Set up the gfx DMA ring buffers and enable them. 520 * Returns 0 for success, error for failure. 521 */ 522 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) 523 { 524 struct amdgpu_ring *ring; 525 u32 rb_cntl, ib_cntl; 526 u32 rb_bufsz; 527 u32 doorbell; 528 u32 doorbell_offset; 529 u32 temp; 530 u32 wptr_poll_cntl; 531 u64 wptr_gpu_addr; 532 int i, r; 533 534 for (i = 0; i < adev->sdma.num_instances; i++) { 535 ring = &adev->sdma.instance[i].ring; 536 537 if (!amdgpu_sriov_vf(adev)) 538 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 539 540 /* Set ring buffer size in dwords */ 541 rb_bufsz = order_base_2(ring->ring_size / 4); 542 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 543 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 544 #ifdef __BIG_ENDIAN 545 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 546 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 547 RPTR_WRITEBACK_SWAP_ENABLE, 1); 548 #endif 549 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 550 551 /* Initialize the ring buffer's read and write pointers */ 552 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 553 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 554 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 555 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 556 557 /* setup the wptr shadow polling */ 558 wptr_gpu_addr = ring->wptr_gpu_addr; 559 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 560 lower_32_bits(wptr_gpu_addr)); 561 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 562 upper_32_bits(wptr_gpu_addr)); 563 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 564 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 565 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 566 SDMA0_GFX_RB_WPTR_POLL_CNTL, 567 F32_POLL_ENABLE, 1); 568 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 569 wptr_poll_cntl); 570 571 /* set the wb address whether it's enabled or not */ 572 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 573 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 574 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 575 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 576 577 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 578 579 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 580 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 581 582 ring->wptr = 0; 583 584 /* before programing wptr to a less value, need set minor_ptr_update first */ 585 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 586 587 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 588 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); 589 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); 590 } 591 592 doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 593 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); 594 595 if (ring->use_doorbell) { 596 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 597 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 598 OFFSET, ring->doorbell_index); 599 } else { 600 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 601 } 602 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 603 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 604 605 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 606 ring->doorbell_index, 607 adev->doorbell_index.sdma_doorbell_range); 608 609 if (amdgpu_sriov_vf(adev)) 610 sdma_v5_2_ring_set_wptr(ring); 611 612 /* set minor_ptr_update to 0 after wptr programed */ 613 614 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 615 616 /* SRIOV VF has no control of any of registers below */ 617 if (!amdgpu_sriov_vf(adev)) { 618 /* set utc l1 enable flag always to 1 */ 619 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); 620 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 621 622 /* enable MCBP */ 623 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); 624 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 625 626 /* Set up RESP_MODE to non-copy addresses */ 627 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); 628 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 629 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 630 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); 631 632 /* program default cache read and write policy */ 633 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); 634 /* clean read policy and write policy bits */ 635 temp &= 0xFF0FFF; 636 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | 637 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | 638 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK); 639 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); 640 641 /* unhalt engine */ 642 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 643 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 644 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 645 } 646 647 /* enable DMA RB */ 648 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 649 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 650 651 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 652 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 653 #ifdef __BIG_ENDIAN 654 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 655 #endif 656 /* enable DMA IBs */ 657 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 658 659 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 660 sdma_v5_2_ctx_switch_enable(adev, true); 661 sdma_v5_2_enable(adev, true); 662 } 663 664 r = amdgpu_ring_test_helper(ring); 665 if (r) 666 return r; 667 } 668 669 return 0; 670 } 671 672 /** 673 * sdma_v5_2_rlc_resume - setup and start the async dma engines 674 * 675 * @adev: amdgpu_device pointer 676 * 677 * Set up the compute DMA queues and enable them. 678 * Returns 0 for success, error for failure. 679 */ 680 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev) 681 { 682 return 0; 683 } 684 685 /** 686 * sdma_v5_2_load_microcode - load the sDMA ME ucode 687 * 688 * @adev: amdgpu_device pointer 689 * 690 * Loads the sDMA0/1/2/3 ucode. 691 * Returns 0 for success, -EINVAL if the ucode is not available. 692 */ 693 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev) 694 { 695 const struct sdma_firmware_header_v1_0 *hdr; 696 const __le32 *fw_data; 697 u32 fw_size; 698 int i, j; 699 700 /* halt the MEs */ 701 sdma_v5_2_enable(adev, false); 702 703 for (i = 0; i < adev->sdma.num_instances; i++) { 704 if (!adev->sdma.instance[i].fw) 705 return -EINVAL; 706 707 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 708 amdgpu_ucode_print_sdma_hdr(&hdr->header); 709 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 710 711 fw_data = (const __le32 *) 712 (adev->sdma.instance[i].fw->data + 713 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 714 715 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 716 717 for (j = 0; j < fw_size; j++) { 718 if (amdgpu_emu_mode == 1 && j % 500 == 0) 719 msleep(1); 720 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 721 } 722 723 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 724 } 725 726 return 0; 727 } 728 729 static int sdma_v5_2_soft_reset(void *handle) 730 { 731 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 732 u32 grbm_soft_reset; 733 u32 tmp; 734 int i; 735 736 for (i = 0; i < adev->sdma.num_instances; i++) { 737 grbm_soft_reset = REG_SET_FIELD(0, 738 GRBM_SOFT_RESET, SOFT_RESET_SDMA0, 739 1); 740 grbm_soft_reset <<= i; 741 742 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 743 tmp |= grbm_soft_reset; 744 DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp); 745 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 746 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 747 748 udelay(50); 749 750 tmp &= ~grbm_soft_reset; 751 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 752 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 753 754 udelay(50); 755 } 756 757 return 0; 758 } 759 760 /** 761 * sdma_v5_2_start - setup and start the async dma engines 762 * 763 * @adev: amdgpu_device pointer 764 * 765 * Set up the DMA engines and enable them. 766 * Returns 0 for success, error for failure. 767 */ 768 static int sdma_v5_2_start(struct amdgpu_device *adev) 769 { 770 int r = 0; 771 772 if (amdgpu_sriov_vf(adev)) { 773 sdma_v5_2_ctx_switch_enable(adev, false); 774 sdma_v5_2_enable(adev, false); 775 776 /* set RB registers */ 777 r = sdma_v5_2_gfx_resume(adev); 778 return r; 779 } 780 781 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 782 r = sdma_v5_2_load_microcode(adev); 783 if (r) 784 return r; 785 786 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */ 787 if (amdgpu_emu_mode == 1) 788 msleep(1000); 789 } 790 791 sdma_v5_2_soft_reset(adev); 792 /* unhalt the MEs */ 793 sdma_v5_2_enable(adev, true); 794 /* enable sdma ring preemption */ 795 sdma_v5_2_ctx_switch_enable(adev, true); 796 797 /* start the gfx rings and rlc compute queues */ 798 r = sdma_v5_2_gfx_resume(adev); 799 if (r) 800 return r; 801 r = sdma_v5_2_rlc_resume(adev); 802 803 return r; 804 } 805 806 static int sdma_v5_2_mqd_init(struct amdgpu_device *adev, void *mqd, 807 struct amdgpu_mqd_prop *prop) 808 { 809 struct v10_sdma_mqd *m = mqd; 810 uint64_t wb_gpu_addr; 811 812 m->sdmax_rlcx_rb_cntl = 813 order_base_2(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 814 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 815 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | 816 1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT; 817 818 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8); 819 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); 820 821 m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0, 822 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 823 824 wb_gpu_addr = prop->wptr_gpu_addr; 825 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); 826 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); 827 828 wb_gpu_addr = prop->rptr_gpu_addr; 829 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); 830 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); 831 832 m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0, 833 mmSDMA0_GFX_IB_CNTL)); 834 835 m->sdmax_rlcx_doorbell_offset = 836 prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 837 838 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1); 839 840 return 0; 841 } 842 843 static void sdma_v5_2_set_mqd_funcs(struct amdgpu_device *adev) 844 { 845 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v10_sdma_mqd); 846 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v5_2_mqd_init; 847 } 848 849 /** 850 * sdma_v5_2_ring_test_ring - simple async dma engine test 851 * 852 * @ring: amdgpu_ring structure holding ring information 853 * 854 * Test the DMA engine by writing using it to write an 855 * value to memory. 856 * Returns 0 for success, error for failure. 857 */ 858 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring) 859 { 860 struct amdgpu_device *adev = ring->adev; 861 unsigned i; 862 unsigned index; 863 int r; 864 u32 tmp; 865 u64 gpu_addr; 866 volatile uint32_t *cpu_ptr = NULL; 867 868 tmp = 0xCAFEDEAD; 869 870 if (ring->is_mes_queue) { 871 uint32_t offset = 0; 872 offset = amdgpu_mes_ctx_get_offs(ring, 873 AMDGPU_MES_CTX_PADDING_OFFS); 874 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 875 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 876 *cpu_ptr = tmp; 877 } else { 878 r = amdgpu_device_wb_get(adev, &index); 879 if (r) { 880 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 881 return r; 882 } 883 884 gpu_addr = adev->wb.gpu_addr + (index * 4); 885 adev->wb.wb[index] = cpu_to_le32(tmp); 886 } 887 888 r = amdgpu_ring_alloc(ring, 20); 889 if (r) { 890 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 891 if (!ring->is_mes_queue) 892 amdgpu_device_wb_free(adev, index); 893 return r; 894 } 895 896 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 897 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 898 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 899 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 900 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 901 amdgpu_ring_write(ring, 0xDEADBEEF); 902 amdgpu_ring_commit(ring); 903 904 for (i = 0; i < adev->usec_timeout; i++) { 905 if (ring->is_mes_queue) 906 tmp = le32_to_cpu(*cpu_ptr); 907 else 908 tmp = le32_to_cpu(adev->wb.wb[index]); 909 if (tmp == 0xDEADBEEF) 910 break; 911 if (amdgpu_emu_mode == 1) 912 msleep(1); 913 else 914 udelay(1); 915 } 916 917 if (i >= adev->usec_timeout) 918 r = -ETIMEDOUT; 919 920 if (!ring->is_mes_queue) 921 amdgpu_device_wb_free(adev, index); 922 923 return r; 924 } 925 926 /** 927 * sdma_v5_2_ring_test_ib - test an IB on the DMA engine 928 * 929 * @ring: amdgpu_ring structure holding ring information 930 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 931 * 932 * Test a simple IB in the DMA ring. 933 * Returns 0 on success, error on failure. 934 */ 935 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) 936 { 937 struct amdgpu_device *adev = ring->adev; 938 struct amdgpu_ib ib; 939 struct dma_fence *f = NULL; 940 unsigned index; 941 long r; 942 u32 tmp = 0; 943 u64 gpu_addr; 944 volatile uint32_t *cpu_ptr = NULL; 945 946 tmp = 0xCAFEDEAD; 947 memset(&ib, 0, sizeof(ib)); 948 949 if (ring->is_mes_queue) { 950 uint32_t offset = 0; 951 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 952 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 953 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 954 955 offset = amdgpu_mes_ctx_get_offs(ring, 956 AMDGPU_MES_CTX_PADDING_OFFS); 957 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 958 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 959 *cpu_ptr = tmp; 960 } else { 961 r = amdgpu_device_wb_get(adev, &index); 962 if (r) { 963 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 964 return r; 965 } 966 967 gpu_addr = adev->wb.gpu_addr + (index * 4); 968 adev->wb.wb[index] = cpu_to_le32(tmp); 969 970 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 971 if (r) { 972 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 973 goto err0; 974 } 975 } 976 977 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 978 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 979 ib.ptr[1] = lower_32_bits(gpu_addr); 980 ib.ptr[2] = upper_32_bits(gpu_addr); 981 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 982 ib.ptr[4] = 0xDEADBEEF; 983 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 984 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 985 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 986 ib.length_dw = 8; 987 988 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 989 if (r) 990 goto err1; 991 992 r = dma_fence_wait_timeout(f, false, timeout); 993 if (r == 0) { 994 DRM_ERROR("amdgpu: IB test timed out\n"); 995 r = -ETIMEDOUT; 996 goto err1; 997 } else if (r < 0) { 998 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 999 goto err1; 1000 } 1001 1002 if (ring->is_mes_queue) 1003 tmp = le32_to_cpu(*cpu_ptr); 1004 else 1005 tmp = le32_to_cpu(adev->wb.wb[index]); 1006 1007 if (tmp == 0xDEADBEEF) 1008 r = 0; 1009 else 1010 r = -EINVAL; 1011 1012 err1: 1013 amdgpu_ib_free(adev, &ib, NULL); 1014 dma_fence_put(f); 1015 err0: 1016 if (!ring->is_mes_queue) 1017 amdgpu_device_wb_free(adev, index); 1018 return r; 1019 } 1020 1021 1022 /** 1023 * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART 1024 * 1025 * @ib: indirect buffer to fill with commands 1026 * @pe: addr of the page entry 1027 * @src: src addr to copy from 1028 * @count: number of page entries to update 1029 * 1030 * Update PTEs by copying them from the GART using sDMA. 1031 */ 1032 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib, 1033 uint64_t pe, uint64_t src, 1034 unsigned count) 1035 { 1036 unsigned bytes = count * 8; 1037 1038 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1039 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1040 ib->ptr[ib->length_dw++] = bytes - 1; 1041 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1042 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1043 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1044 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1045 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1046 1047 } 1048 1049 /** 1050 * sdma_v5_2_vm_write_pte - update PTEs by writing them manually 1051 * 1052 * @ib: indirect buffer to fill with commands 1053 * @pe: addr of the page entry 1054 * @value: dst addr to write into pe 1055 * @count: number of page entries to update 1056 * @incr: increase next addr by incr bytes 1057 * 1058 * Update PTEs by writing them manually using sDMA. 1059 */ 1060 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1061 uint64_t value, unsigned count, 1062 uint32_t incr) 1063 { 1064 unsigned ndw = count * 2; 1065 1066 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1067 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1068 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1069 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1070 ib->ptr[ib->length_dw++] = ndw - 1; 1071 for (; ndw > 0; ndw -= 2) { 1072 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1073 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1074 value += incr; 1075 } 1076 } 1077 1078 /** 1079 * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA 1080 * 1081 * @ib: indirect buffer to fill with commands 1082 * @pe: addr of the page entry 1083 * @addr: dst addr to write into pe 1084 * @count: number of page entries to update 1085 * @incr: increase next addr by incr bytes 1086 * @flags: access flags 1087 * 1088 * Update the page tables using sDMA. 1089 */ 1090 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib, 1091 uint64_t pe, 1092 uint64_t addr, unsigned count, 1093 uint32_t incr, uint64_t flags) 1094 { 1095 /* for physically contiguous pages (vram) */ 1096 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1097 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1098 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1099 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1100 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1101 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1102 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1103 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1104 ib->ptr[ib->length_dw++] = 0; 1105 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1106 } 1107 1108 /** 1109 * sdma_v5_2_ring_pad_ib - pad the IB 1110 * 1111 * @ib: indirect buffer to fill with padding 1112 * @ring: amdgpu_ring structure holding ring information 1113 * 1114 * Pad the IB with NOPs to a boundary multiple of 8. 1115 */ 1116 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1117 { 1118 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1119 u32 pad_count; 1120 int i; 1121 1122 pad_count = (-ib->length_dw) & 0x7; 1123 for (i = 0; i < pad_count; i++) 1124 if (sdma && sdma->burst_nop && (i == 0)) 1125 ib->ptr[ib->length_dw++] = 1126 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1127 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1128 else 1129 ib->ptr[ib->length_dw++] = 1130 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1131 } 1132 1133 1134 /** 1135 * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline 1136 * 1137 * @ring: amdgpu_ring pointer 1138 * 1139 * Make sure all previous operations are completed (CIK). 1140 */ 1141 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1142 { 1143 uint32_t seq = ring->fence_drv.sync_seq; 1144 uint64_t addr = ring->fence_drv.gpu_addr; 1145 1146 /* wait for idle */ 1147 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1148 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1149 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1150 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1151 amdgpu_ring_write(ring, addr & 0xfffffffc); 1152 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1153 amdgpu_ring_write(ring, seq); /* reference */ 1154 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1155 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1156 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1157 } 1158 1159 1160 /** 1161 * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA 1162 * 1163 * @ring: amdgpu_ring pointer 1164 * @vmid: vmid number to use 1165 * @pd_addr: address 1166 * 1167 * Update the page table base and flush the VM TLB 1168 * using sDMA. 1169 */ 1170 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring, 1171 unsigned vmid, uint64_t pd_addr) 1172 { 1173 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1174 } 1175 1176 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring, 1177 uint32_t reg, uint32_t val) 1178 { 1179 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1180 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1181 amdgpu_ring_write(ring, reg); 1182 amdgpu_ring_write(ring, val); 1183 } 1184 1185 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1186 uint32_t val, uint32_t mask) 1187 { 1188 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1189 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1190 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1191 amdgpu_ring_write(ring, reg << 2); 1192 amdgpu_ring_write(ring, 0); 1193 amdgpu_ring_write(ring, val); /* reference */ 1194 amdgpu_ring_write(ring, mask); /* mask */ 1195 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1196 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1197 } 1198 1199 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1200 uint32_t reg0, uint32_t reg1, 1201 uint32_t ref, uint32_t mask) 1202 { 1203 amdgpu_ring_emit_wreg(ring, reg0, ref); 1204 /* wait for a cycle to reset vm_inv_eng*_ack */ 1205 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1206 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1207 } 1208 1209 static int sdma_v5_2_early_init(void *handle) 1210 { 1211 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1212 int r; 1213 1214 r = amdgpu_sdma_init_microcode(adev, 0, true); 1215 if (r) 1216 return r; 1217 1218 sdma_v5_2_set_ring_funcs(adev); 1219 sdma_v5_2_set_buffer_funcs(adev); 1220 sdma_v5_2_set_vm_pte_funcs(adev); 1221 sdma_v5_2_set_irq_funcs(adev); 1222 sdma_v5_2_set_mqd_funcs(adev); 1223 1224 return 0; 1225 } 1226 1227 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num) 1228 { 1229 switch (seq_num) { 1230 case 0: 1231 return SOC15_IH_CLIENTID_SDMA0; 1232 case 1: 1233 return SOC15_IH_CLIENTID_SDMA1; 1234 case 2: 1235 return SOC15_IH_CLIENTID_SDMA2; 1236 case 3: 1237 return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid; 1238 default: 1239 break; 1240 } 1241 return -EINVAL; 1242 } 1243 1244 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num) 1245 { 1246 switch (seq_num) { 1247 case 0: 1248 return SDMA0_5_0__SRCID__SDMA_TRAP; 1249 case 1: 1250 return SDMA1_5_0__SRCID__SDMA_TRAP; 1251 case 2: 1252 return SDMA2_5_0__SRCID__SDMA_TRAP; 1253 case 3: 1254 return SDMA3_5_0__SRCID__SDMA_TRAP; 1255 default: 1256 break; 1257 } 1258 return -EINVAL; 1259 } 1260 1261 static int sdma_v5_2_sw_init(void *handle) 1262 { 1263 struct amdgpu_ring *ring; 1264 int r, i; 1265 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1266 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2); 1267 uint32_t *ptr; 1268 1269 /* SDMA trap event */ 1270 for (i = 0; i < adev->sdma.num_instances; i++) { 1271 r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i), 1272 sdma_v5_2_seq_to_trap_id(i), 1273 &adev->sdma.trap_irq); 1274 if (r) 1275 return r; 1276 } 1277 1278 for (i = 0; i < adev->sdma.num_instances; i++) { 1279 ring = &adev->sdma.instance[i].ring; 1280 ring->ring_obj = NULL; 1281 ring->use_doorbell = true; 1282 ring->me = i; 1283 1284 DRM_INFO("use_doorbell being set to: [%s]\n", 1285 ring->use_doorbell?"true":"false"); 1286 1287 ring->doorbell_index = 1288 (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset 1289 1290 ring->vm_hub = AMDGPU_GFXHUB(0); 1291 sprintf(ring->name, "sdma%d", i); 1292 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1293 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1294 AMDGPU_RING_PRIO_DEFAULT, NULL); 1295 if (r) 1296 return r; 1297 } 1298 1299 /* Allocate memory for SDMA IP Dump buffer */ 1300 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); 1301 if (ptr) 1302 adev->sdma.ip_dump = ptr; 1303 else 1304 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n"); 1305 1306 return r; 1307 } 1308 1309 static int sdma_v5_2_sw_fini(void *handle) 1310 { 1311 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1312 int i; 1313 1314 for (i = 0; i < adev->sdma.num_instances; i++) 1315 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1316 1317 amdgpu_sdma_destroy_inst_ctx(adev, true); 1318 1319 kfree(adev->sdma.ip_dump); 1320 1321 return 0; 1322 } 1323 1324 static int sdma_v5_2_hw_init(void *handle) 1325 { 1326 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1327 1328 return sdma_v5_2_start(adev); 1329 } 1330 1331 static int sdma_v5_2_hw_fini(void *handle) 1332 { 1333 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1334 1335 if (amdgpu_sriov_vf(adev)) 1336 return 0; 1337 1338 sdma_v5_2_ctx_switch_enable(adev, false); 1339 sdma_v5_2_enable(adev, false); 1340 1341 return 0; 1342 } 1343 1344 static int sdma_v5_2_suspend(void *handle) 1345 { 1346 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1347 1348 return sdma_v5_2_hw_fini(adev); 1349 } 1350 1351 static int sdma_v5_2_resume(void *handle) 1352 { 1353 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1354 1355 return sdma_v5_2_hw_init(adev); 1356 } 1357 1358 static bool sdma_v5_2_is_idle(void *handle) 1359 { 1360 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1361 u32 i; 1362 1363 for (i = 0; i < adev->sdma.num_instances; i++) { 1364 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1365 1366 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1367 return false; 1368 } 1369 1370 return true; 1371 } 1372 1373 static int sdma_v5_2_wait_for_idle(void *handle) 1374 { 1375 unsigned i; 1376 u32 sdma0, sdma1, sdma2, sdma3; 1377 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1378 1379 for (i = 0; i < adev->usec_timeout; i++) { 1380 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1381 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1382 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG)); 1383 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG)); 1384 1385 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK) 1386 return 0; 1387 udelay(1); 1388 } 1389 return -ETIMEDOUT; 1390 } 1391 1392 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring) 1393 { 1394 int i, r = 0; 1395 struct amdgpu_device *adev = ring->adev; 1396 u32 index = 0; 1397 u64 sdma_gfx_preempt; 1398 1399 amdgpu_sdma_get_index_from_ring(ring, &index); 1400 sdma_gfx_preempt = 1401 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT); 1402 1403 /* assert preemption condition */ 1404 amdgpu_ring_set_preempt_cond_exec(ring, false); 1405 1406 /* emit the trailing fence */ 1407 ring->trail_seq += 1; 1408 amdgpu_ring_alloc(ring, 10); 1409 sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1410 ring->trail_seq, 0); 1411 amdgpu_ring_commit(ring); 1412 1413 /* assert IB preemption */ 1414 WREG32(sdma_gfx_preempt, 1); 1415 1416 /* poll the trailing fence */ 1417 for (i = 0; i < adev->usec_timeout; i++) { 1418 if (ring->trail_seq == 1419 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1420 break; 1421 udelay(1); 1422 } 1423 1424 if (i >= adev->usec_timeout) { 1425 r = -EINVAL; 1426 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1427 } 1428 1429 /* deassert IB preemption */ 1430 WREG32(sdma_gfx_preempt, 0); 1431 1432 /* deassert the preemption condition */ 1433 amdgpu_ring_set_preempt_cond_exec(ring, true); 1434 return r; 1435 } 1436 1437 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev, 1438 struct amdgpu_irq_src *source, 1439 unsigned type, 1440 enum amdgpu_interrupt_state state) 1441 { 1442 u32 sdma_cntl; 1443 u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL); 1444 1445 if (!amdgpu_sriov_vf(adev)) { 1446 sdma_cntl = RREG32(reg_offset); 1447 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1448 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1449 WREG32(reg_offset, sdma_cntl); 1450 } 1451 1452 return 0; 1453 } 1454 1455 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev, 1456 struct amdgpu_irq_src *source, 1457 struct amdgpu_iv_entry *entry) 1458 { 1459 uint32_t mes_queue_id = entry->src_data[0]; 1460 1461 DRM_DEBUG("IH: SDMA trap\n"); 1462 1463 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 1464 struct amdgpu_mes_queue *queue; 1465 1466 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 1467 1468 spin_lock(&adev->mes.queue_id_lock); 1469 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 1470 if (queue) { 1471 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); 1472 amdgpu_fence_process(queue->ring); 1473 } 1474 spin_unlock(&adev->mes.queue_id_lock); 1475 return 0; 1476 } 1477 1478 switch (entry->client_id) { 1479 case SOC15_IH_CLIENTID_SDMA0: 1480 switch (entry->ring_id) { 1481 case 0: 1482 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1483 break; 1484 case 1: 1485 /* XXX compute */ 1486 break; 1487 case 2: 1488 /* XXX compute */ 1489 break; 1490 case 3: 1491 /* XXX page queue*/ 1492 break; 1493 } 1494 break; 1495 case SOC15_IH_CLIENTID_SDMA1: 1496 switch (entry->ring_id) { 1497 case 0: 1498 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1499 break; 1500 case 1: 1501 /* XXX compute */ 1502 break; 1503 case 2: 1504 /* XXX compute */ 1505 break; 1506 case 3: 1507 /* XXX page queue*/ 1508 break; 1509 } 1510 break; 1511 case SOC15_IH_CLIENTID_SDMA2: 1512 switch (entry->ring_id) { 1513 case 0: 1514 amdgpu_fence_process(&adev->sdma.instance[2].ring); 1515 break; 1516 case 1: 1517 /* XXX compute */ 1518 break; 1519 case 2: 1520 /* XXX compute */ 1521 break; 1522 case 3: 1523 /* XXX page queue*/ 1524 break; 1525 } 1526 break; 1527 case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid: 1528 switch (entry->ring_id) { 1529 case 0: 1530 amdgpu_fence_process(&adev->sdma.instance[3].ring); 1531 break; 1532 case 1: 1533 /* XXX compute */ 1534 break; 1535 case 2: 1536 /* XXX compute */ 1537 break; 1538 case 3: 1539 /* XXX page queue*/ 1540 break; 1541 } 1542 break; 1543 } 1544 return 0; 1545 } 1546 1547 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev, 1548 struct amdgpu_irq_src *source, 1549 struct amdgpu_iv_entry *entry) 1550 { 1551 return 0; 1552 } 1553 1554 static bool sdma_v5_2_firmware_mgcg_support(struct amdgpu_device *adev, 1555 int i) 1556 { 1557 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1558 case IP_VERSION(5, 2, 1): 1559 if (adev->sdma.instance[i].fw_version < 70) 1560 return false; 1561 break; 1562 case IP_VERSION(5, 2, 3): 1563 if (adev->sdma.instance[i].fw_version < 47) 1564 return false; 1565 break; 1566 case IP_VERSION(5, 2, 7): 1567 if (adev->sdma.instance[i].fw_version < 9) 1568 return false; 1569 break; 1570 default: 1571 return true; 1572 } 1573 1574 return true; 1575 1576 } 1577 1578 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev, 1579 bool enable) 1580 { 1581 uint32_t data, def; 1582 int i; 1583 1584 for (i = 0; i < adev->sdma.num_instances; i++) { 1585 1586 if (!sdma_v5_2_firmware_mgcg_support(adev, i)) 1587 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG; 1588 1589 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1590 /* Enable sdma clock gating */ 1591 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1592 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1593 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1594 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1595 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1596 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK | 1597 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK); 1598 if (def != data) 1599 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1600 } else { 1601 /* Disable sdma clock gating */ 1602 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1603 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1604 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1605 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1606 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1607 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK | 1608 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK); 1609 if (def != data) 1610 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1611 } 1612 } 1613 } 1614 1615 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev, 1616 bool enable) 1617 { 1618 uint32_t data, def; 1619 int i; 1620 1621 for (i = 0; i < adev->sdma.num_instances; i++) { 1622 if (adev->sdma.instance[i].fw_version < 70 && 1623 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == 1624 IP_VERSION(5, 2, 1)) 1625 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS; 1626 1627 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1628 /* Enable sdma mem light sleep */ 1629 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1630 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1631 if (def != data) 1632 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1633 1634 } else { 1635 /* Disable sdma mem light sleep */ 1636 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1637 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1638 if (def != data) 1639 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1640 1641 } 1642 } 1643 } 1644 1645 static int sdma_v5_2_set_clockgating_state(void *handle, 1646 enum amd_clockgating_state state) 1647 { 1648 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1649 1650 if (amdgpu_sriov_vf(adev)) 1651 return 0; 1652 1653 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1654 case IP_VERSION(5, 2, 0): 1655 case IP_VERSION(5, 2, 2): 1656 case IP_VERSION(5, 2, 1): 1657 case IP_VERSION(5, 2, 4): 1658 case IP_VERSION(5, 2, 5): 1659 case IP_VERSION(5, 2, 6): 1660 case IP_VERSION(5, 2, 3): 1661 case IP_VERSION(5, 2, 7): 1662 sdma_v5_2_update_medium_grain_clock_gating(adev, 1663 state == AMD_CG_STATE_GATE); 1664 sdma_v5_2_update_medium_grain_light_sleep(adev, 1665 state == AMD_CG_STATE_GATE); 1666 break; 1667 default: 1668 break; 1669 } 1670 1671 return 0; 1672 } 1673 1674 static int sdma_v5_2_set_powergating_state(void *handle, 1675 enum amd_powergating_state state) 1676 { 1677 return 0; 1678 } 1679 1680 static void sdma_v5_2_get_clockgating_state(void *handle, u64 *flags) 1681 { 1682 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1683 int data; 1684 1685 if (amdgpu_sriov_vf(adev)) 1686 *flags = 0; 1687 1688 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1689 data = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL)); 1690 if (!(data & SDMA0_CLK_CTRL__CGCG_EN_OVERRIDE_MASK)) 1691 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1692 1693 /* AMD_CG_SUPPORT_SDMA_LS */ 1694 data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); 1695 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1696 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1697 } 1698 1699 static void sdma_v5_2_ring_begin_use(struct amdgpu_ring *ring) 1700 { 1701 struct amdgpu_device *adev = ring->adev; 1702 1703 /* SDMA 5.2.3 (RMB) FW doesn't seem to properly 1704 * disallow GFXOFF in some cases leading to 1705 * hangs in SDMA. Disallow GFXOFF while SDMA is active. 1706 * We can probably just limit this to 5.2.3, 1707 * but it shouldn't hurt for other parts since 1708 * this GFXOFF will be disallowed anyway when SDMA is 1709 * active, this just makes it explicit. 1710 */ 1711 amdgpu_gfx_off_ctrl(adev, false); 1712 } 1713 1714 static void sdma_v5_2_ring_end_use(struct amdgpu_ring *ring) 1715 { 1716 struct amdgpu_device *adev = ring->adev; 1717 1718 /* SDMA 5.2.3 (RMB) FW doesn't seem to properly 1719 * disallow GFXOFF in some cases leading to 1720 * hangs in SDMA. Allow GFXOFF when SDMA is complete. 1721 */ 1722 amdgpu_gfx_off_ctrl(adev, true); 1723 } 1724 1725 static void sdma_v5_2_print_ip_state(void *handle, struct drm_printer *p) 1726 { 1727 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1728 int i, j; 1729 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2); 1730 uint32_t instance_offset; 1731 1732 if (!adev->sdma.ip_dump) 1733 return; 1734 1735 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances); 1736 for (i = 0; i < adev->sdma.num_instances; i++) { 1737 instance_offset = i * reg_count; 1738 drm_printf(p, "\nInstance:%d\n", i); 1739 1740 for (j = 0; j < reg_count; j++) 1741 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_5_2[j].reg_name, 1742 adev->sdma.ip_dump[instance_offset + j]); 1743 } 1744 } 1745 1746 static void sdma_v5_2_dump_ip_state(void *handle) 1747 { 1748 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1749 int i, j; 1750 uint32_t instance_offset; 1751 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2); 1752 1753 if (!adev->sdma.ip_dump) 1754 return; 1755 1756 amdgpu_gfx_off_ctrl(adev, false); 1757 for (i = 0; i < adev->sdma.num_instances; i++) { 1758 instance_offset = i * reg_count; 1759 for (j = 0; j < reg_count; j++) 1760 adev->sdma.ip_dump[instance_offset + j] = 1761 RREG32(sdma_v5_2_get_reg_offset(adev, i, 1762 sdma_reg_list_5_2[j].reg_offset)); 1763 } 1764 amdgpu_gfx_off_ctrl(adev, true); 1765 } 1766 1767 const struct amd_ip_funcs sdma_v5_2_ip_funcs = { 1768 .name = "sdma_v5_2", 1769 .early_init = sdma_v5_2_early_init, 1770 .late_init = NULL, 1771 .sw_init = sdma_v5_2_sw_init, 1772 .sw_fini = sdma_v5_2_sw_fini, 1773 .hw_init = sdma_v5_2_hw_init, 1774 .hw_fini = sdma_v5_2_hw_fini, 1775 .suspend = sdma_v5_2_suspend, 1776 .resume = sdma_v5_2_resume, 1777 .is_idle = sdma_v5_2_is_idle, 1778 .wait_for_idle = sdma_v5_2_wait_for_idle, 1779 .soft_reset = sdma_v5_2_soft_reset, 1780 .set_clockgating_state = sdma_v5_2_set_clockgating_state, 1781 .set_powergating_state = sdma_v5_2_set_powergating_state, 1782 .get_clockgating_state = sdma_v5_2_get_clockgating_state, 1783 .dump_ip_state = sdma_v5_2_dump_ip_state, 1784 .print_ip_state = sdma_v5_2_print_ip_state, 1785 }; 1786 1787 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = { 1788 .type = AMDGPU_RING_TYPE_SDMA, 1789 .align_mask = 0xf, 1790 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1791 .support_64bit_ptrs = true, 1792 .secure_submission_supported = true, 1793 .get_rptr = sdma_v5_2_ring_get_rptr, 1794 .get_wptr = sdma_v5_2_ring_get_wptr, 1795 .set_wptr = sdma_v5_2_ring_set_wptr, 1796 .emit_frame_size = 1797 5 + /* sdma_v5_2_ring_init_cond_exec */ 1798 6 + /* sdma_v5_2_ring_emit_hdp_flush */ 1799 3 + /* hdp_invalidate */ 1800 6 + /* sdma_v5_2_ring_emit_pipeline_sync */ 1801 /* sdma_v5_2_ring_emit_vm_flush */ 1802 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1803 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1804 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */ 1805 .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */ 1806 .emit_ib = sdma_v5_2_ring_emit_ib, 1807 .emit_mem_sync = sdma_v5_2_ring_emit_mem_sync, 1808 .emit_fence = sdma_v5_2_ring_emit_fence, 1809 .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync, 1810 .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush, 1811 .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush, 1812 .test_ring = sdma_v5_2_ring_test_ring, 1813 .test_ib = sdma_v5_2_ring_test_ib, 1814 .insert_nop = sdma_v5_2_ring_insert_nop, 1815 .pad_ib = sdma_v5_2_ring_pad_ib, 1816 .begin_use = sdma_v5_2_ring_begin_use, 1817 .end_use = sdma_v5_2_ring_end_use, 1818 .emit_wreg = sdma_v5_2_ring_emit_wreg, 1819 .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait, 1820 .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait, 1821 .init_cond_exec = sdma_v5_2_ring_init_cond_exec, 1822 .preempt_ib = sdma_v5_2_ring_preempt_ib, 1823 }; 1824 1825 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev) 1826 { 1827 int i; 1828 1829 for (i = 0; i < adev->sdma.num_instances; i++) { 1830 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs; 1831 adev->sdma.instance[i].ring.me = i; 1832 } 1833 } 1834 1835 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = { 1836 .set = sdma_v5_2_set_trap_irq_state, 1837 .process = sdma_v5_2_process_trap_irq, 1838 }; 1839 1840 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = { 1841 .process = sdma_v5_2_process_illegal_inst_irq, 1842 }; 1843 1844 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev) 1845 { 1846 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1847 adev->sdma.num_instances; 1848 adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs; 1849 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs; 1850 } 1851 1852 /** 1853 * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine 1854 * 1855 * @ib: indirect buffer to copy to 1856 * @src_offset: src GPU address 1857 * @dst_offset: dst GPU address 1858 * @byte_count: number of bytes to xfer 1859 * @copy_flags: copy flags for the buffers 1860 * 1861 * Copy GPU buffers using the DMA engine. 1862 * Used by the amdgpu ttm implementation to move pages if 1863 * registered as the asic copy callback. 1864 */ 1865 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib, 1866 uint64_t src_offset, 1867 uint64_t dst_offset, 1868 uint32_t byte_count, 1869 uint32_t copy_flags) 1870 { 1871 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1872 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1873 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0); 1874 ib->ptr[ib->length_dw++] = byte_count - 1; 1875 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1876 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1877 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1878 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1879 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1880 } 1881 1882 /** 1883 * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine 1884 * 1885 * @ib: indirect buffer to fill 1886 * @src_data: value to write to buffer 1887 * @dst_offset: dst GPU address 1888 * @byte_count: number of bytes to xfer 1889 * 1890 * Fill GPU buffers using the DMA engine. 1891 */ 1892 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib, 1893 uint32_t src_data, 1894 uint64_t dst_offset, 1895 uint32_t byte_count) 1896 { 1897 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1898 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1899 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1900 ib->ptr[ib->length_dw++] = src_data; 1901 ib->ptr[ib->length_dw++] = byte_count - 1; 1902 } 1903 1904 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = { 1905 .copy_max_bytes = 0x400000, 1906 .copy_num_dw = 7, 1907 .emit_copy_buffer = sdma_v5_2_emit_copy_buffer, 1908 1909 .fill_max_bytes = 0x400000, 1910 .fill_num_dw = 5, 1911 .emit_fill_buffer = sdma_v5_2_emit_fill_buffer, 1912 }; 1913 1914 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev) 1915 { 1916 if (adev->mman.buffer_funcs == NULL) { 1917 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs; 1918 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1919 } 1920 } 1921 1922 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = { 1923 .copy_pte_num_dw = 7, 1924 .copy_pte = sdma_v5_2_vm_copy_pte, 1925 .write_pte = sdma_v5_2_vm_write_pte, 1926 .set_pte_pde = sdma_v5_2_vm_set_pte_pde, 1927 }; 1928 1929 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev) 1930 { 1931 unsigned i; 1932 1933 if (adev->vm_manager.vm_pte_funcs == NULL) { 1934 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs; 1935 for (i = 0; i < adev->sdma.num_instances; i++) { 1936 adev->vm_manager.vm_pte_scheds[i] = 1937 &adev->sdma.instance[i].ring.sched; 1938 } 1939 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1940 } 1941 } 1942 1943 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = { 1944 .type = AMD_IP_BLOCK_TYPE_SDMA, 1945 .major = 5, 1946 .minor = 2, 1947 .rev = 0, 1948 .funcs = &sdma_v5_2_ip_funcs, 1949 }; 1950