1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_10_3_0_offset.h" 34 #include "gc/gc_10_3_0_sh_mask.h" 35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h" 36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h" 37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h" 38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h" 39 40 #include "soc15_common.h" 41 #include "soc15.h" 42 #include "navi10_sdma_pkt_open.h" 43 #include "nbio_v2_3.h" 44 #include "sdma_common.h" 45 #include "sdma_v5_2.h" 46 47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin"); 48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin"); 49 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin"); 50 MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin"); 51 52 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin"); 53 MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin"); 54 MODULE_FIRMWARE("amdgpu/sdma_5_2_6.bin"); 55 MODULE_FIRMWARE("amdgpu/sdma_5_2_7.bin"); 56 57 #define SDMA1_REG_OFFSET 0x600 58 #define SDMA3_REG_OFFSET 0x400 59 #define SDMA0_HYP_DEC_REG_START 0x5880 60 #define SDMA0_HYP_DEC_REG_END 0x5893 61 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 62 63 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev); 64 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev); 65 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev); 66 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev); 67 68 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 69 { 70 u32 base; 71 72 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 73 internal_offset <= SDMA0_HYP_DEC_REG_END) { 74 base = adev->reg_offset[GC_HWIP][0][1]; 75 if (instance != 0) 76 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance; 77 } else { 78 if (instance < 2) { 79 base = adev->reg_offset[GC_HWIP][0][0]; 80 if (instance == 1) 81 internal_offset += SDMA1_REG_OFFSET; 82 } else { 83 base = adev->reg_offset[GC_HWIP][0][2]; 84 if (instance == 3) 85 internal_offset += SDMA3_REG_OFFSET; 86 } 87 } 88 89 return base + internal_offset; 90 } 91 92 /** 93 * sdma_v5_2_init_microcode - load ucode images from disk 94 * 95 * @adev: amdgpu_device pointer 96 * 97 * Use the firmware interface to load the ucode images into 98 * the driver (not loaded into hw). 99 * Returns 0 on success, error on failure. 100 */ 101 102 // emulation only, won't work on real chip 103 // navi10 real chip need to use PSP to load firmware 104 static int sdma_v5_2_init_microcode(struct amdgpu_device *adev) 105 { 106 const char *chip_name; 107 char fw_name[40]; 108 109 DRM_DEBUG("\n"); 110 111 switch (adev->ip_versions[SDMA0_HWIP][0]) { 112 case IP_VERSION(5, 2, 0): 113 chip_name = "sienna_cichlid_sdma"; 114 break; 115 case IP_VERSION(5, 2, 2): 116 chip_name = "navy_flounder_sdma"; 117 break; 118 case IP_VERSION(5, 2, 1): 119 chip_name = "vangogh_sdma"; 120 break; 121 case IP_VERSION(5, 2, 4): 122 chip_name = "dimgrey_cavefish_sdma"; 123 break; 124 case IP_VERSION(5, 2, 5): 125 chip_name = "beige_goby_sdma"; 126 break; 127 case IP_VERSION(5, 2, 3): 128 chip_name = "yellow_carp_sdma"; 129 break; 130 case IP_VERSION(5, 2, 6): 131 chip_name = "sdma_5_2_6"; 132 break; 133 case IP_VERSION(5, 2, 7): 134 chip_name = "sdma_5_2_7"; 135 break; 136 default: 137 BUG(); 138 } 139 140 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name); 141 142 return amdgpu_sdma_init_microcode(adev, fw_name, 0, true); 143 } 144 145 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring) 146 { 147 unsigned ret; 148 149 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); 150 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 151 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 152 amdgpu_ring_write(ring, 1); 153 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ 154 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ 155 156 return ret; 157 } 158 159 static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring, 160 unsigned offset) 161 { 162 unsigned cur; 163 164 BUG_ON(offset > ring->buf_mask); 165 BUG_ON(ring->ring[offset] != 0x55aa55aa); 166 167 cur = (ring->wptr - 1) & ring->buf_mask; 168 if (cur > offset) 169 ring->ring[offset] = cur - offset; 170 else 171 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 172 } 173 174 /** 175 * sdma_v5_2_ring_get_rptr - get the current read pointer 176 * 177 * @ring: amdgpu ring pointer 178 * 179 * Get the current rptr from the hardware (NAVI10+). 180 */ 181 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring) 182 { 183 u64 *rptr; 184 185 /* XXX check if swapping is necessary on BE */ 186 rptr = (u64 *)ring->rptr_cpu_addr; 187 188 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 189 return ((*rptr) >> 2); 190 } 191 192 /** 193 * sdma_v5_2_ring_get_wptr - get the current write pointer 194 * 195 * @ring: amdgpu ring pointer 196 * 197 * Get the current wptr from the hardware (NAVI10+). 198 */ 199 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring) 200 { 201 struct amdgpu_device *adev = ring->adev; 202 u64 wptr; 203 204 if (ring->use_doorbell) { 205 /* XXX check if swapping is necessary on BE */ 206 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 207 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 208 } else { 209 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); 210 wptr = wptr << 32; 211 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); 212 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr); 213 } 214 215 return wptr >> 2; 216 } 217 218 /** 219 * sdma_v5_2_ring_set_wptr - commit the write pointer 220 * 221 * @ring: amdgpu ring pointer 222 * 223 * Write the wptr back to the hardware (NAVI10+). 224 */ 225 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring) 226 { 227 struct amdgpu_device *adev = ring->adev; 228 229 DRM_DEBUG("Setting write pointer\n"); 230 if (ring->use_doorbell) { 231 DRM_DEBUG("Using doorbell -- " 232 "wptr_offs == 0x%08x " 233 "lower_32_bits(ring->wptr << 2) == 0x%08x " 234 "upper_32_bits(ring->wptr << 2) == 0x%08x\n", 235 ring->wptr_offs, 236 lower_32_bits(ring->wptr << 2), 237 upper_32_bits(ring->wptr << 2)); 238 /* XXX check if swapping is necessary on BE */ 239 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 240 ring->wptr << 2); 241 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 242 ring->doorbell_index, ring->wptr << 2); 243 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 244 } else { 245 DRM_DEBUG("Not using doorbell -- " 246 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 247 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 248 ring->me, 249 lower_32_bits(ring->wptr << 2), 250 ring->me, 251 upper_32_bits(ring->wptr << 2)); 252 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), 253 lower_32_bits(ring->wptr << 2)); 254 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), 255 upper_32_bits(ring->wptr << 2)); 256 } 257 } 258 259 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 260 { 261 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 262 int i; 263 264 for (i = 0; i < count; i++) 265 if (sdma && sdma->burst_nop && (i == 0)) 266 amdgpu_ring_write(ring, ring->funcs->nop | 267 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 268 else 269 amdgpu_ring_write(ring, ring->funcs->nop); 270 } 271 272 /** 273 * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine 274 * 275 * @ring: amdgpu ring pointer 276 * @job: job to retrieve vmid from 277 * @ib: IB object to schedule 278 * @flags: unused 279 * 280 * Schedule an IB in the DMA ring. 281 */ 282 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring, 283 struct amdgpu_job *job, 284 struct amdgpu_ib *ib, 285 uint32_t flags) 286 { 287 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 288 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 289 290 /* An IB packet must end on a 8 DW boundary--the next dword 291 * must be on a 8-dword boundary. Our IB packet below is 6 292 * dwords long, thus add x number of NOPs, such that, in 293 * modular arithmetic, 294 * wptr + 6 + x = 8k, k >= 0, which in C is, 295 * (wptr + 6 + x) % 8 = 0. 296 * The expression below, is a solution of x. 297 */ 298 sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 299 300 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 301 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 302 /* base must be 32 byte aligned */ 303 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 304 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 305 amdgpu_ring_write(ring, ib->length_dw); 306 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 307 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 308 } 309 310 /** 311 * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse 312 * 313 * @ring: amdgpu ring pointer 314 * 315 * flush the IB by graphics cache rinse. 316 */ 317 static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring) 318 { 319 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | 320 SDMA_GCR_GLM_INV | SDMA_GCR_GL1_INV | 321 SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 322 SDMA_GCR_GLI_INV(1); 323 324 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 325 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ)); 326 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 327 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 328 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 329 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 330 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 331 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 332 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 333 } 334 335 /** 336 * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 337 * 338 * @ring: amdgpu ring pointer 339 * 340 * Emit an hdp flush packet on the requested DMA ring. 341 */ 342 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 343 { 344 struct amdgpu_device *adev = ring->adev; 345 u32 ref_and_mask = 0; 346 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 347 348 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 349 350 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 351 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 352 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 353 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 354 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 355 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 356 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 357 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 358 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 359 } 360 361 /** 362 * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring 363 * 364 * @ring: amdgpu ring pointer 365 * @addr: address 366 * @seq: sequence number 367 * @flags: fence related flags 368 * 369 * Add a DMA fence packet to the ring to write 370 * the fence seq number and DMA trap packet to generate 371 * an interrupt if needed. 372 */ 373 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 374 unsigned flags) 375 { 376 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 377 /* write the fence */ 378 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 379 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 380 /* zero in first two bits */ 381 BUG_ON(addr & 0x3); 382 amdgpu_ring_write(ring, lower_32_bits(addr)); 383 amdgpu_ring_write(ring, upper_32_bits(addr)); 384 amdgpu_ring_write(ring, lower_32_bits(seq)); 385 386 /* optionally write high bits as well */ 387 if (write64bit) { 388 addr += 4; 389 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 390 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 391 /* zero in first two bits */ 392 BUG_ON(addr & 0x3); 393 amdgpu_ring_write(ring, lower_32_bits(addr)); 394 amdgpu_ring_write(ring, upper_32_bits(addr)); 395 amdgpu_ring_write(ring, upper_32_bits(seq)); 396 } 397 398 if ((flags & AMDGPU_FENCE_FLAG_INT)) { 399 uint32_t ctx = ring->is_mes_queue ? 400 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0; 401 /* generate an interrupt */ 402 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 403 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx)); 404 } 405 } 406 407 408 /** 409 * sdma_v5_2_gfx_stop - stop the gfx async dma engines 410 * 411 * @adev: amdgpu_device pointer 412 * 413 * Stop the gfx async dma ring buffers. 414 */ 415 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev) 416 { 417 u32 rb_cntl, ib_cntl; 418 int i; 419 420 amdgpu_sdma_unset_buffer_funcs_helper(adev); 421 422 for (i = 0; i < adev->sdma.num_instances; i++) { 423 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 424 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 425 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 426 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 427 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 428 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 429 } 430 } 431 432 /** 433 * sdma_v5_2_rlc_stop - stop the compute async dma engines 434 * 435 * @adev: amdgpu_device pointer 436 * 437 * Stop the compute async dma queues. 438 */ 439 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev) 440 { 441 /* XXX todo */ 442 } 443 444 /** 445 * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch 446 * 447 * @adev: amdgpu_device pointer 448 * @enable: enable/disable the DMA MEs context switch. 449 * 450 * Halt or unhalt the async dma engines context switch. 451 */ 452 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 453 { 454 u32 f32_cntl, phase_quantum = 0; 455 int i; 456 457 if (amdgpu_sdma_phase_quantum) { 458 unsigned value = amdgpu_sdma_phase_quantum; 459 unsigned unit = 0; 460 461 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 462 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 463 value = (value + 1) >> 1; 464 unit++; 465 } 466 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 467 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 468 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 469 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 470 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 471 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 472 WARN_ONCE(1, 473 "clamping sdma_phase_quantum to %uK clock cycles\n", 474 value << unit); 475 } 476 phase_quantum = 477 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 478 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 479 } 480 481 for (i = 0; i < adev->sdma.num_instances; i++) { 482 if (enable && amdgpu_sdma_phase_quantum) { 483 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 484 phase_quantum); 485 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 486 phase_quantum); 487 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 488 phase_quantum); 489 } 490 491 if (!amdgpu_sriov_vf(adev)) { 492 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); 493 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 494 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 495 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 496 } 497 } 498 499 } 500 501 /** 502 * sdma_v5_2_enable - stop the async dma engines 503 * 504 * @adev: amdgpu_device pointer 505 * @enable: enable/disable the DMA MEs. 506 * 507 * Halt or unhalt the async dma engines. 508 */ 509 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable) 510 { 511 u32 f32_cntl; 512 int i; 513 514 if (!enable) { 515 sdma_v5_2_gfx_stop(adev); 516 sdma_v5_2_rlc_stop(adev); 517 } 518 519 if (!amdgpu_sriov_vf(adev)) { 520 for (i = 0; i < adev->sdma.num_instances; i++) { 521 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 522 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 523 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 524 } 525 } 526 } 527 528 /** 529 * sdma_v5_2_gfx_resume - setup and start the async dma engines 530 * 531 * @adev: amdgpu_device pointer 532 * 533 * Set up the gfx DMA ring buffers and enable them. 534 * Returns 0 for success, error for failure. 535 */ 536 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) 537 { 538 struct amdgpu_ring *ring; 539 u32 rb_cntl, ib_cntl; 540 u32 rb_bufsz; 541 u32 doorbell; 542 u32 doorbell_offset; 543 u32 temp; 544 u32 wptr_poll_cntl; 545 u64 wptr_gpu_addr; 546 int i, r; 547 548 for (i = 0; i < adev->sdma.num_instances; i++) { 549 ring = &adev->sdma.instance[i].ring; 550 551 if (!amdgpu_sriov_vf(adev)) 552 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 553 554 /* Set ring buffer size in dwords */ 555 rb_bufsz = order_base_2(ring->ring_size / 4); 556 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 557 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 558 #ifdef __BIG_ENDIAN 559 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 560 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 561 RPTR_WRITEBACK_SWAP_ENABLE, 1); 562 #endif 563 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 564 565 /* Initialize the ring buffer's read and write pointers */ 566 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 567 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 568 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 569 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 570 571 /* setup the wptr shadow polling */ 572 wptr_gpu_addr = ring->wptr_gpu_addr; 573 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 574 lower_32_bits(wptr_gpu_addr)); 575 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 576 upper_32_bits(wptr_gpu_addr)); 577 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 578 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 579 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 580 SDMA0_GFX_RB_WPTR_POLL_CNTL, 581 F32_POLL_ENABLE, 1); 582 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 583 wptr_poll_cntl); 584 585 /* set the wb address whether it's enabled or not */ 586 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 587 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 588 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 589 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 590 591 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 592 593 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 594 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 595 596 ring->wptr = 0; 597 598 /* before programing wptr to a less value, need set minor_ptr_update first */ 599 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 600 601 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 602 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); 603 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); 604 } 605 606 doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 607 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); 608 609 if (ring->use_doorbell) { 610 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 611 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 612 OFFSET, ring->doorbell_index); 613 } else { 614 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 615 } 616 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 617 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 618 619 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 620 ring->doorbell_index, 621 adev->doorbell_index.sdma_doorbell_range); 622 623 if (amdgpu_sriov_vf(adev)) 624 sdma_v5_2_ring_set_wptr(ring); 625 626 /* set minor_ptr_update to 0 after wptr programed */ 627 628 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 629 630 /* SRIOV VF has no control of any of registers below */ 631 if (!amdgpu_sriov_vf(adev)) { 632 /* set utc l1 enable flag always to 1 */ 633 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); 634 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 635 636 /* enable MCBP */ 637 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); 638 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 639 640 /* Set up RESP_MODE to non-copy addresses */ 641 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); 642 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 643 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 644 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); 645 646 /* program default cache read and write policy */ 647 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); 648 /* clean read policy and write policy bits */ 649 temp &= 0xFF0FFF; 650 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | 651 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | 652 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK); 653 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); 654 655 /* unhalt engine */ 656 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 657 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 658 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 659 } 660 661 /* enable DMA RB */ 662 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 663 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 664 665 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 666 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 667 #ifdef __BIG_ENDIAN 668 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 669 #endif 670 /* enable DMA IBs */ 671 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 672 673 ring->sched.ready = true; 674 675 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 676 sdma_v5_2_ctx_switch_enable(adev, true); 677 sdma_v5_2_enable(adev, true); 678 } 679 680 r = amdgpu_ring_test_ring(ring); 681 if (r) { 682 ring->sched.ready = false; 683 return r; 684 } 685 686 if (adev->mman.buffer_funcs_ring == ring) 687 amdgpu_ttm_set_buffer_funcs_status(adev, true); 688 } 689 690 return 0; 691 } 692 693 /** 694 * sdma_v5_2_rlc_resume - setup and start the async dma engines 695 * 696 * @adev: amdgpu_device pointer 697 * 698 * Set up the compute DMA queues and enable them. 699 * Returns 0 for success, error for failure. 700 */ 701 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev) 702 { 703 return 0; 704 } 705 706 /** 707 * sdma_v5_2_load_microcode - load the sDMA ME ucode 708 * 709 * @adev: amdgpu_device pointer 710 * 711 * Loads the sDMA0/1/2/3 ucode. 712 * Returns 0 for success, -EINVAL if the ucode is not available. 713 */ 714 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev) 715 { 716 const struct sdma_firmware_header_v1_0 *hdr; 717 const __le32 *fw_data; 718 u32 fw_size; 719 int i, j; 720 721 /* halt the MEs */ 722 sdma_v5_2_enable(adev, false); 723 724 for (i = 0; i < adev->sdma.num_instances; i++) { 725 if (!adev->sdma.instance[i].fw) 726 return -EINVAL; 727 728 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 729 amdgpu_ucode_print_sdma_hdr(&hdr->header); 730 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 731 732 fw_data = (const __le32 *) 733 (adev->sdma.instance[i].fw->data + 734 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 735 736 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 737 738 for (j = 0; j < fw_size; j++) { 739 if (amdgpu_emu_mode == 1 && j % 500 == 0) 740 msleep(1); 741 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 742 } 743 744 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 745 } 746 747 return 0; 748 } 749 750 static int sdma_v5_2_soft_reset(void *handle) 751 { 752 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 753 u32 grbm_soft_reset; 754 u32 tmp; 755 int i; 756 757 for (i = 0; i < adev->sdma.num_instances; i++) { 758 grbm_soft_reset = REG_SET_FIELD(0, 759 GRBM_SOFT_RESET, SOFT_RESET_SDMA0, 760 1); 761 grbm_soft_reset <<= i; 762 763 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 764 tmp |= grbm_soft_reset; 765 DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp); 766 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 767 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 768 769 udelay(50); 770 771 tmp &= ~grbm_soft_reset; 772 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 773 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 774 775 udelay(50); 776 } 777 778 return 0; 779 } 780 781 /** 782 * sdma_v5_2_start - setup and start the async dma engines 783 * 784 * @adev: amdgpu_device pointer 785 * 786 * Set up the DMA engines and enable them. 787 * Returns 0 for success, error for failure. 788 */ 789 static int sdma_v5_2_start(struct amdgpu_device *adev) 790 { 791 int r = 0; 792 793 if (amdgpu_sriov_vf(adev)) { 794 sdma_v5_2_ctx_switch_enable(adev, false); 795 sdma_v5_2_enable(adev, false); 796 797 /* set RB registers */ 798 r = sdma_v5_2_gfx_resume(adev); 799 return r; 800 } 801 802 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 803 r = sdma_v5_2_load_microcode(adev); 804 if (r) 805 return r; 806 807 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */ 808 if (amdgpu_emu_mode == 1) 809 msleep(1000); 810 } 811 812 sdma_v5_2_soft_reset(adev); 813 /* unhalt the MEs */ 814 sdma_v5_2_enable(adev, true); 815 /* enable sdma ring preemption */ 816 sdma_v5_2_ctx_switch_enable(adev, true); 817 818 /* start the gfx rings and rlc compute queues */ 819 r = sdma_v5_2_gfx_resume(adev); 820 if (r) 821 return r; 822 r = sdma_v5_2_rlc_resume(adev); 823 824 return r; 825 } 826 827 static int sdma_v5_2_mqd_init(struct amdgpu_device *adev, void *mqd, 828 struct amdgpu_mqd_prop *prop) 829 { 830 struct v10_sdma_mqd *m = mqd; 831 uint64_t wb_gpu_addr; 832 833 m->sdmax_rlcx_rb_cntl = 834 order_base_2(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 835 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 836 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | 837 1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT; 838 839 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8); 840 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); 841 842 m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0, 843 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 844 845 wb_gpu_addr = prop->wptr_gpu_addr; 846 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); 847 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); 848 849 wb_gpu_addr = prop->rptr_gpu_addr; 850 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); 851 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); 852 853 m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0, 854 mmSDMA0_GFX_IB_CNTL)); 855 856 m->sdmax_rlcx_doorbell_offset = 857 prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 858 859 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1); 860 861 return 0; 862 } 863 864 static void sdma_v5_2_set_mqd_funcs(struct amdgpu_device *adev) 865 { 866 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v10_sdma_mqd); 867 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v5_2_mqd_init; 868 } 869 870 /** 871 * sdma_v5_2_ring_test_ring - simple async dma engine test 872 * 873 * @ring: amdgpu_ring structure holding ring information 874 * 875 * Test the DMA engine by writing using it to write an 876 * value to memory. 877 * Returns 0 for success, error for failure. 878 */ 879 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring) 880 { 881 struct amdgpu_device *adev = ring->adev; 882 unsigned i; 883 unsigned index; 884 int r; 885 u32 tmp; 886 u64 gpu_addr; 887 volatile uint32_t *cpu_ptr = NULL; 888 889 tmp = 0xCAFEDEAD; 890 891 if (ring->is_mes_queue) { 892 uint32_t offset = 0; 893 offset = amdgpu_mes_ctx_get_offs(ring, 894 AMDGPU_MES_CTX_PADDING_OFFS); 895 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 896 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 897 *cpu_ptr = tmp; 898 } else { 899 r = amdgpu_device_wb_get(adev, &index); 900 if (r) { 901 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 902 return r; 903 } 904 905 gpu_addr = adev->wb.gpu_addr + (index * 4); 906 adev->wb.wb[index] = cpu_to_le32(tmp); 907 } 908 909 r = amdgpu_ring_alloc(ring, 20); 910 if (r) { 911 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 912 amdgpu_device_wb_free(adev, index); 913 return r; 914 } 915 916 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 917 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 918 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 919 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 920 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 921 amdgpu_ring_write(ring, 0xDEADBEEF); 922 amdgpu_ring_commit(ring); 923 924 for (i = 0; i < adev->usec_timeout; i++) { 925 if (ring->is_mes_queue) 926 tmp = le32_to_cpu(*cpu_ptr); 927 else 928 tmp = le32_to_cpu(adev->wb.wb[index]); 929 if (tmp == 0xDEADBEEF) 930 break; 931 if (amdgpu_emu_mode == 1) 932 msleep(1); 933 else 934 udelay(1); 935 } 936 937 if (i >= adev->usec_timeout) 938 r = -ETIMEDOUT; 939 940 if (!ring->is_mes_queue) 941 amdgpu_device_wb_free(adev, index); 942 943 return r; 944 } 945 946 /** 947 * sdma_v5_2_ring_test_ib - test an IB on the DMA engine 948 * 949 * @ring: amdgpu_ring structure holding ring information 950 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 951 * 952 * Test a simple IB in the DMA ring. 953 * Returns 0 on success, error on failure. 954 */ 955 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) 956 { 957 struct amdgpu_device *adev = ring->adev; 958 struct amdgpu_ib ib; 959 struct dma_fence *f = NULL; 960 unsigned index; 961 long r; 962 u32 tmp = 0; 963 u64 gpu_addr; 964 volatile uint32_t *cpu_ptr = NULL; 965 966 tmp = 0xCAFEDEAD; 967 memset(&ib, 0, sizeof(ib)); 968 969 if (ring->is_mes_queue) { 970 uint32_t offset = 0; 971 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 972 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 973 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 974 975 offset = amdgpu_mes_ctx_get_offs(ring, 976 AMDGPU_MES_CTX_PADDING_OFFS); 977 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 978 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 979 *cpu_ptr = tmp; 980 } else { 981 r = amdgpu_device_wb_get(adev, &index); 982 if (r) { 983 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 984 return r; 985 } 986 987 gpu_addr = adev->wb.gpu_addr + (index * 4); 988 adev->wb.wb[index] = cpu_to_le32(tmp); 989 990 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 991 if (r) { 992 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 993 goto err0; 994 } 995 } 996 997 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 998 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 999 ib.ptr[1] = lower_32_bits(gpu_addr); 1000 ib.ptr[2] = upper_32_bits(gpu_addr); 1001 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1002 ib.ptr[4] = 0xDEADBEEF; 1003 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1004 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1005 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1006 ib.length_dw = 8; 1007 1008 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1009 if (r) 1010 goto err1; 1011 1012 r = dma_fence_wait_timeout(f, false, timeout); 1013 if (r == 0) { 1014 DRM_ERROR("amdgpu: IB test timed out\n"); 1015 r = -ETIMEDOUT; 1016 goto err1; 1017 } else if (r < 0) { 1018 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1019 goto err1; 1020 } 1021 1022 if (ring->is_mes_queue) 1023 tmp = le32_to_cpu(*cpu_ptr); 1024 else 1025 tmp = le32_to_cpu(adev->wb.wb[index]); 1026 1027 if (tmp == 0xDEADBEEF) 1028 r = 0; 1029 else 1030 r = -EINVAL; 1031 1032 err1: 1033 amdgpu_ib_free(adev, &ib, NULL); 1034 dma_fence_put(f); 1035 err0: 1036 if (!ring->is_mes_queue) 1037 amdgpu_device_wb_free(adev, index); 1038 return r; 1039 } 1040 1041 1042 /** 1043 * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART 1044 * 1045 * @ib: indirect buffer to fill with commands 1046 * @pe: addr of the page entry 1047 * @src: src addr to copy from 1048 * @count: number of page entries to update 1049 * 1050 * Update PTEs by copying them from the GART using sDMA. 1051 */ 1052 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib, 1053 uint64_t pe, uint64_t src, 1054 unsigned count) 1055 { 1056 unsigned bytes = count * 8; 1057 1058 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1059 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1060 ib->ptr[ib->length_dw++] = bytes - 1; 1061 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1062 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1063 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1064 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1065 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1066 1067 } 1068 1069 /** 1070 * sdma_v5_2_vm_write_pte - update PTEs by writing them manually 1071 * 1072 * @ib: indirect buffer to fill with commands 1073 * @pe: addr of the page entry 1074 * @value: dst addr to write into pe 1075 * @count: number of page entries to update 1076 * @incr: increase next addr by incr bytes 1077 * 1078 * Update PTEs by writing them manually using sDMA. 1079 */ 1080 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1081 uint64_t value, unsigned count, 1082 uint32_t incr) 1083 { 1084 unsigned ndw = count * 2; 1085 1086 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1087 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1088 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1089 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1090 ib->ptr[ib->length_dw++] = ndw - 1; 1091 for (; ndw > 0; ndw -= 2) { 1092 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1093 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1094 value += incr; 1095 } 1096 } 1097 1098 /** 1099 * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA 1100 * 1101 * @ib: indirect buffer to fill with commands 1102 * @pe: addr of the page entry 1103 * @addr: dst addr to write into pe 1104 * @count: number of page entries to update 1105 * @incr: increase next addr by incr bytes 1106 * @flags: access flags 1107 * 1108 * Update the page tables using sDMA. 1109 */ 1110 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib, 1111 uint64_t pe, 1112 uint64_t addr, unsigned count, 1113 uint32_t incr, uint64_t flags) 1114 { 1115 /* for physically contiguous pages (vram) */ 1116 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1117 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1118 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1119 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1120 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1121 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1122 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1123 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1124 ib->ptr[ib->length_dw++] = 0; 1125 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1126 } 1127 1128 /** 1129 * sdma_v5_2_ring_pad_ib - pad the IB 1130 * 1131 * @ib: indirect buffer to fill with padding 1132 * @ring: amdgpu_ring structure holding ring information 1133 * 1134 * Pad the IB with NOPs to a boundary multiple of 8. 1135 */ 1136 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1137 { 1138 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1139 u32 pad_count; 1140 int i; 1141 1142 pad_count = (-ib->length_dw) & 0x7; 1143 for (i = 0; i < pad_count; i++) 1144 if (sdma && sdma->burst_nop && (i == 0)) 1145 ib->ptr[ib->length_dw++] = 1146 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1147 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1148 else 1149 ib->ptr[ib->length_dw++] = 1150 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1151 } 1152 1153 1154 /** 1155 * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline 1156 * 1157 * @ring: amdgpu_ring pointer 1158 * 1159 * Make sure all previous operations are completed (CIK). 1160 */ 1161 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1162 { 1163 uint32_t seq = ring->fence_drv.sync_seq; 1164 uint64_t addr = ring->fence_drv.gpu_addr; 1165 1166 /* wait for idle */ 1167 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1168 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1169 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1170 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1171 amdgpu_ring_write(ring, addr & 0xfffffffc); 1172 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1173 amdgpu_ring_write(ring, seq); /* reference */ 1174 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1175 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1176 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1177 } 1178 1179 1180 /** 1181 * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA 1182 * 1183 * @ring: amdgpu_ring pointer 1184 * @vmid: vmid number to use 1185 * @pd_addr: address 1186 * 1187 * Update the page table base and flush the VM TLB 1188 * using sDMA. 1189 */ 1190 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring, 1191 unsigned vmid, uint64_t pd_addr) 1192 { 1193 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1194 } 1195 1196 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring, 1197 uint32_t reg, uint32_t val) 1198 { 1199 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1200 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1201 amdgpu_ring_write(ring, reg); 1202 amdgpu_ring_write(ring, val); 1203 } 1204 1205 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1206 uint32_t val, uint32_t mask) 1207 { 1208 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1209 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1210 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1211 amdgpu_ring_write(ring, reg << 2); 1212 amdgpu_ring_write(ring, 0); 1213 amdgpu_ring_write(ring, val); /* reference */ 1214 amdgpu_ring_write(ring, mask); /* mask */ 1215 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1216 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1217 } 1218 1219 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1220 uint32_t reg0, uint32_t reg1, 1221 uint32_t ref, uint32_t mask) 1222 { 1223 amdgpu_ring_emit_wreg(ring, reg0, ref); 1224 /* wait for a cycle to reset vm_inv_eng*_ack */ 1225 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1226 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1227 } 1228 1229 static int sdma_v5_2_early_init(void *handle) 1230 { 1231 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1232 1233 sdma_v5_2_set_ring_funcs(adev); 1234 sdma_v5_2_set_buffer_funcs(adev); 1235 sdma_v5_2_set_vm_pte_funcs(adev); 1236 sdma_v5_2_set_irq_funcs(adev); 1237 sdma_v5_2_set_mqd_funcs(adev); 1238 1239 return 0; 1240 } 1241 1242 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num) 1243 { 1244 switch (seq_num) { 1245 case 0: 1246 return SOC15_IH_CLIENTID_SDMA0; 1247 case 1: 1248 return SOC15_IH_CLIENTID_SDMA1; 1249 case 2: 1250 return SOC15_IH_CLIENTID_SDMA2; 1251 case 3: 1252 return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid; 1253 default: 1254 break; 1255 } 1256 return -EINVAL; 1257 } 1258 1259 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num) 1260 { 1261 switch (seq_num) { 1262 case 0: 1263 return SDMA0_5_0__SRCID__SDMA_TRAP; 1264 case 1: 1265 return SDMA1_5_0__SRCID__SDMA_TRAP; 1266 case 2: 1267 return SDMA2_5_0__SRCID__SDMA_TRAP; 1268 case 3: 1269 return SDMA3_5_0__SRCID__SDMA_TRAP; 1270 default: 1271 break; 1272 } 1273 return -EINVAL; 1274 } 1275 1276 static int sdma_v5_2_sw_init(void *handle) 1277 { 1278 struct amdgpu_ring *ring; 1279 int r, i; 1280 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1281 1282 /* SDMA trap event */ 1283 for (i = 0; i < adev->sdma.num_instances; i++) { 1284 r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i), 1285 sdma_v5_2_seq_to_trap_id(i), 1286 &adev->sdma.trap_irq); 1287 if (r) 1288 return r; 1289 } 1290 1291 r = sdma_v5_2_init_microcode(adev); 1292 if (r) { 1293 DRM_ERROR("Failed to load sdma firmware!\n"); 1294 return r; 1295 } 1296 1297 for (i = 0; i < adev->sdma.num_instances; i++) { 1298 ring = &adev->sdma.instance[i].ring; 1299 ring->ring_obj = NULL; 1300 ring->use_doorbell = true; 1301 ring->me = i; 1302 1303 DRM_INFO("use_doorbell being set to: [%s]\n", 1304 ring->use_doorbell?"true":"false"); 1305 1306 ring->doorbell_index = 1307 (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset 1308 1309 sprintf(ring->name, "sdma%d", i); 1310 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1311 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1312 AMDGPU_RING_PRIO_DEFAULT, NULL); 1313 if (r) 1314 return r; 1315 } 1316 1317 return r; 1318 } 1319 1320 static int sdma_v5_2_sw_fini(void *handle) 1321 { 1322 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1323 int i; 1324 1325 for (i = 0; i < adev->sdma.num_instances; i++) 1326 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1327 1328 amdgpu_sdma_destroy_inst_ctx(adev, true); 1329 1330 return 0; 1331 } 1332 1333 static int sdma_v5_2_hw_init(void *handle) 1334 { 1335 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1336 1337 return sdma_v5_2_start(adev); 1338 } 1339 1340 static int sdma_v5_2_hw_fini(void *handle) 1341 { 1342 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1343 1344 if (amdgpu_sriov_vf(adev)) { 1345 /* disable the scheduler for SDMA */ 1346 amdgpu_sdma_unset_buffer_funcs_helper(adev); 1347 return 0; 1348 } 1349 1350 sdma_v5_2_ctx_switch_enable(adev, false); 1351 sdma_v5_2_enable(adev, false); 1352 1353 return 0; 1354 } 1355 1356 static int sdma_v5_2_suspend(void *handle) 1357 { 1358 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1359 1360 return sdma_v5_2_hw_fini(adev); 1361 } 1362 1363 static int sdma_v5_2_resume(void *handle) 1364 { 1365 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1366 1367 return sdma_v5_2_hw_init(adev); 1368 } 1369 1370 static bool sdma_v5_2_is_idle(void *handle) 1371 { 1372 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1373 u32 i; 1374 1375 for (i = 0; i < adev->sdma.num_instances; i++) { 1376 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1377 1378 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1379 return false; 1380 } 1381 1382 return true; 1383 } 1384 1385 static int sdma_v5_2_wait_for_idle(void *handle) 1386 { 1387 unsigned i; 1388 u32 sdma0, sdma1, sdma2, sdma3; 1389 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1390 1391 for (i = 0; i < adev->usec_timeout; i++) { 1392 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1393 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1394 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG)); 1395 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG)); 1396 1397 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK) 1398 return 0; 1399 udelay(1); 1400 } 1401 return -ETIMEDOUT; 1402 } 1403 1404 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring) 1405 { 1406 int i, r = 0; 1407 struct amdgpu_device *adev = ring->adev; 1408 u32 index = 0; 1409 u64 sdma_gfx_preempt; 1410 1411 amdgpu_sdma_get_index_from_ring(ring, &index); 1412 sdma_gfx_preempt = 1413 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT); 1414 1415 /* assert preemption condition */ 1416 amdgpu_ring_set_preempt_cond_exec(ring, false); 1417 1418 /* emit the trailing fence */ 1419 ring->trail_seq += 1; 1420 amdgpu_ring_alloc(ring, 10); 1421 sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1422 ring->trail_seq, 0); 1423 amdgpu_ring_commit(ring); 1424 1425 /* assert IB preemption */ 1426 WREG32(sdma_gfx_preempt, 1); 1427 1428 /* poll the trailing fence */ 1429 for (i = 0; i < adev->usec_timeout; i++) { 1430 if (ring->trail_seq == 1431 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1432 break; 1433 udelay(1); 1434 } 1435 1436 if (i >= adev->usec_timeout) { 1437 r = -EINVAL; 1438 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1439 } 1440 1441 /* deassert IB preemption */ 1442 WREG32(sdma_gfx_preempt, 0); 1443 1444 /* deassert the preemption condition */ 1445 amdgpu_ring_set_preempt_cond_exec(ring, true); 1446 return r; 1447 } 1448 1449 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev, 1450 struct amdgpu_irq_src *source, 1451 unsigned type, 1452 enum amdgpu_interrupt_state state) 1453 { 1454 u32 sdma_cntl; 1455 u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL); 1456 1457 if (!amdgpu_sriov_vf(adev)) { 1458 sdma_cntl = RREG32(reg_offset); 1459 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1460 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1461 WREG32(reg_offset, sdma_cntl); 1462 } 1463 1464 return 0; 1465 } 1466 1467 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev, 1468 struct amdgpu_irq_src *source, 1469 struct amdgpu_iv_entry *entry) 1470 { 1471 uint32_t mes_queue_id = entry->src_data[0]; 1472 1473 DRM_DEBUG("IH: SDMA trap\n"); 1474 1475 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 1476 struct amdgpu_mes_queue *queue; 1477 1478 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 1479 1480 spin_lock(&adev->mes.queue_id_lock); 1481 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 1482 if (queue) { 1483 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); 1484 amdgpu_fence_process(queue->ring); 1485 } 1486 spin_unlock(&adev->mes.queue_id_lock); 1487 return 0; 1488 } 1489 1490 switch (entry->client_id) { 1491 case SOC15_IH_CLIENTID_SDMA0: 1492 switch (entry->ring_id) { 1493 case 0: 1494 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1495 break; 1496 case 1: 1497 /* XXX compute */ 1498 break; 1499 case 2: 1500 /* XXX compute */ 1501 break; 1502 case 3: 1503 /* XXX page queue*/ 1504 break; 1505 } 1506 break; 1507 case SOC15_IH_CLIENTID_SDMA1: 1508 switch (entry->ring_id) { 1509 case 0: 1510 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1511 break; 1512 case 1: 1513 /* XXX compute */ 1514 break; 1515 case 2: 1516 /* XXX compute */ 1517 break; 1518 case 3: 1519 /* XXX page queue*/ 1520 break; 1521 } 1522 break; 1523 case SOC15_IH_CLIENTID_SDMA2: 1524 switch (entry->ring_id) { 1525 case 0: 1526 amdgpu_fence_process(&adev->sdma.instance[2].ring); 1527 break; 1528 case 1: 1529 /* XXX compute */ 1530 break; 1531 case 2: 1532 /* XXX compute */ 1533 break; 1534 case 3: 1535 /* XXX page queue*/ 1536 break; 1537 } 1538 break; 1539 case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid: 1540 switch (entry->ring_id) { 1541 case 0: 1542 amdgpu_fence_process(&adev->sdma.instance[3].ring); 1543 break; 1544 case 1: 1545 /* XXX compute */ 1546 break; 1547 case 2: 1548 /* XXX compute */ 1549 break; 1550 case 3: 1551 /* XXX page queue*/ 1552 break; 1553 } 1554 break; 1555 } 1556 return 0; 1557 } 1558 1559 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev, 1560 struct amdgpu_irq_src *source, 1561 struct amdgpu_iv_entry *entry) 1562 { 1563 return 0; 1564 } 1565 1566 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev, 1567 bool enable) 1568 { 1569 uint32_t data, def; 1570 int i; 1571 1572 for (i = 0; i < adev->sdma.num_instances; i++) { 1573 1574 if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1)) 1575 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG; 1576 1577 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1578 /* Enable sdma clock gating */ 1579 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1580 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1581 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1582 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1583 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1584 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK | 1585 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK); 1586 if (def != data) 1587 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1588 } else { 1589 /* Disable sdma clock gating */ 1590 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1591 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1592 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1593 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1594 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1595 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK | 1596 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK); 1597 if (def != data) 1598 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1599 } 1600 } 1601 } 1602 1603 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev, 1604 bool enable) 1605 { 1606 uint32_t data, def; 1607 int i; 1608 1609 for (i = 0; i < adev->sdma.num_instances; i++) { 1610 1611 if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1)) 1612 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS; 1613 1614 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1615 /* Enable sdma mem light sleep */ 1616 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1617 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1618 if (def != data) 1619 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1620 1621 } else { 1622 /* Disable sdma mem light sleep */ 1623 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1624 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1625 if (def != data) 1626 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1627 1628 } 1629 } 1630 } 1631 1632 static int sdma_v5_2_set_clockgating_state(void *handle, 1633 enum amd_clockgating_state state) 1634 { 1635 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1636 1637 if (amdgpu_sriov_vf(adev)) 1638 return 0; 1639 1640 switch (adev->ip_versions[SDMA0_HWIP][0]) { 1641 case IP_VERSION(5, 2, 0): 1642 case IP_VERSION(5, 2, 2): 1643 case IP_VERSION(5, 2, 1): 1644 case IP_VERSION(5, 2, 4): 1645 case IP_VERSION(5, 2, 5): 1646 case IP_VERSION(5, 2, 6): 1647 case IP_VERSION(5, 2, 3): 1648 sdma_v5_2_update_medium_grain_clock_gating(adev, 1649 state == AMD_CG_STATE_GATE); 1650 sdma_v5_2_update_medium_grain_light_sleep(adev, 1651 state == AMD_CG_STATE_GATE); 1652 break; 1653 default: 1654 break; 1655 } 1656 1657 return 0; 1658 } 1659 1660 static int sdma_v5_2_set_powergating_state(void *handle, 1661 enum amd_powergating_state state) 1662 { 1663 return 0; 1664 } 1665 1666 static void sdma_v5_2_get_clockgating_state(void *handle, u64 *flags) 1667 { 1668 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1669 int data; 1670 1671 if (amdgpu_sriov_vf(adev)) 1672 *flags = 0; 1673 1674 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1675 data = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL)); 1676 if (!(data & SDMA0_CLK_CTRL__CGCG_EN_OVERRIDE_MASK)) 1677 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1678 1679 /* AMD_CG_SUPPORT_SDMA_LS */ 1680 data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); 1681 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1682 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1683 } 1684 1685 const struct amd_ip_funcs sdma_v5_2_ip_funcs = { 1686 .name = "sdma_v5_2", 1687 .early_init = sdma_v5_2_early_init, 1688 .late_init = NULL, 1689 .sw_init = sdma_v5_2_sw_init, 1690 .sw_fini = sdma_v5_2_sw_fini, 1691 .hw_init = sdma_v5_2_hw_init, 1692 .hw_fini = sdma_v5_2_hw_fini, 1693 .suspend = sdma_v5_2_suspend, 1694 .resume = sdma_v5_2_resume, 1695 .is_idle = sdma_v5_2_is_idle, 1696 .wait_for_idle = sdma_v5_2_wait_for_idle, 1697 .soft_reset = sdma_v5_2_soft_reset, 1698 .set_clockgating_state = sdma_v5_2_set_clockgating_state, 1699 .set_powergating_state = sdma_v5_2_set_powergating_state, 1700 .get_clockgating_state = sdma_v5_2_get_clockgating_state, 1701 }; 1702 1703 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = { 1704 .type = AMDGPU_RING_TYPE_SDMA, 1705 .align_mask = 0xf, 1706 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1707 .support_64bit_ptrs = true, 1708 .secure_submission_supported = true, 1709 .vmhub = AMDGPU_GFXHUB_0, 1710 .get_rptr = sdma_v5_2_ring_get_rptr, 1711 .get_wptr = sdma_v5_2_ring_get_wptr, 1712 .set_wptr = sdma_v5_2_ring_set_wptr, 1713 .emit_frame_size = 1714 5 + /* sdma_v5_2_ring_init_cond_exec */ 1715 6 + /* sdma_v5_2_ring_emit_hdp_flush */ 1716 3 + /* hdp_invalidate */ 1717 6 + /* sdma_v5_2_ring_emit_pipeline_sync */ 1718 /* sdma_v5_2_ring_emit_vm_flush */ 1719 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1720 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1721 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */ 1722 .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */ 1723 .emit_ib = sdma_v5_2_ring_emit_ib, 1724 .emit_mem_sync = sdma_v5_2_ring_emit_mem_sync, 1725 .emit_fence = sdma_v5_2_ring_emit_fence, 1726 .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync, 1727 .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush, 1728 .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush, 1729 .test_ring = sdma_v5_2_ring_test_ring, 1730 .test_ib = sdma_v5_2_ring_test_ib, 1731 .insert_nop = sdma_v5_2_ring_insert_nop, 1732 .pad_ib = sdma_v5_2_ring_pad_ib, 1733 .emit_wreg = sdma_v5_2_ring_emit_wreg, 1734 .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait, 1735 .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait, 1736 .init_cond_exec = sdma_v5_2_ring_init_cond_exec, 1737 .patch_cond_exec = sdma_v5_2_ring_patch_cond_exec, 1738 .preempt_ib = sdma_v5_2_ring_preempt_ib, 1739 }; 1740 1741 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev) 1742 { 1743 int i; 1744 1745 for (i = 0; i < adev->sdma.num_instances; i++) { 1746 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs; 1747 adev->sdma.instance[i].ring.me = i; 1748 } 1749 } 1750 1751 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = { 1752 .set = sdma_v5_2_set_trap_irq_state, 1753 .process = sdma_v5_2_process_trap_irq, 1754 }; 1755 1756 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = { 1757 .process = sdma_v5_2_process_illegal_inst_irq, 1758 }; 1759 1760 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev) 1761 { 1762 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1763 adev->sdma.num_instances; 1764 adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs; 1765 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs; 1766 } 1767 1768 /** 1769 * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine 1770 * 1771 * @ib: indirect buffer to copy to 1772 * @src_offset: src GPU address 1773 * @dst_offset: dst GPU address 1774 * @byte_count: number of bytes to xfer 1775 * @tmz: if a secure copy should be used 1776 * 1777 * Copy GPU buffers using the DMA engine. 1778 * Used by the amdgpu ttm implementation to move pages if 1779 * registered as the asic copy callback. 1780 */ 1781 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib, 1782 uint64_t src_offset, 1783 uint64_t dst_offset, 1784 uint32_t byte_count, 1785 bool tmz) 1786 { 1787 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1788 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1789 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 1790 ib->ptr[ib->length_dw++] = byte_count - 1; 1791 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1792 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1793 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1794 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1795 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1796 } 1797 1798 /** 1799 * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine 1800 * 1801 * @ib: indirect buffer to fill 1802 * @src_data: value to write to buffer 1803 * @dst_offset: dst GPU address 1804 * @byte_count: number of bytes to xfer 1805 * 1806 * Fill GPU buffers using the DMA engine. 1807 */ 1808 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib, 1809 uint32_t src_data, 1810 uint64_t dst_offset, 1811 uint32_t byte_count) 1812 { 1813 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1814 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1815 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1816 ib->ptr[ib->length_dw++] = src_data; 1817 ib->ptr[ib->length_dw++] = byte_count - 1; 1818 } 1819 1820 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = { 1821 .copy_max_bytes = 0x400000, 1822 .copy_num_dw = 7, 1823 .emit_copy_buffer = sdma_v5_2_emit_copy_buffer, 1824 1825 .fill_max_bytes = 0x400000, 1826 .fill_num_dw = 5, 1827 .emit_fill_buffer = sdma_v5_2_emit_fill_buffer, 1828 }; 1829 1830 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev) 1831 { 1832 if (adev->mman.buffer_funcs == NULL) { 1833 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs; 1834 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1835 } 1836 } 1837 1838 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = { 1839 .copy_pte_num_dw = 7, 1840 .copy_pte = sdma_v5_2_vm_copy_pte, 1841 .write_pte = sdma_v5_2_vm_write_pte, 1842 .set_pte_pde = sdma_v5_2_vm_set_pte_pde, 1843 }; 1844 1845 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev) 1846 { 1847 unsigned i; 1848 1849 if (adev->vm_manager.vm_pte_funcs == NULL) { 1850 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs; 1851 for (i = 0; i < adev->sdma.num_instances; i++) { 1852 adev->vm_manager.vm_pte_scheds[i] = 1853 &adev->sdma.instance[i].ring.sched; 1854 } 1855 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1856 } 1857 } 1858 1859 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = { 1860 .type = AMD_IP_BLOCK_TYPE_SDMA, 1861 .major = 5, 1862 .minor = 2, 1863 .rev = 0, 1864 .funcs = &sdma_v5_2_ip_funcs, 1865 }; 1866