1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_10_1_0_offset.h" 34 #include "gc/gc_10_1_0_sh_mask.h" 35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h" 36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h" 37 38 #include "soc15_common.h" 39 #include "soc15.h" 40 #include "navi10_sdma_pkt_open.h" 41 #include "nbio_v2_3.h" 42 #include "sdma_common.h" 43 #include "sdma_v5_0.h" 44 45 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin"); 46 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin"); 47 48 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin"); 49 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin"); 50 51 MODULE_FIRMWARE("amdgpu/navi12_sdma.bin"); 52 MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin"); 53 54 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma.bin"); 55 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma1.bin"); 56 57 #define SDMA1_REG_OFFSET 0x600 58 #define SDMA0_HYP_DEC_REG_START 0x5880 59 #define SDMA0_HYP_DEC_REG_END 0x5893 60 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 61 62 static const struct amdgpu_hwip_reg_entry sdma_reg_list_5_0[] = { 63 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG), 64 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG), 65 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG), 66 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG), 67 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UCODE_CHECKSUM), 68 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH_HI), 69 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH), 70 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_STATUS), 71 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_STATUS), 72 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK0), 73 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK1), 74 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK0), 75 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK1), 76 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_CNTL), 77 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR), 78 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR_HI), 79 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR), 80 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR_HI), 81 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_OFFSET), 82 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_LO), 83 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_HI), 84 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_CNTL), 85 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_RPTR), 86 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_SUB_REMAIN), 87 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_DUMMY_REG), 88 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_CNTL), 89 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR), 90 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR_HI), 91 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR), 92 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR_HI), 93 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_OFFSET), 94 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_LO), 95 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_HI), 96 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_DUMMY_REG), 97 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_CNTL), 98 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR), 99 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR_HI), 100 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR), 101 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR_HI), 102 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_OFFSET), 103 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_LO), 104 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_HI), 105 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_DUMMY_REG), 106 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_INT_STATUS), 107 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_VM_CNTL), 108 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2) 109 }; 110 111 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev); 112 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev); 113 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev); 114 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev); 115 116 static const struct soc15_reg_golden golden_settings_sdma_5[] = { 117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), 118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00), 129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), 130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00) 141 }; 142 143 static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = { 144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 164 }; 165 166 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = { 167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 169 }; 170 171 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = { 172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 174 }; 175 176 static const struct soc15_reg_golden golden_settings_sdma_nv12[] = { 177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044), 179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044), 180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044), 181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044), 182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 183 }; 184 185 static const struct soc15_reg_golden golden_settings_sdma_cyan_skillfish[] = { 186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), 187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044), 188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044), 189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x007fffff, 0x004c5c00), 200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), 201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044), 202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044), 203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x007fffff, 0x004c5c00) 214 }; 215 216 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 217 { 218 u32 base; 219 220 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 221 internal_offset <= SDMA0_HYP_DEC_REG_END) { 222 base = adev->reg_offset[GC_HWIP][0][1]; 223 if (instance == 1) 224 internal_offset += SDMA1_HYP_DEC_REG_OFFSET; 225 } else { 226 base = adev->reg_offset[GC_HWIP][0][0]; 227 if (instance == 1) 228 internal_offset += SDMA1_REG_OFFSET; 229 } 230 231 return base + internal_offset; 232 } 233 234 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev) 235 { 236 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 237 case IP_VERSION(5, 0, 0): 238 soc15_program_register_sequence(adev, 239 golden_settings_sdma_5, 240 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 241 soc15_program_register_sequence(adev, 242 golden_settings_sdma_nv10, 243 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10)); 244 break; 245 case IP_VERSION(5, 0, 2): 246 soc15_program_register_sequence(adev, 247 golden_settings_sdma_5, 248 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 249 soc15_program_register_sequence(adev, 250 golden_settings_sdma_nv14, 251 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14)); 252 break; 253 case IP_VERSION(5, 0, 5): 254 if (amdgpu_sriov_vf(adev)) 255 soc15_program_register_sequence(adev, 256 golden_settings_sdma_5_sriov, 257 (const u32)ARRAY_SIZE(golden_settings_sdma_5_sriov)); 258 else 259 soc15_program_register_sequence(adev, 260 golden_settings_sdma_5, 261 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 262 soc15_program_register_sequence(adev, 263 golden_settings_sdma_nv12, 264 (const u32)ARRAY_SIZE(golden_settings_sdma_nv12)); 265 break; 266 case IP_VERSION(5, 0, 1): 267 soc15_program_register_sequence(adev, 268 golden_settings_sdma_cyan_skillfish, 269 (const u32)ARRAY_SIZE(golden_settings_sdma_cyan_skillfish)); 270 break; 271 default: 272 break; 273 } 274 } 275 276 /** 277 * sdma_v5_0_init_microcode - load ucode images from disk 278 * 279 * @adev: amdgpu_device pointer 280 * 281 * Use the firmware interface to load the ucode images into 282 * the driver (not loaded into hw). 283 * Returns 0 on success, error on failure. 284 */ 285 286 // emulation only, won't work on real chip 287 // navi10 real chip need to use PSP to load firmware 288 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev) 289 { 290 int ret, i; 291 292 for (i = 0; i < adev->sdma.num_instances; i++) { 293 ret = amdgpu_sdma_init_microcode(adev, i, false); 294 if (ret) 295 return ret; 296 } 297 298 return ret; 299 } 300 301 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring, 302 uint64_t addr) 303 { 304 unsigned ret; 305 306 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); 307 amdgpu_ring_write(ring, lower_32_bits(addr)); 308 amdgpu_ring_write(ring, upper_32_bits(addr)); 309 amdgpu_ring_write(ring, 1); 310 /* this is the offset we need patch later */ 311 ret = ring->wptr & ring->buf_mask; 312 /* insert dummy here and patch it later */ 313 amdgpu_ring_write(ring, 0); 314 315 return ret; 316 } 317 318 /** 319 * sdma_v5_0_ring_get_rptr - get the current read pointer 320 * 321 * @ring: amdgpu ring pointer 322 * 323 * Get the current rptr from the hardware (NAVI10+). 324 */ 325 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring) 326 { 327 u64 *rptr; 328 329 /* XXX check if swapping is necessary on BE */ 330 rptr = (u64 *)ring->rptr_cpu_addr; 331 332 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 333 return ((*rptr) >> 2); 334 } 335 336 /** 337 * sdma_v5_0_ring_get_wptr - get the current write pointer 338 * 339 * @ring: amdgpu ring pointer 340 * 341 * Get the current wptr from the hardware (NAVI10+). 342 */ 343 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring) 344 { 345 struct amdgpu_device *adev = ring->adev; 346 u64 wptr; 347 348 if (ring->use_doorbell) { 349 /* XXX check if swapping is necessary on BE */ 350 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 351 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 352 } else { 353 wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); 354 wptr = wptr << 32; 355 wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); 356 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr); 357 } 358 359 return wptr >> 2; 360 } 361 362 /** 363 * sdma_v5_0_ring_set_wptr - commit the write pointer 364 * 365 * @ring: amdgpu ring pointer 366 * 367 * Write the wptr back to the hardware (NAVI10+). 368 */ 369 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring) 370 { 371 struct amdgpu_device *adev = ring->adev; 372 373 DRM_DEBUG("Setting write pointer\n"); 374 if (ring->use_doorbell) { 375 DRM_DEBUG("Using doorbell -- " 376 "wptr_offs == 0x%08x " 377 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 378 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 379 ring->wptr_offs, 380 lower_32_bits(ring->wptr << 2), 381 upper_32_bits(ring->wptr << 2)); 382 /* XXX check if swapping is necessary on BE */ 383 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 384 ring->wptr << 2); 385 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 386 ring->doorbell_index, ring->wptr << 2); 387 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 388 } else { 389 DRM_DEBUG("Not using doorbell -- " 390 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 391 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 392 ring->me, 393 lower_32_bits(ring->wptr << 2), 394 ring->me, 395 upper_32_bits(ring->wptr << 2)); 396 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, 397 ring->me, mmSDMA0_GFX_RB_WPTR), 398 lower_32_bits(ring->wptr << 2)); 399 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, 400 ring->me, mmSDMA0_GFX_RB_WPTR_HI), 401 upper_32_bits(ring->wptr << 2)); 402 } 403 } 404 405 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 406 { 407 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 408 int i; 409 410 for (i = 0; i < count; i++) 411 if (sdma && sdma->burst_nop && (i == 0)) 412 amdgpu_ring_write(ring, ring->funcs->nop | 413 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 414 else 415 amdgpu_ring_write(ring, ring->funcs->nop); 416 } 417 418 /** 419 * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine 420 * 421 * @ring: amdgpu ring pointer 422 * @job: job to retrieve vmid from 423 * @ib: IB object to schedule 424 * @flags: unused 425 * 426 * Schedule an IB in the DMA ring (NAVI10). 427 */ 428 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 429 struct amdgpu_job *job, 430 struct amdgpu_ib *ib, 431 uint32_t flags) 432 { 433 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 434 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 435 436 /* An IB packet must end on a 8 DW boundary--the next dword 437 * must be on a 8-dword boundary. Our IB packet below is 6 438 * dwords long, thus add x number of NOPs, such that, in 439 * modular arithmetic, 440 * wptr + 6 + x = 8k, k >= 0, which in C is, 441 * (wptr + 6 + x) % 8 = 0. 442 * The expression below, is a solution of x. 443 */ 444 sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 445 446 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 447 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 448 /* base must be 32 byte aligned */ 449 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 450 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 451 amdgpu_ring_write(ring, ib->length_dw); 452 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 453 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 454 } 455 456 /** 457 * sdma_v5_0_ring_emit_mem_sync - flush the IB by graphics cache rinse 458 * 459 * @ring: amdgpu ring pointer 460 * 461 * flush the IB by graphics cache rinse. 462 */ 463 static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring) 464 { 465 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV | 466 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 467 SDMA_GCR_GLI_INV(1); 468 469 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 470 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ)); 471 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 472 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 473 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 474 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 475 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 476 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 477 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 478 } 479 480 /** 481 * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 482 * 483 * @ring: amdgpu ring pointer 484 * 485 * Emit an hdp flush packet on the requested DMA ring. 486 */ 487 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 488 { 489 struct amdgpu_device *adev = ring->adev; 490 u32 ref_and_mask = 0; 491 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 492 493 if (ring->me == 0) 494 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; 495 else 496 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; 497 498 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 499 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 500 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 501 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 502 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 503 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 504 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 505 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 506 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 507 } 508 509 /** 510 * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring 511 * 512 * @ring: amdgpu ring pointer 513 * @addr: address 514 * @seq: sequence number 515 * @flags: fence related flags 516 * 517 * Add a DMA fence packet to the ring to write 518 * the fence seq number and DMA trap packet to generate 519 * an interrupt if needed (NAVI10). 520 */ 521 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 522 unsigned flags) 523 { 524 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 525 /* write the fence */ 526 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 527 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 528 /* zero in first two bits */ 529 BUG_ON(addr & 0x3); 530 amdgpu_ring_write(ring, lower_32_bits(addr)); 531 amdgpu_ring_write(ring, upper_32_bits(addr)); 532 amdgpu_ring_write(ring, lower_32_bits(seq)); 533 534 /* optionally write high bits as well */ 535 if (write64bit) { 536 addr += 4; 537 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 538 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 539 /* zero in first two bits */ 540 BUG_ON(addr & 0x3); 541 amdgpu_ring_write(ring, lower_32_bits(addr)); 542 amdgpu_ring_write(ring, upper_32_bits(addr)); 543 amdgpu_ring_write(ring, upper_32_bits(seq)); 544 } 545 546 if (flags & AMDGPU_FENCE_FLAG_INT) { 547 /* generate an interrupt */ 548 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 549 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 550 } 551 } 552 553 554 /** 555 * sdma_v5_0_gfx_stop - stop the gfx async dma engines 556 * 557 * @adev: amdgpu_device pointer 558 * 559 * Stop the gfx async dma ring buffers (NAVI10). 560 */ 561 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev) 562 { 563 u32 rb_cntl, ib_cntl; 564 int i; 565 566 for (i = 0; i < adev->sdma.num_instances; i++) { 567 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 568 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 569 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 570 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 571 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 572 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 573 } 574 } 575 576 /** 577 * sdma_v5_0_rlc_stop - stop the compute async dma engines 578 * 579 * @adev: amdgpu_device pointer 580 * 581 * Stop the compute async dma queues (NAVI10). 582 */ 583 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev) 584 { 585 /* XXX todo */ 586 } 587 588 /** 589 * sdma_v5_0_ctx_switch_enable - stop the async dma engines context switch 590 * 591 * @adev: amdgpu_device pointer 592 * @enable: enable/disable the DMA MEs context switch. 593 * 594 * Halt or unhalt the async dma engines context switch (NAVI10). 595 */ 596 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 597 { 598 u32 f32_cntl = 0, phase_quantum = 0; 599 int i; 600 601 if (amdgpu_sdma_phase_quantum) { 602 unsigned value = amdgpu_sdma_phase_quantum; 603 unsigned unit = 0; 604 605 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 606 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 607 value = (value + 1) >> 1; 608 unit++; 609 } 610 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 611 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 612 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 613 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 614 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 615 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 616 WARN_ONCE(1, 617 "clamping sdma_phase_quantum to %uK clock cycles\n", 618 value << unit); 619 } 620 phase_quantum = 621 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 622 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 623 } 624 625 for (i = 0; i < adev->sdma.num_instances; i++) { 626 if (!amdgpu_sriov_vf(adev)) { 627 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 628 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 629 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 630 } 631 632 if (enable && amdgpu_sdma_phase_quantum) { 633 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 634 phase_quantum); 635 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 636 phase_quantum); 637 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 638 phase_quantum); 639 } 640 if (!amdgpu_sriov_vf(adev)) 641 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 642 } 643 644 } 645 646 /** 647 * sdma_v5_0_enable - stop the async dma engines 648 * 649 * @adev: amdgpu_device pointer 650 * @enable: enable/disable the DMA MEs. 651 * 652 * Halt or unhalt the async dma engines (NAVI10). 653 */ 654 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable) 655 { 656 u32 f32_cntl; 657 int i; 658 659 if (!enable) { 660 sdma_v5_0_gfx_stop(adev); 661 sdma_v5_0_rlc_stop(adev); 662 } 663 664 if (amdgpu_sriov_vf(adev)) 665 return; 666 667 for (i = 0; i < adev->sdma.num_instances; i++) { 668 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 669 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 670 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 671 } 672 } 673 674 /** 675 * sdma_v5_0_gfx_resume_instance - start/restart a certain sdma engine 676 * 677 * @adev: amdgpu_device pointer 678 * @i: instance 679 * @restore: used to restore wptr when restart 680 * 681 * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr. 682 * Return 0 for success. 683 */ 684 static int sdma_v5_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore) 685 { 686 struct amdgpu_ring *ring; 687 u32 rb_cntl, ib_cntl; 688 u32 rb_bufsz; 689 u32 doorbell; 690 u32 doorbell_offset; 691 u32 temp; 692 u32 wptr_poll_cntl; 693 u64 wptr_gpu_addr; 694 695 ring = &adev->sdma.instance[i].ring; 696 697 if (!amdgpu_sriov_vf(adev)) 698 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 699 700 /* Set ring buffer size in dwords */ 701 rb_bufsz = order_base_2(ring->ring_size / 4); 702 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 703 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 704 #ifdef __BIG_ENDIAN 705 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 706 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 707 RPTR_WRITEBACK_SWAP_ENABLE, 1); 708 #endif 709 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 710 711 /* Initialize the ring buffer's read and write pointers */ 712 if (restore) { 713 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), lower_32_bits(ring->wptr << 2)); 714 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring->wptr << 2)); 715 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); 716 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); 717 } else { 718 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 719 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 720 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 721 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 722 } 723 /* setup the wptr shadow polling */ 724 wptr_gpu_addr = ring->wptr_gpu_addr; 725 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 726 lower_32_bits(wptr_gpu_addr)); 727 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 728 upper_32_bits(wptr_gpu_addr)); 729 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, 730 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 731 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 732 SDMA0_GFX_RB_WPTR_POLL_CNTL, 733 F32_POLL_ENABLE, 1); 734 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 735 wptr_poll_cntl); 736 737 /* set the wb address whether it's enabled or not */ 738 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 739 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 740 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 741 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 742 743 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 744 745 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), 746 ring->gpu_addr >> 8); 747 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), 748 ring->gpu_addr >> 40); 749 750 if (!restore) 751 ring->wptr = 0; 752 753 /* before programing wptr to a less value, need set minor_ptr_update first */ 754 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 755 756 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 757 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 758 lower_32_bits(ring->wptr << 2)); 759 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 760 upper_32_bits(ring->wptr << 2)); 761 } 762 763 doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 764 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, 765 mmSDMA0_GFX_DOORBELL_OFFSET)); 766 767 if (ring->use_doorbell) { 768 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 769 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 770 OFFSET, ring->doorbell_index); 771 } else { 772 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 773 } 774 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 775 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), 776 doorbell_offset); 777 778 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 779 ring->doorbell_index, 20); 780 781 if (amdgpu_sriov_vf(adev)) 782 sdma_v5_0_ring_set_wptr(ring); 783 784 /* set minor_ptr_update to 0 after wptr programed */ 785 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 786 787 if (!amdgpu_sriov_vf(adev)) { 788 /* set utc l1 enable flag always to 1 */ 789 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 790 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 791 792 /* enable MCBP */ 793 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); 794 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 795 796 /* Set up RESP_MODE to non-copy addresses */ 797 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); 798 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 799 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 800 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); 801 802 /* program default cache read and write policy */ 803 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); 804 /* clean read policy and write policy bits */ 805 temp &= 0xFF0FFF; 806 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14)); 807 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); 808 } 809 810 if (!amdgpu_sriov_vf(adev)) { 811 /* unhalt engine */ 812 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 813 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 814 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 815 } 816 817 /* enable DMA RB */ 818 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 819 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 820 821 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 822 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 823 #ifdef __BIG_ENDIAN 824 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 825 #endif 826 /* enable DMA IBs */ 827 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 828 829 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 830 sdma_v5_0_ctx_switch_enable(adev, true); 831 sdma_v5_0_enable(adev, true); 832 } 833 834 return amdgpu_ring_test_helper(ring); 835 } 836 837 /** 838 * sdma_v5_0_gfx_resume - setup and start the async dma engines 839 * 840 * @adev: amdgpu_device pointer 841 * 842 * Set up the gfx DMA ring buffers and enable them (NAVI10). 843 * Returns 0 for success, error for failure. 844 */ 845 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev) 846 { 847 int i, r; 848 849 for (i = 0; i < adev->sdma.num_instances; i++) { 850 r = sdma_v5_0_gfx_resume_instance(adev, i, false); 851 if (r) 852 return r; 853 } 854 855 return 0; 856 } 857 858 /** 859 * sdma_v5_0_rlc_resume - setup and start the async dma engines 860 * 861 * @adev: amdgpu_device pointer 862 * 863 * Set up the compute DMA queues and enable them (NAVI10). 864 * Returns 0 for success, error for failure. 865 */ 866 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev) 867 { 868 return 0; 869 } 870 871 /** 872 * sdma_v5_0_load_microcode - load the sDMA ME ucode 873 * 874 * @adev: amdgpu_device pointer 875 * 876 * Loads the sDMA0/1 ucode. 877 * Returns 0 for success, -EINVAL if the ucode is not available. 878 */ 879 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev) 880 { 881 const struct sdma_firmware_header_v1_0 *hdr; 882 const __le32 *fw_data; 883 u32 fw_size; 884 int i, j; 885 886 /* halt the MEs */ 887 sdma_v5_0_enable(adev, false); 888 889 for (i = 0; i < adev->sdma.num_instances; i++) { 890 if (!adev->sdma.instance[i].fw) 891 return -EINVAL; 892 893 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 894 amdgpu_ucode_print_sdma_hdr(&hdr->header); 895 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 896 897 fw_data = (const __le32 *) 898 (adev->sdma.instance[i].fw->data + 899 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 900 901 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 902 903 for (j = 0; j < fw_size; j++) { 904 if (amdgpu_emu_mode == 1 && j % 500 == 0) 905 msleep(1); 906 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 907 } 908 909 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 910 } 911 912 return 0; 913 } 914 915 /** 916 * sdma_v5_0_start - setup and start the async dma engines 917 * 918 * @adev: amdgpu_device pointer 919 * 920 * Set up the DMA engines and enable them (NAVI10). 921 * Returns 0 for success, error for failure. 922 */ 923 static int sdma_v5_0_start(struct amdgpu_device *adev) 924 { 925 int r = 0; 926 927 if (amdgpu_sriov_vf(adev)) { 928 sdma_v5_0_ctx_switch_enable(adev, false); 929 sdma_v5_0_enable(adev, false); 930 931 /* set RB registers */ 932 r = sdma_v5_0_gfx_resume(adev); 933 return r; 934 } 935 936 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 937 r = sdma_v5_0_load_microcode(adev); 938 if (r) 939 return r; 940 } 941 942 /* unhalt the MEs */ 943 sdma_v5_0_enable(adev, true); 944 /* enable sdma ring preemption */ 945 sdma_v5_0_ctx_switch_enable(adev, true); 946 947 /* start the gfx rings and rlc compute queues */ 948 r = sdma_v5_0_gfx_resume(adev); 949 if (r) 950 return r; 951 r = sdma_v5_0_rlc_resume(adev); 952 953 return r; 954 } 955 956 static int sdma_v5_0_mqd_init(struct amdgpu_device *adev, void *mqd, 957 struct amdgpu_mqd_prop *prop) 958 { 959 struct v10_sdma_mqd *m = mqd; 960 uint64_t wb_gpu_addr; 961 962 m->sdmax_rlcx_rb_cntl = 963 order_base_2(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 964 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 965 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | 966 1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT; 967 968 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8); 969 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); 970 971 m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0, 972 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 973 974 wb_gpu_addr = prop->wptr_gpu_addr; 975 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); 976 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); 977 978 wb_gpu_addr = prop->rptr_gpu_addr; 979 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); 980 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); 981 982 m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0, 983 mmSDMA0_GFX_IB_CNTL)); 984 985 m->sdmax_rlcx_doorbell_offset = 986 prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 987 988 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1); 989 990 return 0; 991 } 992 993 static void sdma_v5_0_set_mqd_funcs(struct amdgpu_device *adev) 994 { 995 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v10_sdma_mqd); 996 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v5_0_mqd_init; 997 } 998 999 /** 1000 * sdma_v5_0_ring_test_ring - simple async dma engine test 1001 * 1002 * @ring: amdgpu_ring structure holding ring information 1003 * 1004 * Test the DMA engine by writing using it to write an 1005 * value to memory. (NAVI10). 1006 * Returns 0 for success, error for failure. 1007 */ 1008 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring) 1009 { 1010 struct amdgpu_device *adev = ring->adev; 1011 unsigned i; 1012 unsigned index; 1013 int r; 1014 u32 tmp; 1015 u64 gpu_addr; 1016 1017 tmp = 0xCAFEDEAD; 1018 1019 r = amdgpu_device_wb_get(adev, &index); 1020 if (r) { 1021 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 1022 return r; 1023 } 1024 1025 gpu_addr = adev->wb.gpu_addr + (index * 4); 1026 adev->wb.wb[index] = cpu_to_le32(tmp); 1027 1028 r = amdgpu_ring_alloc(ring, 20); 1029 if (r) { 1030 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 1031 amdgpu_device_wb_free(adev, index); 1032 return r; 1033 } 1034 1035 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1036 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1037 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1038 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1039 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1040 amdgpu_ring_write(ring, 0xDEADBEEF); 1041 amdgpu_ring_commit(ring); 1042 1043 for (i = 0; i < adev->usec_timeout; i++) { 1044 tmp = le32_to_cpu(adev->wb.wb[index]); 1045 if (tmp == 0xDEADBEEF) 1046 break; 1047 if (amdgpu_emu_mode == 1) 1048 msleep(1); 1049 else 1050 udelay(1); 1051 } 1052 1053 if (i >= adev->usec_timeout) 1054 r = -ETIMEDOUT; 1055 1056 amdgpu_device_wb_free(adev, index); 1057 1058 return r; 1059 } 1060 1061 /** 1062 * sdma_v5_0_ring_test_ib - test an IB on the DMA engine 1063 * 1064 * @ring: amdgpu_ring structure holding ring information 1065 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1066 * 1067 * Test a simple IB in the DMA ring (NAVI10). 1068 * Returns 0 on success, error on failure. 1069 */ 1070 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1071 { 1072 struct amdgpu_device *adev = ring->adev; 1073 struct amdgpu_ib ib; 1074 struct dma_fence *f = NULL; 1075 unsigned index; 1076 long r; 1077 u32 tmp = 0; 1078 u64 gpu_addr; 1079 1080 tmp = 0xCAFEDEAD; 1081 memset(&ib, 0, sizeof(ib)); 1082 1083 r = amdgpu_device_wb_get(adev, &index); 1084 if (r) { 1085 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 1086 return r; 1087 } 1088 1089 gpu_addr = adev->wb.gpu_addr + (index * 4); 1090 adev->wb.wb[index] = cpu_to_le32(tmp); 1091 1092 r = amdgpu_ib_get(adev, NULL, 256, 1093 AMDGPU_IB_POOL_DIRECT, &ib); 1094 if (r) { 1095 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 1096 goto err0; 1097 } 1098 1099 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1100 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1101 ib.ptr[1] = lower_32_bits(gpu_addr); 1102 ib.ptr[2] = upper_32_bits(gpu_addr); 1103 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1104 ib.ptr[4] = 0xDEADBEEF; 1105 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1106 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1107 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1108 ib.length_dw = 8; 1109 1110 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1111 if (r) 1112 goto err1; 1113 1114 r = dma_fence_wait_timeout(f, false, timeout); 1115 if (r == 0) { 1116 DRM_ERROR("amdgpu: IB test timed out\n"); 1117 r = -ETIMEDOUT; 1118 goto err1; 1119 } else if (r < 0) { 1120 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1121 goto err1; 1122 } 1123 1124 tmp = le32_to_cpu(adev->wb.wb[index]); 1125 1126 if (tmp == 0xDEADBEEF) 1127 r = 0; 1128 else 1129 r = -EINVAL; 1130 1131 err1: 1132 amdgpu_ib_free(&ib, NULL); 1133 dma_fence_put(f); 1134 err0: 1135 amdgpu_device_wb_free(adev, index); 1136 return r; 1137 } 1138 1139 1140 /** 1141 * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART 1142 * 1143 * @ib: indirect buffer to fill with commands 1144 * @pe: addr of the page entry 1145 * @src: src addr to copy from 1146 * @count: number of page entries to update 1147 * 1148 * Update PTEs by copying them from the GART using sDMA (NAVI10). 1149 */ 1150 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib, 1151 uint64_t pe, uint64_t src, 1152 unsigned count) 1153 { 1154 unsigned bytes = count * 8; 1155 1156 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1157 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1158 ib->ptr[ib->length_dw++] = bytes - 1; 1159 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1160 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1161 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1162 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1163 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1164 1165 } 1166 1167 /** 1168 * sdma_v5_0_vm_write_pte - update PTEs by writing them manually 1169 * 1170 * @ib: indirect buffer to fill with commands 1171 * @pe: addr of the page entry 1172 * @value: dst addr to write into pe 1173 * @count: number of page entries to update 1174 * @incr: increase next addr by incr bytes 1175 * 1176 * Update PTEs by writing them manually using sDMA (NAVI10). 1177 */ 1178 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1179 uint64_t value, unsigned count, 1180 uint32_t incr) 1181 { 1182 unsigned ndw = count * 2; 1183 1184 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1185 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1186 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1187 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1188 ib->ptr[ib->length_dw++] = ndw - 1; 1189 for (; ndw > 0; ndw -= 2) { 1190 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1191 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1192 value += incr; 1193 } 1194 } 1195 1196 /** 1197 * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA 1198 * 1199 * @ib: indirect buffer to fill with commands 1200 * @pe: addr of the page entry 1201 * @addr: dst addr to write into pe 1202 * @count: number of page entries to update 1203 * @incr: increase next addr by incr bytes 1204 * @flags: access flags 1205 * 1206 * Update the page tables using sDMA (NAVI10). 1207 */ 1208 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1209 uint64_t pe, 1210 uint64_t addr, unsigned count, 1211 uint32_t incr, uint64_t flags) 1212 { 1213 /* for physically contiguous pages (vram) */ 1214 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1215 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1216 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1217 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1218 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1219 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1220 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1221 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1222 ib->ptr[ib->length_dw++] = 0; 1223 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1224 } 1225 1226 /** 1227 * sdma_v5_0_ring_pad_ib - pad the IB 1228 * @ring: amdgpu_ring structure holding ring information 1229 * @ib: indirect buffer to fill with padding 1230 * 1231 * Pad the IB with NOPs to a boundary multiple of 8. 1232 */ 1233 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1234 { 1235 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1236 u32 pad_count; 1237 int i; 1238 1239 pad_count = (-ib->length_dw) & 0x7; 1240 for (i = 0; i < pad_count; i++) 1241 if (sdma && sdma->burst_nop && (i == 0)) 1242 ib->ptr[ib->length_dw++] = 1243 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1244 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1245 else 1246 ib->ptr[ib->length_dw++] = 1247 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1248 } 1249 1250 1251 /** 1252 * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline 1253 * 1254 * @ring: amdgpu_ring pointer 1255 * 1256 * Make sure all previous operations are completed (CIK). 1257 */ 1258 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1259 { 1260 uint32_t seq = ring->fence_drv.sync_seq; 1261 uint64_t addr = ring->fence_drv.gpu_addr; 1262 1263 /* wait for idle */ 1264 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1265 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1266 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1267 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1268 amdgpu_ring_write(ring, addr & 0xfffffffc); 1269 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1270 amdgpu_ring_write(ring, seq); /* reference */ 1271 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1272 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1273 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1274 } 1275 1276 1277 /** 1278 * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA 1279 * 1280 * @ring: amdgpu_ring pointer 1281 * @vmid: vmid number to use 1282 * @pd_addr: address 1283 * 1284 * Update the page table base and flush the VM TLB 1285 * using sDMA (NAVI10). 1286 */ 1287 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1288 unsigned vmid, uint64_t pd_addr) 1289 { 1290 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1291 } 1292 1293 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring, 1294 uint32_t reg, uint32_t val) 1295 { 1296 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1297 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1298 amdgpu_ring_write(ring, reg); 1299 amdgpu_ring_write(ring, val); 1300 } 1301 1302 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1303 uint32_t val, uint32_t mask) 1304 { 1305 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1306 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1307 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1308 amdgpu_ring_write(ring, reg << 2); 1309 amdgpu_ring_write(ring, 0); 1310 amdgpu_ring_write(ring, val); /* reference */ 1311 amdgpu_ring_write(ring, mask); /* mask */ 1312 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1313 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1314 } 1315 1316 static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1317 uint32_t reg0, uint32_t reg1, 1318 uint32_t ref, uint32_t mask) 1319 { 1320 amdgpu_ring_emit_wreg(ring, reg0, ref); 1321 /* wait for a cycle to reset vm_inv_eng*_ack */ 1322 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1323 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1324 } 1325 1326 static int sdma_v5_0_early_init(struct amdgpu_ip_block *ip_block) 1327 { 1328 struct amdgpu_device *adev = ip_block->adev; 1329 int r; 1330 1331 r = sdma_v5_0_init_microcode(adev); 1332 if (r) 1333 return r; 1334 1335 sdma_v5_0_set_ring_funcs(adev); 1336 sdma_v5_0_set_buffer_funcs(adev); 1337 sdma_v5_0_set_vm_pte_funcs(adev); 1338 sdma_v5_0_set_irq_funcs(adev); 1339 sdma_v5_0_set_mqd_funcs(adev); 1340 1341 return 0; 1342 } 1343 1344 1345 static int sdma_v5_0_sw_init(struct amdgpu_ip_block *ip_block) 1346 { 1347 struct amdgpu_ring *ring; 1348 int r, i; 1349 struct amdgpu_device *adev = ip_block->adev; 1350 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_0); 1351 uint32_t *ptr; 1352 1353 /* SDMA trap event */ 1354 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, 1355 SDMA0_5_0__SRCID__SDMA_TRAP, 1356 &adev->sdma.trap_irq); 1357 if (r) 1358 return r; 1359 1360 /* SDMA trap event */ 1361 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, 1362 SDMA1_5_0__SRCID__SDMA_TRAP, 1363 &adev->sdma.trap_irq); 1364 if (r) 1365 return r; 1366 1367 for (i = 0; i < adev->sdma.num_instances; i++) { 1368 ring = &adev->sdma.instance[i].ring; 1369 ring->ring_obj = NULL; 1370 ring->use_doorbell = true; 1371 1372 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1373 ring->use_doorbell?"true":"false"); 1374 1375 ring->doorbell_index = (i == 0) ? 1376 (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset 1377 : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset 1378 1379 ring->vm_hub = AMDGPU_GFXHUB(0); 1380 sprintf(ring->name, "sdma%d", i); 1381 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1382 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 : 1383 AMDGPU_SDMA_IRQ_INSTANCE1, 1384 AMDGPU_RING_PRIO_DEFAULT, NULL); 1385 if (r) 1386 return r; 1387 } 1388 1389 adev->sdma.supported_reset = 1390 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); 1391 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1392 case IP_VERSION(5, 0, 0): 1393 case IP_VERSION(5, 0, 2): 1394 case IP_VERSION(5, 0, 5): 1395 if (adev->sdma.instance[0].fw_version >= 35) 1396 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1397 break; 1398 default: 1399 break; 1400 } 1401 1402 /* Allocate memory for SDMA IP Dump buffer */ 1403 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); 1404 if (ptr) 1405 adev->sdma.ip_dump = ptr; 1406 else 1407 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n"); 1408 1409 r = amdgpu_sdma_sysfs_reset_mask_init(adev); 1410 if (r) 1411 return r; 1412 1413 return r; 1414 } 1415 1416 static int sdma_v5_0_sw_fini(struct amdgpu_ip_block *ip_block) 1417 { 1418 struct amdgpu_device *adev = ip_block->adev; 1419 int i; 1420 1421 for (i = 0; i < adev->sdma.num_instances; i++) 1422 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1423 1424 amdgpu_sdma_sysfs_reset_mask_fini(adev); 1425 amdgpu_sdma_destroy_inst_ctx(adev, false); 1426 1427 kfree(adev->sdma.ip_dump); 1428 1429 return 0; 1430 } 1431 1432 static int sdma_v5_0_hw_init(struct amdgpu_ip_block *ip_block) 1433 { 1434 int r; 1435 struct amdgpu_device *adev = ip_block->adev; 1436 1437 sdma_v5_0_init_golden_registers(adev); 1438 1439 r = sdma_v5_0_start(adev); 1440 1441 return r; 1442 } 1443 1444 static int sdma_v5_0_hw_fini(struct amdgpu_ip_block *ip_block) 1445 { 1446 struct amdgpu_device *adev = ip_block->adev; 1447 1448 if (amdgpu_sriov_vf(adev)) 1449 return 0; 1450 1451 sdma_v5_0_ctx_switch_enable(adev, false); 1452 sdma_v5_0_enable(adev, false); 1453 1454 return 0; 1455 } 1456 1457 static int sdma_v5_0_suspend(struct amdgpu_ip_block *ip_block) 1458 { 1459 return sdma_v5_0_hw_fini(ip_block); 1460 } 1461 1462 static int sdma_v5_0_resume(struct amdgpu_ip_block *ip_block) 1463 { 1464 return sdma_v5_0_hw_init(ip_block); 1465 } 1466 1467 static bool sdma_v5_0_is_idle(struct amdgpu_ip_block *ip_block) 1468 { 1469 struct amdgpu_device *adev = ip_block->adev; 1470 u32 i; 1471 1472 for (i = 0; i < adev->sdma.num_instances; i++) { 1473 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1474 1475 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1476 return false; 1477 } 1478 1479 return true; 1480 } 1481 1482 static int sdma_v5_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1483 { 1484 unsigned i; 1485 u32 sdma0, sdma1; 1486 struct amdgpu_device *adev = ip_block->adev; 1487 1488 for (i = 0; i < adev->usec_timeout; i++) { 1489 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1490 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1491 1492 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1493 return 0; 1494 udelay(1); 1495 } 1496 return -ETIMEDOUT; 1497 } 1498 1499 static int sdma_v5_0_soft_reset(struct amdgpu_ip_block *ip_block) 1500 { 1501 /* todo */ 1502 1503 return 0; 1504 } 1505 1506 static int sdma_v5_0_reset_queue(struct amdgpu_ring *ring, unsigned int vmid) 1507 { 1508 struct amdgpu_device *adev = ring->adev; 1509 int i, j, r; 1510 u32 rb_cntl, ib_cntl, f32_cntl, freeze, cntl, preempt, soft_reset, stat1_reg; 1511 1512 if (amdgpu_sriov_vf(adev)) 1513 return -EINVAL; 1514 1515 for (i = 0; i < adev->sdma.num_instances; i++) { 1516 if (ring == &adev->sdma.instance[i].ring) 1517 break; 1518 } 1519 1520 if (i == adev->sdma.num_instances) { 1521 DRM_ERROR("sdma instance not found\n"); 1522 return -EINVAL; 1523 } 1524 1525 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 1526 1527 /* stop queue */ 1528 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 1529 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 1530 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 1531 1532 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 1533 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 1534 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 1535 1536 /* engine stop SDMA1_F32_CNTL.HALT to 1 and SDMAx_FREEZE freeze bit to 1 */ 1537 freeze = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE)); 1538 freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 1); 1539 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE), freeze); 1540 1541 for (j = 0; j < adev->usec_timeout; j++) { 1542 freeze = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE)); 1543 if (REG_GET_FIELD(freeze, SDMA0_FREEZE, FROZEN) & 1) 1544 break; 1545 udelay(1); 1546 } 1547 1548 /* check sdma copy engine all idle if frozen not received*/ 1549 if (j == adev->usec_timeout) { 1550 stat1_reg = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS1_REG)); 1551 if ((stat1_reg & 0x3FF) != 0x3FF) { 1552 DRM_ERROR("cannot soft reset as sdma not idle\n"); 1553 r = -ETIMEDOUT; 1554 goto err0; 1555 } 1556 } 1557 1558 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 1559 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 1560 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 1561 1562 cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 1563 cntl = REG_SET_FIELD(cntl, SDMA0_CNTL, UTC_L1_ENABLE, 0); 1564 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), cntl); 1565 1566 /* soft reset SDMA_GFX_PREEMPT.IB_PREEMPT = 0 mmGRBM_SOFT_RESET.SOFT_RESET_SDMA0/1 = 1 */ 1567 preempt = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_PREEMPT)); 1568 preempt = REG_SET_FIELD(preempt, SDMA0_GFX_PREEMPT, IB_PREEMPT, 0); 1569 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_PREEMPT), preempt); 1570 1571 soft_reset = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 1572 soft_reset |= 1 << GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT << i; 1573 1574 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, soft_reset); 1575 1576 udelay(50); 1577 1578 soft_reset &= ~(1 << GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT << i); 1579 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, soft_reset); 1580 1581 /* unfreeze*/ 1582 freeze = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE)); 1583 freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 0); 1584 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE), freeze); 1585 1586 r = sdma_v5_0_gfx_resume_instance(adev, i, true); 1587 1588 err0: 1589 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 1590 return r; 1591 } 1592 1593 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring) 1594 { 1595 int i, r = 0; 1596 struct amdgpu_device *adev = ring->adev; 1597 u32 index = 0; 1598 u64 sdma_gfx_preempt; 1599 1600 amdgpu_sdma_get_index_from_ring(ring, &index); 1601 if (index == 0) 1602 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT; 1603 else 1604 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT; 1605 1606 /* assert preemption condition */ 1607 amdgpu_ring_set_preempt_cond_exec(ring, false); 1608 1609 /* emit the trailing fence */ 1610 ring->trail_seq += 1; 1611 amdgpu_ring_alloc(ring, 10); 1612 sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1613 ring->trail_seq, 0); 1614 amdgpu_ring_commit(ring); 1615 1616 /* assert IB preemption */ 1617 WREG32(sdma_gfx_preempt, 1); 1618 1619 /* poll the trailing fence */ 1620 for (i = 0; i < adev->usec_timeout; i++) { 1621 if (ring->trail_seq == 1622 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1623 break; 1624 udelay(1); 1625 } 1626 1627 if (i >= adev->usec_timeout) { 1628 r = -EINVAL; 1629 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1630 } 1631 1632 /* deassert IB preemption */ 1633 WREG32(sdma_gfx_preempt, 0); 1634 1635 /* deassert the preemption condition */ 1636 amdgpu_ring_set_preempt_cond_exec(ring, true); 1637 return r; 1638 } 1639 1640 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev, 1641 struct amdgpu_irq_src *source, 1642 unsigned type, 1643 enum amdgpu_interrupt_state state) 1644 { 1645 u32 sdma_cntl; 1646 1647 if (!amdgpu_sriov_vf(adev)) { 1648 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ? 1649 sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) : 1650 sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL); 1651 1652 sdma_cntl = RREG32(reg_offset); 1653 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1654 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1655 WREG32(reg_offset, sdma_cntl); 1656 } 1657 1658 return 0; 1659 } 1660 1661 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev, 1662 struct amdgpu_irq_src *source, 1663 struct amdgpu_iv_entry *entry) 1664 { 1665 uint32_t mes_queue_id = entry->src_data[0]; 1666 1667 DRM_DEBUG("IH: SDMA trap\n"); 1668 1669 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 1670 struct amdgpu_mes_queue *queue; 1671 1672 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 1673 1674 spin_lock(&adev->mes.queue_id_lock); 1675 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 1676 if (queue) { 1677 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); 1678 amdgpu_fence_process(queue->ring); 1679 } 1680 spin_unlock(&adev->mes.queue_id_lock); 1681 return 0; 1682 } 1683 1684 switch (entry->client_id) { 1685 case SOC15_IH_CLIENTID_SDMA0: 1686 switch (entry->ring_id) { 1687 case 0: 1688 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1689 break; 1690 case 1: 1691 /* XXX compute */ 1692 break; 1693 case 2: 1694 /* XXX compute */ 1695 break; 1696 case 3: 1697 /* XXX page queue*/ 1698 break; 1699 } 1700 break; 1701 case SOC15_IH_CLIENTID_SDMA1: 1702 switch (entry->ring_id) { 1703 case 0: 1704 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1705 break; 1706 case 1: 1707 /* XXX compute */ 1708 break; 1709 case 2: 1710 /* XXX compute */ 1711 break; 1712 case 3: 1713 /* XXX page queue*/ 1714 break; 1715 } 1716 break; 1717 } 1718 return 0; 1719 } 1720 1721 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1722 struct amdgpu_irq_src *source, 1723 struct amdgpu_iv_entry *entry) 1724 { 1725 return 0; 1726 } 1727 1728 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 1729 bool enable) 1730 { 1731 uint32_t data, def; 1732 int i; 1733 1734 for (i = 0; i < adev->sdma.num_instances; i++) { 1735 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1736 /* Enable sdma clock gating */ 1737 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1738 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1739 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1740 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1741 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1742 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1743 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1744 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1745 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1746 if (def != data) 1747 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1748 } else { 1749 /* Disable sdma clock gating */ 1750 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1751 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1752 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1753 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1754 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1755 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1756 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1757 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1758 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1759 if (def != data) 1760 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1761 } 1762 } 1763 } 1764 1765 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 1766 bool enable) 1767 { 1768 uint32_t data, def; 1769 int i; 1770 1771 for (i = 0; i < adev->sdma.num_instances; i++) { 1772 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1773 /* Enable sdma mem light sleep */ 1774 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1775 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1776 if (def != data) 1777 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1778 1779 } else { 1780 /* Disable sdma mem light sleep */ 1781 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1782 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1783 if (def != data) 1784 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1785 1786 } 1787 } 1788 } 1789 1790 static int sdma_v5_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1791 enum amd_clockgating_state state) 1792 { 1793 struct amdgpu_device *adev = ip_block->adev; 1794 1795 if (amdgpu_sriov_vf(adev)) 1796 return 0; 1797 1798 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1799 case IP_VERSION(5, 0, 0): 1800 case IP_VERSION(5, 0, 2): 1801 case IP_VERSION(5, 0, 5): 1802 sdma_v5_0_update_medium_grain_clock_gating(adev, 1803 state == AMD_CG_STATE_GATE); 1804 sdma_v5_0_update_medium_grain_light_sleep(adev, 1805 state == AMD_CG_STATE_GATE); 1806 break; 1807 default: 1808 break; 1809 } 1810 1811 return 0; 1812 } 1813 1814 static int sdma_v5_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 1815 enum amd_powergating_state state) 1816 { 1817 return 0; 1818 } 1819 1820 static void sdma_v5_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1821 { 1822 struct amdgpu_device *adev = ip_block->adev; 1823 int data; 1824 1825 if (amdgpu_sriov_vf(adev)) 1826 *flags = 0; 1827 1828 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1829 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL)); 1830 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 1831 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1832 1833 /* AMD_CG_SUPPORT_SDMA_LS */ 1834 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); 1835 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1836 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1837 } 1838 1839 static void sdma_v5_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 1840 { 1841 struct amdgpu_device *adev = ip_block->adev; 1842 int i, j; 1843 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_0); 1844 uint32_t instance_offset; 1845 1846 if (!adev->sdma.ip_dump) 1847 return; 1848 1849 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances); 1850 for (i = 0; i < adev->sdma.num_instances; i++) { 1851 instance_offset = i * reg_count; 1852 drm_printf(p, "\nInstance:%d\n", i); 1853 1854 for (j = 0; j < reg_count; j++) 1855 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_5_0[j].reg_name, 1856 adev->sdma.ip_dump[instance_offset + j]); 1857 } 1858 } 1859 1860 static void sdma_v5_0_dump_ip_state(struct amdgpu_ip_block *ip_block) 1861 { 1862 struct amdgpu_device *adev = ip_block->adev; 1863 int i, j; 1864 uint32_t instance_offset; 1865 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_0); 1866 1867 if (!adev->sdma.ip_dump) 1868 return; 1869 1870 amdgpu_gfx_off_ctrl(adev, false); 1871 for (i = 0; i < adev->sdma.num_instances; i++) { 1872 instance_offset = i * reg_count; 1873 for (j = 0; j < reg_count; j++) 1874 adev->sdma.ip_dump[instance_offset + j] = 1875 RREG32(sdma_v5_0_get_reg_offset(adev, i, 1876 sdma_reg_list_5_0[j].reg_offset)); 1877 } 1878 amdgpu_gfx_off_ctrl(adev, true); 1879 } 1880 1881 static const struct amd_ip_funcs sdma_v5_0_ip_funcs = { 1882 .name = "sdma_v5_0", 1883 .early_init = sdma_v5_0_early_init, 1884 .sw_init = sdma_v5_0_sw_init, 1885 .sw_fini = sdma_v5_0_sw_fini, 1886 .hw_init = sdma_v5_0_hw_init, 1887 .hw_fini = sdma_v5_0_hw_fini, 1888 .suspend = sdma_v5_0_suspend, 1889 .resume = sdma_v5_0_resume, 1890 .is_idle = sdma_v5_0_is_idle, 1891 .wait_for_idle = sdma_v5_0_wait_for_idle, 1892 .soft_reset = sdma_v5_0_soft_reset, 1893 .set_clockgating_state = sdma_v5_0_set_clockgating_state, 1894 .set_powergating_state = sdma_v5_0_set_powergating_state, 1895 .get_clockgating_state = sdma_v5_0_get_clockgating_state, 1896 .dump_ip_state = sdma_v5_0_dump_ip_state, 1897 .print_ip_state = sdma_v5_0_print_ip_state, 1898 }; 1899 1900 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = { 1901 .type = AMDGPU_RING_TYPE_SDMA, 1902 .align_mask = 0xf, 1903 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1904 .support_64bit_ptrs = true, 1905 .secure_submission_supported = true, 1906 .get_rptr = sdma_v5_0_ring_get_rptr, 1907 .get_wptr = sdma_v5_0_ring_get_wptr, 1908 .set_wptr = sdma_v5_0_ring_set_wptr, 1909 .emit_frame_size = 1910 5 + /* sdma_v5_0_ring_init_cond_exec */ 1911 6 + /* sdma_v5_0_ring_emit_hdp_flush */ 1912 3 + /* hdp_invalidate */ 1913 6 + /* sdma_v5_0_ring_emit_pipeline_sync */ 1914 /* sdma_v5_0_ring_emit_vm_flush */ 1915 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1916 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 + 1917 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */ 1918 .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */ 1919 .emit_ib = sdma_v5_0_ring_emit_ib, 1920 .emit_mem_sync = sdma_v5_0_ring_emit_mem_sync, 1921 .emit_fence = sdma_v5_0_ring_emit_fence, 1922 .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync, 1923 .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush, 1924 .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush, 1925 .test_ring = sdma_v5_0_ring_test_ring, 1926 .test_ib = sdma_v5_0_ring_test_ib, 1927 .insert_nop = sdma_v5_0_ring_insert_nop, 1928 .pad_ib = sdma_v5_0_ring_pad_ib, 1929 .emit_wreg = sdma_v5_0_ring_emit_wreg, 1930 .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait, 1931 .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait, 1932 .init_cond_exec = sdma_v5_0_ring_init_cond_exec, 1933 .preempt_ib = sdma_v5_0_ring_preempt_ib, 1934 .reset = sdma_v5_0_reset_queue, 1935 }; 1936 1937 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev) 1938 { 1939 int i; 1940 1941 for (i = 0; i < adev->sdma.num_instances; i++) { 1942 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs; 1943 adev->sdma.instance[i].ring.me = i; 1944 } 1945 } 1946 1947 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = { 1948 .set = sdma_v5_0_set_trap_irq_state, 1949 .process = sdma_v5_0_process_trap_irq, 1950 }; 1951 1952 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = { 1953 .process = sdma_v5_0_process_illegal_inst_irq, 1954 }; 1955 1956 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev) 1957 { 1958 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1959 adev->sdma.num_instances; 1960 adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs; 1961 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs; 1962 } 1963 1964 /** 1965 * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine 1966 * 1967 * @ib: indirect buffer to copy to 1968 * @src_offset: src GPU address 1969 * @dst_offset: dst GPU address 1970 * @byte_count: number of bytes to xfer 1971 * @copy_flags: copy flags for the buffers 1972 * 1973 * Copy GPU buffers using the DMA engine (NAVI10). 1974 * Used by the amdgpu ttm implementation to move pages if 1975 * registered as the asic copy callback. 1976 */ 1977 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib, 1978 uint64_t src_offset, 1979 uint64_t dst_offset, 1980 uint32_t byte_count, 1981 uint32_t copy_flags) 1982 { 1983 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1984 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1985 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0); 1986 ib->ptr[ib->length_dw++] = byte_count - 1; 1987 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1988 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1989 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1990 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1991 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1992 } 1993 1994 /** 1995 * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine 1996 * 1997 * @ib: indirect buffer to fill 1998 * @src_data: value to write to buffer 1999 * @dst_offset: dst GPU address 2000 * @byte_count: number of bytes to xfer 2001 * 2002 * Fill GPU buffers using the DMA engine (NAVI10). 2003 */ 2004 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib, 2005 uint32_t src_data, 2006 uint64_t dst_offset, 2007 uint32_t byte_count) 2008 { 2009 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2010 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2011 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2012 ib->ptr[ib->length_dw++] = src_data; 2013 ib->ptr[ib->length_dw++] = byte_count - 1; 2014 } 2015 2016 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = { 2017 .copy_max_bytes = 0x400000, 2018 .copy_num_dw = 7, 2019 .emit_copy_buffer = sdma_v5_0_emit_copy_buffer, 2020 2021 .fill_max_bytes = 0x400000, 2022 .fill_num_dw = 5, 2023 .emit_fill_buffer = sdma_v5_0_emit_fill_buffer, 2024 }; 2025 2026 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev) 2027 { 2028 if (adev->mman.buffer_funcs == NULL) { 2029 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs; 2030 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2031 } 2032 } 2033 2034 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = { 2035 .copy_pte_num_dw = 7, 2036 .copy_pte = sdma_v5_0_vm_copy_pte, 2037 .write_pte = sdma_v5_0_vm_write_pte, 2038 .set_pte_pde = sdma_v5_0_vm_set_pte_pde, 2039 }; 2040 2041 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev) 2042 { 2043 unsigned i; 2044 2045 if (adev->vm_manager.vm_pte_funcs == NULL) { 2046 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs; 2047 for (i = 0; i < adev->sdma.num_instances; i++) { 2048 adev->vm_manager.vm_pte_scheds[i] = 2049 &adev->sdma.instance[i].ring.sched; 2050 } 2051 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 2052 } 2053 } 2054 2055 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = { 2056 .type = AMD_IP_BLOCK_TYPE_SDMA, 2057 .major = 5, 2058 .minor = 0, 2059 .rev = 0, 2060 .funcs = &sdma_v5_0_ip_funcs, 2061 }; 2062