1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_10_1_0_offset.h" 34 #include "gc/gc_10_1_0_sh_mask.h" 35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h" 36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h" 37 38 #include "soc15_common.h" 39 #include "soc15.h" 40 #include "navi10_sdma_pkt_open.h" 41 #include "nbio_v2_3.h" 42 #include "sdma_common.h" 43 #include "sdma_v5_0.h" 44 45 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin"); 46 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin"); 47 48 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin"); 49 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin"); 50 51 MODULE_FIRMWARE("amdgpu/navi12_sdma.bin"); 52 MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin"); 53 54 #define SDMA1_REG_OFFSET 0x600 55 #define SDMA0_HYP_DEC_REG_START 0x5880 56 #define SDMA0_HYP_DEC_REG_END 0x5893 57 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 58 59 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev); 60 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev); 61 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev); 62 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev); 63 64 static const struct soc15_reg_golden golden_settings_sdma_5[] = { 65 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), 66 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 67 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 68 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 69 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 70 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 71 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 72 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 73 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 74 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 75 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 76 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00), 77 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), 78 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 79 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 80 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 81 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 82 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 83 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 84 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 85 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 86 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 87 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 88 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00) 89 }; 90 91 static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = { 92 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 93 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 94 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 95 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 96 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 112 }; 113 114 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = { 115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 117 }; 118 119 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = { 120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 122 }; 123 124 static const struct soc15_reg_golden golden_settings_sdma_nv12[] = { 125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044), 127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044), 128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044), 129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044), 130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 131 }; 132 133 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 134 { 135 u32 base; 136 137 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 138 internal_offset <= SDMA0_HYP_DEC_REG_END) { 139 base = adev->reg_offset[GC_HWIP][0][1]; 140 if (instance == 1) 141 internal_offset += SDMA1_HYP_DEC_REG_OFFSET; 142 } else { 143 base = adev->reg_offset[GC_HWIP][0][0]; 144 if (instance == 1) 145 internal_offset += SDMA1_REG_OFFSET; 146 } 147 148 return base + internal_offset; 149 } 150 151 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev) 152 { 153 switch (adev->asic_type) { 154 case CHIP_NAVI10: 155 soc15_program_register_sequence(adev, 156 golden_settings_sdma_5, 157 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 158 soc15_program_register_sequence(adev, 159 golden_settings_sdma_nv10, 160 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10)); 161 break; 162 case CHIP_NAVI14: 163 soc15_program_register_sequence(adev, 164 golden_settings_sdma_5, 165 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 166 soc15_program_register_sequence(adev, 167 golden_settings_sdma_nv14, 168 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14)); 169 break; 170 case CHIP_NAVI12: 171 if (amdgpu_sriov_vf(adev)) 172 soc15_program_register_sequence(adev, 173 golden_settings_sdma_5_sriov, 174 (const u32)ARRAY_SIZE(golden_settings_sdma_5_sriov)); 175 else 176 soc15_program_register_sequence(adev, 177 golden_settings_sdma_5, 178 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 179 soc15_program_register_sequence(adev, 180 golden_settings_sdma_nv12, 181 (const u32)ARRAY_SIZE(golden_settings_sdma_nv12)); 182 break; 183 default: 184 break; 185 } 186 } 187 188 /** 189 * sdma_v5_0_init_microcode - load ucode images from disk 190 * 191 * @adev: amdgpu_device pointer 192 * 193 * Use the firmware interface to load the ucode images into 194 * the driver (not loaded into hw). 195 * Returns 0 on success, error on failure. 196 */ 197 198 // emulation only, won't work on real chip 199 // navi10 real chip need to use PSP to load firmware 200 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev) 201 { 202 const char *chip_name; 203 char fw_name[30]; 204 int err = 0, i; 205 struct amdgpu_firmware_info *info = NULL; 206 const struct common_firmware_header *header = NULL; 207 const struct sdma_firmware_header_v1_0 *hdr; 208 209 if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_NAVI12)) 210 return 0; 211 212 DRM_DEBUG("\n"); 213 214 switch (adev->asic_type) { 215 case CHIP_NAVI10: 216 chip_name = "navi10"; 217 break; 218 case CHIP_NAVI14: 219 chip_name = "navi14"; 220 break; 221 case CHIP_NAVI12: 222 chip_name = "navi12"; 223 break; 224 default: 225 BUG(); 226 } 227 228 for (i = 0; i < adev->sdma.num_instances; i++) { 229 if (i == 0) 230 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 231 else 232 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 233 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 234 if (err) 235 goto out; 236 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 237 if (err) 238 goto out; 239 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 240 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 241 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 242 if (adev->sdma.instance[i].feature_version >= 20) 243 adev->sdma.instance[i].burst_nop = true; 244 DRM_DEBUG("psp_load == '%s'\n", 245 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 246 247 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 248 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 249 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 250 info->fw = adev->sdma.instance[i].fw; 251 header = (const struct common_firmware_header *)info->fw->data; 252 adev->firmware.fw_size += 253 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 254 } 255 } 256 out: 257 if (err) { 258 DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name); 259 for (i = 0; i < adev->sdma.num_instances; i++) { 260 release_firmware(adev->sdma.instance[i].fw); 261 adev->sdma.instance[i].fw = NULL; 262 } 263 } 264 return err; 265 } 266 267 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring) 268 { 269 unsigned ret; 270 271 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); 272 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 273 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 274 amdgpu_ring_write(ring, 1); 275 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ 276 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ 277 278 return ret; 279 } 280 281 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring, 282 unsigned offset) 283 { 284 unsigned cur; 285 286 BUG_ON(offset > ring->buf_mask); 287 BUG_ON(ring->ring[offset] != 0x55aa55aa); 288 289 cur = (ring->wptr - 1) & ring->buf_mask; 290 if (cur > offset) 291 ring->ring[offset] = cur - offset; 292 else 293 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 294 } 295 296 /** 297 * sdma_v5_0_ring_get_rptr - get the current read pointer 298 * 299 * @ring: amdgpu ring pointer 300 * 301 * Get the current rptr from the hardware (NAVI10+). 302 */ 303 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring) 304 { 305 u64 *rptr; 306 307 /* XXX check if swapping is necessary on BE */ 308 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 309 310 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 311 return ((*rptr) >> 2); 312 } 313 314 /** 315 * sdma_v5_0_ring_get_wptr - get the current write pointer 316 * 317 * @ring: amdgpu ring pointer 318 * 319 * Get the current wptr from the hardware (NAVI10+). 320 */ 321 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring) 322 { 323 struct amdgpu_device *adev = ring->adev; 324 u64 wptr; 325 326 if (ring->use_doorbell) { 327 /* XXX check if swapping is necessary on BE */ 328 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 329 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 330 } else { 331 wptr = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); 332 wptr = wptr << 32; 333 wptr |= RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); 334 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr); 335 } 336 337 return wptr >> 2; 338 } 339 340 /** 341 * sdma_v5_0_ring_set_wptr - commit the write pointer 342 * 343 * @ring: amdgpu ring pointer 344 * 345 * Write the wptr back to the hardware (NAVI10+). 346 */ 347 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring) 348 { 349 struct amdgpu_device *adev = ring->adev; 350 351 DRM_DEBUG("Setting write pointer\n"); 352 if (ring->use_doorbell) { 353 DRM_DEBUG("Using doorbell -- " 354 "wptr_offs == 0x%08x " 355 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 356 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 357 ring->wptr_offs, 358 lower_32_bits(ring->wptr << 2), 359 upper_32_bits(ring->wptr << 2)); 360 /* XXX check if swapping is necessary on BE */ 361 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); 362 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); 363 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 364 ring->doorbell_index, ring->wptr << 2); 365 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 366 } else { 367 DRM_DEBUG("Not using doorbell -- " 368 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 369 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 370 ring->me, 371 lower_32_bits(ring->wptr << 2), 372 ring->me, 373 upper_32_bits(ring->wptr << 2)); 374 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), 375 lower_32_bits(ring->wptr << 2)); 376 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), 377 upper_32_bits(ring->wptr << 2)); 378 } 379 } 380 381 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 382 { 383 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 384 int i; 385 386 for (i = 0; i < count; i++) 387 if (sdma && sdma->burst_nop && (i == 0)) 388 amdgpu_ring_write(ring, ring->funcs->nop | 389 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 390 else 391 amdgpu_ring_write(ring, ring->funcs->nop); 392 } 393 394 /** 395 * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine 396 * 397 * @ring: amdgpu ring pointer 398 * @job: job to retrieve vmid from 399 * @ib: IB object to schedule 400 * @flags: unused 401 * 402 * Schedule an IB in the DMA ring (NAVI10). 403 */ 404 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 405 struct amdgpu_job *job, 406 struct amdgpu_ib *ib, 407 uint32_t flags) 408 { 409 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 410 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 411 412 /* An IB packet must end on a 8 DW boundary--the next dword 413 * must be on a 8-dword boundary. Our IB packet below is 6 414 * dwords long, thus add x number of NOPs, such that, in 415 * modular arithmetic, 416 * wptr + 6 + x = 8k, k >= 0, which in C is, 417 * (wptr + 6 + x) % 8 = 0. 418 * The expression below, is a solution of x. 419 */ 420 sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 421 422 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 423 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 424 /* base must be 32 byte aligned */ 425 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 426 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 427 amdgpu_ring_write(ring, ib->length_dw); 428 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 429 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 430 } 431 432 /** 433 * sdma_v5_0_ring_emit_mem_sync - flush the IB by graphics cache rinse 434 * 435 * @ring: amdgpu ring pointer 436 * @job: job to retrieve vmid from 437 * @ib: IB object to schedule 438 * 439 * flush the IB by graphics cache rinse. 440 */ 441 static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring) 442 { 443 uint32_t gcr_cntl = 444 SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV | 445 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 446 SDMA_GCR_GLI_INV(1); 447 448 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 449 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ)); 450 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 451 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 452 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 453 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 454 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 455 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 456 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 457 } 458 459 /** 460 * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 461 * 462 * @ring: amdgpu ring pointer 463 * 464 * Emit an hdp flush packet on the requested DMA ring. 465 */ 466 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 467 { 468 struct amdgpu_device *adev = ring->adev; 469 u32 ref_and_mask = 0; 470 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 471 472 if (ring->me == 0) 473 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; 474 else 475 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; 476 477 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 478 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 479 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 480 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 481 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 482 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 483 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 484 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 485 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 486 } 487 488 /** 489 * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring 490 * 491 * @ring: amdgpu ring pointer 492 * @addr: address 493 * @seq: sequence number 494 * @flags: fence related flags 495 * 496 * Add a DMA fence packet to the ring to write 497 * the fence seq number and DMA trap packet to generate 498 * an interrupt if needed (NAVI10). 499 */ 500 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 501 unsigned flags) 502 { 503 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 504 /* write the fence */ 505 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 506 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 507 /* zero in first two bits */ 508 BUG_ON(addr & 0x3); 509 amdgpu_ring_write(ring, lower_32_bits(addr)); 510 amdgpu_ring_write(ring, upper_32_bits(addr)); 511 amdgpu_ring_write(ring, lower_32_bits(seq)); 512 513 /* optionally write high bits as well */ 514 if (write64bit) { 515 addr += 4; 516 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 517 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 518 /* zero in first two bits */ 519 BUG_ON(addr & 0x3); 520 amdgpu_ring_write(ring, lower_32_bits(addr)); 521 amdgpu_ring_write(ring, upper_32_bits(addr)); 522 amdgpu_ring_write(ring, upper_32_bits(seq)); 523 } 524 525 if (flags & AMDGPU_FENCE_FLAG_INT) { 526 /* generate an interrupt */ 527 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 528 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 529 } 530 } 531 532 533 /** 534 * sdma_v5_0_gfx_stop - stop the gfx async dma engines 535 * 536 * @adev: amdgpu_device pointer 537 * 538 * Stop the gfx async dma ring buffers (NAVI10). 539 */ 540 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev) 541 { 542 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 543 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 544 u32 rb_cntl, ib_cntl; 545 int i; 546 547 if ((adev->mman.buffer_funcs_ring == sdma0) || 548 (adev->mman.buffer_funcs_ring == sdma1)) 549 amdgpu_ttm_set_buffer_funcs_status(adev, false); 550 551 for (i = 0; i < adev->sdma.num_instances; i++) { 552 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 553 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 554 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 555 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 556 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 557 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 558 } 559 } 560 561 /** 562 * sdma_v5_0_rlc_stop - stop the compute async dma engines 563 * 564 * @adev: amdgpu_device pointer 565 * 566 * Stop the compute async dma queues (NAVI10). 567 */ 568 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev) 569 { 570 /* XXX todo */ 571 } 572 573 /** 574 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch 575 * 576 * @adev: amdgpu_device pointer 577 * @enable: enable/disable the DMA MEs context switch. 578 * 579 * Halt or unhalt the async dma engines context switch (NAVI10). 580 */ 581 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 582 { 583 u32 f32_cntl = 0, phase_quantum = 0; 584 int i; 585 586 if (amdgpu_sdma_phase_quantum) { 587 unsigned value = amdgpu_sdma_phase_quantum; 588 unsigned unit = 0; 589 590 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 591 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 592 value = (value + 1) >> 1; 593 unit++; 594 } 595 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 596 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 597 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 598 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 599 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 600 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 601 WARN_ONCE(1, 602 "clamping sdma_phase_quantum to %uK clock cycles\n", 603 value << unit); 604 } 605 phase_quantum = 606 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 607 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 608 } 609 610 for (i = 0; i < adev->sdma.num_instances; i++) { 611 if (!amdgpu_sriov_vf(adev)) { 612 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 613 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 614 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 615 } 616 617 if (enable && amdgpu_sdma_phase_quantum) { 618 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 619 phase_quantum); 620 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 621 phase_quantum); 622 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 623 phase_quantum); 624 } 625 if (!amdgpu_sriov_vf(adev)) 626 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 627 } 628 629 } 630 631 /** 632 * sdma_v5_0_enable - stop the async dma engines 633 * 634 * @adev: amdgpu_device pointer 635 * @enable: enable/disable the DMA MEs. 636 * 637 * Halt or unhalt the async dma engines (NAVI10). 638 */ 639 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable) 640 { 641 u32 f32_cntl; 642 int i; 643 644 if (!enable) { 645 sdma_v5_0_gfx_stop(adev); 646 sdma_v5_0_rlc_stop(adev); 647 } 648 649 if (amdgpu_sriov_vf(adev)) 650 return; 651 652 for (i = 0; i < adev->sdma.num_instances; i++) { 653 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 654 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 655 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 656 } 657 } 658 659 /** 660 * sdma_v5_0_gfx_resume - setup and start the async dma engines 661 * 662 * @adev: amdgpu_device pointer 663 * 664 * Set up the gfx DMA ring buffers and enable them (NAVI10). 665 * Returns 0 for success, error for failure. 666 */ 667 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev) 668 { 669 struct amdgpu_ring *ring; 670 u32 rb_cntl, ib_cntl; 671 u32 rb_bufsz; 672 u32 wb_offset; 673 u32 doorbell; 674 u32 doorbell_offset; 675 u32 temp; 676 u32 wptr_poll_cntl; 677 u64 wptr_gpu_addr; 678 int i, r; 679 680 for (i = 0; i < adev->sdma.num_instances; i++) { 681 ring = &adev->sdma.instance[i].ring; 682 wb_offset = (ring->rptr_offs * 4); 683 684 if (!amdgpu_sriov_vf(adev)) 685 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 686 687 /* Set ring buffer size in dwords */ 688 rb_bufsz = order_base_2(ring->ring_size / 4); 689 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 690 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 691 #ifdef __BIG_ENDIAN 692 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 693 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 694 RPTR_WRITEBACK_SWAP_ENABLE, 1); 695 #endif 696 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 697 698 /* Initialize the ring buffer's read and write pointers */ 699 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 700 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 701 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 702 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 703 704 /* setup the wptr shadow polling */ 705 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 706 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 707 lower_32_bits(wptr_gpu_addr)); 708 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 709 upper_32_bits(wptr_gpu_addr)); 710 wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, 711 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 712 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 713 SDMA0_GFX_RB_WPTR_POLL_CNTL, 714 F32_POLL_ENABLE, 1); 715 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 716 wptr_poll_cntl); 717 718 /* set the wb address whether it's enabled or not */ 719 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 720 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 721 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 722 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 723 724 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 725 726 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 727 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 728 729 ring->wptr = 0; 730 731 /* before programing wptr to a less value, need set minor_ptr_update first */ 732 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 733 734 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 735 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); 736 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 737 } 738 739 doorbell = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 740 doorbell_offset = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); 741 742 if (ring->use_doorbell) { 743 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 744 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 745 OFFSET, ring->doorbell_index); 746 } else { 747 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 748 } 749 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 750 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 751 752 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 753 ring->doorbell_index, 20); 754 755 if (amdgpu_sriov_vf(adev)) 756 sdma_v5_0_ring_set_wptr(ring); 757 758 /* set minor_ptr_update to 0 after wptr programed */ 759 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 760 761 if (!amdgpu_sriov_vf(adev)) { 762 /* set utc l1 enable flag always to 1 */ 763 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 764 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 765 766 /* enable MCBP */ 767 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); 768 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 769 770 /* Set up RESP_MODE to non-copy addresses */ 771 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); 772 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 773 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 774 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); 775 776 /* program default cache read and write policy */ 777 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); 778 /* clean read policy and write policy bits */ 779 temp &= 0xFF0FFF; 780 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14)); 781 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); 782 } 783 784 if (!amdgpu_sriov_vf(adev)) { 785 /* unhalt engine */ 786 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 787 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 788 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 789 } 790 791 /* enable DMA RB */ 792 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 793 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 794 795 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 796 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 797 #ifdef __BIG_ENDIAN 798 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 799 #endif 800 /* enable DMA IBs */ 801 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 802 803 ring->sched.ready = true; 804 805 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 806 sdma_v5_0_ctx_switch_enable(adev, true); 807 sdma_v5_0_enable(adev, true); 808 } 809 810 r = amdgpu_ring_test_helper(ring); 811 if (r) 812 return r; 813 814 if (adev->mman.buffer_funcs_ring == ring) 815 amdgpu_ttm_set_buffer_funcs_status(adev, true); 816 } 817 818 return 0; 819 } 820 821 /** 822 * sdma_v5_0_rlc_resume - setup and start the async dma engines 823 * 824 * @adev: amdgpu_device pointer 825 * 826 * Set up the compute DMA queues and enable them (NAVI10). 827 * Returns 0 for success, error for failure. 828 */ 829 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev) 830 { 831 return 0; 832 } 833 834 /** 835 * sdma_v5_0_load_microcode - load the sDMA ME ucode 836 * 837 * @adev: amdgpu_device pointer 838 * 839 * Loads the sDMA0/1 ucode. 840 * Returns 0 for success, -EINVAL if the ucode is not available. 841 */ 842 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev) 843 { 844 const struct sdma_firmware_header_v1_0 *hdr; 845 const __le32 *fw_data; 846 u32 fw_size; 847 int i, j; 848 849 /* halt the MEs */ 850 sdma_v5_0_enable(adev, false); 851 852 for (i = 0; i < adev->sdma.num_instances; i++) { 853 if (!adev->sdma.instance[i].fw) 854 return -EINVAL; 855 856 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 857 amdgpu_ucode_print_sdma_hdr(&hdr->header); 858 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 859 860 fw_data = (const __le32 *) 861 (adev->sdma.instance[i].fw->data + 862 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 863 864 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 865 866 for (j = 0; j < fw_size; j++) { 867 if (amdgpu_emu_mode == 1 && j % 500 == 0) 868 msleep(1); 869 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 870 } 871 872 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 873 } 874 875 return 0; 876 } 877 878 /** 879 * sdma_v5_0_start - setup and start the async dma engines 880 * 881 * @adev: amdgpu_device pointer 882 * 883 * Set up the DMA engines and enable them (NAVI10). 884 * Returns 0 for success, error for failure. 885 */ 886 static int sdma_v5_0_start(struct amdgpu_device *adev) 887 { 888 int r = 0; 889 890 if (amdgpu_sriov_vf(adev)) { 891 sdma_v5_0_ctx_switch_enable(adev, false); 892 sdma_v5_0_enable(adev, false); 893 894 /* set RB registers */ 895 r = sdma_v5_0_gfx_resume(adev); 896 return r; 897 } 898 899 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 900 r = sdma_v5_0_load_microcode(adev); 901 if (r) 902 return r; 903 } 904 905 /* unhalt the MEs */ 906 sdma_v5_0_enable(adev, true); 907 /* enable sdma ring preemption */ 908 sdma_v5_0_ctx_switch_enable(adev, true); 909 910 /* start the gfx rings and rlc compute queues */ 911 r = sdma_v5_0_gfx_resume(adev); 912 if (r) 913 return r; 914 r = sdma_v5_0_rlc_resume(adev); 915 916 return r; 917 } 918 919 /** 920 * sdma_v5_0_ring_test_ring - simple async dma engine test 921 * 922 * @ring: amdgpu_ring structure holding ring information 923 * 924 * Test the DMA engine by writing using it to write an 925 * value to memory. (NAVI10). 926 * Returns 0 for success, error for failure. 927 */ 928 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring) 929 { 930 struct amdgpu_device *adev = ring->adev; 931 unsigned i; 932 unsigned index; 933 int r; 934 u32 tmp; 935 u64 gpu_addr; 936 937 r = amdgpu_device_wb_get(adev, &index); 938 if (r) { 939 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 940 return r; 941 } 942 943 gpu_addr = adev->wb.gpu_addr + (index * 4); 944 tmp = 0xCAFEDEAD; 945 adev->wb.wb[index] = cpu_to_le32(tmp); 946 947 r = amdgpu_ring_alloc(ring, 5); 948 if (r) { 949 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 950 amdgpu_device_wb_free(adev, index); 951 return r; 952 } 953 954 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 955 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 956 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 957 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 958 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 959 amdgpu_ring_write(ring, 0xDEADBEEF); 960 amdgpu_ring_commit(ring); 961 962 for (i = 0; i < adev->usec_timeout; i++) { 963 tmp = le32_to_cpu(adev->wb.wb[index]); 964 if (tmp == 0xDEADBEEF) 965 break; 966 if (amdgpu_emu_mode == 1) 967 msleep(1); 968 else 969 udelay(1); 970 } 971 972 if (i >= adev->usec_timeout) 973 r = -ETIMEDOUT; 974 975 amdgpu_device_wb_free(adev, index); 976 977 return r; 978 } 979 980 /** 981 * sdma_v5_0_ring_test_ib - test an IB on the DMA engine 982 * 983 * @ring: amdgpu_ring structure holding ring information 984 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 985 * 986 * Test a simple IB in the DMA ring (NAVI10). 987 * Returns 0 on success, error on failure. 988 */ 989 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 990 { 991 struct amdgpu_device *adev = ring->adev; 992 struct amdgpu_ib ib; 993 struct dma_fence *f = NULL; 994 unsigned index; 995 long r; 996 u32 tmp = 0; 997 u64 gpu_addr; 998 999 r = amdgpu_device_wb_get(adev, &index); 1000 if (r) { 1001 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 1002 return r; 1003 } 1004 1005 gpu_addr = adev->wb.gpu_addr + (index * 4); 1006 tmp = 0xCAFEDEAD; 1007 adev->wb.wb[index] = cpu_to_le32(tmp); 1008 memset(&ib, 0, sizeof(ib)); 1009 r = amdgpu_ib_get(adev, NULL, 256, 1010 AMDGPU_IB_POOL_DIRECT, &ib); 1011 if (r) { 1012 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 1013 goto err0; 1014 } 1015 1016 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1017 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1018 ib.ptr[1] = lower_32_bits(gpu_addr); 1019 ib.ptr[2] = upper_32_bits(gpu_addr); 1020 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1021 ib.ptr[4] = 0xDEADBEEF; 1022 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1023 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1024 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1025 ib.length_dw = 8; 1026 1027 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1028 if (r) 1029 goto err1; 1030 1031 r = dma_fence_wait_timeout(f, false, timeout); 1032 if (r == 0) { 1033 DRM_ERROR("amdgpu: IB test timed out\n"); 1034 r = -ETIMEDOUT; 1035 goto err1; 1036 } else if (r < 0) { 1037 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1038 goto err1; 1039 } 1040 tmp = le32_to_cpu(adev->wb.wb[index]); 1041 if (tmp == 0xDEADBEEF) 1042 r = 0; 1043 else 1044 r = -EINVAL; 1045 1046 err1: 1047 amdgpu_ib_free(adev, &ib, NULL); 1048 dma_fence_put(f); 1049 err0: 1050 amdgpu_device_wb_free(adev, index); 1051 return r; 1052 } 1053 1054 1055 /** 1056 * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART 1057 * 1058 * @ib: indirect buffer to fill with commands 1059 * @pe: addr of the page entry 1060 * @src: src addr to copy from 1061 * @count: number of page entries to update 1062 * 1063 * Update PTEs by copying them from the GART using sDMA (NAVI10). 1064 */ 1065 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib, 1066 uint64_t pe, uint64_t src, 1067 unsigned count) 1068 { 1069 unsigned bytes = count * 8; 1070 1071 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1072 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1073 ib->ptr[ib->length_dw++] = bytes - 1; 1074 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1075 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1076 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1077 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1078 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1079 1080 } 1081 1082 /** 1083 * sdma_v5_0_vm_write_pte - update PTEs by writing them manually 1084 * 1085 * @ib: indirect buffer to fill with commands 1086 * @pe: addr of the page entry 1087 * @value: dst addr to write into pe 1088 * @count: number of page entries to update 1089 * @incr: increase next addr by incr bytes 1090 * 1091 * Update PTEs by writing them manually using sDMA (NAVI10). 1092 */ 1093 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1094 uint64_t value, unsigned count, 1095 uint32_t incr) 1096 { 1097 unsigned ndw = count * 2; 1098 1099 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1100 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1101 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1102 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1103 ib->ptr[ib->length_dw++] = ndw - 1; 1104 for (; ndw > 0; ndw -= 2) { 1105 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1106 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1107 value += incr; 1108 } 1109 } 1110 1111 /** 1112 * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA 1113 * 1114 * @ib: indirect buffer to fill with commands 1115 * @pe: addr of the page entry 1116 * @addr: dst addr to write into pe 1117 * @count: number of page entries to update 1118 * @incr: increase next addr by incr bytes 1119 * @flags: access flags 1120 * 1121 * Update the page tables using sDMA (NAVI10). 1122 */ 1123 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1124 uint64_t pe, 1125 uint64_t addr, unsigned count, 1126 uint32_t incr, uint64_t flags) 1127 { 1128 /* for physically contiguous pages (vram) */ 1129 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1130 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1131 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1132 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1133 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1134 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1135 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1136 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1137 ib->ptr[ib->length_dw++] = 0; 1138 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1139 } 1140 1141 /** 1142 * sdma_v5_0_ring_pad_ib - pad the IB 1143 * @ring: amdgpu_ring structure holding ring information 1144 * @ib: indirect buffer to fill with padding 1145 * 1146 * Pad the IB with NOPs to a boundary multiple of 8. 1147 */ 1148 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1149 { 1150 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1151 u32 pad_count; 1152 int i; 1153 1154 pad_count = (-ib->length_dw) & 0x7; 1155 for (i = 0; i < pad_count; i++) 1156 if (sdma && sdma->burst_nop && (i == 0)) 1157 ib->ptr[ib->length_dw++] = 1158 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1159 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1160 else 1161 ib->ptr[ib->length_dw++] = 1162 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1163 } 1164 1165 1166 /** 1167 * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline 1168 * 1169 * @ring: amdgpu_ring pointer 1170 * 1171 * Make sure all previous operations are completed (CIK). 1172 */ 1173 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1174 { 1175 uint32_t seq = ring->fence_drv.sync_seq; 1176 uint64_t addr = ring->fence_drv.gpu_addr; 1177 1178 /* wait for idle */ 1179 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1180 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1181 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1182 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1183 amdgpu_ring_write(ring, addr & 0xfffffffc); 1184 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1185 amdgpu_ring_write(ring, seq); /* reference */ 1186 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1187 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1188 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1189 } 1190 1191 1192 /** 1193 * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA 1194 * 1195 * @ring: amdgpu_ring pointer 1196 * @vmid: vmid number to use 1197 * @pd_addr: address 1198 * 1199 * Update the page table base and flush the VM TLB 1200 * using sDMA (NAVI10). 1201 */ 1202 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1203 unsigned vmid, uint64_t pd_addr) 1204 { 1205 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1206 } 1207 1208 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring, 1209 uint32_t reg, uint32_t val) 1210 { 1211 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1212 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1213 amdgpu_ring_write(ring, reg); 1214 amdgpu_ring_write(ring, val); 1215 } 1216 1217 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1218 uint32_t val, uint32_t mask) 1219 { 1220 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1221 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1222 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1223 amdgpu_ring_write(ring, reg << 2); 1224 amdgpu_ring_write(ring, 0); 1225 amdgpu_ring_write(ring, val); /* reference */ 1226 amdgpu_ring_write(ring, mask); /* mask */ 1227 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1228 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1229 } 1230 1231 static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1232 uint32_t reg0, uint32_t reg1, 1233 uint32_t ref, uint32_t mask) 1234 { 1235 amdgpu_ring_emit_wreg(ring, reg0, ref); 1236 /* wait for a cycle to reset vm_inv_eng*_ack */ 1237 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1238 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1239 } 1240 1241 static int sdma_v5_0_early_init(void *handle) 1242 { 1243 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1244 1245 adev->sdma.num_instances = 2; 1246 1247 sdma_v5_0_set_ring_funcs(adev); 1248 sdma_v5_0_set_buffer_funcs(adev); 1249 sdma_v5_0_set_vm_pte_funcs(adev); 1250 sdma_v5_0_set_irq_funcs(adev); 1251 1252 return 0; 1253 } 1254 1255 1256 static int sdma_v5_0_sw_init(void *handle) 1257 { 1258 struct amdgpu_ring *ring; 1259 int r, i; 1260 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1261 1262 /* SDMA trap event */ 1263 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, 1264 SDMA0_5_0__SRCID__SDMA_TRAP, 1265 &adev->sdma.trap_irq); 1266 if (r) 1267 return r; 1268 1269 /* SDMA trap event */ 1270 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, 1271 SDMA1_5_0__SRCID__SDMA_TRAP, 1272 &adev->sdma.trap_irq); 1273 if (r) 1274 return r; 1275 1276 r = sdma_v5_0_init_microcode(adev); 1277 if (r) { 1278 DRM_ERROR("Failed to load sdma firmware!\n"); 1279 return r; 1280 } 1281 1282 for (i = 0; i < adev->sdma.num_instances; i++) { 1283 ring = &adev->sdma.instance[i].ring; 1284 ring->ring_obj = NULL; 1285 ring->use_doorbell = true; 1286 1287 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1288 ring->use_doorbell?"true":"false"); 1289 1290 ring->doorbell_index = (i == 0) ? 1291 (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset 1292 : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset 1293 1294 sprintf(ring->name, "sdma%d", i); 1295 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1296 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 : 1297 AMDGPU_SDMA_IRQ_INSTANCE1, 1298 AMDGPU_RING_PRIO_DEFAULT, NULL); 1299 if (r) 1300 return r; 1301 } 1302 1303 return r; 1304 } 1305 1306 static int sdma_v5_0_sw_fini(void *handle) 1307 { 1308 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1309 int i; 1310 1311 for (i = 0; i < adev->sdma.num_instances; i++) { 1312 release_firmware(adev->sdma.instance[i].fw); 1313 adev->sdma.instance[i].fw = NULL; 1314 1315 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1316 } 1317 1318 return 0; 1319 } 1320 1321 static int sdma_v5_0_hw_init(void *handle) 1322 { 1323 int r; 1324 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1325 1326 sdma_v5_0_init_golden_registers(adev); 1327 1328 r = sdma_v5_0_start(adev); 1329 1330 return r; 1331 } 1332 1333 static int sdma_v5_0_hw_fini(void *handle) 1334 { 1335 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1336 1337 if (amdgpu_sriov_vf(adev)) 1338 return 0; 1339 1340 sdma_v5_0_ctx_switch_enable(adev, false); 1341 sdma_v5_0_enable(adev, false); 1342 1343 return 0; 1344 } 1345 1346 static int sdma_v5_0_suspend(void *handle) 1347 { 1348 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1349 1350 return sdma_v5_0_hw_fini(adev); 1351 } 1352 1353 static int sdma_v5_0_resume(void *handle) 1354 { 1355 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1356 1357 return sdma_v5_0_hw_init(adev); 1358 } 1359 1360 static bool sdma_v5_0_is_idle(void *handle) 1361 { 1362 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1363 u32 i; 1364 1365 for (i = 0; i < adev->sdma.num_instances; i++) { 1366 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1367 1368 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1369 return false; 1370 } 1371 1372 return true; 1373 } 1374 1375 static int sdma_v5_0_wait_for_idle(void *handle) 1376 { 1377 unsigned i; 1378 u32 sdma0, sdma1; 1379 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1380 1381 for (i = 0; i < adev->usec_timeout; i++) { 1382 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1383 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1384 1385 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1386 return 0; 1387 udelay(1); 1388 } 1389 return -ETIMEDOUT; 1390 } 1391 1392 static int sdma_v5_0_soft_reset(void *handle) 1393 { 1394 /* todo */ 1395 1396 return 0; 1397 } 1398 1399 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring) 1400 { 1401 int i, r = 0; 1402 struct amdgpu_device *adev = ring->adev; 1403 u32 index = 0; 1404 u64 sdma_gfx_preempt; 1405 1406 amdgpu_sdma_get_index_from_ring(ring, &index); 1407 if (index == 0) 1408 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT; 1409 else 1410 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT; 1411 1412 /* assert preemption condition */ 1413 amdgpu_ring_set_preempt_cond_exec(ring, false); 1414 1415 /* emit the trailing fence */ 1416 ring->trail_seq += 1; 1417 amdgpu_ring_alloc(ring, 10); 1418 sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1419 ring->trail_seq, 0); 1420 amdgpu_ring_commit(ring); 1421 1422 /* assert IB preemption */ 1423 WREG32(sdma_gfx_preempt, 1); 1424 1425 /* poll the trailing fence */ 1426 for (i = 0; i < adev->usec_timeout; i++) { 1427 if (ring->trail_seq == 1428 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1429 break; 1430 udelay(1); 1431 } 1432 1433 if (i >= adev->usec_timeout) { 1434 r = -EINVAL; 1435 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1436 } 1437 1438 /* deassert IB preemption */ 1439 WREG32(sdma_gfx_preempt, 0); 1440 1441 /* deassert the preemption condition */ 1442 amdgpu_ring_set_preempt_cond_exec(ring, true); 1443 return r; 1444 } 1445 1446 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev, 1447 struct amdgpu_irq_src *source, 1448 unsigned type, 1449 enum amdgpu_interrupt_state state) 1450 { 1451 u32 sdma_cntl; 1452 1453 if (!amdgpu_sriov_vf(adev)) { 1454 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ? 1455 sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) : 1456 sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL); 1457 1458 sdma_cntl = RREG32(reg_offset); 1459 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1460 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1461 WREG32(reg_offset, sdma_cntl); 1462 } 1463 1464 return 0; 1465 } 1466 1467 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev, 1468 struct amdgpu_irq_src *source, 1469 struct amdgpu_iv_entry *entry) 1470 { 1471 DRM_DEBUG("IH: SDMA trap\n"); 1472 switch (entry->client_id) { 1473 case SOC15_IH_CLIENTID_SDMA0: 1474 switch (entry->ring_id) { 1475 case 0: 1476 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1477 break; 1478 case 1: 1479 /* XXX compute */ 1480 break; 1481 case 2: 1482 /* XXX compute */ 1483 break; 1484 case 3: 1485 /* XXX page queue*/ 1486 break; 1487 } 1488 break; 1489 case SOC15_IH_CLIENTID_SDMA1: 1490 switch (entry->ring_id) { 1491 case 0: 1492 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1493 break; 1494 case 1: 1495 /* XXX compute */ 1496 break; 1497 case 2: 1498 /* XXX compute */ 1499 break; 1500 case 3: 1501 /* XXX page queue*/ 1502 break; 1503 } 1504 break; 1505 } 1506 return 0; 1507 } 1508 1509 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1510 struct amdgpu_irq_src *source, 1511 struct amdgpu_iv_entry *entry) 1512 { 1513 return 0; 1514 } 1515 1516 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 1517 bool enable) 1518 { 1519 uint32_t data, def; 1520 int i; 1521 1522 for (i = 0; i < adev->sdma.num_instances; i++) { 1523 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1524 /* Enable sdma clock gating */ 1525 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1526 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1527 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1528 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1529 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1530 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1531 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1532 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1533 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1534 if (def != data) 1535 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1536 } else { 1537 /* Disable sdma clock gating */ 1538 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1539 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1540 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1541 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1542 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1543 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1544 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1545 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1546 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1547 if (def != data) 1548 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1549 } 1550 } 1551 } 1552 1553 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 1554 bool enable) 1555 { 1556 uint32_t data, def; 1557 int i; 1558 1559 for (i = 0; i < adev->sdma.num_instances; i++) { 1560 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1561 /* Enable sdma mem light sleep */ 1562 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1563 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1564 if (def != data) 1565 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1566 1567 } else { 1568 /* Disable sdma mem light sleep */ 1569 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1570 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1571 if (def != data) 1572 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1573 1574 } 1575 } 1576 } 1577 1578 static int sdma_v5_0_set_clockgating_state(void *handle, 1579 enum amd_clockgating_state state) 1580 { 1581 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1582 1583 if (amdgpu_sriov_vf(adev)) 1584 return 0; 1585 1586 switch (adev->asic_type) { 1587 case CHIP_NAVI10: 1588 case CHIP_NAVI14: 1589 case CHIP_NAVI12: 1590 sdma_v5_0_update_medium_grain_clock_gating(adev, 1591 state == AMD_CG_STATE_GATE); 1592 sdma_v5_0_update_medium_grain_light_sleep(adev, 1593 state == AMD_CG_STATE_GATE); 1594 break; 1595 default: 1596 break; 1597 } 1598 1599 return 0; 1600 } 1601 1602 static int sdma_v5_0_set_powergating_state(void *handle, 1603 enum amd_powergating_state state) 1604 { 1605 return 0; 1606 } 1607 1608 static void sdma_v5_0_get_clockgating_state(void *handle, u32 *flags) 1609 { 1610 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1611 int data; 1612 1613 if (amdgpu_sriov_vf(adev)) 1614 *flags = 0; 1615 1616 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1617 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL)); 1618 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 1619 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1620 1621 /* AMD_CG_SUPPORT_SDMA_LS */ 1622 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); 1623 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1624 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1625 } 1626 1627 const struct amd_ip_funcs sdma_v5_0_ip_funcs = { 1628 .name = "sdma_v5_0", 1629 .early_init = sdma_v5_0_early_init, 1630 .late_init = NULL, 1631 .sw_init = sdma_v5_0_sw_init, 1632 .sw_fini = sdma_v5_0_sw_fini, 1633 .hw_init = sdma_v5_0_hw_init, 1634 .hw_fini = sdma_v5_0_hw_fini, 1635 .suspend = sdma_v5_0_suspend, 1636 .resume = sdma_v5_0_resume, 1637 .is_idle = sdma_v5_0_is_idle, 1638 .wait_for_idle = sdma_v5_0_wait_for_idle, 1639 .soft_reset = sdma_v5_0_soft_reset, 1640 .set_clockgating_state = sdma_v5_0_set_clockgating_state, 1641 .set_powergating_state = sdma_v5_0_set_powergating_state, 1642 .get_clockgating_state = sdma_v5_0_get_clockgating_state, 1643 }; 1644 1645 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = { 1646 .type = AMDGPU_RING_TYPE_SDMA, 1647 .align_mask = 0xf, 1648 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1649 .support_64bit_ptrs = true, 1650 .vmhub = AMDGPU_GFXHUB_0, 1651 .get_rptr = sdma_v5_0_ring_get_rptr, 1652 .get_wptr = sdma_v5_0_ring_get_wptr, 1653 .set_wptr = sdma_v5_0_ring_set_wptr, 1654 .emit_frame_size = 1655 5 + /* sdma_v5_0_ring_init_cond_exec */ 1656 6 + /* sdma_v5_0_ring_emit_hdp_flush */ 1657 3 + /* hdp_invalidate */ 1658 6 + /* sdma_v5_0_ring_emit_pipeline_sync */ 1659 /* sdma_v5_0_ring_emit_vm_flush */ 1660 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1661 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 + 1662 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */ 1663 .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */ 1664 .emit_ib = sdma_v5_0_ring_emit_ib, 1665 .emit_mem_sync = sdma_v5_0_ring_emit_mem_sync, 1666 .emit_fence = sdma_v5_0_ring_emit_fence, 1667 .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync, 1668 .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush, 1669 .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush, 1670 .test_ring = sdma_v5_0_ring_test_ring, 1671 .test_ib = sdma_v5_0_ring_test_ib, 1672 .insert_nop = sdma_v5_0_ring_insert_nop, 1673 .pad_ib = sdma_v5_0_ring_pad_ib, 1674 .emit_wreg = sdma_v5_0_ring_emit_wreg, 1675 .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait, 1676 .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait, 1677 .init_cond_exec = sdma_v5_0_ring_init_cond_exec, 1678 .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec, 1679 .preempt_ib = sdma_v5_0_ring_preempt_ib, 1680 }; 1681 1682 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev) 1683 { 1684 int i; 1685 1686 for (i = 0; i < adev->sdma.num_instances; i++) { 1687 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs; 1688 adev->sdma.instance[i].ring.me = i; 1689 } 1690 } 1691 1692 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = { 1693 .set = sdma_v5_0_set_trap_irq_state, 1694 .process = sdma_v5_0_process_trap_irq, 1695 }; 1696 1697 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = { 1698 .process = sdma_v5_0_process_illegal_inst_irq, 1699 }; 1700 1701 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev) 1702 { 1703 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1704 adev->sdma.num_instances; 1705 adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs; 1706 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs; 1707 } 1708 1709 /** 1710 * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine 1711 * 1712 * @ib: indirect buffer to copy to 1713 * @src_offset: src GPU address 1714 * @dst_offset: dst GPU address 1715 * @byte_count: number of bytes to xfer 1716 * @tmz: if a secure copy should be used 1717 * 1718 * Copy GPU buffers using the DMA engine (NAVI10). 1719 * Used by the amdgpu ttm implementation to move pages if 1720 * registered as the asic copy callback. 1721 */ 1722 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib, 1723 uint64_t src_offset, 1724 uint64_t dst_offset, 1725 uint32_t byte_count, 1726 bool tmz) 1727 { 1728 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1729 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1730 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 1731 ib->ptr[ib->length_dw++] = byte_count - 1; 1732 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1733 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1734 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1735 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1736 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1737 } 1738 1739 /** 1740 * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine 1741 * 1742 * @ib: indirect buffer to fill 1743 * @src_data: value to write to buffer 1744 * @dst_offset: dst GPU address 1745 * @byte_count: number of bytes to xfer 1746 * 1747 * Fill GPU buffers using the DMA engine (NAVI10). 1748 */ 1749 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib, 1750 uint32_t src_data, 1751 uint64_t dst_offset, 1752 uint32_t byte_count) 1753 { 1754 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1755 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1756 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1757 ib->ptr[ib->length_dw++] = src_data; 1758 ib->ptr[ib->length_dw++] = byte_count - 1; 1759 } 1760 1761 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = { 1762 .copy_max_bytes = 0x400000, 1763 .copy_num_dw = 7, 1764 .emit_copy_buffer = sdma_v5_0_emit_copy_buffer, 1765 1766 .fill_max_bytes = 0x400000, 1767 .fill_num_dw = 5, 1768 .emit_fill_buffer = sdma_v5_0_emit_fill_buffer, 1769 }; 1770 1771 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev) 1772 { 1773 if (adev->mman.buffer_funcs == NULL) { 1774 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs; 1775 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1776 } 1777 } 1778 1779 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = { 1780 .copy_pte_num_dw = 7, 1781 .copy_pte = sdma_v5_0_vm_copy_pte, 1782 .write_pte = sdma_v5_0_vm_write_pte, 1783 .set_pte_pde = sdma_v5_0_vm_set_pte_pde, 1784 }; 1785 1786 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1787 { 1788 unsigned i; 1789 1790 if (adev->vm_manager.vm_pte_funcs == NULL) { 1791 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs; 1792 for (i = 0; i < adev->sdma.num_instances; i++) { 1793 adev->vm_manager.vm_pte_scheds[i] = 1794 &adev->sdma.instance[i].ring.sched; 1795 } 1796 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1797 } 1798 } 1799 1800 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = { 1801 .type = AMD_IP_BLOCK_TYPE_SDMA, 1802 .major = 5, 1803 .minor = 0, 1804 .rev = 0, 1805 .funcs = &sdma_v5_0_ip_funcs, 1806 }; 1807