1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_10_1_0_offset.h" 34 #include "gc/gc_10_1_0_sh_mask.h" 35 #include "hdp/hdp_5_0_0_offset.h" 36 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h" 37 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h" 38 39 #include "soc15_common.h" 40 #include "soc15.h" 41 #include "navi10_sdma_pkt_open.h" 42 #include "nbio_v2_3.h" 43 #include "sdma_v5_0.h" 44 45 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin"); 46 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin"); 47 48 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin"); 49 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin"); 50 51 MODULE_FIRMWARE("amdgpu/navi12_sdma.bin"); 52 MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin"); 53 54 #define SDMA1_REG_OFFSET 0x600 55 #define SDMA0_HYP_DEC_REG_START 0x5880 56 #define SDMA0_HYP_DEC_REG_END 0x5893 57 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 58 59 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev); 60 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev); 61 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev); 62 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev); 63 64 static const struct soc15_reg_golden golden_settings_sdma_5[] = { 65 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), 66 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 67 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 68 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 69 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 70 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 71 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 72 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 73 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 74 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 75 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 76 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00), 77 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), 78 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 79 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 80 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 81 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 82 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 83 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 84 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 85 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 86 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 87 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 88 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00) 89 }; 90 91 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = { 92 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 93 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 94 }; 95 96 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = { 97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 99 }; 100 101 static const struct soc15_reg_golden golden_settings_sdma_nv12[] = { 102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 104 }; 105 106 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 107 { 108 u32 base; 109 110 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 111 internal_offset <= SDMA0_HYP_DEC_REG_END) { 112 base = adev->reg_offset[GC_HWIP][0][1]; 113 if (instance == 1) 114 internal_offset += SDMA1_HYP_DEC_REG_OFFSET; 115 } else { 116 base = adev->reg_offset[GC_HWIP][0][0]; 117 if (instance == 1) 118 internal_offset += SDMA1_REG_OFFSET; 119 } 120 121 return base + internal_offset; 122 } 123 124 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev) 125 { 126 switch (adev->asic_type) { 127 case CHIP_NAVI10: 128 soc15_program_register_sequence(adev, 129 golden_settings_sdma_5, 130 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 131 soc15_program_register_sequence(adev, 132 golden_settings_sdma_nv10, 133 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10)); 134 break; 135 case CHIP_NAVI14: 136 soc15_program_register_sequence(adev, 137 golden_settings_sdma_5, 138 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 139 soc15_program_register_sequence(adev, 140 golden_settings_sdma_nv14, 141 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14)); 142 break; 143 case CHIP_NAVI12: 144 soc15_program_register_sequence(adev, 145 golden_settings_sdma_5, 146 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 147 soc15_program_register_sequence(adev, 148 golden_settings_sdma_nv12, 149 (const u32)ARRAY_SIZE(golden_settings_sdma_nv12)); 150 break; 151 default: 152 break; 153 } 154 } 155 156 /** 157 * sdma_v5_0_init_microcode - load ucode images from disk 158 * 159 * @adev: amdgpu_device pointer 160 * 161 * Use the firmware interface to load the ucode images into 162 * the driver (not loaded into hw). 163 * Returns 0 on success, error on failure. 164 */ 165 166 // emulation only, won't work on real chip 167 // navi10 real chip need to use PSP to load firmware 168 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev) 169 { 170 const char *chip_name; 171 char fw_name[30]; 172 int err = 0, i; 173 struct amdgpu_firmware_info *info = NULL; 174 const struct common_firmware_header *header = NULL; 175 const struct sdma_firmware_header_v1_0 *hdr; 176 177 DRM_DEBUG("\n"); 178 179 switch (adev->asic_type) { 180 case CHIP_NAVI10: 181 chip_name = "navi10"; 182 break; 183 case CHIP_NAVI14: 184 chip_name = "navi14"; 185 break; 186 case CHIP_NAVI12: 187 chip_name = "navi12"; 188 break; 189 default: 190 BUG(); 191 } 192 193 for (i = 0; i < adev->sdma.num_instances; i++) { 194 if (i == 0) 195 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 196 else 197 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 198 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 199 if (err) 200 goto out; 201 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 202 if (err) 203 goto out; 204 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 205 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 206 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 207 if (adev->sdma.instance[i].feature_version >= 20) 208 adev->sdma.instance[i].burst_nop = true; 209 DRM_DEBUG("psp_load == '%s'\n", 210 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 211 212 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 213 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 214 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 215 info->fw = adev->sdma.instance[i].fw; 216 header = (const struct common_firmware_header *)info->fw->data; 217 adev->firmware.fw_size += 218 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 219 } 220 } 221 out: 222 if (err) { 223 DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name); 224 for (i = 0; i < adev->sdma.num_instances; i++) { 225 release_firmware(adev->sdma.instance[i].fw); 226 adev->sdma.instance[i].fw = NULL; 227 } 228 } 229 return err; 230 } 231 232 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring) 233 { 234 unsigned ret; 235 236 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); 237 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 238 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 239 amdgpu_ring_write(ring, 1); 240 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ 241 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ 242 243 return ret; 244 } 245 246 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring, 247 unsigned offset) 248 { 249 unsigned cur; 250 251 BUG_ON(offset > ring->buf_mask); 252 BUG_ON(ring->ring[offset] != 0x55aa55aa); 253 254 cur = (ring->wptr - 1) & ring->buf_mask; 255 if (cur > offset) 256 ring->ring[offset] = cur - offset; 257 else 258 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 259 } 260 261 /** 262 * sdma_v5_0_ring_get_rptr - get the current read pointer 263 * 264 * @ring: amdgpu ring pointer 265 * 266 * Get the current rptr from the hardware (NAVI10+). 267 */ 268 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring) 269 { 270 u64 *rptr; 271 272 /* XXX check if swapping is necessary on BE */ 273 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 274 275 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 276 return ((*rptr) >> 2); 277 } 278 279 /** 280 * sdma_v5_0_ring_get_wptr - get the current write pointer 281 * 282 * @ring: amdgpu ring pointer 283 * 284 * Get the current wptr from the hardware (NAVI10+). 285 */ 286 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring) 287 { 288 struct amdgpu_device *adev = ring->adev; 289 u64 *wptr = NULL; 290 uint64_t local_wptr = 0; 291 292 if (ring->use_doorbell) { 293 /* XXX check if swapping is necessary on BE */ 294 wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]); 295 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr); 296 *wptr = (*wptr) >> 2; 297 DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr); 298 } else { 299 u32 lowbit, highbit; 300 301 wptr = &local_wptr; 302 lowbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2; 303 highbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2; 304 305 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n", 306 ring->me, highbit, lowbit); 307 *wptr = highbit; 308 *wptr = (*wptr) << 32; 309 *wptr |= lowbit; 310 } 311 312 return *wptr; 313 } 314 315 /** 316 * sdma_v5_0_ring_set_wptr - commit the write pointer 317 * 318 * @ring: amdgpu ring pointer 319 * 320 * Write the wptr back to the hardware (NAVI10+). 321 */ 322 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring) 323 { 324 struct amdgpu_device *adev = ring->adev; 325 326 DRM_DEBUG("Setting write pointer\n"); 327 if (ring->use_doorbell) { 328 DRM_DEBUG("Using doorbell -- " 329 "wptr_offs == 0x%08x " 330 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 331 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 332 ring->wptr_offs, 333 lower_32_bits(ring->wptr << 2), 334 upper_32_bits(ring->wptr << 2)); 335 /* XXX check if swapping is necessary on BE */ 336 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); 337 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); 338 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 339 ring->doorbell_index, ring->wptr << 2); 340 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 341 } else { 342 DRM_DEBUG("Not using doorbell -- " 343 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 344 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 345 ring->me, 346 lower_32_bits(ring->wptr << 2), 347 ring->me, 348 upper_32_bits(ring->wptr << 2)); 349 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), 350 lower_32_bits(ring->wptr << 2)); 351 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), 352 upper_32_bits(ring->wptr << 2)); 353 } 354 } 355 356 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 357 { 358 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 359 int i; 360 361 for (i = 0; i < count; i++) 362 if (sdma && sdma->burst_nop && (i == 0)) 363 amdgpu_ring_write(ring, ring->funcs->nop | 364 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 365 else 366 amdgpu_ring_write(ring, ring->funcs->nop); 367 } 368 369 /** 370 * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine 371 * 372 * @ring: amdgpu ring pointer 373 * @ib: IB object to schedule 374 * 375 * Schedule an IB in the DMA ring (NAVI10). 376 */ 377 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 378 struct amdgpu_job *job, 379 struct amdgpu_ib *ib, 380 uint32_t flags) 381 { 382 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 383 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 384 385 /* Invalidate L2, because if we don't do it, we might get stale cache 386 * lines from previous IBs. 387 */ 388 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ)); 389 amdgpu_ring_write(ring, 0); 390 amdgpu_ring_write(ring, (SDMA_GCR_GL2_INV | 391 SDMA_GCR_GL2_WB | 392 SDMA_GCR_GLM_INV | 393 SDMA_GCR_GLM_WB) << 16); 394 amdgpu_ring_write(ring, 0xffffff80); 395 amdgpu_ring_write(ring, 0xffff); 396 397 /* An IB packet must end on a 8 DW boundary--the next dword 398 * must be on a 8-dword boundary. Our IB packet below is 6 399 * dwords long, thus add x number of NOPs, such that, in 400 * modular arithmetic, 401 * wptr + 6 + x = 8k, k >= 0, which in C is, 402 * (wptr + 6 + x) % 8 = 0. 403 * The expression below, is a solution of x. 404 */ 405 sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 406 407 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 408 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 409 /* base must be 32 byte aligned */ 410 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 411 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 412 amdgpu_ring_write(ring, ib->length_dw); 413 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 414 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 415 } 416 417 /** 418 * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 419 * 420 * @ring: amdgpu ring pointer 421 * 422 * Emit an hdp flush packet on the requested DMA ring. 423 */ 424 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 425 { 426 struct amdgpu_device *adev = ring->adev; 427 u32 ref_and_mask = 0; 428 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 429 430 if (ring->me == 0) 431 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; 432 else 433 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; 434 435 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 436 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 437 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 438 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 439 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 440 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 441 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 442 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 443 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 444 } 445 446 /** 447 * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring 448 * 449 * @ring: amdgpu ring pointer 450 * @fence: amdgpu fence object 451 * 452 * Add a DMA fence packet to the ring to write 453 * the fence seq number and DMA trap packet to generate 454 * an interrupt if needed (NAVI10). 455 */ 456 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 457 unsigned flags) 458 { 459 struct amdgpu_device *adev = ring->adev; 460 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 461 /* write the fence */ 462 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 463 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 464 /* zero in first two bits */ 465 BUG_ON(addr & 0x3); 466 amdgpu_ring_write(ring, lower_32_bits(addr)); 467 amdgpu_ring_write(ring, upper_32_bits(addr)); 468 amdgpu_ring_write(ring, lower_32_bits(seq)); 469 470 /* optionally write high bits as well */ 471 if (write64bit) { 472 addr += 4; 473 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 474 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 475 /* zero in first two bits */ 476 BUG_ON(addr & 0x3); 477 amdgpu_ring_write(ring, lower_32_bits(addr)); 478 amdgpu_ring_write(ring, upper_32_bits(addr)); 479 amdgpu_ring_write(ring, upper_32_bits(seq)); 480 } 481 482 /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */ 483 if ((flags & AMDGPU_FENCE_FLAG_INT) && adev->pdev->device != 0x50) { 484 /* generate an interrupt */ 485 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 486 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 487 } 488 } 489 490 491 /** 492 * sdma_v5_0_gfx_stop - stop the gfx async dma engines 493 * 494 * @adev: amdgpu_device pointer 495 * 496 * Stop the gfx async dma ring buffers (NAVI10). 497 */ 498 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev) 499 { 500 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 501 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 502 u32 rb_cntl, ib_cntl; 503 int i; 504 505 if ((adev->mman.buffer_funcs_ring == sdma0) || 506 (adev->mman.buffer_funcs_ring == sdma1)) 507 amdgpu_ttm_set_buffer_funcs_status(adev, false); 508 509 for (i = 0; i < adev->sdma.num_instances; i++) { 510 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 511 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 512 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 513 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 514 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 515 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 516 } 517 518 sdma0->sched.ready = false; 519 sdma1->sched.ready = false; 520 } 521 522 /** 523 * sdma_v5_0_rlc_stop - stop the compute async dma engines 524 * 525 * @adev: amdgpu_device pointer 526 * 527 * Stop the compute async dma queues (NAVI10). 528 */ 529 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev) 530 { 531 /* XXX todo */ 532 } 533 534 /** 535 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch 536 * 537 * @adev: amdgpu_device pointer 538 * @enable: enable/disable the DMA MEs context switch. 539 * 540 * Halt or unhalt the async dma engines context switch (NAVI10). 541 */ 542 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 543 { 544 u32 f32_cntl, phase_quantum = 0; 545 int i; 546 547 if (amdgpu_sdma_phase_quantum) { 548 unsigned value = amdgpu_sdma_phase_quantum; 549 unsigned unit = 0; 550 551 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 552 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 553 value = (value + 1) >> 1; 554 unit++; 555 } 556 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 557 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 558 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 559 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 560 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 561 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 562 WARN_ONCE(1, 563 "clamping sdma_phase_quantum to %uK clock cycles\n", 564 value << unit); 565 } 566 phase_quantum = 567 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 568 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 569 } 570 571 for (i = 0; i < adev->sdma.num_instances; i++) { 572 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 573 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 574 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 575 if (enable && amdgpu_sdma_phase_quantum) { 576 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 577 phase_quantum); 578 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 579 phase_quantum); 580 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 581 phase_quantum); 582 } 583 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 584 } 585 586 } 587 588 /** 589 * sdma_v5_0_enable - stop the async dma engines 590 * 591 * @adev: amdgpu_device pointer 592 * @enable: enable/disable the DMA MEs. 593 * 594 * Halt or unhalt the async dma engines (NAVI10). 595 */ 596 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable) 597 { 598 u32 f32_cntl; 599 int i; 600 601 if (enable == false) { 602 sdma_v5_0_gfx_stop(adev); 603 sdma_v5_0_rlc_stop(adev); 604 } 605 606 for (i = 0; i < adev->sdma.num_instances; i++) { 607 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 608 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 609 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 610 } 611 } 612 613 /** 614 * sdma_v5_0_gfx_resume - setup and start the async dma engines 615 * 616 * @adev: amdgpu_device pointer 617 * 618 * Set up the gfx DMA ring buffers and enable them (NAVI10). 619 * Returns 0 for success, error for failure. 620 */ 621 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev) 622 { 623 struct amdgpu_ring *ring; 624 u32 rb_cntl, ib_cntl; 625 u32 rb_bufsz; 626 u32 wb_offset; 627 u32 doorbell; 628 u32 doorbell_offset; 629 u32 temp; 630 u32 wptr_poll_cntl; 631 u64 wptr_gpu_addr; 632 int i, r; 633 634 for (i = 0; i < adev->sdma.num_instances; i++) { 635 ring = &adev->sdma.instance[i].ring; 636 wb_offset = (ring->rptr_offs * 4); 637 638 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 639 640 /* Set ring buffer size in dwords */ 641 rb_bufsz = order_base_2(ring->ring_size / 4); 642 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 643 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 644 #ifdef __BIG_ENDIAN 645 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 646 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 647 RPTR_WRITEBACK_SWAP_ENABLE, 1); 648 #endif 649 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 650 651 /* Initialize the ring buffer's read and write pointers */ 652 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 653 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 654 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 655 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 656 657 /* setup the wptr shadow polling */ 658 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 659 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 660 lower_32_bits(wptr_gpu_addr)); 661 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 662 upper_32_bits(wptr_gpu_addr)); 663 wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, 664 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 665 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 666 SDMA0_GFX_RB_WPTR_POLL_CNTL, 667 F32_POLL_ENABLE, 1); 668 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 669 wptr_poll_cntl); 670 671 /* set the wb address whether it's enabled or not */ 672 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 673 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 674 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 675 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 676 677 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 678 679 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 680 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 681 682 ring->wptr = 0; 683 684 /* before programing wptr to a less value, need set minor_ptr_update first */ 685 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 686 687 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 688 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); 689 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 690 } 691 692 doorbell = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 693 doorbell_offset = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); 694 695 if (ring->use_doorbell) { 696 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 697 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 698 OFFSET, ring->doorbell_index); 699 } else { 700 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 701 } 702 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 703 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 704 705 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 706 ring->doorbell_index, 20); 707 708 if (amdgpu_sriov_vf(adev)) 709 sdma_v5_0_ring_set_wptr(ring); 710 711 /* set minor_ptr_update to 0 after wptr programed */ 712 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 713 714 /* set utc l1 enable flag always to 1 */ 715 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 716 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 717 718 /* enable MCBP */ 719 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); 720 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 721 722 /* Set up RESP_MODE to non-copy addresses */ 723 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); 724 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 725 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 726 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); 727 728 /* program default cache read and write policy */ 729 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); 730 /* clean read policy and write policy bits */ 731 temp &= 0xFF0FFF; 732 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14)); 733 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); 734 735 if (!amdgpu_sriov_vf(adev)) { 736 /* unhalt engine */ 737 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 738 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 739 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 740 } 741 742 /* enable DMA RB */ 743 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 744 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 745 746 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 747 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 748 #ifdef __BIG_ENDIAN 749 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 750 #endif 751 /* enable DMA IBs */ 752 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 753 754 ring->sched.ready = true; 755 756 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 757 sdma_v5_0_ctx_switch_enable(adev, true); 758 sdma_v5_0_enable(adev, true); 759 } 760 761 r = amdgpu_ring_test_helper(ring); 762 if (r) 763 return r; 764 765 if (adev->mman.buffer_funcs_ring == ring) 766 amdgpu_ttm_set_buffer_funcs_status(adev, true); 767 } 768 769 return 0; 770 } 771 772 /** 773 * sdma_v5_0_rlc_resume - setup and start the async dma engines 774 * 775 * @adev: amdgpu_device pointer 776 * 777 * Set up the compute DMA queues and enable them (NAVI10). 778 * Returns 0 for success, error for failure. 779 */ 780 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev) 781 { 782 return 0; 783 } 784 785 /** 786 * sdma_v5_0_load_microcode - load the sDMA ME ucode 787 * 788 * @adev: amdgpu_device pointer 789 * 790 * Loads the sDMA0/1 ucode. 791 * Returns 0 for success, -EINVAL if the ucode is not available. 792 */ 793 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev) 794 { 795 const struct sdma_firmware_header_v1_0 *hdr; 796 const __le32 *fw_data; 797 u32 fw_size; 798 int i, j; 799 800 /* halt the MEs */ 801 sdma_v5_0_enable(adev, false); 802 803 for (i = 0; i < adev->sdma.num_instances; i++) { 804 if (!adev->sdma.instance[i].fw) 805 return -EINVAL; 806 807 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 808 amdgpu_ucode_print_sdma_hdr(&hdr->header); 809 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 810 811 fw_data = (const __le32 *) 812 (adev->sdma.instance[i].fw->data + 813 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 814 815 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 816 817 for (j = 0; j < fw_size; j++) { 818 if (amdgpu_emu_mode == 1 && j % 500 == 0) 819 msleep(1); 820 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 821 } 822 823 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 824 } 825 826 return 0; 827 } 828 829 /** 830 * sdma_v5_0_start - setup and start the async dma engines 831 * 832 * @adev: amdgpu_device pointer 833 * 834 * Set up the DMA engines and enable them (NAVI10). 835 * Returns 0 for success, error for failure. 836 */ 837 static int sdma_v5_0_start(struct amdgpu_device *adev) 838 { 839 int r = 0; 840 841 if (amdgpu_sriov_vf(adev)) { 842 sdma_v5_0_ctx_switch_enable(adev, false); 843 sdma_v5_0_enable(adev, false); 844 845 /* set RB registers */ 846 r = sdma_v5_0_gfx_resume(adev); 847 return r; 848 } 849 850 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 851 r = sdma_v5_0_load_microcode(adev); 852 if (r) 853 return r; 854 855 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */ 856 if (amdgpu_emu_mode == 1 && adev->pdev->device == 0x4d) 857 msleep(1000); 858 } 859 860 /* unhalt the MEs */ 861 sdma_v5_0_enable(adev, true); 862 /* enable sdma ring preemption */ 863 sdma_v5_0_ctx_switch_enable(adev, true); 864 865 /* start the gfx rings and rlc compute queues */ 866 r = sdma_v5_0_gfx_resume(adev); 867 if (r) 868 return r; 869 r = sdma_v5_0_rlc_resume(adev); 870 871 return r; 872 } 873 874 /** 875 * sdma_v5_0_ring_test_ring - simple async dma engine test 876 * 877 * @ring: amdgpu_ring structure holding ring information 878 * 879 * Test the DMA engine by writing using it to write an 880 * value to memory. (NAVI10). 881 * Returns 0 for success, error for failure. 882 */ 883 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring) 884 { 885 struct amdgpu_device *adev = ring->adev; 886 unsigned i; 887 unsigned index; 888 int r; 889 u32 tmp; 890 u64 gpu_addr; 891 892 r = amdgpu_device_wb_get(adev, &index); 893 if (r) { 894 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 895 return r; 896 } 897 898 gpu_addr = adev->wb.gpu_addr + (index * 4); 899 tmp = 0xCAFEDEAD; 900 adev->wb.wb[index] = cpu_to_le32(tmp); 901 902 r = amdgpu_ring_alloc(ring, 5); 903 if (r) { 904 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 905 amdgpu_device_wb_free(adev, index); 906 return r; 907 } 908 909 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 910 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 911 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 912 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 913 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 914 amdgpu_ring_write(ring, 0xDEADBEEF); 915 amdgpu_ring_commit(ring); 916 917 for (i = 0; i < adev->usec_timeout; i++) { 918 tmp = le32_to_cpu(adev->wb.wb[index]); 919 if (tmp == 0xDEADBEEF) 920 break; 921 if (amdgpu_emu_mode == 1) 922 msleep(1); 923 else 924 udelay(1); 925 } 926 927 if (i >= adev->usec_timeout) 928 r = -ETIMEDOUT; 929 930 amdgpu_device_wb_free(adev, index); 931 932 return r; 933 } 934 935 /** 936 * sdma_v5_0_ring_test_ib - test an IB on the DMA engine 937 * 938 * @ring: amdgpu_ring structure holding ring information 939 * 940 * Test a simple IB in the DMA ring (NAVI10). 941 * Returns 0 on success, error on failure. 942 */ 943 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 944 { 945 struct amdgpu_device *adev = ring->adev; 946 struct amdgpu_ib ib; 947 struct dma_fence *f = NULL; 948 unsigned index; 949 long r; 950 u32 tmp = 0; 951 u64 gpu_addr; 952 953 r = amdgpu_device_wb_get(adev, &index); 954 if (r) { 955 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 956 return r; 957 } 958 959 gpu_addr = adev->wb.gpu_addr + (index * 4); 960 tmp = 0xCAFEDEAD; 961 adev->wb.wb[index] = cpu_to_le32(tmp); 962 memset(&ib, 0, sizeof(ib)); 963 r = amdgpu_ib_get(adev, NULL, 256, &ib); 964 if (r) { 965 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 966 goto err0; 967 } 968 969 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 970 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 971 ib.ptr[1] = lower_32_bits(gpu_addr); 972 ib.ptr[2] = upper_32_bits(gpu_addr); 973 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 974 ib.ptr[4] = 0xDEADBEEF; 975 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 976 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 977 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 978 ib.length_dw = 8; 979 980 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 981 if (r) 982 goto err1; 983 984 r = dma_fence_wait_timeout(f, false, timeout); 985 if (r == 0) { 986 DRM_ERROR("amdgpu: IB test timed out\n"); 987 r = -ETIMEDOUT; 988 goto err1; 989 } else if (r < 0) { 990 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 991 goto err1; 992 } 993 tmp = le32_to_cpu(adev->wb.wb[index]); 994 if (tmp == 0xDEADBEEF) 995 r = 0; 996 else 997 r = -EINVAL; 998 999 err1: 1000 amdgpu_ib_free(adev, &ib, NULL); 1001 dma_fence_put(f); 1002 err0: 1003 amdgpu_device_wb_free(adev, index); 1004 return r; 1005 } 1006 1007 1008 /** 1009 * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART 1010 * 1011 * @ib: indirect buffer to fill with commands 1012 * @pe: addr of the page entry 1013 * @src: src addr to copy from 1014 * @count: number of page entries to update 1015 * 1016 * Update PTEs by copying them from the GART using sDMA (NAVI10). 1017 */ 1018 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib, 1019 uint64_t pe, uint64_t src, 1020 unsigned count) 1021 { 1022 unsigned bytes = count * 8; 1023 1024 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1025 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1026 ib->ptr[ib->length_dw++] = bytes - 1; 1027 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1028 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1029 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1030 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1031 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1032 1033 } 1034 1035 /** 1036 * sdma_v5_0_vm_write_pte - update PTEs by writing them manually 1037 * 1038 * @ib: indirect buffer to fill with commands 1039 * @pe: addr of the page entry 1040 * @addr: dst addr to write into pe 1041 * @count: number of page entries to update 1042 * @incr: increase next addr by incr bytes 1043 * @flags: access flags 1044 * 1045 * Update PTEs by writing them manually using sDMA (NAVI10). 1046 */ 1047 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1048 uint64_t value, unsigned count, 1049 uint32_t incr) 1050 { 1051 unsigned ndw = count * 2; 1052 1053 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1054 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1055 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1056 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1057 ib->ptr[ib->length_dw++] = ndw - 1; 1058 for (; ndw > 0; ndw -= 2) { 1059 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1060 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1061 value += incr; 1062 } 1063 } 1064 1065 /** 1066 * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA 1067 * 1068 * @ib: indirect buffer to fill with commands 1069 * @pe: addr of the page entry 1070 * @addr: dst addr to write into pe 1071 * @count: number of page entries to update 1072 * @incr: increase next addr by incr bytes 1073 * @flags: access flags 1074 * 1075 * Update the page tables using sDMA (NAVI10). 1076 */ 1077 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1078 uint64_t pe, 1079 uint64_t addr, unsigned count, 1080 uint32_t incr, uint64_t flags) 1081 { 1082 /* for physically contiguous pages (vram) */ 1083 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1084 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1085 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1086 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1087 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1088 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1089 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1090 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1091 ib->ptr[ib->length_dw++] = 0; 1092 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1093 } 1094 1095 /** 1096 * sdma_v5_0_ring_pad_ib - pad the IB 1097 * @ib: indirect buffer to fill with padding 1098 * 1099 * Pad the IB with NOPs to a boundary multiple of 8. 1100 */ 1101 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1102 { 1103 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1104 u32 pad_count; 1105 int i; 1106 1107 pad_count = (-ib->length_dw) & 0x7; 1108 for (i = 0; i < pad_count; i++) 1109 if (sdma && sdma->burst_nop && (i == 0)) 1110 ib->ptr[ib->length_dw++] = 1111 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1112 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1113 else 1114 ib->ptr[ib->length_dw++] = 1115 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1116 } 1117 1118 1119 /** 1120 * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline 1121 * 1122 * @ring: amdgpu_ring pointer 1123 * 1124 * Make sure all previous operations are completed (CIK). 1125 */ 1126 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1127 { 1128 uint32_t seq = ring->fence_drv.sync_seq; 1129 uint64_t addr = ring->fence_drv.gpu_addr; 1130 1131 /* wait for idle */ 1132 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1133 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1134 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1135 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1136 amdgpu_ring_write(ring, addr & 0xfffffffc); 1137 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1138 amdgpu_ring_write(ring, seq); /* reference */ 1139 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1140 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1141 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1142 } 1143 1144 1145 /** 1146 * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA 1147 * 1148 * @ring: amdgpu_ring pointer 1149 * @vm: amdgpu_vm pointer 1150 * 1151 * Update the page table base and flush the VM TLB 1152 * using sDMA (NAVI10). 1153 */ 1154 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1155 unsigned vmid, uint64_t pd_addr) 1156 { 1157 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1158 } 1159 1160 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring, 1161 uint32_t reg, uint32_t val) 1162 { 1163 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1164 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1165 amdgpu_ring_write(ring, reg); 1166 amdgpu_ring_write(ring, val); 1167 } 1168 1169 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1170 uint32_t val, uint32_t mask) 1171 { 1172 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1173 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1174 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1175 amdgpu_ring_write(ring, reg << 2); 1176 amdgpu_ring_write(ring, 0); 1177 amdgpu_ring_write(ring, val); /* reference */ 1178 amdgpu_ring_write(ring, mask); /* mask */ 1179 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1180 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1181 } 1182 1183 static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1184 uint32_t reg0, uint32_t reg1, 1185 uint32_t ref, uint32_t mask) 1186 { 1187 amdgpu_ring_emit_wreg(ring, reg0, ref); 1188 /* wait for a cycle to reset vm_inv_eng*_ack */ 1189 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1190 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1191 } 1192 1193 static int sdma_v5_0_early_init(void *handle) 1194 { 1195 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1196 1197 adev->sdma.num_instances = 2; 1198 1199 sdma_v5_0_set_ring_funcs(adev); 1200 sdma_v5_0_set_buffer_funcs(adev); 1201 sdma_v5_0_set_vm_pte_funcs(adev); 1202 sdma_v5_0_set_irq_funcs(adev); 1203 1204 return 0; 1205 } 1206 1207 1208 static int sdma_v5_0_sw_init(void *handle) 1209 { 1210 struct amdgpu_ring *ring; 1211 int r, i; 1212 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1213 1214 /* SDMA trap event */ 1215 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, 1216 SDMA0_5_0__SRCID__SDMA_TRAP, 1217 &adev->sdma.trap_irq); 1218 if (r) 1219 return r; 1220 1221 /* SDMA trap event */ 1222 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, 1223 SDMA1_5_0__SRCID__SDMA_TRAP, 1224 &adev->sdma.trap_irq); 1225 if (r) 1226 return r; 1227 1228 r = sdma_v5_0_init_microcode(adev); 1229 if (r) { 1230 DRM_ERROR("Failed to load sdma firmware!\n"); 1231 return r; 1232 } 1233 1234 for (i = 0; i < adev->sdma.num_instances; i++) { 1235 ring = &adev->sdma.instance[i].ring; 1236 ring->ring_obj = NULL; 1237 ring->use_doorbell = true; 1238 1239 DRM_INFO("use_doorbell being set to: [%s]\n", 1240 ring->use_doorbell?"true":"false"); 1241 1242 ring->doorbell_index = (i == 0) ? 1243 (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset 1244 : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset 1245 1246 sprintf(ring->name, "sdma%d", i); 1247 r = amdgpu_ring_init(adev, ring, 1024, 1248 &adev->sdma.trap_irq, 1249 (i == 0) ? 1250 AMDGPU_SDMA_IRQ_INSTANCE0 : 1251 AMDGPU_SDMA_IRQ_INSTANCE1); 1252 if (r) 1253 return r; 1254 } 1255 1256 return r; 1257 } 1258 1259 static int sdma_v5_0_sw_fini(void *handle) 1260 { 1261 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1262 int i; 1263 1264 for (i = 0; i < adev->sdma.num_instances; i++) 1265 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1266 1267 return 0; 1268 } 1269 1270 static int sdma_v5_0_hw_init(void *handle) 1271 { 1272 int r; 1273 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1274 1275 sdma_v5_0_init_golden_registers(adev); 1276 1277 r = sdma_v5_0_start(adev); 1278 1279 return r; 1280 } 1281 1282 static int sdma_v5_0_hw_fini(void *handle) 1283 { 1284 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1285 1286 if (amdgpu_sriov_vf(adev)) 1287 return 0; 1288 1289 sdma_v5_0_ctx_switch_enable(adev, false); 1290 sdma_v5_0_enable(adev, false); 1291 1292 return 0; 1293 } 1294 1295 static int sdma_v5_0_suspend(void *handle) 1296 { 1297 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1298 1299 return sdma_v5_0_hw_fini(adev); 1300 } 1301 1302 static int sdma_v5_0_resume(void *handle) 1303 { 1304 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1305 1306 return sdma_v5_0_hw_init(adev); 1307 } 1308 1309 static bool sdma_v5_0_is_idle(void *handle) 1310 { 1311 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1312 u32 i; 1313 1314 for (i = 0; i < adev->sdma.num_instances; i++) { 1315 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1316 1317 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1318 return false; 1319 } 1320 1321 return true; 1322 } 1323 1324 static int sdma_v5_0_wait_for_idle(void *handle) 1325 { 1326 unsigned i; 1327 u32 sdma0, sdma1; 1328 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1329 1330 for (i = 0; i < adev->usec_timeout; i++) { 1331 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1332 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1333 1334 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1335 return 0; 1336 udelay(1); 1337 } 1338 return -ETIMEDOUT; 1339 } 1340 1341 static int sdma_v5_0_soft_reset(void *handle) 1342 { 1343 /* todo */ 1344 1345 return 0; 1346 } 1347 1348 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring) 1349 { 1350 int i, r = 0; 1351 struct amdgpu_device *adev = ring->adev; 1352 u32 index = 0; 1353 u64 sdma_gfx_preempt; 1354 1355 amdgpu_sdma_get_index_from_ring(ring, &index); 1356 if (index == 0) 1357 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT; 1358 else 1359 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT; 1360 1361 /* assert preemption condition */ 1362 amdgpu_ring_set_preempt_cond_exec(ring, false); 1363 1364 /* emit the trailing fence */ 1365 ring->trail_seq += 1; 1366 amdgpu_ring_alloc(ring, 10); 1367 sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1368 ring->trail_seq, 0); 1369 amdgpu_ring_commit(ring); 1370 1371 /* assert IB preemption */ 1372 WREG32(sdma_gfx_preempt, 1); 1373 1374 /* poll the trailing fence */ 1375 for (i = 0; i < adev->usec_timeout; i++) { 1376 if (ring->trail_seq == 1377 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1378 break; 1379 udelay(1); 1380 } 1381 1382 if (i >= adev->usec_timeout) { 1383 r = -EINVAL; 1384 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1385 } 1386 1387 /* deassert IB preemption */ 1388 WREG32(sdma_gfx_preempt, 0); 1389 1390 /* deassert the preemption condition */ 1391 amdgpu_ring_set_preempt_cond_exec(ring, true); 1392 return r; 1393 } 1394 1395 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev, 1396 struct amdgpu_irq_src *source, 1397 unsigned type, 1398 enum amdgpu_interrupt_state state) 1399 { 1400 u32 sdma_cntl; 1401 1402 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ? 1403 sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) : 1404 sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL); 1405 1406 sdma_cntl = RREG32(reg_offset); 1407 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1408 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1409 WREG32(reg_offset, sdma_cntl); 1410 1411 return 0; 1412 } 1413 1414 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev, 1415 struct amdgpu_irq_src *source, 1416 struct amdgpu_iv_entry *entry) 1417 { 1418 DRM_DEBUG("IH: SDMA trap\n"); 1419 switch (entry->client_id) { 1420 case SOC15_IH_CLIENTID_SDMA0: 1421 switch (entry->ring_id) { 1422 case 0: 1423 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1424 break; 1425 case 1: 1426 /* XXX compute */ 1427 break; 1428 case 2: 1429 /* XXX compute */ 1430 break; 1431 case 3: 1432 /* XXX page queue*/ 1433 break; 1434 } 1435 break; 1436 case SOC15_IH_CLIENTID_SDMA1: 1437 switch (entry->ring_id) { 1438 case 0: 1439 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1440 break; 1441 case 1: 1442 /* XXX compute */ 1443 break; 1444 case 2: 1445 /* XXX compute */ 1446 break; 1447 case 3: 1448 /* XXX page queue*/ 1449 break; 1450 } 1451 break; 1452 } 1453 return 0; 1454 } 1455 1456 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1457 struct amdgpu_irq_src *source, 1458 struct amdgpu_iv_entry *entry) 1459 { 1460 return 0; 1461 } 1462 1463 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 1464 bool enable) 1465 { 1466 uint32_t data, def; 1467 int i; 1468 1469 for (i = 0; i < adev->sdma.num_instances; i++) { 1470 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1471 /* Enable sdma clock gating */ 1472 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1473 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1474 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1475 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1476 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1477 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1478 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1479 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1480 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1481 if (def != data) 1482 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1483 } else { 1484 /* Disable sdma clock gating */ 1485 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1486 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1487 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1488 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1489 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1490 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1491 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1492 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1493 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1494 if (def != data) 1495 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1496 } 1497 } 1498 } 1499 1500 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 1501 bool enable) 1502 { 1503 uint32_t data, def; 1504 int i; 1505 1506 for (i = 0; i < adev->sdma.num_instances; i++) { 1507 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1508 /* Enable sdma mem light sleep */ 1509 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1510 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1511 if (def != data) 1512 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1513 1514 } else { 1515 /* Disable sdma mem light sleep */ 1516 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1517 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1518 if (def != data) 1519 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1520 1521 } 1522 } 1523 } 1524 1525 static int sdma_v5_0_set_clockgating_state(void *handle, 1526 enum amd_clockgating_state state) 1527 { 1528 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1529 1530 if (amdgpu_sriov_vf(adev)) 1531 return 0; 1532 1533 switch (adev->asic_type) { 1534 case CHIP_NAVI10: 1535 case CHIP_NAVI14: 1536 case CHIP_NAVI12: 1537 sdma_v5_0_update_medium_grain_clock_gating(adev, 1538 state == AMD_CG_STATE_GATE); 1539 sdma_v5_0_update_medium_grain_light_sleep(adev, 1540 state == AMD_CG_STATE_GATE); 1541 break; 1542 default: 1543 break; 1544 } 1545 1546 return 0; 1547 } 1548 1549 static int sdma_v5_0_set_powergating_state(void *handle, 1550 enum amd_powergating_state state) 1551 { 1552 return 0; 1553 } 1554 1555 static void sdma_v5_0_get_clockgating_state(void *handle, u32 *flags) 1556 { 1557 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1558 int data; 1559 1560 if (amdgpu_sriov_vf(adev)) 1561 *flags = 0; 1562 1563 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1564 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL)); 1565 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 1566 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1567 1568 /* AMD_CG_SUPPORT_SDMA_LS */ 1569 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); 1570 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1571 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1572 } 1573 1574 const struct amd_ip_funcs sdma_v5_0_ip_funcs = { 1575 .name = "sdma_v5_0", 1576 .early_init = sdma_v5_0_early_init, 1577 .late_init = NULL, 1578 .sw_init = sdma_v5_0_sw_init, 1579 .sw_fini = sdma_v5_0_sw_fini, 1580 .hw_init = sdma_v5_0_hw_init, 1581 .hw_fini = sdma_v5_0_hw_fini, 1582 .suspend = sdma_v5_0_suspend, 1583 .resume = sdma_v5_0_resume, 1584 .is_idle = sdma_v5_0_is_idle, 1585 .wait_for_idle = sdma_v5_0_wait_for_idle, 1586 .soft_reset = sdma_v5_0_soft_reset, 1587 .set_clockgating_state = sdma_v5_0_set_clockgating_state, 1588 .set_powergating_state = sdma_v5_0_set_powergating_state, 1589 .get_clockgating_state = sdma_v5_0_get_clockgating_state, 1590 }; 1591 1592 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = { 1593 .type = AMDGPU_RING_TYPE_SDMA, 1594 .align_mask = 0xf, 1595 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1596 .support_64bit_ptrs = true, 1597 .vmhub = AMDGPU_GFXHUB_0, 1598 .get_rptr = sdma_v5_0_ring_get_rptr, 1599 .get_wptr = sdma_v5_0_ring_get_wptr, 1600 .set_wptr = sdma_v5_0_ring_set_wptr, 1601 .emit_frame_size = 1602 5 + /* sdma_v5_0_ring_init_cond_exec */ 1603 6 + /* sdma_v5_0_ring_emit_hdp_flush */ 1604 3 + /* hdp_invalidate */ 1605 6 + /* sdma_v5_0_ring_emit_pipeline_sync */ 1606 /* sdma_v5_0_ring_emit_vm_flush */ 1607 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1608 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 + 1609 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */ 1610 .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */ 1611 .emit_ib = sdma_v5_0_ring_emit_ib, 1612 .emit_fence = sdma_v5_0_ring_emit_fence, 1613 .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync, 1614 .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush, 1615 .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush, 1616 .test_ring = sdma_v5_0_ring_test_ring, 1617 .test_ib = sdma_v5_0_ring_test_ib, 1618 .insert_nop = sdma_v5_0_ring_insert_nop, 1619 .pad_ib = sdma_v5_0_ring_pad_ib, 1620 .emit_wreg = sdma_v5_0_ring_emit_wreg, 1621 .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait, 1622 .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait, 1623 .init_cond_exec = sdma_v5_0_ring_init_cond_exec, 1624 .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec, 1625 .preempt_ib = sdma_v5_0_ring_preempt_ib, 1626 }; 1627 1628 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev) 1629 { 1630 int i; 1631 1632 for (i = 0; i < adev->sdma.num_instances; i++) { 1633 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs; 1634 adev->sdma.instance[i].ring.me = i; 1635 } 1636 } 1637 1638 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = { 1639 .set = sdma_v5_0_set_trap_irq_state, 1640 .process = sdma_v5_0_process_trap_irq, 1641 }; 1642 1643 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = { 1644 .process = sdma_v5_0_process_illegal_inst_irq, 1645 }; 1646 1647 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev) 1648 { 1649 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1650 adev->sdma.num_instances; 1651 adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs; 1652 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs; 1653 } 1654 1655 /** 1656 * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine 1657 * 1658 * @ring: amdgpu_ring structure holding ring information 1659 * @src_offset: src GPU address 1660 * @dst_offset: dst GPU address 1661 * @byte_count: number of bytes to xfer 1662 * 1663 * Copy GPU buffers using the DMA engine (NAVI10). 1664 * Used by the amdgpu ttm implementation to move pages if 1665 * registered as the asic copy callback. 1666 */ 1667 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib, 1668 uint64_t src_offset, 1669 uint64_t dst_offset, 1670 uint32_t byte_count) 1671 { 1672 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1673 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1674 ib->ptr[ib->length_dw++] = byte_count - 1; 1675 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1676 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1677 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1678 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1679 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1680 } 1681 1682 /** 1683 * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine 1684 * 1685 * @ring: amdgpu_ring structure holding ring information 1686 * @src_data: value to write to buffer 1687 * @dst_offset: dst GPU address 1688 * @byte_count: number of bytes to xfer 1689 * 1690 * Fill GPU buffers using the DMA engine (NAVI10). 1691 */ 1692 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib, 1693 uint32_t src_data, 1694 uint64_t dst_offset, 1695 uint32_t byte_count) 1696 { 1697 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1698 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1699 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1700 ib->ptr[ib->length_dw++] = src_data; 1701 ib->ptr[ib->length_dw++] = byte_count - 1; 1702 } 1703 1704 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = { 1705 .copy_max_bytes = 0x400000, 1706 .copy_num_dw = 7, 1707 .emit_copy_buffer = sdma_v5_0_emit_copy_buffer, 1708 1709 .fill_max_bytes = 0x400000, 1710 .fill_num_dw = 5, 1711 .emit_fill_buffer = sdma_v5_0_emit_fill_buffer, 1712 }; 1713 1714 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev) 1715 { 1716 if (adev->mman.buffer_funcs == NULL) { 1717 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs; 1718 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1719 } 1720 } 1721 1722 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = { 1723 .copy_pte_num_dw = 7, 1724 .copy_pte = sdma_v5_0_vm_copy_pte, 1725 .write_pte = sdma_v5_0_vm_write_pte, 1726 .set_pte_pde = sdma_v5_0_vm_set_pte_pde, 1727 }; 1728 1729 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1730 { 1731 unsigned i; 1732 1733 if (adev->vm_manager.vm_pte_funcs == NULL) { 1734 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs; 1735 for (i = 0; i < adev->sdma.num_instances; i++) { 1736 adev->vm_manager.vm_pte_scheds[i] = 1737 &adev->sdma.instance[i].ring.sched; 1738 } 1739 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1740 } 1741 } 1742 1743 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = { 1744 .type = AMD_IP_BLOCK_TYPE_SDMA, 1745 .major = 5, 1746 .minor = 0, 1747 .rev = 0, 1748 .funcs = &sdma_v5_0_ip_funcs, 1749 }; 1750