1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_xcp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_trace.h" 33 34 #include "sdma/sdma_4_4_2_offset.h" 35 #include "sdma/sdma_4_4_2_sh_mask.h" 36 37 #include "soc15_common.h" 38 #include "soc15.h" 39 #include "vega10_sdma_pkt_open.h" 40 41 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 42 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 43 44 #include "amdgpu_ras.h" 45 46 MODULE_FIRMWARE("amdgpu/sdma_4_4_2.bin"); 47 MODULE_FIRMWARE("amdgpu/sdma_4_4_5.bin"); 48 49 static const struct amdgpu_hwip_reg_entry sdma_reg_list_4_4_2[] = { 50 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS_REG), 51 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS1_REG), 52 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS2_REG), 53 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS3_REG), 54 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UCODE_CHECKSUM), 55 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH_HI), 56 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH), 57 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_STATUS), 58 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_STATUS), 59 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK0), 60 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK1), 61 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK0), 62 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK1), 63 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_CNTL), 64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR), 65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR_HI), 66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR), 67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR_HI), 68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_OFFSET), 69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_LO), 70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_HI), 71 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_CNTL), 72 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_RPTR), 73 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_SUB_REMAIN), 74 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_DUMMY_REG), 75 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_CNTL), 76 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR), 77 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR_HI), 78 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR), 79 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR_HI), 80 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_OFFSET), 81 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_LO), 82 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_HI), 83 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_DUMMY_REG), 84 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_CNTL), 85 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR), 86 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR_HI), 87 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR), 88 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR_HI), 89 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_OFFSET), 90 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_LO), 91 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_HI), 92 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_DUMMY_REG), 93 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_VM_CNTL) 94 }; 95 96 #define mmSMNAID_AID0_MCA_SMU 0x03b30400 97 98 #define WREG32_SDMA(instance, offset, value) \ 99 WREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)), value) 100 #define RREG32_SDMA(instance, offset) \ 101 RREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset))) 102 103 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev); 104 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev); 105 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev); 106 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev); 107 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev); 108 109 static u32 sdma_v4_4_2_get_reg_offset(struct amdgpu_device *adev, 110 u32 instance, u32 offset) 111 { 112 u32 dev_inst = GET_INST(SDMA0, instance); 113 114 return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset); 115 } 116 117 static unsigned sdma_v4_4_2_seq_to_irq_id(int seq_num) 118 { 119 switch (seq_num) { 120 case 0: 121 return SOC15_IH_CLIENTID_SDMA0; 122 case 1: 123 return SOC15_IH_CLIENTID_SDMA1; 124 case 2: 125 return SOC15_IH_CLIENTID_SDMA2; 126 case 3: 127 return SOC15_IH_CLIENTID_SDMA3; 128 default: 129 return -EINVAL; 130 } 131 } 132 133 static int sdma_v4_4_2_irq_id_to_seq(struct amdgpu_device *adev, unsigned client_id) 134 { 135 switch (client_id) { 136 case SOC15_IH_CLIENTID_SDMA0: 137 return 0; 138 case SOC15_IH_CLIENTID_SDMA1: 139 return 1; 140 case SOC15_IH_CLIENTID_SDMA2: 141 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) 142 return 0; 143 else 144 return 2; 145 case SOC15_IH_CLIENTID_SDMA3: 146 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) 147 return 1; 148 else 149 return 3; 150 default: 151 return -EINVAL; 152 } 153 } 154 155 static void sdma_v4_4_2_inst_init_golden_registers(struct amdgpu_device *adev, 156 uint32_t inst_mask) 157 { 158 u32 val; 159 int i; 160 161 for (i = 0; i < adev->sdma.num_instances; i++) { 162 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG); 163 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4); 164 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, 165 PIPE_INTERLEAVE_SIZE, 0); 166 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG, val); 167 168 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ); 169 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS, 170 4); 171 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, 172 PIPE_INTERLEAVE_SIZE, 0); 173 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ, val); 174 } 175 } 176 177 /** 178 * sdma_v4_4_2_init_microcode - load ucode images from disk 179 * 180 * @adev: amdgpu_device pointer 181 * 182 * Use the firmware interface to load the ucode images into 183 * the driver (not loaded into hw). 184 * Returns 0 on success, error on failure. 185 */ 186 static int sdma_v4_4_2_init_microcode(struct amdgpu_device *adev) 187 { 188 int ret, i; 189 190 for (i = 0; i < adev->sdma.num_instances; i++) { 191 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) || 192 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 4) || 193 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) { 194 ret = amdgpu_sdma_init_microcode(adev, 0, true); 195 break; 196 } else { 197 ret = amdgpu_sdma_init_microcode(adev, i, false); 198 if (ret) 199 return ret; 200 } 201 } 202 203 return ret; 204 } 205 206 /** 207 * sdma_v4_4_2_ring_get_rptr - get the current read pointer 208 * 209 * @ring: amdgpu ring pointer 210 * 211 * Get the current rptr from the hardware. 212 */ 213 static uint64_t sdma_v4_4_2_ring_get_rptr(struct amdgpu_ring *ring) 214 { 215 u64 rptr; 216 217 /* XXX check if swapping is necessary on BE */ 218 rptr = READ_ONCE(*((u64 *)&ring->adev->wb.wb[ring->rptr_offs])); 219 220 DRM_DEBUG("rptr before shift == 0x%016llx\n", rptr); 221 return rptr >> 2; 222 } 223 224 /** 225 * sdma_v4_4_2_ring_get_wptr - get the current write pointer 226 * 227 * @ring: amdgpu ring pointer 228 * 229 * Get the current wptr from the hardware. 230 */ 231 static uint64_t sdma_v4_4_2_ring_get_wptr(struct amdgpu_ring *ring) 232 { 233 struct amdgpu_device *adev = ring->adev; 234 u64 wptr; 235 236 if (ring->use_doorbell) { 237 /* XXX check if swapping is necessary on BE */ 238 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 239 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 240 } else { 241 wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI); 242 wptr = wptr << 32; 243 wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR); 244 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 245 ring->me, wptr); 246 } 247 248 return wptr >> 2; 249 } 250 251 /** 252 * sdma_v4_4_2_ring_set_wptr - commit the write pointer 253 * 254 * @ring: amdgpu ring pointer 255 * 256 * Write the wptr back to the hardware. 257 */ 258 static void sdma_v4_4_2_ring_set_wptr(struct amdgpu_ring *ring) 259 { 260 struct amdgpu_device *adev = ring->adev; 261 262 DRM_DEBUG("Setting write pointer\n"); 263 if (ring->use_doorbell) { 264 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 265 266 DRM_DEBUG("Using doorbell -- " 267 "wptr_offs == 0x%08x " 268 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 269 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 270 ring->wptr_offs, 271 lower_32_bits(ring->wptr << 2), 272 upper_32_bits(ring->wptr << 2)); 273 /* XXX check if swapping is necessary on BE */ 274 WRITE_ONCE(*wb, (ring->wptr << 2)); 275 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 276 ring->doorbell_index, ring->wptr << 2); 277 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 278 } else { 279 DRM_DEBUG("Not using doorbell -- " 280 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 281 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 282 ring->me, 283 lower_32_bits(ring->wptr << 2), 284 ring->me, 285 upper_32_bits(ring->wptr << 2)); 286 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR, 287 lower_32_bits(ring->wptr << 2)); 288 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI, 289 upper_32_bits(ring->wptr << 2)); 290 } 291 } 292 293 /** 294 * sdma_v4_4_2_page_ring_get_wptr - get the current write pointer 295 * 296 * @ring: amdgpu ring pointer 297 * 298 * Get the current wptr from the hardware. 299 */ 300 static uint64_t sdma_v4_4_2_page_ring_get_wptr(struct amdgpu_ring *ring) 301 { 302 struct amdgpu_device *adev = ring->adev; 303 u64 wptr; 304 305 if (ring->use_doorbell) { 306 /* XXX check if swapping is necessary on BE */ 307 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 308 } else { 309 wptr = RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI); 310 wptr = wptr << 32; 311 wptr |= RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR); 312 } 313 314 return wptr >> 2; 315 } 316 317 /** 318 * sdma_v4_4_2_page_ring_set_wptr - commit the write pointer 319 * 320 * @ring: amdgpu ring pointer 321 * 322 * Write the wptr back to the hardware. 323 */ 324 static void sdma_v4_4_2_page_ring_set_wptr(struct amdgpu_ring *ring) 325 { 326 struct amdgpu_device *adev = ring->adev; 327 328 if (ring->use_doorbell) { 329 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 330 331 /* XXX check if swapping is necessary on BE */ 332 WRITE_ONCE(*wb, (ring->wptr << 2)); 333 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 334 } else { 335 uint64_t wptr = ring->wptr << 2; 336 337 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR, 338 lower_32_bits(wptr)); 339 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI, 340 upper_32_bits(wptr)); 341 } 342 } 343 344 static void sdma_v4_4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 345 { 346 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 347 int i; 348 349 for (i = 0; i < count; i++) 350 if (sdma && sdma->burst_nop && (i == 0)) 351 amdgpu_ring_write(ring, ring->funcs->nop | 352 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 353 else 354 amdgpu_ring_write(ring, ring->funcs->nop); 355 } 356 357 /** 358 * sdma_v4_4_2_ring_emit_ib - Schedule an IB on the DMA engine 359 * 360 * @ring: amdgpu ring pointer 361 * @job: job to retrieve vmid from 362 * @ib: IB object to schedule 363 * @flags: unused 364 * 365 * Schedule an IB in the DMA ring. 366 */ 367 static void sdma_v4_4_2_ring_emit_ib(struct amdgpu_ring *ring, 368 struct amdgpu_job *job, 369 struct amdgpu_ib *ib, 370 uint32_t flags) 371 { 372 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 373 374 /* IB packet must end on a 8 DW boundary */ 375 sdma_v4_4_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 376 377 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 378 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 379 /* base must be 32 byte aligned */ 380 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 381 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 382 amdgpu_ring_write(ring, ib->length_dw); 383 amdgpu_ring_write(ring, 0); 384 amdgpu_ring_write(ring, 0); 385 386 } 387 388 static void sdma_v4_4_2_wait_reg_mem(struct amdgpu_ring *ring, 389 int mem_space, int hdp, 390 uint32_t addr0, uint32_t addr1, 391 uint32_t ref, uint32_t mask, 392 uint32_t inv) 393 { 394 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 395 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 396 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 397 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 398 if (mem_space) { 399 /* memory */ 400 amdgpu_ring_write(ring, addr0); 401 amdgpu_ring_write(ring, addr1); 402 } else { 403 /* registers */ 404 amdgpu_ring_write(ring, addr0 << 2); 405 amdgpu_ring_write(ring, addr1 << 2); 406 } 407 amdgpu_ring_write(ring, ref); /* reference */ 408 amdgpu_ring_write(ring, mask); /* mask */ 409 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 410 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 411 } 412 413 /** 414 * sdma_v4_4_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 415 * 416 * @ring: amdgpu ring pointer 417 * 418 * Emit an hdp flush packet on the requested DMA ring. 419 */ 420 static void sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 421 { 422 struct amdgpu_device *adev = ring->adev; 423 u32 ref_and_mask = 0; 424 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 425 426 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 427 << (ring->me % adev->sdma.num_inst_per_aid); 428 429 sdma_v4_4_2_wait_reg_mem(ring, 0, 1, 430 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 431 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 432 ref_and_mask, ref_and_mask, 10); 433 } 434 435 /** 436 * sdma_v4_4_2_ring_emit_fence - emit a fence on the DMA ring 437 * 438 * @ring: amdgpu ring pointer 439 * @addr: address 440 * @seq: sequence number 441 * @flags: fence related flags 442 * 443 * Add a DMA fence packet to the ring to write 444 * the fence seq number and DMA trap packet to generate 445 * an interrupt if needed. 446 */ 447 static void sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 448 unsigned flags) 449 { 450 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 451 /* write the fence */ 452 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 453 /* zero in first two bits */ 454 BUG_ON(addr & 0x3); 455 amdgpu_ring_write(ring, lower_32_bits(addr)); 456 amdgpu_ring_write(ring, upper_32_bits(addr)); 457 amdgpu_ring_write(ring, lower_32_bits(seq)); 458 459 /* optionally write high bits as well */ 460 if (write64bit) { 461 addr += 4; 462 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 463 /* zero in first two bits */ 464 BUG_ON(addr & 0x3); 465 amdgpu_ring_write(ring, lower_32_bits(addr)); 466 amdgpu_ring_write(ring, upper_32_bits(addr)); 467 amdgpu_ring_write(ring, upper_32_bits(seq)); 468 } 469 470 /* generate an interrupt */ 471 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 472 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 473 } 474 475 476 /** 477 * sdma_v4_4_2_inst_gfx_stop - stop the gfx async dma engines 478 * 479 * @adev: amdgpu_device pointer 480 * @inst_mask: mask of dma engine instances to be disabled 481 * 482 * Stop the gfx async dma ring buffers. 483 */ 484 static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev, 485 uint32_t inst_mask) 486 { 487 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 488 u32 doorbell_offset, doorbell; 489 u32 rb_cntl, ib_cntl; 490 int i; 491 492 for_each_inst(i, inst_mask) { 493 sdma[i] = &adev->sdma.instance[i].ring; 494 495 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); 496 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0); 497 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 498 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 499 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0); 500 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 501 502 if (sdma[i]->use_doorbell) { 503 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL); 504 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET); 505 506 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 0); 507 doorbell_offset = REG_SET_FIELD(doorbell_offset, 508 SDMA_GFX_DOORBELL_OFFSET, 509 OFFSET, 0); 510 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell); 511 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset); 512 } 513 } 514 } 515 516 /** 517 * sdma_v4_4_2_inst_rlc_stop - stop the compute async dma engines 518 * 519 * @adev: amdgpu_device pointer 520 * @inst_mask: mask of dma engine instances to be disabled 521 * 522 * Stop the compute async dma queues. 523 */ 524 static void sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device *adev, 525 uint32_t inst_mask) 526 { 527 /* XXX todo */ 528 } 529 530 /** 531 * sdma_v4_4_2_inst_page_stop - stop the page async dma engines 532 * 533 * @adev: amdgpu_device pointer 534 * @inst_mask: mask of dma engine instances to be disabled 535 * 536 * Stop the page async dma ring buffers. 537 */ 538 static void sdma_v4_4_2_inst_page_stop(struct amdgpu_device *adev, 539 uint32_t inst_mask) 540 { 541 u32 rb_cntl, ib_cntl; 542 int i; 543 544 for_each_inst(i, inst_mask) { 545 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); 546 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, 547 RB_ENABLE, 0); 548 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 549 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); 550 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, 551 IB_ENABLE, 0); 552 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); 553 } 554 } 555 556 /** 557 * sdma_v4_4_2_inst_ctx_switch_enable - stop the async dma engines context switch 558 * 559 * @adev: amdgpu_device pointer 560 * @enable: enable/disable the DMA MEs context switch. 561 * @inst_mask: mask of dma engine instances to be enabled 562 * 563 * Halt or unhalt the async dma engines context switch. 564 */ 565 static void sdma_v4_4_2_inst_ctx_switch_enable(struct amdgpu_device *adev, 566 bool enable, uint32_t inst_mask) 567 { 568 u32 f32_cntl, phase_quantum = 0; 569 int i; 570 571 if (amdgpu_sdma_phase_quantum) { 572 unsigned value = amdgpu_sdma_phase_quantum; 573 unsigned unit = 0; 574 575 while (value > (SDMA_PHASE0_QUANTUM__VALUE_MASK >> 576 SDMA_PHASE0_QUANTUM__VALUE__SHIFT)) { 577 value = (value + 1) >> 1; 578 unit++; 579 } 580 if (unit > (SDMA_PHASE0_QUANTUM__UNIT_MASK >> 581 SDMA_PHASE0_QUANTUM__UNIT__SHIFT)) { 582 value = (SDMA_PHASE0_QUANTUM__VALUE_MASK >> 583 SDMA_PHASE0_QUANTUM__VALUE__SHIFT); 584 unit = (SDMA_PHASE0_QUANTUM__UNIT_MASK >> 585 SDMA_PHASE0_QUANTUM__UNIT__SHIFT); 586 WARN_ONCE(1, 587 "clamping sdma_phase_quantum to %uK clock cycles\n", 588 value << unit); 589 } 590 phase_quantum = 591 value << SDMA_PHASE0_QUANTUM__VALUE__SHIFT | 592 unit << SDMA_PHASE0_QUANTUM__UNIT__SHIFT; 593 } 594 595 for_each_inst(i, inst_mask) { 596 f32_cntl = RREG32_SDMA(i, regSDMA_CNTL); 597 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_CNTL, 598 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 599 if (enable && amdgpu_sdma_phase_quantum) { 600 WREG32_SDMA(i, regSDMA_PHASE0_QUANTUM, phase_quantum); 601 WREG32_SDMA(i, regSDMA_PHASE1_QUANTUM, phase_quantum); 602 WREG32_SDMA(i, regSDMA_PHASE2_QUANTUM, phase_quantum); 603 } 604 WREG32_SDMA(i, regSDMA_CNTL, f32_cntl); 605 606 /* Extend page fault timeout to avoid interrupt storm */ 607 WREG32_SDMA(i, regSDMA_UTCL1_TIMEOUT, 0x00800080); 608 } 609 } 610 611 /** 612 * sdma_v4_4_2_inst_enable - stop the async dma engines 613 * 614 * @adev: amdgpu_device pointer 615 * @enable: enable/disable the DMA MEs. 616 * @inst_mask: mask of dma engine instances to be enabled 617 * 618 * Halt or unhalt the async dma engines. 619 */ 620 static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable, 621 uint32_t inst_mask) 622 { 623 u32 f32_cntl; 624 int i; 625 626 if (!enable) { 627 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask); 628 sdma_v4_4_2_inst_rlc_stop(adev, inst_mask); 629 if (adev->sdma.has_page_queue) 630 sdma_v4_4_2_inst_page_stop(adev, inst_mask); 631 632 /* SDMA FW needs to respond to FREEZE requests during reset. 633 * Keep it running during reset */ 634 if (!amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 635 return; 636 } 637 638 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 639 return; 640 641 for_each_inst(i, inst_mask) { 642 f32_cntl = RREG32_SDMA(i, regSDMA_F32_CNTL); 643 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1); 644 WREG32_SDMA(i, regSDMA_F32_CNTL, f32_cntl); 645 } 646 } 647 648 /* 649 * sdma_v4_4_2_rb_cntl - get parameters for rb_cntl 650 */ 651 static uint32_t sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 652 { 653 /* Set ring buffer size in dwords */ 654 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 655 656 barrier(); /* work around https://llvm.org/pr42576 */ 657 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 658 #ifdef __BIG_ENDIAN 659 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 660 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, 661 RPTR_WRITEBACK_SWAP_ENABLE, 1); 662 #endif 663 return rb_cntl; 664 } 665 666 /** 667 * sdma_v4_4_2_gfx_resume - setup and start the async dma engines 668 * 669 * @adev: amdgpu_device pointer 670 * @i: instance to resume 671 * @restore: used to restore wptr when restart 672 * 673 * Set up the gfx DMA ring buffers and enable them. 674 * Returns 0 for success, error for failure. 675 */ 676 static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i, bool restore) 677 { 678 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 679 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 680 u32 wb_offset; 681 u32 doorbell; 682 u32 doorbell_offset; 683 u64 wptr_gpu_addr; 684 685 wb_offset = (ring->rptr_offs * 4); 686 687 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); 688 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 689 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 690 691 /* set the wb address whether it's enabled or not */ 692 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_HI, 693 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 694 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_LO, 695 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 696 697 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, 698 RPTR_WRITEBACK_ENABLE, 1); 699 700 WREG32_SDMA(i, regSDMA_GFX_RB_BASE, ring->gpu_addr >> 8); 701 WREG32_SDMA(i, regSDMA_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 702 703 if (!restore) 704 ring->wptr = 0; 705 706 /* before programing wptr to a less value, need set minor_ptr_update first */ 707 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 1); 708 709 /* Initialize the ring buffer's read and write pointers */ 710 if (restore) { 711 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, lower_32_bits(ring->wptr << 2)); 712 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, upper_32_bits(ring->wptr << 2)); 713 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, lower_32_bits(ring->wptr << 2)); 714 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, upper_32_bits(ring->wptr << 2)); 715 } else { 716 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0); 717 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0); 718 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0); 719 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0); 720 } 721 722 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL); 723 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET); 724 725 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 726 ring->use_doorbell); 727 doorbell_offset = REG_SET_FIELD(doorbell_offset, 728 SDMA_GFX_DOORBELL_OFFSET, 729 OFFSET, ring->doorbell_index); 730 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell); 731 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset); 732 733 sdma_v4_4_2_ring_set_wptr(ring); 734 735 /* set minor_ptr_update to 0 after wptr programed */ 736 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 0); 737 738 /* setup the wptr shadow polling */ 739 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 740 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_LO, 741 lower_32_bits(wptr_gpu_addr)); 742 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_HI, 743 upper_32_bits(wptr_gpu_addr)); 744 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL); 745 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 746 SDMA_GFX_RB_WPTR_POLL_CNTL, 747 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 748 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 749 750 /* enable DMA RB */ 751 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 1); 752 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 753 754 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 755 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 1); 756 #ifdef __BIG_ENDIAN 757 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 758 #endif 759 /* enable DMA IBs */ 760 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 761 } 762 763 /** 764 * sdma_v4_4_2_page_resume - setup and start the async dma engines 765 * 766 * @adev: amdgpu_device pointer 767 * @i: instance to resume 768 * @restore: boolean to say restore needed or not 769 * 770 * Set up the page DMA ring buffers and enable them. 771 * Returns 0 for success, error for failure. 772 */ 773 static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i, bool restore) 774 { 775 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 776 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 777 u32 wb_offset; 778 u32 doorbell; 779 u32 doorbell_offset; 780 u64 wptr_gpu_addr; 781 782 wb_offset = (ring->rptr_offs * 4); 783 784 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); 785 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 786 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 787 788 /* Initialize the ring buffer's read and write pointers */ 789 if (restore) { 790 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, lower_32_bits(ring->wptr << 2)); 791 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, upper_32_bits(ring->wptr << 2)); 792 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, lower_32_bits(ring->wptr << 2)); 793 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, upper_32_bits(ring->wptr << 2)); 794 } else { 795 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, 0); 796 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, 0); 797 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, 0); 798 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, 0); 799 } 800 801 /* set the wb address whether it's enabled or not */ 802 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_HI, 803 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 804 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_LO, 805 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 806 807 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, 808 RPTR_WRITEBACK_ENABLE, 1); 809 810 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE, ring->gpu_addr >> 8); 811 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 812 813 if (!restore) 814 ring->wptr = 0; 815 816 /* before programing wptr to a less value, need set minor_ptr_update first */ 817 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 1); 818 819 doorbell = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL); 820 doorbell_offset = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET); 821 822 doorbell = REG_SET_FIELD(doorbell, SDMA_PAGE_DOORBELL, ENABLE, 823 ring->use_doorbell); 824 doorbell_offset = REG_SET_FIELD(doorbell_offset, 825 SDMA_PAGE_DOORBELL_OFFSET, 826 OFFSET, ring->doorbell_index); 827 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL, doorbell); 828 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET, doorbell_offset); 829 830 /* paging queue doorbell range is setup at sdma_v4_4_2_gfx_resume */ 831 sdma_v4_4_2_page_ring_set_wptr(ring); 832 833 /* set minor_ptr_update to 0 after wptr programed */ 834 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 0); 835 836 /* setup the wptr shadow polling */ 837 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 838 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_LO, 839 lower_32_bits(wptr_gpu_addr)); 840 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_HI, 841 upper_32_bits(wptr_gpu_addr)); 842 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL); 843 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 844 SDMA_PAGE_RB_WPTR_POLL_CNTL, 845 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 846 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 847 848 /* enable DMA RB */ 849 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, RB_ENABLE, 1); 850 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 851 852 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); 853 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_ENABLE, 1); 854 #ifdef __BIG_ENDIAN 855 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 856 #endif 857 /* enable DMA IBs */ 858 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); 859 } 860 861 static void sdma_v4_4_2_init_pg(struct amdgpu_device *adev) 862 { 863 864 } 865 866 /** 867 * sdma_v4_4_2_inst_rlc_resume - setup and start the async dma engines 868 * 869 * @adev: amdgpu_device pointer 870 * @inst_mask: mask of dma engine instances to be enabled 871 * 872 * Set up the compute DMA queues and enable them. 873 * Returns 0 for success, error for failure. 874 */ 875 static int sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device *adev, 876 uint32_t inst_mask) 877 { 878 sdma_v4_4_2_init_pg(adev); 879 880 return 0; 881 } 882 883 /** 884 * sdma_v4_4_2_inst_load_microcode - load the sDMA ME ucode 885 * 886 * @adev: amdgpu_device pointer 887 * @inst_mask: mask of dma engine instances to be enabled 888 * 889 * Loads the sDMA0/1 ucode. 890 * Returns 0 for success, -EINVAL if the ucode is not available. 891 */ 892 static int sdma_v4_4_2_inst_load_microcode(struct amdgpu_device *adev, 893 uint32_t inst_mask) 894 { 895 const struct sdma_firmware_header_v1_0 *hdr; 896 const __le32 *fw_data; 897 u32 fw_size; 898 int i, j; 899 900 /* halt the MEs */ 901 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 902 903 for_each_inst(i, inst_mask) { 904 if (!adev->sdma.instance[i].fw) 905 return -EINVAL; 906 907 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 908 amdgpu_ucode_print_sdma_hdr(&hdr->header); 909 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 910 911 fw_data = (const __le32 *) 912 (adev->sdma.instance[i].fw->data + 913 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 914 915 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 0); 916 917 for (j = 0; j < fw_size; j++) 918 WREG32_SDMA(i, regSDMA_UCODE_DATA, 919 le32_to_cpup(fw_data++)); 920 921 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 922 adev->sdma.instance[i].fw_version); 923 } 924 925 return 0; 926 } 927 928 /** 929 * sdma_v4_4_2_inst_start - setup and start the async dma engines 930 * 931 * @adev: amdgpu_device pointer 932 * @inst_mask: mask of dma engine instances to be enabled 933 * @restore: boolean to say restore needed or not 934 * 935 * Set up the DMA engines and enable them. 936 * Returns 0 for success, error for failure. 937 */ 938 static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev, 939 uint32_t inst_mask, bool restore) 940 { 941 struct amdgpu_ring *ring; 942 uint32_t tmp_mask; 943 int i, r = 0; 944 945 if (amdgpu_sriov_vf(adev)) { 946 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 947 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 948 } else { 949 /* bypass sdma microcode loading on Gopher */ 950 if (!restore && adev->firmware.load_type != AMDGPU_FW_LOAD_PSP && 951 adev->sdma.instance[0].fw) { 952 r = sdma_v4_4_2_inst_load_microcode(adev, inst_mask); 953 if (r) 954 return r; 955 } 956 957 /* unhalt the MEs */ 958 sdma_v4_4_2_inst_enable(adev, true, inst_mask); 959 /* enable sdma ring preemption */ 960 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask); 961 } 962 963 /* start the gfx rings and rlc compute queues */ 964 tmp_mask = inst_mask; 965 for_each_inst(i, tmp_mask) { 966 uint32_t temp; 967 968 WREG32_SDMA(i, regSDMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); 969 sdma_v4_4_2_gfx_resume(adev, i, restore); 970 if (adev->sdma.has_page_queue) 971 sdma_v4_4_2_page_resume(adev, i, restore); 972 973 /* set utc l1 enable flag always to 1 */ 974 temp = RREG32_SDMA(i, regSDMA_CNTL); 975 temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1); 976 977 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) < IP_VERSION(4, 4, 5)) { 978 /* enable context empty interrupt during initialization */ 979 temp = REG_SET_FIELD(temp, SDMA_CNTL, CTXEMPTY_INT_ENABLE, 1); 980 WREG32_SDMA(i, regSDMA_CNTL, temp); 981 } 982 if (!amdgpu_sriov_vf(adev)) { 983 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 984 /* unhalt engine */ 985 temp = RREG32_SDMA(i, regSDMA_F32_CNTL); 986 temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0); 987 WREG32_SDMA(i, regSDMA_F32_CNTL, temp); 988 } 989 } 990 } 991 992 if (amdgpu_sriov_vf(adev)) { 993 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask); 994 sdma_v4_4_2_inst_enable(adev, true, inst_mask); 995 } else { 996 r = sdma_v4_4_2_inst_rlc_resume(adev, inst_mask); 997 if (r) 998 return r; 999 } 1000 1001 tmp_mask = inst_mask; 1002 for_each_inst(i, tmp_mask) { 1003 ring = &adev->sdma.instance[i].ring; 1004 1005 r = amdgpu_ring_test_helper(ring); 1006 if (r) 1007 return r; 1008 1009 if (adev->sdma.has_page_queue) { 1010 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 1011 1012 r = amdgpu_ring_test_helper(page); 1013 if (r) 1014 return r; 1015 } 1016 } 1017 1018 return r; 1019 } 1020 1021 /** 1022 * sdma_v4_4_2_ring_test_ring - simple async dma engine test 1023 * 1024 * @ring: amdgpu_ring structure holding ring information 1025 * 1026 * Test the DMA engine by writing using it to write an 1027 * value to memory. 1028 * Returns 0 for success, error for failure. 1029 */ 1030 static int sdma_v4_4_2_ring_test_ring(struct amdgpu_ring *ring) 1031 { 1032 struct amdgpu_device *adev = ring->adev; 1033 unsigned i; 1034 unsigned index; 1035 int r; 1036 u32 tmp; 1037 u64 gpu_addr; 1038 1039 r = amdgpu_device_wb_get(adev, &index); 1040 if (r) 1041 return r; 1042 1043 gpu_addr = adev->wb.gpu_addr + (index * 4); 1044 tmp = 0xCAFEDEAD; 1045 adev->wb.wb[index] = cpu_to_le32(tmp); 1046 1047 r = amdgpu_ring_alloc(ring, 5); 1048 if (r) 1049 goto error_free_wb; 1050 1051 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1052 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1053 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1054 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1055 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1056 amdgpu_ring_write(ring, 0xDEADBEEF); 1057 amdgpu_ring_commit(ring); 1058 1059 for (i = 0; i < adev->usec_timeout; i++) { 1060 tmp = le32_to_cpu(adev->wb.wb[index]); 1061 if (tmp == 0xDEADBEEF) 1062 break; 1063 udelay(1); 1064 } 1065 1066 if (i >= adev->usec_timeout) 1067 r = -ETIMEDOUT; 1068 1069 error_free_wb: 1070 amdgpu_device_wb_free(adev, index); 1071 return r; 1072 } 1073 1074 /** 1075 * sdma_v4_4_2_ring_test_ib - test an IB on the DMA engine 1076 * 1077 * @ring: amdgpu_ring structure holding ring information 1078 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1079 * 1080 * Test a simple IB in the DMA ring. 1081 * Returns 0 on success, error on failure. 1082 */ 1083 static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1084 { 1085 struct amdgpu_device *adev = ring->adev; 1086 struct amdgpu_ib ib; 1087 struct dma_fence *f = NULL; 1088 unsigned index; 1089 long r; 1090 u32 tmp = 0; 1091 u64 gpu_addr; 1092 1093 r = amdgpu_device_wb_get(adev, &index); 1094 if (r) 1095 return r; 1096 1097 gpu_addr = adev->wb.gpu_addr + (index * 4); 1098 tmp = 0xCAFEDEAD; 1099 adev->wb.wb[index] = cpu_to_le32(tmp); 1100 memset(&ib, 0, sizeof(ib)); 1101 r = amdgpu_ib_get(adev, NULL, 256, 1102 AMDGPU_IB_POOL_DIRECT, &ib); 1103 if (r) 1104 goto err0; 1105 1106 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1107 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1108 ib.ptr[1] = lower_32_bits(gpu_addr); 1109 ib.ptr[2] = upper_32_bits(gpu_addr); 1110 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1111 ib.ptr[4] = 0xDEADBEEF; 1112 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1113 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1114 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1115 ib.length_dw = 8; 1116 1117 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1118 if (r) 1119 goto err1; 1120 1121 r = dma_fence_wait_timeout(f, false, timeout); 1122 if (r == 0) { 1123 r = -ETIMEDOUT; 1124 goto err1; 1125 } else if (r < 0) { 1126 goto err1; 1127 } 1128 tmp = le32_to_cpu(adev->wb.wb[index]); 1129 if (tmp == 0xDEADBEEF) 1130 r = 0; 1131 else 1132 r = -EINVAL; 1133 1134 err1: 1135 amdgpu_ib_free(&ib, NULL); 1136 dma_fence_put(f); 1137 err0: 1138 amdgpu_device_wb_free(adev, index); 1139 return r; 1140 } 1141 1142 1143 /** 1144 * sdma_v4_4_2_vm_copy_pte - update PTEs by copying them from the GART 1145 * 1146 * @ib: indirect buffer to fill with commands 1147 * @pe: addr of the page entry 1148 * @src: src addr to copy from 1149 * @count: number of page entries to update 1150 * 1151 * Update PTEs by copying them from the GART using sDMA. 1152 */ 1153 static void sdma_v4_4_2_vm_copy_pte(struct amdgpu_ib *ib, 1154 uint64_t pe, uint64_t src, 1155 unsigned count) 1156 { 1157 unsigned bytes = count * 8; 1158 1159 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1160 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1161 ib->ptr[ib->length_dw++] = bytes - 1; 1162 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1163 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1164 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1165 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1166 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1167 1168 } 1169 1170 /** 1171 * sdma_v4_4_2_vm_write_pte - update PTEs by writing them manually 1172 * 1173 * @ib: indirect buffer to fill with commands 1174 * @pe: addr of the page entry 1175 * @value: dst addr to write into pe 1176 * @count: number of page entries to update 1177 * @incr: increase next addr by incr bytes 1178 * 1179 * Update PTEs by writing them manually using sDMA. 1180 */ 1181 static void sdma_v4_4_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1182 uint64_t value, unsigned count, 1183 uint32_t incr) 1184 { 1185 unsigned ndw = count * 2; 1186 1187 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1188 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1189 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1190 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1191 ib->ptr[ib->length_dw++] = ndw - 1; 1192 for (; ndw > 0; ndw -= 2) { 1193 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1194 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1195 value += incr; 1196 } 1197 } 1198 1199 /** 1200 * sdma_v4_4_2_vm_set_pte_pde - update the page tables using sDMA 1201 * 1202 * @ib: indirect buffer to fill with commands 1203 * @pe: addr of the page entry 1204 * @addr: dst addr to write into pe 1205 * @count: number of page entries to update 1206 * @incr: increase next addr by incr bytes 1207 * @flags: access flags 1208 * 1209 * Update the page tables using sDMA. 1210 */ 1211 static void sdma_v4_4_2_vm_set_pte_pde(struct amdgpu_ib *ib, 1212 uint64_t pe, 1213 uint64_t addr, unsigned count, 1214 uint32_t incr, uint64_t flags) 1215 { 1216 /* for physically contiguous pages (vram) */ 1217 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1218 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1219 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1220 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1221 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1222 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1223 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1224 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1225 ib->ptr[ib->length_dw++] = 0; 1226 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1227 } 1228 1229 /** 1230 * sdma_v4_4_2_ring_pad_ib - pad the IB to the required number of dw 1231 * 1232 * @ring: amdgpu_ring structure holding ring information 1233 * @ib: indirect buffer to fill with padding 1234 */ 1235 static void sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1236 { 1237 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1238 u32 pad_count; 1239 int i; 1240 1241 pad_count = (-ib->length_dw) & 7; 1242 for (i = 0; i < pad_count; i++) 1243 if (sdma && sdma->burst_nop && (i == 0)) 1244 ib->ptr[ib->length_dw++] = 1245 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1246 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1247 else 1248 ib->ptr[ib->length_dw++] = 1249 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1250 } 1251 1252 1253 /** 1254 * sdma_v4_4_2_ring_emit_pipeline_sync - sync the pipeline 1255 * 1256 * @ring: amdgpu_ring pointer 1257 * 1258 * Make sure all previous operations are completed (CIK). 1259 */ 1260 static void sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1261 { 1262 uint32_t seq = ring->fence_drv.sync_seq; 1263 uint64_t addr = ring->fence_drv.gpu_addr; 1264 1265 /* wait for idle */ 1266 sdma_v4_4_2_wait_reg_mem(ring, 1, 0, 1267 addr & 0xfffffffc, 1268 upper_32_bits(addr) & 0xffffffff, 1269 seq, 0xffffffff, 4); 1270 } 1271 1272 1273 /** 1274 * sdma_v4_4_2_ring_emit_vm_flush - vm flush using sDMA 1275 * 1276 * @ring: amdgpu_ring pointer 1277 * @vmid: vmid number to use 1278 * @pd_addr: address 1279 * 1280 * Update the page table base and flush the VM TLB 1281 * using sDMA. 1282 */ 1283 static void sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring *ring, 1284 unsigned vmid, uint64_t pd_addr) 1285 { 1286 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1287 } 1288 1289 static void sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring *ring, 1290 uint32_t reg, uint32_t val) 1291 { 1292 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1293 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1294 amdgpu_ring_write(ring, reg); 1295 amdgpu_ring_write(ring, val); 1296 } 1297 1298 static void sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1299 uint32_t val, uint32_t mask) 1300 { 1301 sdma_v4_4_2_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1302 } 1303 1304 static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev) 1305 { 1306 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1307 case IP_VERSION(4, 4, 2): 1308 case IP_VERSION(4, 4, 5): 1309 return false; 1310 default: 1311 return false; 1312 } 1313 } 1314 1315 static int sdma_v4_4_2_early_init(struct amdgpu_ip_block *ip_block) 1316 { 1317 struct amdgpu_device *adev = ip_block->adev; 1318 int r; 1319 1320 r = sdma_v4_4_2_init_microcode(adev); 1321 if (r) 1322 return r; 1323 1324 /* TODO: Page queue breaks driver reload under SRIOV */ 1325 if (sdma_v4_4_2_fw_support_paging_queue(adev)) 1326 adev->sdma.has_page_queue = true; 1327 1328 sdma_v4_4_2_set_ring_funcs(adev); 1329 sdma_v4_4_2_set_buffer_funcs(adev); 1330 sdma_v4_4_2_set_vm_pte_funcs(adev); 1331 sdma_v4_4_2_set_irq_funcs(adev); 1332 sdma_v4_4_2_set_ras_funcs(adev); 1333 1334 return 0; 1335 } 1336 1337 #if 0 1338 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, 1339 void *err_data, 1340 struct amdgpu_iv_entry *entry); 1341 #endif 1342 1343 static int sdma_v4_4_2_late_init(struct amdgpu_ip_block *ip_block) 1344 { 1345 struct amdgpu_device *adev = ip_block->adev; 1346 #if 0 1347 struct ras_ih_if ih_info = { 1348 .cb = sdma_v4_4_2_process_ras_data_cb, 1349 }; 1350 #endif 1351 if (!amdgpu_persistent_edc_harvesting_supported(adev)) 1352 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__SDMA); 1353 1354 return 0; 1355 } 1356 1357 static int sdma_v4_4_2_sw_init(struct amdgpu_ip_block *ip_block) 1358 { 1359 struct amdgpu_ring *ring; 1360 int r, i; 1361 struct amdgpu_device *adev = ip_block->adev; 1362 u32 aid_id; 1363 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); 1364 uint32_t *ptr; 1365 1366 /* SDMA trap event */ 1367 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1368 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1369 SDMA0_4_0__SRCID__SDMA_TRAP, 1370 &adev->sdma.trap_irq); 1371 if (r) 1372 return r; 1373 } 1374 1375 /* SDMA SRAM ECC event */ 1376 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1377 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1378 SDMA0_4_0__SRCID__SDMA_SRAM_ECC, 1379 &adev->sdma.ecc_irq); 1380 if (r) 1381 return r; 1382 } 1383 1384 /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/ 1385 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1386 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1387 SDMA0_4_0__SRCID__SDMA_VM_HOLE, 1388 &adev->sdma.vm_hole_irq); 1389 if (r) 1390 return r; 1391 1392 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1393 SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID, 1394 &adev->sdma.doorbell_invalid_irq); 1395 if (r) 1396 return r; 1397 1398 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1399 SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT, 1400 &adev->sdma.pool_timeout_irq); 1401 if (r) 1402 return r; 1403 1404 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1405 SDMA0_4_0__SRCID__SDMA_SRBMWRITE, 1406 &adev->sdma.srbm_write_irq); 1407 if (r) 1408 return r; 1409 } 1410 1411 for (i = 0; i < adev->sdma.num_instances; i++) { 1412 ring = &adev->sdma.instance[i].ring; 1413 ring->ring_obj = NULL; 1414 ring->use_doorbell = true; 1415 aid_id = adev->sdma.instance[i].aid_id; 1416 1417 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1418 ring->use_doorbell?"true":"false"); 1419 1420 /* doorbell size is 2 dwords, get DWORD offset */ 1421 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1422 ring->vm_hub = AMDGPU_MMHUB0(aid_id); 1423 1424 sprintf(ring->name, "sdma%d.%d", aid_id, 1425 i % adev->sdma.num_inst_per_aid); 1426 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1427 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1428 AMDGPU_RING_PRIO_DEFAULT, NULL); 1429 if (r) 1430 return r; 1431 1432 if (adev->sdma.has_page_queue) { 1433 ring = &adev->sdma.instance[i].page; 1434 ring->ring_obj = NULL; 1435 ring->use_doorbell = true; 1436 1437 /* doorbell index of page queue is assigned right after 1438 * gfx queue on the same instance 1439 */ 1440 ring->doorbell_index = 1441 (adev->doorbell_index.sdma_engine[i] + 1) << 1; 1442 ring->vm_hub = AMDGPU_MMHUB0(aid_id); 1443 1444 sprintf(ring->name, "page%d.%d", aid_id, 1445 i % adev->sdma.num_inst_per_aid); 1446 r = amdgpu_ring_init(adev, ring, 1024, 1447 &adev->sdma.trap_irq, 1448 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1449 AMDGPU_RING_PRIO_DEFAULT, NULL); 1450 if (r) 1451 return r; 1452 } 1453 } 1454 1455 /* TODO: Add queue reset mask when FW fully supports it */ 1456 adev->sdma.supported_reset = 1457 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); 1458 1459 if (amdgpu_sdma_ras_sw_init(adev)) { 1460 dev_err(adev->dev, "fail to initialize sdma ras block\n"); 1461 return -EINVAL; 1462 } 1463 1464 /* Allocate memory for SDMA IP Dump buffer */ 1465 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); 1466 if (ptr) 1467 adev->sdma.ip_dump = ptr; 1468 else 1469 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n"); 1470 1471 r = amdgpu_sdma_sysfs_reset_mask_init(adev); 1472 if (r) 1473 return r; 1474 1475 return r; 1476 } 1477 1478 static int sdma_v4_4_2_sw_fini(struct amdgpu_ip_block *ip_block) 1479 { 1480 struct amdgpu_device *adev = ip_block->adev; 1481 int i; 1482 1483 for (i = 0; i < adev->sdma.num_instances; i++) { 1484 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1485 if (adev->sdma.has_page_queue) 1486 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1487 } 1488 1489 amdgpu_sdma_sysfs_reset_mask_fini(adev); 1490 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) || 1491 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 4) || 1492 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) 1493 amdgpu_sdma_destroy_inst_ctx(adev, true); 1494 else 1495 amdgpu_sdma_destroy_inst_ctx(adev, false); 1496 1497 kfree(adev->sdma.ip_dump); 1498 1499 return 0; 1500 } 1501 1502 static int sdma_v4_4_2_hw_init(struct amdgpu_ip_block *ip_block) 1503 { 1504 int r; 1505 struct amdgpu_device *adev = ip_block->adev; 1506 uint32_t inst_mask; 1507 1508 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1509 if (!amdgpu_sriov_vf(adev)) 1510 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask); 1511 1512 r = sdma_v4_4_2_inst_start(adev, inst_mask, false); 1513 1514 return r; 1515 } 1516 1517 static int sdma_v4_4_2_hw_fini(struct amdgpu_ip_block *ip_block) 1518 { 1519 struct amdgpu_device *adev = ip_block->adev; 1520 uint32_t inst_mask; 1521 int i; 1522 1523 if (amdgpu_sriov_vf(adev)) 1524 return 0; 1525 1526 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1527 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 1528 for (i = 0; i < adev->sdma.num_instances; i++) { 1529 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 1530 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1531 } 1532 } 1533 1534 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 1535 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 1536 1537 return 0; 1538 } 1539 1540 static int sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1541 enum amd_clockgating_state state); 1542 1543 static int sdma_v4_4_2_suspend(struct amdgpu_ip_block *ip_block) 1544 { 1545 struct amdgpu_device *adev = ip_block->adev; 1546 1547 if (amdgpu_in_reset(adev)) 1548 sdma_v4_4_2_set_clockgating_state(ip_block, AMD_CG_STATE_UNGATE); 1549 1550 return sdma_v4_4_2_hw_fini(ip_block); 1551 } 1552 1553 static int sdma_v4_4_2_resume(struct amdgpu_ip_block *ip_block) 1554 { 1555 return sdma_v4_4_2_hw_init(ip_block); 1556 } 1557 1558 static bool sdma_v4_4_2_is_idle(void *handle) 1559 { 1560 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1561 u32 i; 1562 1563 for (i = 0; i < adev->sdma.num_instances; i++) { 1564 u32 tmp = RREG32_SDMA(i, regSDMA_STATUS_REG); 1565 1566 if (!(tmp & SDMA_STATUS_REG__IDLE_MASK)) 1567 return false; 1568 } 1569 1570 return true; 1571 } 1572 1573 static int sdma_v4_4_2_wait_for_idle(struct amdgpu_ip_block *ip_block) 1574 { 1575 unsigned i, j; 1576 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; 1577 struct amdgpu_device *adev = ip_block->adev; 1578 1579 for (i = 0; i < adev->usec_timeout; i++) { 1580 for (j = 0; j < adev->sdma.num_instances; j++) { 1581 sdma[j] = RREG32_SDMA(j, regSDMA_STATUS_REG); 1582 if (!(sdma[j] & SDMA_STATUS_REG__IDLE_MASK)) 1583 break; 1584 } 1585 if (j == adev->sdma.num_instances) 1586 return 0; 1587 udelay(1); 1588 } 1589 return -ETIMEDOUT; 1590 } 1591 1592 static int sdma_v4_4_2_soft_reset(struct amdgpu_ip_block *ip_block) 1593 { 1594 /* todo */ 1595 1596 return 0; 1597 } 1598 1599 static int sdma_v4_4_2_reset_queue(struct amdgpu_ring *ring, unsigned int vmid) 1600 { 1601 struct amdgpu_device *adev = ring->adev; 1602 int i, r; 1603 u32 inst_mask; 1604 1605 if (amdgpu_sriov_vf(adev)) 1606 return -EINVAL; 1607 1608 /* stop queue */ 1609 inst_mask = 1 << ring->me; 1610 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask); 1611 if (adev->sdma.has_page_queue) 1612 sdma_v4_4_2_inst_page_stop(adev, inst_mask); 1613 1614 r = amdgpu_dpm_reset_sdma(adev, 1 << GET_INST(SDMA0, ring->me)); 1615 if (r) 1616 return r; 1617 1618 udelay(50); 1619 1620 for (i = 0; i < adev->usec_timeout; i++) { 1621 if (!REG_GET_FIELD(RREG32_SDMA(ring->me, regSDMA_F32_CNTL), SDMA_F32_CNTL, HALT)) 1622 break; 1623 udelay(1); 1624 } 1625 1626 if (i == adev->usec_timeout) { 1627 dev_err(adev->dev, "timed out waiting for SDMA%d unhalt after reset\n", 1628 ring->me); 1629 return -ETIMEDOUT; 1630 } 1631 1632 return sdma_v4_4_2_inst_start(adev, inst_mask, true); 1633 } 1634 1635 static int sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device *adev, 1636 struct amdgpu_irq_src *source, 1637 unsigned type, 1638 enum amdgpu_interrupt_state state) 1639 { 1640 u32 sdma_cntl; 1641 1642 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); 1643 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE, 1644 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1645 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); 1646 1647 return 0; 1648 } 1649 1650 static int sdma_v4_4_2_process_trap_irq(struct amdgpu_device *adev, 1651 struct amdgpu_irq_src *source, 1652 struct amdgpu_iv_entry *entry) 1653 { 1654 uint32_t instance, i; 1655 1656 DRM_DEBUG("IH: SDMA trap\n"); 1657 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1658 1659 /* Client id gives the SDMA instance in AID. To know the exact SDMA 1660 * instance, interrupt entry gives the node id which corresponds to the AID instance. 1661 * Match node id with the AID id associated with the SDMA instance. */ 1662 for (i = instance; i < adev->sdma.num_instances; 1663 i += adev->sdma.num_inst_per_aid) { 1664 if (adev->sdma.instance[i].aid_id == 1665 node_id_to_phys_map[entry->node_id]) 1666 break; 1667 } 1668 1669 if (i >= adev->sdma.num_instances) { 1670 dev_WARN_ONCE( 1671 adev->dev, 1, 1672 "Couldn't find the right sdma instance in trap handler"); 1673 return 0; 1674 } 1675 1676 switch (entry->ring_id) { 1677 case 0: 1678 amdgpu_fence_process(&adev->sdma.instance[i].ring); 1679 break; 1680 default: 1681 break; 1682 } 1683 return 0; 1684 } 1685 1686 #if 0 1687 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, 1688 void *err_data, 1689 struct amdgpu_iv_entry *entry) 1690 { 1691 int instance; 1692 1693 /* When “Full RAS” is enabled, the per-IP interrupt sources should 1694 * be disabled and the driver should only look for the aggregated 1695 * interrupt via sync flood 1696 */ 1697 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) 1698 goto out; 1699 1700 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1701 if (instance < 0) 1702 goto out; 1703 1704 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry); 1705 1706 out: 1707 return AMDGPU_RAS_SUCCESS; 1708 } 1709 #endif 1710 1711 static int sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device *adev, 1712 struct amdgpu_irq_src *source, 1713 struct amdgpu_iv_entry *entry) 1714 { 1715 int instance; 1716 1717 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1718 1719 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1720 if (instance < 0) 1721 return 0; 1722 1723 switch (entry->ring_id) { 1724 case 0: 1725 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 1726 break; 1727 } 1728 return 0; 1729 } 1730 1731 static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev, 1732 struct amdgpu_irq_src *source, 1733 unsigned type, 1734 enum amdgpu_interrupt_state state) 1735 { 1736 u32 sdma_cntl; 1737 1738 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); 1739 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, DRAM_ECC_INT_ENABLE, 1740 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1741 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); 1742 1743 return 0; 1744 } 1745 1746 static int sdma_v4_4_2_print_iv_entry(struct amdgpu_device *adev, 1747 struct amdgpu_iv_entry *entry) 1748 { 1749 int instance; 1750 struct amdgpu_task_info *task_info; 1751 u64 addr; 1752 1753 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1754 if (instance < 0 || instance >= adev->sdma.num_instances) { 1755 dev_err(adev->dev, "sdma instance invalid %d\n", instance); 1756 return -EINVAL; 1757 } 1758 1759 addr = (u64)entry->src_data[0] << 12; 1760 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 1761 1762 dev_dbg_ratelimited(adev->dev, 1763 "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u pasid:%u\n", 1764 instance, addr, entry->src_id, entry->ring_id, entry->vmid, 1765 entry->pasid); 1766 1767 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 1768 if (task_info) { 1769 dev_dbg_ratelimited(adev->dev, " for process %s pid %d thread %s pid %d\n", 1770 task_info->process_name, task_info->tgid, 1771 task_info->task_name, task_info->pid); 1772 amdgpu_vm_put_task_info(task_info); 1773 } 1774 1775 return 0; 1776 } 1777 1778 static int sdma_v4_4_2_process_vm_hole_irq(struct amdgpu_device *adev, 1779 struct amdgpu_irq_src *source, 1780 struct amdgpu_iv_entry *entry) 1781 { 1782 dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n"); 1783 sdma_v4_4_2_print_iv_entry(adev, entry); 1784 return 0; 1785 } 1786 1787 static int sdma_v4_4_2_process_doorbell_invalid_irq(struct amdgpu_device *adev, 1788 struct amdgpu_irq_src *source, 1789 struct amdgpu_iv_entry *entry) 1790 { 1791 1792 dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n"); 1793 sdma_v4_4_2_print_iv_entry(adev, entry); 1794 return 0; 1795 } 1796 1797 static int sdma_v4_4_2_process_pool_timeout_irq(struct amdgpu_device *adev, 1798 struct amdgpu_irq_src *source, 1799 struct amdgpu_iv_entry *entry) 1800 { 1801 dev_dbg_ratelimited(adev->dev, 1802 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n"); 1803 sdma_v4_4_2_print_iv_entry(adev, entry); 1804 return 0; 1805 } 1806 1807 static int sdma_v4_4_2_process_srbm_write_irq(struct amdgpu_device *adev, 1808 struct amdgpu_irq_src *source, 1809 struct amdgpu_iv_entry *entry) 1810 { 1811 dev_dbg_ratelimited(adev->dev, 1812 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n"); 1813 sdma_v4_4_2_print_iv_entry(adev, entry); 1814 return 0; 1815 } 1816 1817 static void sdma_v4_4_2_inst_update_medium_grain_light_sleep( 1818 struct amdgpu_device *adev, bool enable, uint32_t inst_mask) 1819 { 1820 uint32_t data, def; 1821 int i; 1822 1823 /* leave as default if it is not driver controlled */ 1824 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) 1825 return; 1826 1827 if (enable) { 1828 for_each_inst(i, inst_mask) { 1829 /* 1-not override: enable sdma mem light sleep */ 1830 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL); 1831 data |= SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1832 if (def != data) 1833 WREG32_SDMA(i, regSDMA_POWER_CNTL, data); 1834 } 1835 } else { 1836 for_each_inst(i, inst_mask) { 1837 /* 0-override:disable sdma mem light sleep */ 1838 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL); 1839 data &= ~SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1840 if (def != data) 1841 WREG32_SDMA(i, regSDMA_POWER_CNTL, data); 1842 } 1843 } 1844 } 1845 1846 static void sdma_v4_4_2_inst_update_medium_grain_clock_gating( 1847 struct amdgpu_device *adev, bool enable, uint32_t inst_mask) 1848 { 1849 uint32_t data, def; 1850 int i; 1851 1852 /* leave as default if it is not driver controlled */ 1853 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) 1854 return; 1855 1856 if (enable) { 1857 for_each_inst(i, inst_mask) { 1858 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL); 1859 data &= ~(SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1860 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1861 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1862 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1863 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1864 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1865 if (def != data) 1866 WREG32_SDMA(i, regSDMA_CLK_CTRL, data); 1867 } 1868 } else { 1869 for_each_inst(i, inst_mask) { 1870 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL); 1871 data |= (SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1872 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1873 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1874 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1875 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1876 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1877 if (def != data) 1878 WREG32_SDMA(i, regSDMA_CLK_CTRL, data); 1879 } 1880 } 1881 } 1882 1883 static int sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1884 enum amd_clockgating_state state) 1885 { 1886 struct amdgpu_device *adev = ip_block->adev; 1887 uint32_t inst_mask; 1888 1889 if (amdgpu_sriov_vf(adev)) 1890 return 0; 1891 1892 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1893 1894 sdma_v4_4_2_inst_update_medium_grain_clock_gating( 1895 adev, state == AMD_CG_STATE_GATE, inst_mask); 1896 sdma_v4_4_2_inst_update_medium_grain_light_sleep( 1897 adev, state == AMD_CG_STATE_GATE, inst_mask); 1898 return 0; 1899 } 1900 1901 static int sdma_v4_4_2_set_powergating_state(struct amdgpu_ip_block *ip_block, 1902 enum amd_powergating_state state) 1903 { 1904 return 0; 1905 } 1906 1907 static void sdma_v4_4_2_get_clockgating_state(void *handle, u64 *flags) 1908 { 1909 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1910 int data; 1911 1912 if (amdgpu_sriov_vf(adev)) 1913 *flags = 0; 1914 1915 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1916 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL)); 1917 if (!(data & SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK)) 1918 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1919 1920 /* AMD_CG_SUPPORT_SDMA_LS */ 1921 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL)); 1922 if (data & SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1923 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1924 } 1925 1926 static void sdma_v4_4_2_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 1927 { 1928 struct amdgpu_device *adev = ip_block->adev; 1929 int i, j; 1930 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); 1931 uint32_t instance_offset; 1932 1933 if (!adev->sdma.ip_dump) 1934 return; 1935 1936 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances); 1937 for (i = 0; i < adev->sdma.num_instances; i++) { 1938 instance_offset = i * reg_count; 1939 drm_printf(p, "\nInstance:%d\n", i); 1940 1941 for (j = 0; j < reg_count; j++) 1942 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_4_4_2[j].reg_name, 1943 adev->sdma.ip_dump[instance_offset + j]); 1944 } 1945 } 1946 1947 static void sdma_v4_4_2_dump_ip_state(struct amdgpu_ip_block *ip_block) 1948 { 1949 struct amdgpu_device *adev = ip_block->adev; 1950 int i, j; 1951 uint32_t instance_offset; 1952 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); 1953 1954 if (!adev->sdma.ip_dump) 1955 return; 1956 1957 for (i = 0; i < adev->sdma.num_instances; i++) { 1958 instance_offset = i * reg_count; 1959 for (j = 0; j < reg_count; j++) 1960 adev->sdma.ip_dump[instance_offset + j] = 1961 RREG32(sdma_v4_4_2_get_reg_offset(adev, i, 1962 sdma_reg_list_4_4_2[j].reg_offset)); 1963 } 1964 } 1965 1966 const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = { 1967 .name = "sdma_v4_4_2", 1968 .early_init = sdma_v4_4_2_early_init, 1969 .late_init = sdma_v4_4_2_late_init, 1970 .sw_init = sdma_v4_4_2_sw_init, 1971 .sw_fini = sdma_v4_4_2_sw_fini, 1972 .hw_init = sdma_v4_4_2_hw_init, 1973 .hw_fini = sdma_v4_4_2_hw_fini, 1974 .suspend = sdma_v4_4_2_suspend, 1975 .resume = sdma_v4_4_2_resume, 1976 .is_idle = sdma_v4_4_2_is_idle, 1977 .wait_for_idle = sdma_v4_4_2_wait_for_idle, 1978 .soft_reset = sdma_v4_4_2_soft_reset, 1979 .set_clockgating_state = sdma_v4_4_2_set_clockgating_state, 1980 .set_powergating_state = sdma_v4_4_2_set_powergating_state, 1981 .get_clockgating_state = sdma_v4_4_2_get_clockgating_state, 1982 .dump_ip_state = sdma_v4_4_2_dump_ip_state, 1983 .print_ip_state = sdma_v4_4_2_print_ip_state, 1984 }; 1985 1986 static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = { 1987 .type = AMDGPU_RING_TYPE_SDMA, 1988 .align_mask = 0xff, 1989 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1990 .support_64bit_ptrs = true, 1991 .get_rptr = sdma_v4_4_2_ring_get_rptr, 1992 .get_wptr = sdma_v4_4_2_ring_get_wptr, 1993 .set_wptr = sdma_v4_4_2_ring_set_wptr, 1994 .emit_frame_size = 1995 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */ 1996 3 + /* hdp invalidate */ 1997 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */ 1998 /* sdma_v4_4_2_ring_emit_vm_flush */ 1999 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2000 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2001 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */ 2002 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */ 2003 .emit_ib = sdma_v4_4_2_ring_emit_ib, 2004 .emit_fence = sdma_v4_4_2_ring_emit_fence, 2005 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync, 2006 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush, 2007 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush, 2008 .test_ring = sdma_v4_4_2_ring_test_ring, 2009 .test_ib = sdma_v4_4_2_ring_test_ib, 2010 .insert_nop = sdma_v4_4_2_ring_insert_nop, 2011 .pad_ib = sdma_v4_4_2_ring_pad_ib, 2012 .emit_wreg = sdma_v4_4_2_ring_emit_wreg, 2013 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, 2014 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2015 .reset = sdma_v4_4_2_reset_queue, 2016 }; 2017 2018 static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = { 2019 .type = AMDGPU_RING_TYPE_SDMA, 2020 .align_mask = 0xff, 2021 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2022 .support_64bit_ptrs = true, 2023 .get_rptr = sdma_v4_4_2_ring_get_rptr, 2024 .get_wptr = sdma_v4_4_2_page_ring_get_wptr, 2025 .set_wptr = sdma_v4_4_2_page_ring_set_wptr, 2026 .emit_frame_size = 2027 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */ 2028 3 + /* hdp invalidate */ 2029 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */ 2030 /* sdma_v4_4_2_ring_emit_vm_flush */ 2031 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2032 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2033 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */ 2034 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */ 2035 .emit_ib = sdma_v4_4_2_ring_emit_ib, 2036 .emit_fence = sdma_v4_4_2_ring_emit_fence, 2037 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync, 2038 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush, 2039 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush, 2040 .test_ring = sdma_v4_4_2_ring_test_ring, 2041 .test_ib = sdma_v4_4_2_ring_test_ib, 2042 .insert_nop = sdma_v4_4_2_ring_insert_nop, 2043 .pad_ib = sdma_v4_4_2_ring_pad_ib, 2044 .emit_wreg = sdma_v4_4_2_ring_emit_wreg, 2045 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, 2046 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2047 }; 2048 2049 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev) 2050 { 2051 int i, dev_inst; 2052 2053 for (i = 0; i < adev->sdma.num_instances; i++) { 2054 adev->sdma.instance[i].ring.funcs = &sdma_v4_4_2_ring_funcs; 2055 adev->sdma.instance[i].ring.me = i; 2056 if (adev->sdma.has_page_queue) { 2057 adev->sdma.instance[i].page.funcs = 2058 &sdma_v4_4_2_page_ring_funcs; 2059 adev->sdma.instance[i].page.me = i; 2060 } 2061 2062 dev_inst = GET_INST(SDMA0, i); 2063 /* AID to which SDMA belongs depends on physical instance */ 2064 adev->sdma.instance[i].aid_id = 2065 dev_inst / adev->sdma.num_inst_per_aid; 2066 } 2067 } 2068 2069 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_trap_irq_funcs = { 2070 .set = sdma_v4_4_2_set_trap_irq_state, 2071 .process = sdma_v4_4_2_process_trap_irq, 2072 }; 2073 2074 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_illegal_inst_irq_funcs = { 2075 .process = sdma_v4_4_2_process_illegal_inst_irq, 2076 }; 2077 2078 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ecc_irq_funcs = { 2079 .set = sdma_v4_4_2_set_ecc_irq_state, 2080 .process = amdgpu_sdma_process_ecc_irq, 2081 }; 2082 2083 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_vm_hole_irq_funcs = { 2084 .process = sdma_v4_4_2_process_vm_hole_irq, 2085 }; 2086 2087 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_doorbell_invalid_irq_funcs = { 2088 .process = sdma_v4_4_2_process_doorbell_invalid_irq, 2089 }; 2090 2091 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_pool_timeout_irq_funcs = { 2092 .process = sdma_v4_4_2_process_pool_timeout_irq, 2093 }; 2094 2095 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_srbm_write_irq_funcs = { 2096 .process = sdma_v4_4_2_process_srbm_write_irq, 2097 }; 2098 2099 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev) 2100 { 2101 adev->sdma.trap_irq.num_types = adev->sdma.num_instances; 2102 adev->sdma.ecc_irq.num_types = adev->sdma.num_instances; 2103 adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances; 2104 adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances; 2105 adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances; 2106 adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances; 2107 2108 adev->sdma.trap_irq.funcs = &sdma_v4_4_2_trap_irq_funcs; 2109 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_4_2_illegal_inst_irq_funcs; 2110 adev->sdma.ecc_irq.funcs = &sdma_v4_4_2_ecc_irq_funcs; 2111 adev->sdma.vm_hole_irq.funcs = &sdma_v4_4_2_vm_hole_irq_funcs; 2112 adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_4_2_doorbell_invalid_irq_funcs; 2113 adev->sdma.pool_timeout_irq.funcs = &sdma_v4_4_2_pool_timeout_irq_funcs; 2114 adev->sdma.srbm_write_irq.funcs = &sdma_v4_4_2_srbm_write_irq_funcs; 2115 } 2116 2117 /** 2118 * sdma_v4_4_2_emit_copy_buffer - copy buffer using the sDMA engine 2119 * 2120 * @ib: indirect buffer to copy to 2121 * @src_offset: src GPU address 2122 * @dst_offset: dst GPU address 2123 * @byte_count: number of bytes to xfer 2124 * @copy_flags: copy flags for the buffers 2125 * 2126 * Copy GPU buffers using the DMA engine. 2127 * Used by the amdgpu ttm implementation to move pages if 2128 * registered as the asic copy callback. 2129 */ 2130 static void sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib *ib, 2131 uint64_t src_offset, 2132 uint64_t dst_offset, 2133 uint32_t byte_count, 2134 uint32_t copy_flags) 2135 { 2136 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 2137 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 2138 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0); 2139 ib->ptr[ib->length_dw++] = byte_count - 1; 2140 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 2141 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 2142 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 2143 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2144 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2145 } 2146 2147 /** 2148 * sdma_v4_4_2_emit_fill_buffer - fill buffer using the sDMA engine 2149 * 2150 * @ib: indirect buffer to copy to 2151 * @src_data: value to write to buffer 2152 * @dst_offset: dst GPU address 2153 * @byte_count: number of bytes to xfer 2154 * 2155 * Fill GPU buffers using the DMA engine. 2156 */ 2157 static void sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib *ib, 2158 uint32_t src_data, 2159 uint64_t dst_offset, 2160 uint32_t byte_count) 2161 { 2162 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2163 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2164 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2165 ib->ptr[ib->length_dw++] = src_data; 2166 ib->ptr[ib->length_dw++] = byte_count - 1; 2167 } 2168 2169 static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = { 2170 .copy_max_bytes = 0x400000, 2171 .copy_num_dw = 7, 2172 .emit_copy_buffer = sdma_v4_4_2_emit_copy_buffer, 2173 2174 .fill_max_bytes = 0x400000, 2175 .fill_num_dw = 5, 2176 .emit_fill_buffer = sdma_v4_4_2_emit_fill_buffer, 2177 }; 2178 2179 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev) 2180 { 2181 adev->mman.buffer_funcs = &sdma_v4_4_2_buffer_funcs; 2182 if (adev->sdma.has_page_queue) 2183 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; 2184 else 2185 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2186 } 2187 2188 static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = { 2189 .copy_pte_num_dw = 7, 2190 .copy_pte = sdma_v4_4_2_vm_copy_pte, 2191 2192 .write_pte = sdma_v4_4_2_vm_write_pte, 2193 .set_pte_pde = sdma_v4_4_2_vm_set_pte_pde, 2194 }; 2195 2196 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev) 2197 { 2198 struct drm_gpu_scheduler *sched; 2199 unsigned i; 2200 2201 adev->vm_manager.vm_pte_funcs = &sdma_v4_4_2_vm_pte_funcs; 2202 for (i = 0; i < adev->sdma.num_instances; i++) { 2203 if (adev->sdma.has_page_queue) 2204 sched = &adev->sdma.instance[i].page.sched; 2205 else 2206 sched = &adev->sdma.instance[i].ring.sched; 2207 adev->vm_manager.vm_pte_scheds[i] = sched; 2208 } 2209 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 2210 } 2211 2212 const struct amdgpu_ip_block_version sdma_v4_4_2_ip_block = { 2213 .type = AMD_IP_BLOCK_TYPE_SDMA, 2214 .major = 4, 2215 .minor = 4, 2216 .rev = 2, 2217 .funcs = &sdma_v4_4_2_ip_funcs, 2218 }; 2219 2220 static int sdma_v4_4_2_xcp_resume(void *handle, uint32_t inst_mask) 2221 { 2222 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2223 int r; 2224 2225 if (!amdgpu_sriov_vf(adev)) 2226 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask); 2227 2228 r = sdma_v4_4_2_inst_start(adev, inst_mask, false); 2229 2230 return r; 2231 } 2232 2233 static int sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask) 2234 { 2235 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2236 uint32_t tmp_mask = inst_mask; 2237 int i; 2238 2239 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2240 for_each_inst(i, tmp_mask) { 2241 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 2242 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 2243 } 2244 } 2245 2246 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 2247 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 2248 2249 return 0; 2250 } 2251 2252 struct amdgpu_xcp_ip_funcs sdma_v4_4_2_xcp_funcs = { 2253 .suspend = &sdma_v4_4_2_xcp_suspend, 2254 .resume = &sdma_v4_4_2_xcp_resume 2255 }; 2256 2257 static const struct amdgpu_ras_err_status_reg_entry sdma_v4_2_2_ue_reg_list[] = { 2258 {AMDGPU_RAS_REG_ENTRY(SDMA0, 0, regSDMA_UE_ERR_STATUS_LO, regSDMA_UE_ERR_STATUS_HI), 2259 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SDMA"}, 2260 }; 2261 2262 static const struct amdgpu_ras_memory_id_entry sdma_v4_4_2_ras_memory_list[] = { 2263 {AMDGPU_SDMA_MBANK_DATA_BUF0, "SDMA_MBANK_DATA_BUF0"}, 2264 {AMDGPU_SDMA_MBANK_DATA_BUF1, "SDMA_MBANK_DATA_BUF1"}, 2265 {AMDGPU_SDMA_MBANK_DATA_BUF2, "SDMA_MBANK_DATA_BUF2"}, 2266 {AMDGPU_SDMA_MBANK_DATA_BUF3, "SDMA_MBANK_DATA_BUF3"}, 2267 {AMDGPU_SDMA_MBANK_DATA_BUF4, "SDMA_MBANK_DATA_BUF4"}, 2268 {AMDGPU_SDMA_MBANK_DATA_BUF5, "SDMA_MBANK_DATA_BUF5"}, 2269 {AMDGPU_SDMA_MBANK_DATA_BUF6, "SDMA_MBANK_DATA_BUF6"}, 2270 {AMDGPU_SDMA_MBANK_DATA_BUF7, "SDMA_MBANK_DATA_BUF7"}, 2271 {AMDGPU_SDMA_MBANK_DATA_BUF8, "SDMA_MBANK_DATA_BUF8"}, 2272 {AMDGPU_SDMA_MBANK_DATA_BUF9, "SDMA_MBANK_DATA_BUF9"}, 2273 {AMDGPU_SDMA_MBANK_DATA_BUF10, "SDMA_MBANK_DATA_BUF10"}, 2274 {AMDGPU_SDMA_MBANK_DATA_BUF11, "SDMA_MBANK_DATA_BUF11"}, 2275 {AMDGPU_SDMA_MBANK_DATA_BUF12, "SDMA_MBANK_DATA_BUF12"}, 2276 {AMDGPU_SDMA_MBANK_DATA_BUF13, "SDMA_MBANK_DATA_BUF13"}, 2277 {AMDGPU_SDMA_MBANK_DATA_BUF14, "SDMA_MBANK_DATA_BUF14"}, 2278 {AMDGPU_SDMA_MBANK_DATA_BUF15, "SDMA_MBANK_DATA_BUF15"}, 2279 {AMDGPU_SDMA_UCODE_BUF, "SDMA_UCODE_BUF"}, 2280 {AMDGPU_SDMA_RB_CMD_BUF, "SDMA_RB_CMD_BUF"}, 2281 {AMDGPU_SDMA_IB_CMD_BUF, "SDMA_IB_CMD_BUF"}, 2282 {AMDGPU_SDMA_UTCL1_RD_FIFO, "SDMA_UTCL1_RD_FIFO"}, 2283 {AMDGPU_SDMA_UTCL1_RDBST_FIFO, "SDMA_UTCL1_RDBST_FIFO"}, 2284 {AMDGPU_SDMA_UTCL1_WR_FIFO, "SDMA_UTCL1_WR_FIFO"}, 2285 {AMDGPU_SDMA_DATA_LUT_FIFO, "SDMA_DATA_LUT_FIFO"}, 2286 {AMDGPU_SDMA_SPLIT_DAT_BUF, "SDMA_SPLIT_DAT_BUF"}, 2287 }; 2288 2289 static void sdma_v4_4_2_inst_query_ras_error_count(struct amdgpu_device *adev, 2290 uint32_t sdma_inst, 2291 void *ras_err_status) 2292 { 2293 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 2294 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); 2295 unsigned long ue_count = 0; 2296 struct amdgpu_smuio_mcm_config_info mcm_info = { 2297 .socket_id = adev->smuio.funcs->get_socket_id(adev), 2298 .die_id = adev->sdma.instance[sdma_inst].aid_id, 2299 }; 2300 2301 /* sdma v4_4_2 doesn't support query ce counts */ 2302 amdgpu_ras_inst_query_ras_error_count(adev, 2303 sdma_v4_2_2_ue_reg_list, 2304 ARRAY_SIZE(sdma_v4_2_2_ue_reg_list), 2305 sdma_v4_4_2_ras_memory_list, 2306 ARRAY_SIZE(sdma_v4_4_2_ras_memory_list), 2307 sdma_dev_inst, 2308 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 2309 &ue_count); 2310 2311 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count); 2312 } 2313 2314 static void sdma_v4_4_2_query_ras_error_count(struct amdgpu_device *adev, 2315 void *ras_err_status) 2316 { 2317 uint32_t inst_mask; 2318 int i = 0; 2319 2320 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 2321 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2322 for_each_inst(i, inst_mask) 2323 sdma_v4_4_2_inst_query_ras_error_count(adev, i, ras_err_status); 2324 } else { 2325 dev_warn(adev->dev, "SDMA RAS is not supported\n"); 2326 } 2327 } 2328 2329 static void sdma_v4_4_2_inst_reset_ras_error_count(struct amdgpu_device *adev, 2330 uint32_t sdma_inst) 2331 { 2332 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); 2333 2334 amdgpu_ras_inst_reset_ras_error_count(adev, 2335 sdma_v4_2_2_ue_reg_list, 2336 ARRAY_SIZE(sdma_v4_2_2_ue_reg_list), 2337 sdma_dev_inst); 2338 } 2339 2340 static void sdma_v4_4_2_reset_ras_error_count(struct amdgpu_device *adev) 2341 { 2342 uint32_t inst_mask; 2343 int i = 0; 2344 2345 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 2346 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2347 for_each_inst(i, inst_mask) 2348 sdma_v4_4_2_inst_reset_ras_error_count(adev, i); 2349 } else { 2350 dev_warn(adev->dev, "SDMA RAS is not supported\n"); 2351 } 2352 } 2353 2354 static const struct amdgpu_ras_block_hw_ops sdma_v4_4_2_ras_hw_ops = { 2355 .query_ras_error_count = sdma_v4_4_2_query_ras_error_count, 2356 .reset_ras_error_count = sdma_v4_4_2_reset_ras_error_count, 2357 }; 2358 2359 static int sdma_v4_4_2_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, 2360 enum aca_smu_type type, void *data) 2361 { 2362 struct aca_bank_info info; 2363 u64 misc0; 2364 int ret; 2365 2366 ret = aca_bank_info_decode(bank, &info); 2367 if (ret) 2368 return ret; 2369 2370 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 2371 switch (type) { 2372 case ACA_SMU_TYPE_UE: 2373 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE, 2374 1ULL); 2375 break; 2376 case ACA_SMU_TYPE_CE: 2377 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_CE, 2378 ACA_REG__MISC0__ERRCNT(misc0)); 2379 break; 2380 default: 2381 return -EINVAL; 2382 } 2383 2384 return ret; 2385 } 2386 2387 /* CODE_SDMA0 - CODE_SDMA4, reference to smu driver if header file */ 2388 static int sdma_v4_4_2_err_codes[] = { 33, 34, 35, 36 }; 2389 2390 static bool sdma_v4_4_2_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 2391 enum aca_smu_type type, void *data) 2392 { 2393 u32 instlo; 2394 2395 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 2396 instlo &= GENMASK(31, 1); 2397 2398 if (instlo != mmSMNAID_AID0_MCA_SMU) 2399 return false; 2400 2401 if (aca_bank_check_error_codes(handle->adev, bank, 2402 sdma_v4_4_2_err_codes, 2403 ARRAY_SIZE(sdma_v4_4_2_err_codes))) 2404 return false; 2405 2406 return true; 2407 } 2408 2409 static const struct aca_bank_ops sdma_v4_4_2_aca_bank_ops = { 2410 .aca_bank_parser = sdma_v4_4_2_aca_bank_parser, 2411 .aca_bank_is_valid = sdma_v4_4_2_aca_bank_is_valid, 2412 }; 2413 2414 static const struct aca_info sdma_v4_4_2_aca_info = { 2415 .hwip = ACA_HWIP_TYPE_SMU, 2416 .mask = ACA_ERROR_UE_MASK, 2417 .bank_ops = &sdma_v4_4_2_aca_bank_ops, 2418 }; 2419 2420 static int sdma_v4_4_2_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 2421 { 2422 int r; 2423 2424 r = amdgpu_sdma_ras_late_init(adev, ras_block); 2425 if (r) 2426 return r; 2427 2428 return amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__SDMA, 2429 &sdma_v4_4_2_aca_info, NULL); 2430 } 2431 2432 static struct amdgpu_sdma_ras sdma_v4_4_2_ras = { 2433 .ras_block = { 2434 .hw_ops = &sdma_v4_4_2_ras_hw_ops, 2435 .ras_late_init = sdma_v4_4_2_ras_late_init, 2436 }, 2437 }; 2438 2439 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev) 2440 { 2441 adev->sdma.ras = &sdma_v4_4_2_ras; 2442 } 2443