1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_xcp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_trace.h" 33 #include "amdgpu_reset.h" 34 35 #include "sdma/sdma_4_4_2_offset.h" 36 #include "sdma/sdma_4_4_2_sh_mask.h" 37 38 #include "soc15_common.h" 39 #include "soc15.h" 40 #include "vega10_sdma_pkt_open.h" 41 42 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 43 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 44 45 #include "amdgpu_ras.h" 46 47 MODULE_FIRMWARE("amdgpu/sdma_4_4_2.bin"); 48 MODULE_FIRMWARE("amdgpu/sdma_4_4_4.bin"); 49 MODULE_FIRMWARE("amdgpu/sdma_4_4_5.bin"); 50 51 static const struct amdgpu_hwip_reg_entry sdma_reg_list_4_4_2[] = { 52 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS_REG), 53 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS1_REG), 54 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS2_REG), 55 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS3_REG), 56 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UCODE_CHECKSUM), 57 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH_HI), 58 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH), 59 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_STATUS), 60 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_STATUS), 61 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK0), 62 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK1), 63 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK0), 64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK1), 65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_CNTL), 66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR), 67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR_HI), 68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR), 69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR_HI), 70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_OFFSET), 71 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_LO), 72 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_HI), 73 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_CNTL), 74 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_RPTR), 75 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_SUB_REMAIN), 76 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_DUMMY_REG), 77 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_CNTL), 78 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR), 79 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR_HI), 80 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR), 81 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR_HI), 82 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_OFFSET), 83 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_LO), 84 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_HI), 85 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_DUMMY_REG), 86 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_CNTL), 87 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR), 88 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR_HI), 89 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR), 90 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR_HI), 91 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_OFFSET), 92 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_LO), 93 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_HI), 94 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_DUMMY_REG), 95 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_VM_CNTL) 96 }; 97 98 #define mmSMNAID_AID0_MCA_SMU 0x03b30400 99 100 #define WREG32_SDMA(instance, offset, value) \ 101 WREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)), value) 102 #define RREG32_SDMA(instance, offset) \ 103 RREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset))) 104 105 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev); 106 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev); 107 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev); 108 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev); 109 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev); 110 static void sdma_v4_4_2_update_reset_mask(struct amdgpu_device *adev); 111 static int sdma_v4_4_2_stop_queue(struct amdgpu_ring *ring); 112 static int sdma_v4_4_2_restore_queue(struct amdgpu_ring *ring); 113 114 static u32 sdma_v4_4_2_get_reg_offset(struct amdgpu_device *adev, 115 u32 instance, u32 offset) 116 { 117 u32 dev_inst = GET_INST(SDMA0, instance); 118 119 return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset); 120 } 121 122 static unsigned sdma_v4_4_2_seq_to_irq_id(int seq_num) 123 { 124 switch (seq_num) { 125 case 0: 126 return SOC15_IH_CLIENTID_SDMA0; 127 case 1: 128 return SOC15_IH_CLIENTID_SDMA1; 129 case 2: 130 return SOC15_IH_CLIENTID_SDMA2; 131 case 3: 132 return SOC15_IH_CLIENTID_SDMA3; 133 default: 134 return -EINVAL; 135 } 136 } 137 138 static int sdma_v4_4_2_irq_id_to_seq(struct amdgpu_device *adev, unsigned client_id) 139 { 140 switch (client_id) { 141 case SOC15_IH_CLIENTID_SDMA0: 142 return 0; 143 case SOC15_IH_CLIENTID_SDMA1: 144 return 1; 145 case SOC15_IH_CLIENTID_SDMA2: 146 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) 147 return 0; 148 else 149 return 2; 150 case SOC15_IH_CLIENTID_SDMA3: 151 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) 152 return 1; 153 else 154 return 3; 155 default: 156 return -EINVAL; 157 } 158 } 159 160 static void sdma_v4_4_2_inst_init_golden_registers(struct amdgpu_device *adev, 161 uint32_t inst_mask) 162 { 163 u32 val; 164 int i; 165 166 for (i = 0; i < adev->sdma.num_instances; i++) { 167 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG); 168 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4); 169 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, 170 PIPE_INTERLEAVE_SIZE, 0); 171 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG, val); 172 173 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ); 174 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS, 175 4); 176 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, 177 PIPE_INTERLEAVE_SIZE, 0); 178 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ, val); 179 } 180 } 181 182 /** 183 * sdma_v4_4_2_init_microcode - load ucode images from disk 184 * 185 * @adev: amdgpu_device pointer 186 * 187 * Use the firmware interface to load the ucode images into 188 * the driver (not loaded into hw). 189 * Returns 0 on success, error on failure. 190 */ 191 static int sdma_v4_4_2_init_microcode(struct amdgpu_device *adev) 192 { 193 int ret, i; 194 195 for (i = 0; i < adev->sdma.num_instances; i++) { 196 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) || 197 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 4) || 198 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) { 199 ret = amdgpu_sdma_init_microcode(adev, 0, true); 200 break; 201 } else { 202 ret = amdgpu_sdma_init_microcode(adev, i, false); 203 if (ret) 204 return ret; 205 } 206 } 207 208 return ret; 209 } 210 211 /** 212 * sdma_v4_4_2_ring_get_rptr - get the current read pointer 213 * 214 * @ring: amdgpu ring pointer 215 * 216 * Get the current rptr from the hardware. 217 */ 218 static uint64_t sdma_v4_4_2_ring_get_rptr(struct amdgpu_ring *ring) 219 { 220 u64 rptr; 221 222 /* XXX check if swapping is necessary on BE */ 223 rptr = READ_ONCE(*((u64 *)&ring->adev->wb.wb[ring->rptr_offs])); 224 225 DRM_DEBUG("rptr before shift == 0x%016llx\n", rptr); 226 return rptr >> 2; 227 } 228 229 /** 230 * sdma_v4_4_2_ring_get_wptr - get the current write pointer 231 * 232 * @ring: amdgpu ring pointer 233 * 234 * Get the current wptr from the hardware. 235 */ 236 static uint64_t sdma_v4_4_2_ring_get_wptr(struct amdgpu_ring *ring) 237 { 238 struct amdgpu_device *adev = ring->adev; 239 u64 wptr; 240 241 if (ring->use_doorbell) { 242 /* XXX check if swapping is necessary on BE */ 243 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 244 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 245 } else { 246 wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI); 247 wptr = wptr << 32; 248 wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR); 249 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 250 ring->me, wptr); 251 } 252 253 return wptr >> 2; 254 } 255 256 /** 257 * sdma_v4_4_2_ring_set_wptr - commit the write pointer 258 * 259 * @ring: amdgpu ring pointer 260 * 261 * Write the wptr back to the hardware. 262 */ 263 static void sdma_v4_4_2_ring_set_wptr(struct amdgpu_ring *ring) 264 { 265 struct amdgpu_device *adev = ring->adev; 266 267 DRM_DEBUG("Setting write pointer\n"); 268 if (ring->use_doorbell) { 269 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 270 271 DRM_DEBUG("Using doorbell -- " 272 "wptr_offs == 0x%08x " 273 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 274 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 275 ring->wptr_offs, 276 lower_32_bits(ring->wptr << 2), 277 upper_32_bits(ring->wptr << 2)); 278 /* XXX check if swapping is necessary on BE */ 279 WRITE_ONCE(*wb, (ring->wptr << 2)); 280 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 281 ring->doorbell_index, ring->wptr << 2); 282 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 283 } else { 284 DRM_DEBUG("Not using doorbell -- " 285 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 286 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 287 ring->me, 288 lower_32_bits(ring->wptr << 2), 289 ring->me, 290 upper_32_bits(ring->wptr << 2)); 291 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR, 292 lower_32_bits(ring->wptr << 2)); 293 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI, 294 upper_32_bits(ring->wptr << 2)); 295 } 296 } 297 298 /** 299 * sdma_v4_4_2_page_ring_get_wptr - get the current write pointer 300 * 301 * @ring: amdgpu ring pointer 302 * 303 * Get the current wptr from the hardware. 304 */ 305 static uint64_t sdma_v4_4_2_page_ring_get_wptr(struct amdgpu_ring *ring) 306 { 307 struct amdgpu_device *adev = ring->adev; 308 u64 wptr; 309 310 if (ring->use_doorbell) { 311 /* XXX check if swapping is necessary on BE */ 312 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 313 } else { 314 wptr = RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI); 315 wptr = wptr << 32; 316 wptr |= RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR); 317 } 318 319 return wptr >> 2; 320 } 321 322 /** 323 * sdma_v4_4_2_page_ring_set_wptr - commit the write pointer 324 * 325 * @ring: amdgpu ring pointer 326 * 327 * Write the wptr back to the hardware. 328 */ 329 static void sdma_v4_4_2_page_ring_set_wptr(struct amdgpu_ring *ring) 330 { 331 struct amdgpu_device *adev = ring->adev; 332 333 if (ring->use_doorbell) { 334 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 335 336 /* XXX check if swapping is necessary on BE */ 337 WRITE_ONCE(*wb, (ring->wptr << 2)); 338 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 339 } else { 340 uint64_t wptr = ring->wptr << 2; 341 342 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR, 343 lower_32_bits(wptr)); 344 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI, 345 upper_32_bits(wptr)); 346 } 347 } 348 349 static void sdma_v4_4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 350 { 351 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 352 int i; 353 354 for (i = 0; i < count; i++) 355 if (sdma && sdma->burst_nop && (i == 0)) 356 amdgpu_ring_write(ring, ring->funcs->nop | 357 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 358 else 359 amdgpu_ring_write(ring, ring->funcs->nop); 360 } 361 362 /** 363 * sdma_v4_4_2_ring_emit_ib - Schedule an IB on the DMA engine 364 * 365 * @ring: amdgpu ring pointer 366 * @job: job to retrieve vmid from 367 * @ib: IB object to schedule 368 * @flags: unused 369 * 370 * Schedule an IB in the DMA ring. 371 */ 372 static void sdma_v4_4_2_ring_emit_ib(struct amdgpu_ring *ring, 373 struct amdgpu_job *job, 374 struct amdgpu_ib *ib, 375 uint32_t flags) 376 { 377 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 378 379 /* IB packet must end on a 8 DW boundary */ 380 sdma_v4_4_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 381 382 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 383 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 384 /* base must be 32 byte aligned */ 385 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 386 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 387 amdgpu_ring_write(ring, ib->length_dw); 388 amdgpu_ring_write(ring, 0); 389 amdgpu_ring_write(ring, 0); 390 391 } 392 393 static void sdma_v4_4_2_wait_reg_mem(struct amdgpu_ring *ring, 394 int mem_space, int hdp, 395 uint32_t addr0, uint32_t addr1, 396 uint32_t ref, uint32_t mask, 397 uint32_t inv) 398 { 399 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 400 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 401 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 402 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 403 if (mem_space) { 404 /* memory */ 405 amdgpu_ring_write(ring, addr0); 406 amdgpu_ring_write(ring, addr1); 407 } else { 408 /* registers */ 409 amdgpu_ring_write(ring, addr0 << 2); 410 amdgpu_ring_write(ring, addr1 << 2); 411 } 412 amdgpu_ring_write(ring, ref); /* reference */ 413 amdgpu_ring_write(ring, mask); /* mask */ 414 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 415 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 416 } 417 418 /** 419 * sdma_v4_4_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 420 * 421 * @ring: amdgpu ring pointer 422 * 423 * Emit an hdp flush packet on the requested DMA ring. 424 */ 425 static void sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 426 { 427 struct amdgpu_device *adev = ring->adev; 428 u32 ref_and_mask = 0; 429 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 430 431 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 432 << (ring->me % adev->sdma.num_inst_per_aid); 433 434 sdma_v4_4_2_wait_reg_mem(ring, 0, 1, 435 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 436 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 437 ref_and_mask, ref_and_mask, 10); 438 } 439 440 /** 441 * sdma_v4_4_2_ring_emit_fence - emit a fence on the DMA ring 442 * 443 * @ring: amdgpu ring pointer 444 * @addr: address 445 * @seq: sequence number 446 * @flags: fence related flags 447 * 448 * Add a DMA fence packet to the ring to write 449 * the fence seq number and DMA trap packet to generate 450 * an interrupt if needed. 451 */ 452 static void sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 453 unsigned flags) 454 { 455 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 456 /* write the fence */ 457 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 458 /* zero in first two bits */ 459 BUG_ON(addr & 0x3); 460 amdgpu_ring_write(ring, lower_32_bits(addr)); 461 amdgpu_ring_write(ring, upper_32_bits(addr)); 462 amdgpu_ring_write(ring, lower_32_bits(seq)); 463 464 /* optionally write high bits as well */ 465 if (write64bit) { 466 addr += 4; 467 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 468 /* zero in first two bits */ 469 BUG_ON(addr & 0x3); 470 amdgpu_ring_write(ring, lower_32_bits(addr)); 471 amdgpu_ring_write(ring, upper_32_bits(addr)); 472 amdgpu_ring_write(ring, upper_32_bits(seq)); 473 } 474 475 /* generate an interrupt */ 476 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 477 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 478 } 479 480 481 /** 482 * sdma_v4_4_2_inst_gfx_stop - stop the gfx async dma engines 483 * 484 * @adev: amdgpu_device pointer 485 * @inst_mask: mask of dma engine instances to be disabled 486 * 487 * Stop the gfx async dma ring buffers. 488 */ 489 static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev, 490 uint32_t inst_mask) 491 { 492 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 493 u32 doorbell_offset, doorbell; 494 u32 rb_cntl, ib_cntl, sdma_cntl; 495 int i; 496 497 for_each_inst(i, inst_mask) { 498 sdma[i] = &adev->sdma.instance[i].ring; 499 500 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); 501 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0); 502 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 503 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 504 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0); 505 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 506 sdma_cntl = RREG32_SDMA(i, regSDMA_CNTL); 507 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, UTC_L1_ENABLE, 0); 508 WREG32_SDMA(i, regSDMA_CNTL, sdma_cntl); 509 510 if (sdma[i]->use_doorbell) { 511 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL); 512 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET); 513 514 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 0); 515 doorbell_offset = REG_SET_FIELD(doorbell_offset, 516 SDMA_GFX_DOORBELL_OFFSET, 517 OFFSET, 0); 518 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell); 519 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset); 520 } 521 } 522 } 523 524 /** 525 * sdma_v4_4_2_inst_rlc_stop - stop the compute async dma engines 526 * 527 * @adev: amdgpu_device pointer 528 * @inst_mask: mask of dma engine instances to be disabled 529 * 530 * Stop the compute async dma queues. 531 */ 532 static void sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device *adev, 533 uint32_t inst_mask) 534 { 535 /* XXX todo */ 536 } 537 538 /** 539 * sdma_v4_4_2_inst_page_stop - stop the page async dma engines 540 * 541 * @adev: amdgpu_device pointer 542 * @inst_mask: mask of dma engine instances to be disabled 543 * 544 * Stop the page async dma ring buffers. 545 */ 546 static void sdma_v4_4_2_inst_page_stop(struct amdgpu_device *adev, 547 uint32_t inst_mask) 548 { 549 u32 rb_cntl, ib_cntl; 550 int i; 551 552 for_each_inst(i, inst_mask) { 553 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); 554 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, 555 RB_ENABLE, 0); 556 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 557 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); 558 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, 559 IB_ENABLE, 0); 560 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); 561 } 562 } 563 564 /** 565 * sdma_v4_4_2_inst_ctx_switch_enable - stop the async dma engines context switch 566 * 567 * @adev: amdgpu_device pointer 568 * @enable: enable/disable the DMA MEs context switch. 569 * @inst_mask: mask of dma engine instances to be enabled 570 * 571 * Halt or unhalt the async dma engines context switch. 572 */ 573 static void sdma_v4_4_2_inst_ctx_switch_enable(struct amdgpu_device *adev, 574 bool enable, uint32_t inst_mask) 575 { 576 u32 f32_cntl, phase_quantum = 0; 577 int i; 578 579 if (amdgpu_sdma_phase_quantum) { 580 unsigned value = amdgpu_sdma_phase_quantum; 581 unsigned unit = 0; 582 583 while (value > (SDMA_PHASE0_QUANTUM__VALUE_MASK >> 584 SDMA_PHASE0_QUANTUM__VALUE__SHIFT)) { 585 value = (value + 1) >> 1; 586 unit++; 587 } 588 if (unit > (SDMA_PHASE0_QUANTUM__UNIT_MASK >> 589 SDMA_PHASE0_QUANTUM__UNIT__SHIFT)) { 590 value = (SDMA_PHASE0_QUANTUM__VALUE_MASK >> 591 SDMA_PHASE0_QUANTUM__VALUE__SHIFT); 592 unit = (SDMA_PHASE0_QUANTUM__UNIT_MASK >> 593 SDMA_PHASE0_QUANTUM__UNIT__SHIFT); 594 WARN_ONCE(1, 595 "clamping sdma_phase_quantum to %uK clock cycles\n", 596 value << unit); 597 } 598 phase_quantum = 599 value << SDMA_PHASE0_QUANTUM__VALUE__SHIFT | 600 unit << SDMA_PHASE0_QUANTUM__UNIT__SHIFT; 601 } 602 603 for_each_inst(i, inst_mask) { 604 f32_cntl = RREG32_SDMA(i, regSDMA_CNTL); 605 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_CNTL, 606 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 607 if (enable && amdgpu_sdma_phase_quantum) { 608 WREG32_SDMA(i, regSDMA_PHASE0_QUANTUM, phase_quantum); 609 WREG32_SDMA(i, regSDMA_PHASE1_QUANTUM, phase_quantum); 610 WREG32_SDMA(i, regSDMA_PHASE2_QUANTUM, phase_quantum); 611 } 612 WREG32_SDMA(i, regSDMA_CNTL, f32_cntl); 613 614 /* Extend page fault timeout to avoid interrupt storm */ 615 WREG32_SDMA(i, regSDMA_UTCL1_TIMEOUT, 0x00800080); 616 } 617 } 618 619 /** 620 * sdma_v4_4_2_inst_enable - stop the async dma engines 621 * 622 * @adev: amdgpu_device pointer 623 * @enable: enable/disable the DMA MEs. 624 * @inst_mask: mask of dma engine instances to be enabled 625 * 626 * Halt or unhalt the async dma engines. 627 */ 628 static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable, 629 uint32_t inst_mask) 630 { 631 u32 f32_cntl; 632 int i; 633 634 if (!enable) { 635 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask); 636 sdma_v4_4_2_inst_rlc_stop(adev, inst_mask); 637 if (adev->sdma.has_page_queue) 638 sdma_v4_4_2_inst_page_stop(adev, inst_mask); 639 640 /* SDMA FW needs to respond to FREEZE requests during reset. 641 * Keep it running during reset */ 642 if (!amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 643 return; 644 } 645 646 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 647 return; 648 649 for_each_inst(i, inst_mask) { 650 f32_cntl = RREG32_SDMA(i, regSDMA_F32_CNTL); 651 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1); 652 WREG32_SDMA(i, regSDMA_F32_CNTL, f32_cntl); 653 } 654 } 655 656 /* 657 * sdma_v4_4_2_rb_cntl - get parameters for rb_cntl 658 */ 659 static uint32_t sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 660 { 661 /* Set ring buffer size in dwords */ 662 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 663 664 barrier(); /* work around https://llvm.org/pr42576 */ 665 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 666 #ifdef __BIG_ENDIAN 667 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 668 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, 669 RPTR_WRITEBACK_SWAP_ENABLE, 1); 670 #endif 671 return rb_cntl; 672 } 673 674 /** 675 * sdma_v4_4_2_gfx_resume - setup and start the async dma engines 676 * 677 * @adev: amdgpu_device pointer 678 * @i: instance to resume 679 * @restore: used to restore wptr when restart 680 * 681 * Set up the gfx DMA ring buffers and enable them. 682 * Returns 0 for success, error for failure. 683 */ 684 static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i, bool restore) 685 { 686 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 687 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 688 u32 wb_offset; 689 u32 doorbell; 690 u32 doorbell_offset; 691 u64 wptr_gpu_addr; 692 u64 rwptr; 693 694 wb_offset = (ring->rptr_offs * 4); 695 696 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); 697 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 698 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 699 700 /* set the wb address whether it's enabled or not */ 701 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_HI, 702 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 703 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_LO, 704 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 705 706 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, 707 RPTR_WRITEBACK_ENABLE, 1); 708 709 WREG32_SDMA(i, regSDMA_GFX_RB_BASE, ring->gpu_addr >> 8); 710 WREG32_SDMA(i, regSDMA_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 711 712 if (!restore) 713 ring->wptr = 0; 714 715 /* before programing wptr to a less value, need set minor_ptr_update first */ 716 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 1); 717 718 /* For the guilty queue, set RPTR to the current wptr to skip bad commands, 719 * It is not a guilty queue, restore cache_rptr and continue execution. 720 */ 721 if (adev->sdma.instance[i].gfx_guilty) 722 rwptr = ring->wptr; 723 else 724 rwptr = ring->cached_rptr; 725 726 /* Initialize the ring buffer's read and write pointers */ 727 if (restore) { 728 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, lower_32_bits(rwptr << 2)); 729 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, upper_32_bits(rwptr << 2)); 730 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, lower_32_bits(rwptr << 2)); 731 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, upper_32_bits(rwptr << 2)); 732 } else { 733 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0); 734 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0); 735 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0); 736 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0); 737 } 738 739 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL); 740 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET); 741 742 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 743 ring->use_doorbell); 744 doorbell_offset = REG_SET_FIELD(doorbell_offset, 745 SDMA_GFX_DOORBELL_OFFSET, 746 OFFSET, ring->doorbell_index); 747 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell); 748 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset); 749 750 sdma_v4_4_2_ring_set_wptr(ring); 751 752 /* set minor_ptr_update to 0 after wptr programed */ 753 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 0); 754 755 /* setup the wptr shadow polling */ 756 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 757 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_LO, 758 lower_32_bits(wptr_gpu_addr)); 759 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_HI, 760 upper_32_bits(wptr_gpu_addr)); 761 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL); 762 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 763 SDMA_GFX_RB_WPTR_POLL_CNTL, 764 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 765 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 766 767 /* enable DMA RB */ 768 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 1); 769 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 770 771 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 772 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 1); 773 #ifdef __BIG_ENDIAN 774 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 775 #endif 776 /* enable DMA IBs */ 777 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 778 } 779 780 /** 781 * sdma_v4_4_2_page_resume - setup and start the async dma engines 782 * 783 * @adev: amdgpu_device pointer 784 * @i: instance to resume 785 * @restore: boolean to say restore needed or not 786 * 787 * Set up the page DMA ring buffers and enable them. 788 * Returns 0 for success, error for failure. 789 */ 790 static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i, bool restore) 791 { 792 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 793 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 794 u32 wb_offset; 795 u32 doorbell; 796 u32 doorbell_offset; 797 u64 wptr_gpu_addr; 798 u64 rwptr; 799 800 wb_offset = (ring->rptr_offs * 4); 801 802 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); 803 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 804 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 805 806 /* For the guilty queue, set RPTR to the current wptr to skip bad commands, 807 * It is not a guilty queue, restore cache_rptr and continue execution. 808 */ 809 if (adev->sdma.instance[i].page_guilty) 810 rwptr = ring->wptr; 811 else 812 rwptr = ring->cached_rptr; 813 814 /* Initialize the ring buffer's read and write pointers */ 815 if (restore) { 816 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, lower_32_bits(rwptr << 2)); 817 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, upper_32_bits(rwptr << 2)); 818 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, lower_32_bits(rwptr << 2)); 819 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, upper_32_bits(rwptr << 2)); 820 } else { 821 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, 0); 822 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, 0); 823 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, 0); 824 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, 0); 825 } 826 827 /* set the wb address whether it's enabled or not */ 828 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_HI, 829 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 830 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_LO, 831 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 832 833 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, 834 RPTR_WRITEBACK_ENABLE, 1); 835 836 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE, ring->gpu_addr >> 8); 837 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 838 839 if (!restore) 840 ring->wptr = 0; 841 842 /* before programing wptr to a less value, need set minor_ptr_update first */ 843 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 1); 844 845 doorbell = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL); 846 doorbell_offset = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET); 847 848 doorbell = REG_SET_FIELD(doorbell, SDMA_PAGE_DOORBELL, ENABLE, 849 ring->use_doorbell); 850 doorbell_offset = REG_SET_FIELD(doorbell_offset, 851 SDMA_PAGE_DOORBELL_OFFSET, 852 OFFSET, ring->doorbell_index); 853 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL, doorbell); 854 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET, doorbell_offset); 855 856 /* paging queue doorbell range is setup at sdma_v4_4_2_gfx_resume */ 857 sdma_v4_4_2_page_ring_set_wptr(ring); 858 859 /* set minor_ptr_update to 0 after wptr programed */ 860 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 0); 861 862 /* setup the wptr shadow polling */ 863 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 864 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_LO, 865 lower_32_bits(wptr_gpu_addr)); 866 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_HI, 867 upper_32_bits(wptr_gpu_addr)); 868 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL); 869 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 870 SDMA_PAGE_RB_WPTR_POLL_CNTL, 871 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 872 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 873 874 /* enable DMA RB */ 875 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, RB_ENABLE, 1); 876 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 877 878 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); 879 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_ENABLE, 1); 880 #ifdef __BIG_ENDIAN 881 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 882 #endif 883 /* enable DMA IBs */ 884 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); 885 } 886 887 static void sdma_v4_4_2_init_pg(struct amdgpu_device *adev) 888 { 889 890 } 891 892 /** 893 * sdma_v4_4_2_inst_rlc_resume - setup and start the async dma engines 894 * 895 * @adev: amdgpu_device pointer 896 * @inst_mask: mask of dma engine instances to be enabled 897 * 898 * Set up the compute DMA queues and enable them. 899 * Returns 0 for success, error for failure. 900 */ 901 static int sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device *adev, 902 uint32_t inst_mask) 903 { 904 sdma_v4_4_2_init_pg(adev); 905 906 return 0; 907 } 908 909 /** 910 * sdma_v4_4_2_inst_load_microcode - load the sDMA ME ucode 911 * 912 * @adev: amdgpu_device pointer 913 * @inst_mask: mask of dma engine instances to be enabled 914 * 915 * Loads the sDMA0/1 ucode. 916 * Returns 0 for success, -EINVAL if the ucode is not available. 917 */ 918 static int sdma_v4_4_2_inst_load_microcode(struct amdgpu_device *adev, 919 uint32_t inst_mask) 920 { 921 const struct sdma_firmware_header_v1_0 *hdr; 922 const __le32 *fw_data; 923 u32 fw_size; 924 int i, j; 925 926 /* halt the MEs */ 927 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 928 929 for_each_inst(i, inst_mask) { 930 if (!adev->sdma.instance[i].fw) 931 return -EINVAL; 932 933 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 934 amdgpu_ucode_print_sdma_hdr(&hdr->header); 935 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 936 937 fw_data = (const __le32 *) 938 (adev->sdma.instance[i].fw->data + 939 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 940 941 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 0); 942 943 for (j = 0; j < fw_size; j++) 944 WREG32_SDMA(i, regSDMA_UCODE_DATA, 945 le32_to_cpup(fw_data++)); 946 947 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 948 adev->sdma.instance[i].fw_version); 949 } 950 951 return 0; 952 } 953 954 /** 955 * sdma_v4_4_2_inst_start - setup and start the async dma engines 956 * 957 * @adev: amdgpu_device pointer 958 * @inst_mask: mask of dma engine instances to be enabled 959 * @restore: boolean to say restore needed or not 960 * 961 * Set up the DMA engines and enable them. 962 * Returns 0 for success, error for failure. 963 */ 964 static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev, 965 uint32_t inst_mask, bool restore) 966 { 967 struct amdgpu_ring *ring; 968 uint32_t tmp_mask; 969 int i, r = 0; 970 971 if (amdgpu_sriov_vf(adev)) { 972 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 973 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 974 } else { 975 /* bypass sdma microcode loading on Gopher */ 976 if (!restore && adev->firmware.load_type != AMDGPU_FW_LOAD_PSP && 977 adev->sdma.instance[0].fw) { 978 r = sdma_v4_4_2_inst_load_microcode(adev, inst_mask); 979 if (r) 980 return r; 981 } 982 983 /* unhalt the MEs */ 984 sdma_v4_4_2_inst_enable(adev, true, inst_mask); 985 /* enable sdma ring preemption */ 986 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask); 987 } 988 989 /* start the gfx rings and rlc compute queues */ 990 tmp_mask = inst_mask; 991 for_each_inst(i, tmp_mask) { 992 uint32_t temp; 993 994 WREG32_SDMA(i, regSDMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); 995 sdma_v4_4_2_gfx_resume(adev, i, restore); 996 if (adev->sdma.has_page_queue) 997 sdma_v4_4_2_page_resume(adev, i, restore); 998 999 /* set utc l1 enable flag always to 1 */ 1000 temp = RREG32_SDMA(i, regSDMA_CNTL); 1001 temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1); 1002 WREG32_SDMA(i, regSDMA_CNTL, temp); 1003 1004 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) < IP_VERSION(4, 4, 5)) { 1005 /* enable context empty interrupt during initialization */ 1006 temp = REG_SET_FIELD(temp, SDMA_CNTL, CTXEMPTY_INT_ENABLE, 1); 1007 WREG32_SDMA(i, regSDMA_CNTL, temp); 1008 } 1009 if (!amdgpu_sriov_vf(adev)) { 1010 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1011 /* unhalt engine */ 1012 temp = RREG32_SDMA(i, regSDMA_F32_CNTL); 1013 temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0); 1014 WREG32_SDMA(i, regSDMA_F32_CNTL, temp); 1015 } 1016 } 1017 } 1018 1019 if (amdgpu_sriov_vf(adev)) { 1020 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask); 1021 sdma_v4_4_2_inst_enable(adev, true, inst_mask); 1022 } else { 1023 r = sdma_v4_4_2_inst_rlc_resume(adev, inst_mask); 1024 if (r) 1025 return r; 1026 } 1027 1028 tmp_mask = inst_mask; 1029 for_each_inst(i, tmp_mask) { 1030 ring = &adev->sdma.instance[i].ring; 1031 1032 r = amdgpu_ring_test_helper(ring); 1033 if (r) 1034 return r; 1035 1036 if (adev->sdma.has_page_queue) { 1037 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 1038 1039 r = amdgpu_ring_test_helper(page); 1040 if (r) 1041 return r; 1042 } 1043 } 1044 1045 return r; 1046 } 1047 1048 /** 1049 * sdma_v4_4_2_ring_test_ring - simple async dma engine test 1050 * 1051 * @ring: amdgpu_ring structure holding ring information 1052 * 1053 * Test the DMA engine by writing using it to write an 1054 * value to memory. 1055 * Returns 0 for success, error for failure. 1056 */ 1057 static int sdma_v4_4_2_ring_test_ring(struct amdgpu_ring *ring) 1058 { 1059 struct amdgpu_device *adev = ring->adev; 1060 unsigned i; 1061 unsigned index; 1062 int r; 1063 u32 tmp; 1064 u64 gpu_addr; 1065 1066 r = amdgpu_device_wb_get(adev, &index); 1067 if (r) 1068 return r; 1069 1070 gpu_addr = adev->wb.gpu_addr + (index * 4); 1071 tmp = 0xCAFEDEAD; 1072 adev->wb.wb[index] = cpu_to_le32(tmp); 1073 1074 r = amdgpu_ring_alloc(ring, 5); 1075 if (r) 1076 goto error_free_wb; 1077 1078 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1079 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1080 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1081 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1082 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1083 amdgpu_ring_write(ring, 0xDEADBEEF); 1084 amdgpu_ring_commit(ring); 1085 1086 for (i = 0; i < adev->usec_timeout; i++) { 1087 tmp = le32_to_cpu(adev->wb.wb[index]); 1088 if (tmp == 0xDEADBEEF) 1089 break; 1090 udelay(1); 1091 } 1092 1093 if (i >= adev->usec_timeout) 1094 r = -ETIMEDOUT; 1095 1096 error_free_wb: 1097 amdgpu_device_wb_free(adev, index); 1098 return r; 1099 } 1100 1101 /** 1102 * sdma_v4_4_2_ring_test_ib - test an IB on the DMA engine 1103 * 1104 * @ring: amdgpu_ring structure holding ring information 1105 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1106 * 1107 * Test a simple IB in the DMA ring. 1108 * Returns 0 on success, error on failure. 1109 */ 1110 static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1111 { 1112 struct amdgpu_device *adev = ring->adev; 1113 struct amdgpu_ib ib; 1114 struct dma_fence *f = NULL; 1115 unsigned index; 1116 long r; 1117 u32 tmp = 0; 1118 u64 gpu_addr; 1119 1120 r = amdgpu_device_wb_get(adev, &index); 1121 if (r) 1122 return r; 1123 1124 gpu_addr = adev->wb.gpu_addr + (index * 4); 1125 tmp = 0xCAFEDEAD; 1126 adev->wb.wb[index] = cpu_to_le32(tmp); 1127 memset(&ib, 0, sizeof(ib)); 1128 r = amdgpu_ib_get(adev, NULL, 256, 1129 AMDGPU_IB_POOL_DIRECT, &ib); 1130 if (r) 1131 goto err0; 1132 1133 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1134 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1135 ib.ptr[1] = lower_32_bits(gpu_addr); 1136 ib.ptr[2] = upper_32_bits(gpu_addr); 1137 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1138 ib.ptr[4] = 0xDEADBEEF; 1139 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1140 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1141 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1142 ib.length_dw = 8; 1143 1144 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1145 if (r) 1146 goto err1; 1147 1148 r = dma_fence_wait_timeout(f, false, timeout); 1149 if (r == 0) { 1150 r = -ETIMEDOUT; 1151 goto err1; 1152 } else if (r < 0) { 1153 goto err1; 1154 } 1155 tmp = le32_to_cpu(adev->wb.wb[index]); 1156 if (tmp == 0xDEADBEEF) 1157 r = 0; 1158 else 1159 r = -EINVAL; 1160 1161 err1: 1162 amdgpu_ib_free(&ib, NULL); 1163 dma_fence_put(f); 1164 err0: 1165 amdgpu_device_wb_free(adev, index); 1166 return r; 1167 } 1168 1169 1170 /** 1171 * sdma_v4_4_2_vm_copy_pte - update PTEs by copying them from the GART 1172 * 1173 * @ib: indirect buffer to fill with commands 1174 * @pe: addr of the page entry 1175 * @src: src addr to copy from 1176 * @count: number of page entries to update 1177 * 1178 * Update PTEs by copying them from the GART using sDMA. 1179 */ 1180 static void sdma_v4_4_2_vm_copy_pte(struct amdgpu_ib *ib, 1181 uint64_t pe, uint64_t src, 1182 unsigned count) 1183 { 1184 unsigned bytes = count * 8; 1185 1186 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1187 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1188 ib->ptr[ib->length_dw++] = bytes - 1; 1189 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1190 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1191 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1192 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1193 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1194 1195 } 1196 1197 /** 1198 * sdma_v4_4_2_vm_write_pte - update PTEs by writing them manually 1199 * 1200 * @ib: indirect buffer to fill with commands 1201 * @pe: addr of the page entry 1202 * @value: dst addr to write into pe 1203 * @count: number of page entries to update 1204 * @incr: increase next addr by incr bytes 1205 * 1206 * Update PTEs by writing them manually using sDMA. 1207 */ 1208 static void sdma_v4_4_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1209 uint64_t value, unsigned count, 1210 uint32_t incr) 1211 { 1212 unsigned ndw = count * 2; 1213 1214 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1215 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1216 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1217 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1218 ib->ptr[ib->length_dw++] = ndw - 1; 1219 for (; ndw > 0; ndw -= 2) { 1220 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1221 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1222 value += incr; 1223 } 1224 } 1225 1226 /** 1227 * sdma_v4_4_2_vm_set_pte_pde - update the page tables using sDMA 1228 * 1229 * @ib: indirect buffer to fill with commands 1230 * @pe: addr of the page entry 1231 * @addr: dst addr to write into pe 1232 * @count: number of page entries to update 1233 * @incr: increase next addr by incr bytes 1234 * @flags: access flags 1235 * 1236 * Update the page tables using sDMA. 1237 */ 1238 static void sdma_v4_4_2_vm_set_pte_pde(struct amdgpu_ib *ib, 1239 uint64_t pe, 1240 uint64_t addr, unsigned count, 1241 uint32_t incr, uint64_t flags) 1242 { 1243 /* for physically contiguous pages (vram) */ 1244 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1245 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1246 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1247 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1248 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1249 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1250 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1251 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1252 ib->ptr[ib->length_dw++] = 0; 1253 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1254 } 1255 1256 /** 1257 * sdma_v4_4_2_ring_pad_ib - pad the IB to the required number of dw 1258 * 1259 * @ring: amdgpu_ring structure holding ring information 1260 * @ib: indirect buffer to fill with padding 1261 */ 1262 static void sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1263 { 1264 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1265 u32 pad_count; 1266 int i; 1267 1268 pad_count = (-ib->length_dw) & 7; 1269 for (i = 0; i < pad_count; i++) 1270 if (sdma && sdma->burst_nop && (i == 0)) 1271 ib->ptr[ib->length_dw++] = 1272 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1273 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1274 else 1275 ib->ptr[ib->length_dw++] = 1276 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1277 } 1278 1279 1280 /** 1281 * sdma_v4_4_2_ring_emit_pipeline_sync - sync the pipeline 1282 * 1283 * @ring: amdgpu_ring pointer 1284 * 1285 * Make sure all previous operations are completed (CIK). 1286 */ 1287 static void sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1288 { 1289 uint32_t seq = ring->fence_drv.sync_seq; 1290 uint64_t addr = ring->fence_drv.gpu_addr; 1291 1292 /* wait for idle */ 1293 sdma_v4_4_2_wait_reg_mem(ring, 1, 0, 1294 addr & 0xfffffffc, 1295 upper_32_bits(addr) & 0xffffffff, 1296 seq, 0xffffffff, 4); 1297 } 1298 1299 1300 /** 1301 * sdma_v4_4_2_ring_emit_vm_flush - vm flush using sDMA 1302 * 1303 * @ring: amdgpu_ring pointer 1304 * @vmid: vmid number to use 1305 * @pd_addr: address 1306 * 1307 * Update the page table base and flush the VM TLB 1308 * using sDMA. 1309 */ 1310 static void sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring *ring, 1311 unsigned vmid, uint64_t pd_addr) 1312 { 1313 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1314 } 1315 1316 static void sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring *ring, 1317 uint32_t reg, uint32_t val) 1318 { 1319 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1320 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1321 amdgpu_ring_write(ring, reg); 1322 amdgpu_ring_write(ring, val); 1323 } 1324 1325 static void sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1326 uint32_t val, uint32_t mask) 1327 { 1328 sdma_v4_4_2_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1329 } 1330 1331 static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev) 1332 { 1333 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1334 case IP_VERSION(4, 4, 2): 1335 case IP_VERSION(4, 4, 5): 1336 return false; 1337 default: 1338 return false; 1339 } 1340 } 1341 1342 static const struct amdgpu_sdma_funcs sdma_v4_4_2_sdma_funcs = { 1343 .stop_kernel_queue = &sdma_v4_4_2_stop_queue, 1344 .start_kernel_queue = &sdma_v4_4_2_restore_queue, 1345 }; 1346 1347 static int sdma_v4_4_2_early_init(struct amdgpu_ip_block *ip_block) 1348 { 1349 struct amdgpu_device *adev = ip_block->adev; 1350 int r; 1351 1352 r = sdma_v4_4_2_init_microcode(adev); 1353 if (r) 1354 return r; 1355 1356 /* TODO: Page queue breaks driver reload under SRIOV */ 1357 if (sdma_v4_4_2_fw_support_paging_queue(adev)) 1358 adev->sdma.has_page_queue = true; 1359 1360 sdma_v4_4_2_set_ring_funcs(adev); 1361 sdma_v4_4_2_set_buffer_funcs(adev); 1362 sdma_v4_4_2_set_vm_pte_funcs(adev); 1363 sdma_v4_4_2_set_irq_funcs(adev); 1364 sdma_v4_4_2_set_ras_funcs(adev); 1365 return 0; 1366 } 1367 1368 #if 0 1369 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, 1370 void *err_data, 1371 struct amdgpu_iv_entry *entry); 1372 #endif 1373 1374 static int sdma_v4_4_2_late_init(struct amdgpu_ip_block *ip_block) 1375 { 1376 struct amdgpu_device *adev = ip_block->adev; 1377 #if 0 1378 struct ras_ih_if ih_info = { 1379 .cb = sdma_v4_4_2_process_ras_data_cb, 1380 }; 1381 #endif 1382 if (!amdgpu_persistent_edc_harvesting_supported(adev)) 1383 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__SDMA); 1384 1385 /* The initialization is done in the late_init stage to ensure that the SMU 1386 * initialization and capability setup are completed before we check the SDMA 1387 * reset capability 1388 */ 1389 sdma_v4_4_2_update_reset_mask(adev); 1390 1391 return 0; 1392 } 1393 1394 static int sdma_v4_4_2_sw_init(struct amdgpu_ip_block *ip_block) 1395 { 1396 struct amdgpu_ring *ring; 1397 int r, i; 1398 struct amdgpu_device *adev = ip_block->adev; 1399 u32 aid_id; 1400 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); 1401 uint32_t *ptr; 1402 1403 /* SDMA trap event */ 1404 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1405 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1406 SDMA0_4_0__SRCID__SDMA_TRAP, 1407 &adev->sdma.trap_irq); 1408 if (r) 1409 return r; 1410 } 1411 1412 /* SDMA SRAM ECC event */ 1413 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1414 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1415 SDMA0_4_0__SRCID__SDMA_SRAM_ECC, 1416 &adev->sdma.ecc_irq); 1417 if (r) 1418 return r; 1419 } 1420 1421 /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/ 1422 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1423 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1424 SDMA0_4_0__SRCID__SDMA_VM_HOLE, 1425 &adev->sdma.vm_hole_irq); 1426 if (r) 1427 return r; 1428 1429 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1430 SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID, 1431 &adev->sdma.doorbell_invalid_irq); 1432 if (r) 1433 return r; 1434 1435 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1436 SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT, 1437 &adev->sdma.pool_timeout_irq); 1438 if (r) 1439 return r; 1440 1441 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1442 SDMA0_4_0__SRCID__SDMA_SRBMWRITE, 1443 &adev->sdma.srbm_write_irq); 1444 if (r) 1445 return r; 1446 1447 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1448 SDMA0_4_0__SRCID__SDMA_CTXEMPTY, 1449 &adev->sdma.ctxt_empty_irq); 1450 if (r) 1451 return r; 1452 } 1453 1454 for (i = 0; i < adev->sdma.num_instances; i++) { 1455 mutex_init(&adev->sdma.instance[i].engine_reset_mutex); 1456 /* Initialize guilty flags for GFX and PAGE queues */ 1457 adev->sdma.instance[i].gfx_guilty = false; 1458 adev->sdma.instance[i].page_guilty = false; 1459 adev->sdma.instance[i].funcs = &sdma_v4_4_2_sdma_funcs; 1460 1461 ring = &adev->sdma.instance[i].ring; 1462 ring->ring_obj = NULL; 1463 ring->use_doorbell = true; 1464 aid_id = adev->sdma.instance[i].aid_id; 1465 1466 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1467 ring->use_doorbell?"true":"false"); 1468 1469 /* doorbell size is 2 dwords, get DWORD offset */ 1470 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1471 ring->vm_hub = AMDGPU_MMHUB0(aid_id); 1472 1473 sprintf(ring->name, "sdma%d.%d", aid_id, 1474 i % adev->sdma.num_inst_per_aid); 1475 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1476 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1477 AMDGPU_RING_PRIO_DEFAULT, NULL); 1478 if (r) 1479 return r; 1480 1481 if (adev->sdma.has_page_queue) { 1482 ring = &adev->sdma.instance[i].page; 1483 ring->ring_obj = NULL; 1484 ring->use_doorbell = true; 1485 1486 /* doorbell index of page queue is assigned right after 1487 * gfx queue on the same instance 1488 */ 1489 ring->doorbell_index = 1490 (adev->doorbell_index.sdma_engine[i] + 1) << 1; 1491 ring->vm_hub = AMDGPU_MMHUB0(aid_id); 1492 1493 sprintf(ring->name, "page%d.%d", aid_id, 1494 i % adev->sdma.num_inst_per_aid); 1495 r = amdgpu_ring_init(adev, ring, 1024, 1496 &adev->sdma.trap_irq, 1497 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1498 AMDGPU_RING_PRIO_DEFAULT, NULL); 1499 if (r) 1500 return r; 1501 } 1502 } 1503 1504 adev->sdma.supported_reset = 1505 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); 1506 1507 if (amdgpu_sdma_ras_sw_init(adev)) { 1508 dev_err(adev->dev, "fail to initialize sdma ras block\n"); 1509 return -EINVAL; 1510 } 1511 1512 /* Allocate memory for SDMA IP Dump buffer */ 1513 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); 1514 if (ptr) 1515 adev->sdma.ip_dump = ptr; 1516 else 1517 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n"); 1518 1519 r = amdgpu_sdma_sysfs_reset_mask_init(adev); 1520 if (r) 1521 return r; 1522 1523 return r; 1524 } 1525 1526 static int sdma_v4_4_2_sw_fini(struct amdgpu_ip_block *ip_block) 1527 { 1528 struct amdgpu_device *adev = ip_block->adev; 1529 int i; 1530 1531 for (i = 0; i < adev->sdma.num_instances; i++) { 1532 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1533 if (adev->sdma.has_page_queue) 1534 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1535 } 1536 1537 amdgpu_sdma_sysfs_reset_mask_fini(adev); 1538 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) || 1539 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 4) || 1540 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) 1541 amdgpu_sdma_destroy_inst_ctx(adev, true); 1542 else 1543 amdgpu_sdma_destroy_inst_ctx(adev, false); 1544 1545 kfree(adev->sdma.ip_dump); 1546 1547 return 0; 1548 } 1549 1550 static int sdma_v4_4_2_hw_init(struct amdgpu_ip_block *ip_block) 1551 { 1552 int r; 1553 struct amdgpu_device *adev = ip_block->adev; 1554 uint32_t inst_mask; 1555 1556 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1557 if (!amdgpu_sriov_vf(adev)) 1558 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask); 1559 1560 r = sdma_v4_4_2_inst_start(adev, inst_mask, false); 1561 1562 return r; 1563 } 1564 1565 static int sdma_v4_4_2_hw_fini(struct amdgpu_ip_block *ip_block) 1566 { 1567 struct amdgpu_device *adev = ip_block->adev; 1568 uint32_t inst_mask; 1569 int i; 1570 1571 if (amdgpu_sriov_vf(adev)) 1572 return 0; 1573 1574 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1575 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 1576 for (i = 0; i < adev->sdma.num_instances; i++) { 1577 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 1578 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1579 } 1580 } 1581 1582 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 1583 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 1584 1585 return 0; 1586 } 1587 1588 static int sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1589 enum amd_clockgating_state state); 1590 1591 static int sdma_v4_4_2_suspend(struct amdgpu_ip_block *ip_block) 1592 { 1593 struct amdgpu_device *adev = ip_block->adev; 1594 1595 if (amdgpu_in_reset(adev)) 1596 sdma_v4_4_2_set_clockgating_state(ip_block, AMD_CG_STATE_UNGATE); 1597 1598 return sdma_v4_4_2_hw_fini(ip_block); 1599 } 1600 1601 static int sdma_v4_4_2_resume(struct amdgpu_ip_block *ip_block) 1602 { 1603 return sdma_v4_4_2_hw_init(ip_block); 1604 } 1605 1606 static bool sdma_v4_4_2_is_idle(struct amdgpu_ip_block *ip_block) 1607 { 1608 struct amdgpu_device *adev = ip_block->adev; 1609 u32 i; 1610 1611 for (i = 0; i < adev->sdma.num_instances; i++) { 1612 u32 tmp = RREG32_SDMA(i, regSDMA_STATUS_REG); 1613 1614 if (!(tmp & SDMA_STATUS_REG__IDLE_MASK)) 1615 return false; 1616 } 1617 1618 return true; 1619 } 1620 1621 static int sdma_v4_4_2_wait_for_idle(struct amdgpu_ip_block *ip_block) 1622 { 1623 unsigned i, j; 1624 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; 1625 struct amdgpu_device *adev = ip_block->adev; 1626 1627 for (i = 0; i < adev->usec_timeout; i++) { 1628 for (j = 0; j < adev->sdma.num_instances; j++) { 1629 sdma[j] = RREG32_SDMA(j, regSDMA_STATUS_REG); 1630 if (!(sdma[j] & SDMA_STATUS_REG__IDLE_MASK)) 1631 break; 1632 } 1633 if (j == adev->sdma.num_instances) 1634 return 0; 1635 udelay(1); 1636 } 1637 return -ETIMEDOUT; 1638 } 1639 1640 static int sdma_v4_4_2_soft_reset(struct amdgpu_ip_block *ip_block) 1641 { 1642 /* todo */ 1643 1644 return 0; 1645 } 1646 1647 static bool sdma_v4_4_2_is_queue_selected(struct amdgpu_device *adev, uint32_t instance_id, bool is_page_queue) 1648 { 1649 uint32_t reg_offset = is_page_queue ? regSDMA_PAGE_CONTEXT_STATUS : regSDMA_GFX_CONTEXT_STATUS; 1650 uint32_t context_status = RREG32(sdma_v4_4_2_get_reg_offset(adev, instance_id, reg_offset)); 1651 1652 /* Check if the SELECTED bit is set */ 1653 return (context_status & SDMA_GFX_CONTEXT_STATUS__SELECTED_MASK) != 0; 1654 } 1655 1656 static bool sdma_v4_4_2_ring_is_guilty(struct amdgpu_ring *ring) 1657 { 1658 struct amdgpu_device *adev = ring->adev; 1659 uint32_t instance_id = ring->me; 1660 1661 return sdma_v4_4_2_is_queue_selected(adev, instance_id, false); 1662 } 1663 1664 static bool sdma_v4_4_2_page_ring_is_guilty(struct amdgpu_ring *ring) 1665 { 1666 struct amdgpu_device *adev = ring->adev; 1667 uint32_t instance_id = ring->me; 1668 1669 if (!adev->sdma.has_page_queue) 1670 return false; 1671 1672 return sdma_v4_4_2_is_queue_selected(adev, instance_id, true); 1673 } 1674 1675 static int sdma_v4_4_2_reset_queue(struct amdgpu_ring *ring, unsigned int vmid) 1676 { 1677 struct amdgpu_device *adev = ring->adev; 1678 u32 id = ring->me; 1679 int r; 1680 1681 if (!(adev->sdma.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) 1682 return -EOPNOTSUPP; 1683 1684 amdgpu_amdkfd_suspend(adev, false); 1685 r = amdgpu_sdma_reset_engine(adev, id); 1686 amdgpu_amdkfd_resume(adev, false); 1687 1688 return r; 1689 } 1690 1691 static int sdma_v4_4_2_stop_queue(struct amdgpu_ring *ring) 1692 { 1693 struct amdgpu_device *adev = ring->adev; 1694 u32 instance_id = ring->me; 1695 u32 inst_mask; 1696 uint64_t rptr; 1697 1698 if (amdgpu_sriov_vf(adev)) 1699 return -EINVAL; 1700 1701 /* Check if this queue is the guilty one */ 1702 adev->sdma.instance[instance_id].gfx_guilty = 1703 sdma_v4_4_2_is_queue_selected(adev, instance_id, false); 1704 if (adev->sdma.has_page_queue) 1705 adev->sdma.instance[instance_id].page_guilty = 1706 sdma_v4_4_2_is_queue_selected(adev, instance_id, true); 1707 1708 /* Cache the rptr before reset, after the reset, 1709 * all of the registers will be reset to 0 1710 */ 1711 rptr = amdgpu_ring_get_rptr(ring); 1712 ring->cached_rptr = rptr; 1713 /* Cache the rptr for the page queue if it exists */ 1714 if (adev->sdma.has_page_queue) { 1715 struct amdgpu_ring *page_ring = &adev->sdma.instance[instance_id].page; 1716 rptr = amdgpu_ring_get_rptr(page_ring); 1717 page_ring->cached_rptr = rptr; 1718 } 1719 1720 /* stop queue */ 1721 inst_mask = 1 << ring->me; 1722 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask); 1723 if (adev->sdma.has_page_queue) 1724 sdma_v4_4_2_inst_page_stop(adev, inst_mask); 1725 1726 return 0; 1727 } 1728 1729 static int sdma_v4_4_2_restore_queue(struct amdgpu_ring *ring) 1730 { 1731 struct amdgpu_device *adev = ring->adev; 1732 u32 inst_mask; 1733 int i; 1734 1735 inst_mask = 1 << ring->me; 1736 udelay(50); 1737 1738 for (i = 0; i < adev->usec_timeout; i++) { 1739 if (!REG_GET_FIELD(RREG32_SDMA(ring->me, regSDMA_F32_CNTL), SDMA_F32_CNTL, HALT)) 1740 break; 1741 udelay(1); 1742 } 1743 1744 if (i == adev->usec_timeout) { 1745 dev_err(adev->dev, "timed out waiting for SDMA%d unhalt after reset\n", 1746 ring->me); 1747 return -ETIMEDOUT; 1748 } 1749 1750 return sdma_v4_4_2_inst_start(adev, inst_mask, true); 1751 } 1752 1753 static int sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device *adev, 1754 struct amdgpu_irq_src *source, 1755 unsigned type, 1756 enum amdgpu_interrupt_state state) 1757 { 1758 u32 sdma_cntl; 1759 1760 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); 1761 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE, 1762 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1763 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); 1764 1765 return 0; 1766 } 1767 1768 static int sdma_v4_4_2_process_trap_irq(struct amdgpu_device *adev, 1769 struct amdgpu_irq_src *source, 1770 struct amdgpu_iv_entry *entry) 1771 { 1772 uint32_t instance, i; 1773 1774 DRM_DEBUG("IH: SDMA trap\n"); 1775 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1776 1777 /* Client id gives the SDMA instance in AID. To know the exact SDMA 1778 * instance, interrupt entry gives the node id which corresponds to the AID instance. 1779 * Match node id with the AID id associated with the SDMA instance. */ 1780 for (i = instance; i < adev->sdma.num_instances; 1781 i += adev->sdma.num_inst_per_aid) { 1782 if (adev->sdma.instance[i].aid_id == 1783 node_id_to_phys_map[entry->node_id]) 1784 break; 1785 } 1786 1787 if (i >= adev->sdma.num_instances) { 1788 dev_WARN_ONCE( 1789 adev->dev, 1, 1790 "Couldn't find the right sdma instance in trap handler"); 1791 return 0; 1792 } 1793 1794 switch (entry->ring_id) { 1795 case 0: 1796 amdgpu_fence_process(&adev->sdma.instance[i].ring); 1797 break; 1798 case 1: 1799 amdgpu_fence_process(&adev->sdma.instance[i].page); 1800 break; 1801 default: 1802 break; 1803 } 1804 return 0; 1805 } 1806 1807 #if 0 1808 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, 1809 void *err_data, 1810 struct amdgpu_iv_entry *entry) 1811 { 1812 int instance; 1813 1814 /* When “Full RAS” is enabled, the per-IP interrupt sources should 1815 * be disabled and the driver should only look for the aggregated 1816 * interrupt via sync flood 1817 */ 1818 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) 1819 goto out; 1820 1821 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1822 if (instance < 0) 1823 goto out; 1824 1825 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry); 1826 1827 out: 1828 return AMDGPU_RAS_SUCCESS; 1829 } 1830 #endif 1831 1832 static int sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device *adev, 1833 struct amdgpu_irq_src *source, 1834 struct amdgpu_iv_entry *entry) 1835 { 1836 int instance; 1837 1838 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1839 1840 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1841 if (instance < 0) 1842 return 0; 1843 1844 switch (entry->ring_id) { 1845 case 0: 1846 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 1847 break; 1848 } 1849 return 0; 1850 } 1851 1852 static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev, 1853 struct amdgpu_irq_src *source, 1854 unsigned type, 1855 enum amdgpu_interrupt_state state) 1856 { 1857 u32 sdma_cntl; 1858 1859 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); 1860 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, DRAM_ECC_INT_ENABLE, 1861 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1862 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); 1863 1864 return 0; 1865 } 1866 1867 static int sdma_v4_4_2_print_iv_entry(struct amdgpu_device *adev, 1868 struct amdgpu_iv_entry *entry) 1869 { 1870 int instance; 1871 struct amdgpu_task_info *task_info; 1872 u64 addr; 1873 1874 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1875 if (instance < 0 || instance >= adev->sdma.num_instances) { 1876 dev_err(adev->dev, "sdma instance invalid %d\n", instance); 1877 return -EINVAL; 1878 } 1879 1880 addr = (u64)entry->src_data[0] << 12; 1881 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 1882 1883 dev_dbg_ratelimited(adev->dev, 1884 "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u pasid:%u\n", 1885 instance, addr, entry->src_id, entry->ring_id, entry->vmid, 1886 entry->pasid); 1887 1888 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 1889 if (task_info) { 1890 dev_dbg_ratelimited(adev->dev, " for process %s pid %d thread %s pid %d\n", 1891 task_info->process_name, task_info->tgid, 1892 task_info->task_name, task_info->pid); 1893 amdgpu_vm_put_task_info(task_info); 1894 } 1895 1896 return 0; 1897 } 1898 1899 static int sdma_v4_4_2_process_vm_hole_irq(struct amdgpu_device *adev, 1900 struct amdgpu_irq_src *source, 1901 struct amdgpu_iv_entry *entry) 1902 { 1903 dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n"); 1904 sdma_v4_4_2_print_iv_entry(adev, entry); 1905 return 0; 1906 } 1907 1908 static int sdma_v4_4_2_process_doorbell_invalid_irq(struct amdgpu_device *adev, 1909 struct amdgpu_irq_src *source, 1910 struct amdgpu_iv_entry *entry) 1911 { 1912 1913 dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n"); 1914 sdma_v4_4_2_print_iv_entry(adev, entry); 1915 return 0; 1916 } 1917 1918 static int sdma_v4_4_2_process_pool_timeout_irq(struct amdgpu_device *adev, 1919 struct amdgpu_irq_src *source, 1920 struct amdgpu_iv_entry *entry) 1921 { 1922 dev_dbg_ratelimited(adev->dev, 1923 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n"); 1924 sdma_v4_4_2_print_iv_entry(adev, entry); 1925 return 0; 1926 } 1927 1928 static int sdma_v4_4_2_process_srbm_write_irq(struct amdgpu_device *adev, 1929 struct amdgpu_irq_src *source, 1930 struct amdgpu_iv_entry *entry) 1931 { 1932 dev_dbg_ratelimited(adev->dev, 1933 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n"); 1934 sdma_v4_4_2_print_iv_entry(adev, entry); 1935 return 0; 1936 } 1937 1938 static int sdma_v4_4_2_process_ctxt_empty_irq(struct amdgpu_device *adev, 1939 struct amdgpu_irq_src *source, 1940 struct amdgpu_iv_entry *entry) 1941 { 1942 /* There is nothing useful to be done here, only kept for debug */ 1943 dev_dbg_ratelimited(adev->dev, "SDMA context empty interrupt"); 1944 sdma_v4_4_2_print_iv_entry(adev, entry); 1945 return 0; 1946 } 1947 1948 static void sdma_v4_4_2_inst_update_medium_grain_light_sleep( 1949 struct amdgpu_device *adev, bool enable, uint32_t inst_mask) 1950 { 1951 uint32_t data, def; 1952 int i; 1953 1954 /* leave as default if it is not driver controlled */ 1955 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) 1956 return; 1957 1958 if (enable) { 1959 for_each_inst(i, inst_mask) { 1960 /* 1-not override: enable sdma mem light sleep */ 1961 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL); 1962 data |= SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1963 if (def != data) 1964 WREG32_SDMA(i, regSDMA_POWER_CNTL, data); 1965 } 1966 } else { 1967 for_each_inst(i, inst_mask) { 1968 /* 0-override:disable sdma mem light sleep */ 1969 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL); 1970 data &= ~SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1971 if (def != data) 1972 WREG32_SDMA(i, regSDMA_POWER_CNTL, data); 1973 } 1974 } 1975 } 1976 1977 static void sdma_v4_4_2_inst_update_medium_grain_clock_gating( 1978 struct amdgpu_device *adev, bool enable, uint32_t inst_mask) 1979 { 1980 uint32_t data, def; 1981 int i; 1982 1983 /* leave as default if it is not driver controlled */ 1984 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) 1985 return; 1986 1987 if (enable) { 1988 for_each_inst(i, inst_mask) { 1989 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL); 1990 data &= ~(SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1991 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1992 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1993 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1994 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1995 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1996 if (def != data) 1997 WREG32_SDMA(i, regSDMA_CLK_CTRL, data); 1998 } 1999 } else { 2000 for_each_inst(i, inst_mask) { 2001 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL); 2002 data |= (SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2003 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2004 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2005 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2006 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2007 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2008 if (def != data) 2009 WREG32_SDMA(i, regSDMA_CLK_CTRL, data); 2010 } 2011 } 2012 } 2013 2014 static int sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2015 enum amd_clockgating_state state) 2016 { 2017 struct amdgpu_device *adev = ip_block->adev; 2018 uint32_t inst_mask; 2019 2020 if (amdgpu_sriov_vf(adev)) 2021 return 0; 2022 2023 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 2024 2025 sdma_v4_4_2_inst_update_medium_grain_clock_gating( 2026 adev, state == AMD_CG_STATE_GATE, inst_mask); 2027 sdma_v4_4_2_inst_update_medium_grain_light_sleep( 2028 adev, state == AMD_CG_STATE_GATE, inst_mask); 2029 return 0; 2030 } 2031 2032 static int sdma_v4_4_2_set_powergating_state(struct amdgpu_ip_block *ip_block, 2033 enum amd_powergating_state state) 2034 { 2035 return 0; 2036 } 2037 2038 static void sdma_v4_4_2_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 2039 { 2040 struct amdgpu_device *adev = ip_block->adev; 2041 int data; 2042 2043 if (amdgpu_sriov_vf(adev)) 2044 *flags = 0; 2045 2046 /* AMD_CG_SUPPORT_SDMA_MGCG */ 2047 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL)); 2048 if (!(data & SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK)) 2049 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 2050 2051 /* AMD_CG_SUPPORT_SDMA_LS */ 2052 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL)); 2053 if (data & SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 2054 *flags |= AMD_CG_SUPPORT_SDMA_LS; 2055 } 2056 2057 static void sdma_v4_4_2_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 2058 { 2059 struct amdgpu_device *adev = ip_block->adev; 2060 int i, j; 2061 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); 2062 uint32_t instance_offset; 2063 2064 if (!adev->sdma.ip_dump) 2065 return; 2066 2067 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances); 2068 for (i = 0; i < adev->sdma.num_instances; i++) { 2069 instance_offset = i * reg_count; 2070 drm_printf(p, "\nInstance:%d\n", i); 2071 2072 for (j = 0; j < reg_count; j++) 2073 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_4_4_2[j].reg_name, 2074 adev->sdma.ip_dump[instance_offset + j]); 2075 } 2076 } 2077 2078 static void sdma_v4_4_2_dump_ip_state(struct amdgpu_ip_block *ip_block) 2079 { 2080 struct amdgpu_device *adev = ip_block->adev; 2081 int i, j; 2082 uint32_t instance_offset; 2083 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); 2084 2085 if (!adev->sdma.ip_dump) 2086 return; 2087 2088 for (i = 0; i < adev->sdma.num_instances; i++) { 2089 instance_offset = i * reg_count; 2090 for (j = 0; j < reg_count; j++) 2091 adev->sdma.ip_dump[instance_offset + j] = 2092 RREG32(sdma_v4_4_2_get_reg_offset(adev, i, 2093 sdma_reg_list_4_4_2[j].reg_offset)); 2094 } 2095 } 2096 2097 const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = { 2098 .name = "sdma_v4_4_2", 2099 .early_init = sdma_v4_4_2_early_init, 2100 .late_init = sdma_v4_4_2_late_init, 2101 .sw_init = sdma_v4_4_2_sw_init, 2102 .sw_fini = sdma_v4_4_2_sw_fini, 2103 .hw_init = sdma_v4_4_2_hw_init, 2104 .hw_fini = sdma_v4_4_2_hw_fini, 2105 .suspend = sdma_v4_4_2_suspend, 2106 .resume = sdma_v4_4_2_resume, 2107 .is_idle = sdma_v4_4_2_is_idle, 2108 .wait_for_idle = sdma_v4_4_2_wait_for_idle, 2109 .soft_reset = sdma_v4_4_2_soft_reset, 2110 .set_clockgating_state = sdma_v4_4_2_set_clockgating_state, 2111 .set_powergating_state = sdma_v4_4_2_set_powergating_state, 2112 .get_clockgating_state = sdma_v4_4_2_get_clockgating_state, 2113 .dump_ip_state = sdma_v4_4_2_dump_ip_state, 2114 .print_ip_state = sdma_v4_4_2_print_ip_state, 2115 }; 2116 2117 static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = { 2118 .type = AMDGPU_RING_TYPE_SDMA, 2119 .align_mask = 0xff, 2120 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2121 .support_64bit_ptrs = true, 2122 .get_rptr = sdma_v4_4_2_ring_get_rptr, 2123 .get_wptr = sdma_v4_4_2_ring_get_wptr, 2124 .set_wptr = sdma_v4_4_2_ring_set_wptr, 2125 .emit_frame_size = 2126 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */ 2127 3 + /* hdp invalidate */ 2128 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */ 2129 /* sdma_v4_4_2_ring_emit_vm_flush */ 2130 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2131 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2132 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */ 2133 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */ 2134 .emit_ib = sdma_v4_4_2_ring_emit_ib, 2135 .emit_fence = sdma_v4_4_2_ring_emit_fence, 2136 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync, 2137 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush, 2138 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush, 2139 .test_ring = sdma_v4_4_2_ring_test_ring, 2140 .test_ib = sdma_v4_4_2_ring_test_ib, 2141 .insert_nop = sdma_v4_4_2_ring_insert_nop, 2142 .pad_ib = sdma_v4_4_2_ring_pad_ib, 2143 .emit_wreg = sdma_v4_4_2_ring_emit_wreg, 2144 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, 2145 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2146 .reset = sdma_v4_4_2_reset_queue, 2147 .is_guilty = sdma_v4_4_2_ring_is_guilty, 2148 }; 2149 2150 static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = { 2151 .type = AMDGPU_RING_TYPE_SDMA, 2152 .align_mask = 0xff, 2153 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2154 .support_64bit_ptrs = true, 2155 .get_rptr = sdma_v4_4_2_ring_get_rptr, 2156 .get_wptr = sdma_v4_4_2_page_ring_get_wptr, 2157 .set_wptr = sdma_v4_4_2_page_ring_set_wptr, 2158 .emit_frame_size = 2159 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */ 2160 3 + /* hdp invalidate */ 2161 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */ 2162 /* sdma_v4_4_2_ring_emit_vm_flush */ 2163 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2164 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2165 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */ 2166 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */ 2167 .emit_ib = sdma_v4_4_2_ring_emit_ib, 2168 .emit_fence = sdma_v4_4_2_ring_emit_fence, 2169 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync, 2170 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush, 2171 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush, 2172 .test_ring = sdma_v4_4_2_ring_test_ring, 2173 .test_ib = sdma_v4_4_2_ring_test_ib, 2174 .insert_nop = sdma_v4_4_2_ring_insert_nop, 2175 .pad_ib = sdma_v4_4_2_ring_pad_ib, 2176 .emit_wreg = sdma_v4_4_2_ring_emit_wreg, 2177 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, 2178 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2179 .reset = sdma_v4_4_2_reset_queue, 2180 .is_guilty = sdma_v4_4_2_page_ring_is_guilty, 2181 }; 2182 2183 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev) 2184 { 2185 int i, dev_inst; 2186 2187 for (i = 0; i < adev->sdma.num_instances; i++) { 2188 adev->sdma.instance[i].ring.funcs = &sdma_v4_4_2_ring_funcs; 2189 adev->sdma.instance[i].ring.me = i; 2190 if (adev->sdma.has_page_queue) { 2191 adev->sdma.instance[i].page.funcs = 2192 &sdma_v4_4_2_page_ring_funcs; 2193 adev->sdma.instance[i].page.me = i; 2194 } 2195 2196 dev_inst = GET_INST(SDMA0, i); 2197 /* AID to which SDMA belongs depends on physical instance */ 2198 adev->sdma.instance[i].aid_id = 2199 dev_inst / adev->sdma.num_inst_per_aid; 2200 } 2201 } 2202 2203 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_trap_irq_funcs = { 2204 .set = sdma_v4_4_2_set_trap_irq_state, 2205 .process = sdma_v4_4_2_process_trap_irq, 2206 }; 2207 2208 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_illegal_inst_irq_funcs = { 2209 .process = sdma_v4_4_2_process_illegal_inst_irq, 2210 }; 2211 2212 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ecc_irq_funcs = { 2213 .set = sdma_v4_4_2_set_ecc_irq_state, 2214 .process = amdgpu_sdma_process_ecc_irq, 2215 }; 2216 2217 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_vm_hole_irq_funcs = { 2218 .process = sdma_v4_4_2_process_vm_hole_irq, 2219 }; 2220 2221 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_doorbell_invalid_irq_funcs = { 2222 .process = sdma_v4_4_2_process_doorbell_invalid_irq, 2223 }; 2224 2225 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_pool_timeout_irq_funcs = { 2226 .process = sdma_v4_4_2_process_pool_timeout_irq, 2227 }; 2228 2229 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_srbm_write_irq_funcs = { 2230 .process = sdma_v4_4_2_process_srbm_write_irq, 2231 }; 2232 2233 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ctxt_empty_irq_funcs = { 2234 .process = sdma_v4_4_2_process_ctxt_empty_irq, 2235 }; 2236 2237 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev) 2238 { 2239 adev->sdma.trap_irq.num_types = adev->sdma.num_instances; 2240 adev->sdma.ecc_irq.num_types = adev->sdma.num_instances; 2241 adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances; 2242 adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances; 2243 adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances; 2244 adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances; 2245 adev->sdma.ctxt_empty_irq.num_types = adev->sdma.num_instances; 2246 2247 adev->sdma.trap_irq.funcs = &sdma_v4_4_2_trap_irq_funcs; 2248 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_4_2_illegal_inst_irq_funcs; 2249 adev->sdma.ecc_irq.funcs = &sdma_v4_4_2_ecc_irq_funcs; 2250 adev->sdma.vm_hole_irq.funcs = &sdma_v4_4_2_vm_hole_irq_funcs; 2251 adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_4_2_doorbell_invalid_irq_funcs; 2252 adev->sdma.pool_timeout_irq.funcs = &sdma_v4_4_2_pool_timeout_irq_funcs; 2253 adev->sdma.srbm_write_irq.funcs = &sdma_v4_4_2_srbm_write_irq_funcs; 2254 adev->sdma.ctxt_empty_irq.funcs = &sdma_v4_4_2_ctxt_empty_irq_funcs; 2255 } 2256 2257 /** 2258 * sdma_v4_4_2_emit_copy_buffer - copy buffer using the sDMA engine 2259 * 2260 * @ib: indirect buffer to copy to 2261 * @src_offset: src GPU address 2262 * @dst_offset: dst GPU address 2263 * @byte_count: number of bytes to xfer 2264 * @copy_flags: copy flags for the buffers 2265 * 2266 * Copy GPU buffers using the DMA engine. 2267 * Used by the amdgpu ttm implementation to move pages if 2268 * registered as the asic copy callback. 2269 */ 2270 static void sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib *ib, 2271 uint64_t src_offset, 2272 uint64_t dst_offset, 2273 uint32_t byte_count, 2274 uint32_t copy_flags) 2275 { 2276 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 2277 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 2278 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0); 2279 ib->ptr[ib->length_dw++] = byte_count - 1; 2280 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 2281 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 2282 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 2283 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2284 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2285 } 2286 2287 /** 2288 * sdma_v4_4_2_emit_fill_buffer - fill buffer using the sDMA engine 2289 * 2290 * @ib: indirect buffer to copy to 2291 * @src_data: value to write to buffer 2292 * @dst_offset: dst GPU address 2293 * @byte_count: number of bytes to xfer 2294 * 2295 * Fill GPU buffers using the DMA engine. 2296 */ 2297 static void sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib *ib, 2298 uint32_t src_data, 2299 uint64_t dst_offset, 2300 uint32_t byte_count) 2301 { 2302 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2303 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2304 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2305 ib->ptr[ib->length_dw++] = src_data; 2306 ib->ptr[ib->length_dw++] = byte_count - 1; 2307 } 2308 2309 static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = { 2310 .copy_max_bytes = 0x400000, 2311 .copy_num_dw = 7, 2312 .emit_copy_buffer = sdma_v4_4_2_emit_copy_buffer, 2313 2314 .fill_max_bytes = 0x400000, 2315 .fill_num_dw = 5, 2316 .emit_fill_buffer = sdma_v4_4_2_emit_fill_buffer, 2317 }; 2318 2319 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev) 2320 { 2321 adev->mman.buffer_funcs = &sdma_v4_4_2_buffer_funcs; 2322 if (adev->sdma.has_page_queue) 2323 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; 2324 else 2325 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2326 } 2327 2328 static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = { 2329 .copy_pte_num_dw = 7, 2330 .copy_pte = sdma_v4_4_2_vm_copy_pte, 2331 2332 .write_pte = sdma_v4_4_2_vm_write_pte, 2333 .set_pte_pde = sdma_v4_4_2_vm_set_pte_pde, 2334 }; 2335 2336 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev) 2337 { 2338 struct drm_gpu_scheduler *sched; 2339 unsigned i; 2340 2341 adev->vm_manager.vm_pte_funcs = &sdma_v4_4_2_vm_pte_funcs; 2342 for (i = 0; i < adev->sdma.num_instances; i++) { 2343 if (adev->sdma.has_page_queue) 2344 sched = &adev->sdma.instance[i].page.sched; 2345 else 2346 sched = &adev->sdma.instance[i].ring.sched; 2347 adev->vm_manager.vm_pte_scheds[i] = sched; 2348 } 2349 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 2350 } 2351 2352 /** 2353 * sdma_v4_4_2_update_reset_mask - update reset mask for SDMA 2354 * @adev: Pointer to the AMDGPU device structure 2355 * 2356 * This function update reset mask for SDMA and sets the supported 2357 * reset types based on the IP version and firmware versions. 2358 * 2359 */ 2360 static void sdma_v4_4_2_update_reset_mask(struct amdgpu_device *adev) 2361 { 2362 /* per queue reset not supported for SRIOV */ 2363 if (amdgpu_sriov_vf(adev)) 2364 return; 2365 2366 /* 2367 * the user queue relies on MEC fw and pmfw when the sdma queue do reset. 2368 * it needs to check both of them at here to skip old mec and pmfw. 2369 */ 2370 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2371 case IP_VERSION(9, 4, 3): 2372 case IP_VERSION(9, 4, 4): 2373 if ((adev->gfx.mec_fw_version >= 0xb0) && amdgpu_dpm_reset_sdma_is_supported(adev)) 2374 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 2375 break; 2376 case IP_VERSION(9, 5, 0): 2377 if ((adev->gfx.mec_fw_version >= 0xf) && amdgpu_dpm_reset_sdma_is_supported(adev)) 2378 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 2379 break; 2380 default: 2381 break; 2382 } 2383 2384 } 2385 2386 const struct amdgpu_ip_block_version sdma_v4_4_2_ip_block = { 2387 .type = AMD_IP_BLOCK_TYPE_SDMA, 2388 .major = 4, 2389 .minor = 4, 2390 .rev = 2, 2391 .funcs = &sdma_v4_4_2_ip_funcs, 2392 }; 2393 2394 static int sdma_v4_4_2_xcp_resume(void *handle, uint32_t inst_mask) 2395 { 2396 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2397 int r; 2398 2399 if (!amdgpu_sriov_vf(adev)) 2400 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask); 2401 2402 r = sdma_v4_4_2_inst_start(adev, inst_mask, false); 2403 2404 return r; 2405 } 2406 2407 static int sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask) 2408 { 2409 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2410 uint32_t tmp_mask = inst_mask; 2411 int i; 2412 2413 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2414 for_each_inst(i, tmp_mask) { 2415 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 2416 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 2417 } 2418 } 2419 2420 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 2421 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 2422 2423 return 0; 2424 } 2425 2426 struct amdgpu_xcp_ip_funcs sdma_v4_4_2_xcp_funcs = { 2427 .suspend = &sdma_v4_4_2_xcp_suspend, 2428 .resume = &sdma_v4_4_2_xcp_resume 2429 }; 2430 2431 static const struct amdgpu_ras_err_status_reg_entry sdma_v4_2_2_ue_reg_list[] = { 2432 {AMDGPU_RAS_REG_ENTRY(SDMA0, 0, regSDMA_UE_ERR_STATUS_LO, regSDMA_UE_ERR_STATUS_HI), 2433 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SDMA"}, 2434 }; 2435 2436 static const struct amdgpu_ras_memory_id_entry sdma_v4_4_2_ras_memory_list[] = { 2437 {AMDGPU_SDMA_MBANK_DATA_BUF0, "SDMA_MBANK_DATA_BUF0"}, 2438 {AMDGPU_SDMA_MBANK_DATA_BUF1, "SDMA_MBANK_DATA_BUF1"}, 2439 {AMDGPU_SDMA_MBANK_DATA_BUF2, "SDMA_MBANK_DATA_BUF2"}, 2440 {AMDGPU_SDMA_MBANK_DATA_BUF3, "SDMA_MBANK_DATA_BUF3"}, 2441 {AMDGPU_SDMA_MBANK_DATA_BUF4, "SDMA_MBANK_DATA_BUF4"}, 2442 {AMDGPU_SDMA_MBANK_DATA_BUF5, "SDMA_MBANK_DATA_BUF5"}, 2443 {AMDGPU_SDMA_MBANK_DATA_BUF6, "SDMA_MBANK_DATA_BUF6"}, 2444 {AMDGPU_SDMA_MBANK_DATA_BUF7, "SDMA_MBANK_DATA_BUF7"}, 2445 {AMDGPU_SDMA_MBANK_DATA_BUF8, "SDMA_MBANK_DATA_BUF8"}, 2446 {AMDGPU_SDMA_MBANK_DATA_BUF9, "SDMA_MBANK_DATA_BUF9"}, 2447 {AMDGPU_SDMA_MBANK_DATA_BUF10, "SDMA_MBANK_DATA_BUF10"}, 2448 {AMDGPU_SDMA_MBANK_DATA_BUF11, "SDMA_MBANK_DATA_BUF11"}, 2449 {AMDGPU_SDMA_MBANK_DATA_BUF12, "SDMA_MBANK_DATA_BUF12"}, 2450 {AMDGPU_SDMA_MBANK_DATA_BUF13, "SDMA_MBANK_DATA_BUF13"}, 2451 {AMDGPU_SDMA_MBANK_DATA_BUF14, "SDMA_MBANK_DATA_BUF14"}, 2452 {AMDGPU_SDMA_MBANK_DATA_BUF15, "SDMA_MBANK_DATA_BUF15"}, 2453 {AMDGPU_SDMA_UCODE_BUF, "SDMA_UCODE_BUF"}, 2454 {AMDGPU_SDMA_RB_CMD_BUF, "SDMA_RB_CMD_BUF"}, 2455 {AMDGPU_SDMA_IB_CMD_BUF, "SDMA_IB_CMD_BUF"}, 2456 {AMDGPU_SDMA_UTCL1_RD_FIFO, "SDMA_UTCL1_RD_FIFO"}, 2457 {AMDGPU_SDMA_UTCL1_RDBST_FIFO, "SDMA_UTCL1_RDBST_FIFO"}, 2458 {AMDGPU_SDMA_UTCL1_WR_FIFO, "SDMA_UTCL1_WR_FIFO"}, 2459 {AMDGPU_SDMA_DATA_LUT_FIFO, "SDMA_DATA_LUT_FIFO"}, 2460 {AMDGPU_SDMA_SPLIT_DAT_BUF, "SDMA_SPLIT_DAT_BUF"}, 2461 }; 2462 2463 static void sdma_v4_4_2_inst_query_ras_error_count(struct amdgpu_device *adev, 2464 uint32_t sdma_inst, 2465 void *ras_err_status) 2466 { 2467 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 2468 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); 2469 unsigned long ue_count = 0; 2470 struct amdgpu_smuio_mcm_config_info mcm_info = { 2471 .socket_id = adev->smuio.funcs->get_socket_id(adev), 2472 .die_id = adev->sdma.instance[sdma_inst].aid_id, 2473 }; 2474 2475 /* sdma v4_4_2 doesn't support query ce counts */ 2476 amdgpu_ras_inst_query_ras_error_count(adev, 2477 sdma_v4_2_2_ue_reg_list, 2478 ARRAY_SIZE(sdma_v4_2_2_ue_reg_list), 2479 sdma_v4_4_2_ras_memory_list, 2480 ARRAY_SIZE(sdma_v4_4_2_ras_memory_list), 2481 sdma_dev_inst, 2482 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 2483 &ue_count); 2484 2485 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count); 2486 } 2487 2488 static void sdma_v4_4_2_query_ras_error_count(struct amdgpu_device *adev, 2489 void *ras_err_status) 2490 { 2491 uint32_t inst_mask; 2492 int i = 0; 2493 2494 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 2495 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2496 for_each_inst(i, inst_mask) 2497 sdma_v4_4_2_inst_query_ras_error_count(adev, i, ras_err_status); 2498 } else { 2499 dev_warn(adev->dev, "SDMA RAS is not supported\n"); 2500 } 2501 } 2502 2503 static void sdma_v4_4_2_inst_reset_ras_error_count(struct amdgpu_device *adev, 2504 uint32_t sdma_inst) 2505 { 2506 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); 2507 2508 amdgpu_ras_inst_reset_ras_error_count(adev, 2509 sdma_v4_2_2_ue_reg_list, 2510 ARRAY_SIZE(sdma_v4_2_2_ue_reg_list), 2511 sdma_dev_inst); 2512 } 2513 2514 static void sdma_v4_4_2_reset_ras_error_count(struct amdgpu_device *adev) 2515 { 2516 uint32_t inst_mask; 2517 int i = 0; 2518 2519 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 2520 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2521 for_each_inst(i, inst_mask) 2522 sdma_v4_4_2_inst_reset_ras_error_count(adev, i); 2523 } else { 2524 dev_warn(adev->dev, "SDMA RAS is not supported\n"); 2525 } 2526 } 2527 2528 static const struct amdgpu_ras_block_hw_ops sdma_v4_4_2_ras_hw_ops = { 2529 .query_ras_error_count = sdma_v4_4_2_query_ras_error_count, 2530 .reset_ras_error_count = sdma_v4_4_2_reset_ras_error_count, 2531 }; 2532 2533 static int sdma_v4_4_2_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, 2534 enum aca_smu_type type, void *data) 2535 { 2536 struct aca_bank_info info; 2537 u64 misc0; 2538 int ret; 2539 2540 ret = aca_bank_info_decode(bank, &info); 2541 if (ret) 2542 return ret; 2543 2544 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 2545 switch (type) { 2546 case ACA_SMU_TYPE_UE: 2547 bank->aca_err_type = ACA_ERROR_TYPE_UE; 2548 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE, 2549 1ULL); 2550 break; 2551 case ACA_SMU_TYPE_CE: 2552 bank->aca_err_type = ACA_ERROR_TYPE_CE; 2553 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 2554 ACA_REG__MISC0__ERRCNT(misc0)); 2555 break; 2556 default: 2557 return -EINVAL; 2558 } 2559 2560 return ret; 2561 } 2562 2563 /* CODE_SDMA0 - CODE_SDMA4, reference to smu driver if header file */ 2564 static int sdma_v4_4_2_err_codes[] = { 33, 34, 35, 36 }; 2565 2566 static bool sdma_v4_4_2_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 2567 enum aca_smu_type type, void *data) 2568 { 2569 u32 instlo; 2570 2571 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 2572 instlo &= GENMASK(31, 1); 2573 2574 if (instlo != mmSMNAID_AID0_MCA_SMU) 2575 return false; 2576 2577 if (aca_bank_check_error_codes(handle->adev, bank, 2578 sdma_v4_4_2_err_codes, 2579 ARRAY_SIZE(sdma_v4_4_2_err_codes))) 2580 return false; 2581 2582 return true; 2583 } 2584 2585 static const struct aca_bank_ops sdma_v4_4_2_aca_bank_ops = { 2586 .aca_bank_parser = sdma_v4_4_2_aca_bank_parser, 2587 .aca_bank_is_valid = sdma_v4_4_2_aca_bank_is_valid, 2588 }; 2589 2590 static const struct aca_info sdma_v4_4_2_aca_info = { 2591 .hwip = ACA_HWIP_TYPE_SMU, 2592 .mask = ACA_ERROR_UE_MASK, 2593 .bank_ops = &sdma_v4_4_2_aca_bank_ops, 2594 }; 2595 2596 static int sdma_v4_4_2_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 2597 { 2598 int r; 2599 2600 r = amdgpu_sdma_ras_late_init(adev, ras_block); 2601 if (r) 2602 return r; 2603 2604 return amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__SDMA, 2605 &sdma_v4_4_2_aca_info, NULL); 2606 } 2607 2608 static struct amdgpu_sdma_ras sdma_v4_4_2_ras = { 2609 .ras_block = { 2610 .hw_ops = &sdma_v4_4_2_ras_hw_ops, 2611 .ras_late_init = sdma_v4_4_2_ras_late_init, 2612 }, 2613 }; 2614 2615 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev) 2616 { 2617 adev->sdma.ras = &sdma_v4_4_2_ras; 2618 } 2619