1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_xcp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_trace.h" 33 34 #include "sdma/sdma_4_4_2_offset.h" 35 #include "sdma/sdma_4_4_2_sh_mask.h" 36 37 #include "soc15_common.h" 38 #include "soc15.h" 39 #include "vega10_sdma_pkt_open.h" 40 41 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 42 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 43 44 #include "amdgpu_ras.h" 45 46 MODULE_FIRMWARE("amdgpu/sdma_4_4_2.bin"); 47 48 #define mmSMNAID_AID0_MCA_SMU 0x03b30400 49 50 #define WREG32_SDMA(instance, offset, value) \ 51 WREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)), value) 52 #define RREG32_SDMA(instance, offset) \ 53 RREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset))) 54 55 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev); 56 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev); 57 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev); 58 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev); 59 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev); 60 61 static u32 sdma_v4_4_2_get_reg_offset(struct amdgpu_device *adev, 62 u32 instance, u32 offset) 63 { 64 u32 dev_inst = GET_INST(SDMA0, instance); 65 66 return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset); 67 } 68 69 static unsigned sdma_v4_4_2_seq_to_irq_id(int seq_num) 70 { 71 switch (seq_num) { 72 case 0: 73 return SOC15_IH_CLIENTID_SDMA0; 74 case 1: 75 return SOC15_IH_CLIENTID_SDMA1; 76 case 2: 77 return SOC15_IH_CLIENTID_SDMA2; 78 case 3: 79 return SOC15_IH_CLIENTID_SDMA3; 80 default: 81 return -EINVAL; 82 } 83 } 84 85 static int sdma_v4_4_2_irq_id_to_seq(unsigned client_id) 86 { 87 switch (client_id) { 88 case SOC15_IH_CLIENTID_SDMA0: 89 return 0; 90 case SOC15_IH_CLIENTID_SDMA1: 91 return 1; 92 case SOC15_IH_CLIENTID_SDMA2: 93 return 2; 94 case SOC15_IH_CLIENTID_SDMA3: 95 return 3; 96 default: 97 return -EINVAL; 98 } 99 } 100 101 static void sdma_v4_4_2_inst_init_golden_registers(struct amdgpu_device *adev, 102 uint32_t inst_mask) 103 { 104 u32 val; 105 int i; 106 107 for (i = 0; i < adev->sdma.num_instances; i++) { 108 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG); 109 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4); 110 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, 111 PIPE_INTERLEAVE_SIZE, 0); 112 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG, val); 113 114 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ); 115 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS, 116 4); 117 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, 118 PIPE_INTERLEAVE_SIZE, 0); 119 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ, val); 120 } 121 } 122 123 /** 124 * sdma_v4_4_2_init_microcode - load ucode images from disk 125 * 126 * @adev: amdgpu_device pointer 127 * 128 * Use the firmware interface to load the ucode images into 129 * the driver (not loaded into hw). 130 * Returns 0 on success, error on failure. 131 */ 132 static int sdma_v4_4_2_init_microcode(struct amdgpu_device *adev) 133 { 134 int ret, i; 135 136 for (i = 0; i < adev->sdma.num_instances; i++) { 137 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == 138 IP_VERSION(4, 4, 2)) { 139 ret = amdgpu_sdma_init_microcode(adev, 0, true); 140 break; 141 } else { 142 ret = amdgpu_sdma_init_microcode(adev, i, false); 143 if (ret) 144 return ret; 145 } 146 } 147 148 return ret; 149 } 150 151 /** 152 * sdma_v4_4_2_ring_get_rptr - get the current read pointer 153 * 154 * @ring: amdgpu ring pointer 155 * 156 * Get the current rptr from the hardware. 157 */ 158 static uint64_t sdma_v4_4_2_ring_get_rptr(struct amdgpu_ring *ring) 159 { 160 u64 rptr; 161 162 /* XXX check if swapping is necessary on BE */ 163 rptr = READ_ONCE(*((u64 *)&ring->adev->wb.wb[ring->rptr_offs])); 164 165 DRM_DEBUG("rptr before shift == 0x%016llx\n", rptr); 166 return rptr >> 2; 167 } 168 169 /** 170 * sdma_v4_4_2_ring_get_wptr - get the current write pointer 171 * 172 * @ring: amdgpu ring pointer 173 * 174 * Get the current wptr from the hardware. 175 */ 176 static uint64_t sdma_v4_4_2_ring_get_wptr(struct amdgpu_ring *ring) 177 { 178 struct amdgpu_device *adev = ring->adev; 179 u64 wptr; 180 181 if (ring->use_doorbell) { 182 /* XXX check if swapping is necessary on BE */ 183 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 184 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 185 } else { 186 wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI); 187 wptr = wptr << 32; 188 wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR); 189 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 190 ring->me, wptr); 191 } 192 193 return wptr >> 2; 194 } 195 196 /** 197 * sdma_v4_4_2_ring_set_wptr - commit the write pointer 198 * 199 * @ring: amdgpu ring pointer 200 * 201 * Write the wptr back to the hardware. 202 */ 203 static void sdma_v4_4_2_ring_set_wptr(struct amdgpu_ring *ring) 204 { 205 struct amdgpu_device *adev = ring->adev; 206 207 DRM_DEBUG("Setting write pointer\n"); 208 if (ring->use_doorbell) { 209 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 210 211 DRM_DEBUG("Using doorbell -- " 212 "wptr_offs == 0x%08x " 213 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 214 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 215 ring->wptr_offs, 216 lower_32_bits(ring->wptr << 2), 217 upper_32_bits(ring->wptr << 2)); 218 /* XXX check if swapping is necessary on BE */ 219 WRITE_ONCE(*wb, (ring->wptr << 2)); 220 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 221 ring->doorbell_index, ring->wptr << 2); 222 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 223 } else { 224 DRM_DEBUG("Not using doorbell -- " 225 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 226 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 227 ring->me, 228 lower_32_bits(ring->wptr << 2), 229 ring->me, 230 upper_32_bits(ring->wptr << 2)); 231 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR, 232 lower_32_bits(ring->wptr << 2)); 233 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI, 234 upper_32_bits(ring->wptr << 2)); 235 } 236 } 237 238 /** 239 * sdma_v4_4_2_page_ring_get_wptr - get the current write pointer 240 * 241 * @ring: amdgpu ring pointer 242 * 243 * Get the current wptr from the hardware. 244 */ 245 static uint64_t sdma_v4_4_2_page_ring_get_wptr(struct amdgpu_ring *ring) 246 { 247 struct amdgpu_device *adev = ring->adev; 248 u64 wptr; 249 250 if (ring->use_doorbell) { 251 /* XXX check if swapping is necessary on BE */ 252 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 253 } else { 254 wptr = RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI); 255 wptr = wptr << 32; 256 wptr |= RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR); 257 } 258 259 return wptr >> 2; 260 } 261 262 /** 263 * sdma_v4_4_2_page_ring_set_wptr - commit the write pointer 264 * 265 * @ring: amdgpu ring pointer 266 * 267 * Write the wptr back to the hardware. 268 */ 269 static void sdma_v4_4_2_page_ring_set_wptr(struct amdgpu_ring *ring) 270 { 271 struct amdgpu_device *adev = ring->adev; 272 273 if (ring->use_doorbell) { 274 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 275 276 /* XXX check if swapping is necessary on BE */ 277 WRITE_ONCE(*wb, (ring->wptr << 2)); 278 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 279 } else { 280 uint64_t wptr = ring->wptr << 2; 281 282 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR, 283 lower_32_bits(wptr)); 284 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI, 285 upper_32_bits(wptr)); 286 } 287 } 288 289 static void sdma_v4_4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 290 { 291 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 292 int i; 293 294 for (i = 0; i < count; i++) 295 if (sdma && sdma->burst_nop && (i == 0)) 296 amdgpu_ring_write(ring, ring->funcs->nop | 297 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 298 else 299 amdgpu_ring_write(ring, ring->funcs->nop); 300 } 301 302 /** 303 * sdma_v4_4_2_ring_emit_ib - Schedule an IB on the DMA engine 304 * 305 * @ring: amdgpu ring pointer 306 * @job: job to retrieve vmid from 307 * @ib: IB object to schedule 308 * @flags: unused 309 * 310 * Schedule an IB in the DMA ring. 311 */ 312 static void sdma_v4_4_2_ring_emit_ib(struct amdgpu_ring *ring, 313 struct amdgpu_job *job, 314 struct amdgpu_ib *ib, 315 uint32_t flags) 316 { 317 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 318 319 /* IB packet must end on a 8 DW boundary */ 320 sdma_v4_4_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 321 322 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 323 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 324 /* base must be 32 byte aligned */ 325 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 326 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 327 amdgpu_ring_write(ring, ib->length_dw); 328 amdgpu_ring_write(ring, 0); 329 amdgpu_ring_write(ring, 0); 330 331 } 332 333 static void sdma_v4_4_2_wait_reg_mem(struct amdgpu_ring *ring, 334 int mem_space, int hdp, 335 uint32_t addr0, uint32_t addr1, 336 uint32_t ref, uint32_t mask, 337 uint32_t inv) 338 { 339 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 340 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 341 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 342 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 343 if (mem_space) { 344 /* memory */ 345 amdgpu_ring_write(ring, addr0); 346 amdgpu_ring_write(ring, addr1); 347 } else { 348 /* registers */ 349 amdgpu_ring_write(ring, addr0 << 2); 350 amdgpu_ring_write(ring, addr1 << 2); 351 } 352 amdgpu_ring_write(ring, ref); /* reference */ 353 amdgpu_ring_write(ring, mask); /* mask */ 354 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 355 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 356 } 357 358 /** 359 * sdma_v4_4_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 360 * 361 * @ring: amdgpu ring pointer 362 * 363 * Emit an hdp flush packet on the requested DMA ring. 364 */ 365 static void sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 366 { 367 struct amdgpu_device *adev = ring->adev; 368 u32 ref_and_mask = 0; 369 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 370 371 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 372 373 sdma_v4_4_2_wait_reg_mem(ring, 0, 1, 374 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 375 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 376 ref_and_mask, ref_and_mask, 10); 377 } 378 379 /** 380 * sdma_v4_4_2_ring_emit_fence - emit a fence on the DMA ring 381 * 382 * @ring: amdgpu ring pointer 383 * @addr: address 384 * @seq: sequence number 385 * @flags: fence related flags 386 * 387 * Add a DMA fence packet to the ring to write 388 * the fence seq number and DMA trap packet to generate 389 * an interrupt if needed. 390 */ 391 static void sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 392 unsigned flags) 393 { 394 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 395 /* write the fence */ 396 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 397 /* zero in first two bits */ 398 BUG_ON(addr & 0x3); 399 amdgpu_ring_write(ring, lower_32_bits(addr)); 400 amdgpu_ring_write(ring, upper_32_bits(addr)); 401 amdgpu_ring_write(ring, lower_32_bits(seq)); 402 403 /* optionally write high bits as well */ 404 if (write64bit) { 405 addr += 4; 406 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 407 /* zero in first two bits */ 408 BUG_ON(addr & 0x3); 409 amdgpu_ring_write(ring, lower_32_bits(addr)); 410 amdgpu_ring_write(ring, upper_32_bits(addr)); 411 amdgpu_ring_write(ring, upper_32_bits(seq)); 412 } 413 414 /* generate an interrupt */ 415 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 416 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 417 } 418 419 420 /** 421 * sdma_v4_4_2_inst_gfx_stop - stop the gfx async dma engines 422 * 423 * @adev: amdgpu_device pointer 424 * @inst_mask: mask of dma engine instances to be disabled 425 * 426 * Stop the gfx async dma ring buffers. 427 */ 428 static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev, 429 uint32_t inst_mask) 430 { 431 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 432 u32 doorbell_offset, doorbell; 433 u32 rb_cntl, ib_cntl; 434 int i, unset = 0; 435 436 for_each_inst(i, inst_mask) { 437 sdma[i] = &adev->sdma.instance[i].ring; 438 439 if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) { 440 amdgpu_ttm_set_buffer_funcs_status(adev, false); 441 unset = 1; 442 } 443 444 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); 445 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0); 446 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 447 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 448 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0); 449 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 450 451 if (sdma[i]->use_doorbell) { 452 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL); 453 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET); 454 455 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 0); 456 doorbell_offset = REG_SET_FIELD(doorbell_offset, 457 SDMA_GFX_DOORBELL_OFFSET, 458 OFFSET, 0); 459 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell); 460 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset); 461 } 462 } 463 } 464 465 /** 466 * sdma_v4_4_2_inst_rlc_stop - stop the compute async dma engines 467 * 468 * @adev: amdgpu_device pointer 469 * @inst_mask: mask of dma engine instances to be disabled 470 * 471 * Stop the compute async dma queues. 472 */ 473 static void sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device *adev, 474 uint32_t inst_mask) 475 { 476 /* XXX todo */ 477 } 478 479 /** 480 * sdma_v4_4_2_inst_page_stop - stop the page async dma engines 481 * 482 * @adev: amdgpu_device pointer 483 * @inst_mask: mask of dma engine instances to be disabled 484 * 485 * Stop the page async dma ring buffers. 486 */ 487 static void sdma_v4_4_2_inst_page_stop(struct amdgpu_device *adev, 488 uint32_t inst_mask) 489 { 490 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 491 u32 rb_cntl, ib_cntl; 492 int i; 493 bool unset = false; 494 495 for_each_inst(i, inst_mask) { 496 sdma[i] = &adev->sdma.instance[i].page; 497 498 if ((adev->mman.buffer_funcs_ring == sdma[i]) && 499 (!unset)) { 500 amdgpu_ttm_set_buffer_funcs_status(adev, false); 501 unset = true; 502 } 503 504 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); 505 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, 506 RB_ENABLE, 0); 507 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 508 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); 509 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, 510 IB_ENABLE, 0); 511 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); 512 } 513 } 514 515 /** 516 * sdma_v4_4_2_inst_ctx_switch_enable - stop the async dma engines context switch 517 * 518 * @adev: amdgpu_device pointer 519 * @enable: enable/disable the DMA MEs context switch. 520 * @inst_mask: mask of dma engine instances to be enabled 521 * 522 * Halt or unhalt the async dma engines context switch. 523 */ 524 static void sdma_v4_4_2_inst_ctx_switch_enable(struct amdgpu_device *adev, 525 bool enable, uint32_t inst_mask) 526 { 527 u32 f32_cntl, phase_quantum = 0; 528 int i; 529 530 if (amdgpu_sdma_phase_quantum) { 531 unsigned value = amdgpu_sdma_phase_quantum; 532 unsigned unit = 0; 533 534 while (value > (SDMA_PHASE0_QUANTUM__VALUE_MASK >> 535 SDMA_PHASE0_QUANTUM__VALUE__SHIFT)) { 536 value = (value + 1) >> 1; 537 unit++; 538 } 539 if (unit > (SDMA_PHASE0_QUANTUM__UNIT_MASK >> 540 SDMA_PHASE0_QUANTUM__UNIT__SHIFT)) { 541 value = (SDMA_PHASE0_QUANTUM__VALUE_MASK >> 542 SDMA_PHASE0_QUANTUM__VALUE__SHIFT); 543 unit = (SDMA_PHASE0_QUANTUM__UNIT_MASK >> 544 SDMA_PHASE0_QUANTUM__UNIT__SHIFT); 545 WARN_ONCE(1, 546 "clamping sdma_phase_quantum to %uK clock cycles\n", 547 value << unit); 548 } 549 phase_quantum = 550 value << SDMA_PHASE0_QUANTUM__VALUE__SHIFT | 551 unit << SDMA_PHASE0_QUANTUM__UNIT__SHIFT; 552 } 553 554 for_each_inst(i, inst_mask) { 555 f32_cntl = RREG32_SDMA(i, regSDMA_CNTL); 556 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_CNTL, 557 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 558 if (enable && amdgpu_sdma_phase_quantum) { 559 WREG32_SDMA(i, regSDMA_PHASE0_QUANTUM, phase_quantum); 560 WREG32_SDMA(i, regSDMA_PHASE1_QUANTUM, phase_quantum); 561 WREG32_SDMA(i, regSDMA_PHASE2_QUANTUM, phase_quantum); 562 } 563 WREG32_SDMA(i, regSDMA_CNTL, f32_cntl); 564 565 /* Extend page fault timeout to avoid interrupt storm */ 566 WREG32_SDMA(i, regSDMA_UTCL1_TIMEOUT, 0x00800080); 567 } 568 } 569 570 /** 571 * sdma_v4_4_2_inst_enable - stop the async dma engines 572 * 573 * @adev: amdgpu_device pointer 574 * @enable: enable/disable the DMA MEs. 575 * @inst_mask: mask of dma engine instances to be enabled 576 * 577 * Halt or unhalt the async dma engines. 578 */ 579 static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable, 580 uint32_t inst_mask) 581 { 582 u32 f32_cntl; 583 int i; 584 585 if (!enable) { 586 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask); 587 sdma_v4_4_2_inst_rlc_stop(adev, inst_mask); 588 if (adev->sdma.has_page_queue) 589 sdma_v4_4_2_inst_page_stop(adev, inst_mask); 590 591 /* SDMA FW needs to respond to FREEZE requests during reset. 592 * Keep it running during reset */ 593 if (!amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 594 return; 595 } 596 597 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 598 return; 599 600 for_each_inst(i, inst_mask) { 601 f32_cntl = RREG32_SDMA(i, regSDMA_F32_CNTL); 602 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1); 603 WREG32_SDMA(i, regSDMA_F32_CNTL, f32_cntl); 604 } 605 } 606 607 /* 608 * sdma_v4_4_2_rb_cntl - get parameters for rb_cntl 609 */ 610 static uint32_t sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 611 { 612 /* Set ring buffer size in dwords */ 613 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 614 615 barrier(); /* work around https://llvm.org/pr42576 */ 616 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 617 #ifdef __BIG_ENDIAN 618 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 619 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, 620 RPTR_WRITEBACK_SWAP_ENABLE, 1); 621 #endif 622 return rb_cntl; 623 } 624 625 /** 626 * sdma_v4_4_2_gfx_resume - setup and start the async dma engines 627 * 628 * @adev: amdgpu_device pointer 629 * @i: instance to resume 630 * 631 * Set up the gfx DMA ring buffers and enable them. 632 * Returns 0 for success, error for failure. 633 */ 634 static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i) 635 { 636 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 637 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 638 u32 wb_offset; 639 u32 doorbell; 640 u32 doorbell_offset; 641 u64 wptr_gpu_addr; 642 643 wb_offset = (ring->rptr_offs * 4); 644 645 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); 646 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 647 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 648 649 /* set the wb address whether it's enabled or not */ 650 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_HI, 651 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 652 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_LO, 653 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 654 655 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, 656 RPTR_WRITEBACK_ENABLE, 1); 657 658 WREG32_SDMA(i, regSDMA_GFX_RB_BASE, ring->gpu_addr >> 8); 659 WREG32_SDMA(i, regSDMA_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 660 661 ring->wptr = 0; 662 663 /* before programing wptr to a less value, need set minor_ptr_update first */ 664 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 1); 665 666 /* Initialize the ring buffer's read and write pointers */ 667 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0); 668 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0); 669 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0); 670 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0); 671 672 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL); 673 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET); 674 675 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 676 ring->use_doorbell); 677 doorbell_offset = REG_SET_FIELD(doorbell_offset, 678 SDMA_GFX_DOORBELL_OFFSET, 679 OFFSET, ring->doorbell_index); 680 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell); 681 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset); 682 683 sdma_v4_4_2_ring_set_wptr(ring); 684 685 /* set minor_ptr_update to 0 after wptr programed */ 686 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 0); 687 688 /* setup the wptr shadow polling */ 689 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 690 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_LO, 691 lower_32_bits(wptr_gpu_addr)); 692 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_HI, 693 upper_32_bits(wptr_gpu_addr)); 694 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL); 695 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 696 SDMA_GFX_RB_WPTR_POLL_CNTL, 697 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 698 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 699 700 /* enable DMA RB */ 701 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 1); 702 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 703 704 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 705 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 1); 706 #ifdef __BIG_ENDIAN 707 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 708 #endif 709 /* enable DMA IBs */ 710 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 711 } 712 713 /** 714 * sdma_v4_4_2_page_resume - setup and start the async dma engines 715 * 716 * @adev: amdgpu_device pointer 717 * @i: instance to resume 718 * 719 * Set up the page DMA ring buffers and enable them. 720 * Returns 0 for success, error for failure. 721 */ 722 static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i) 723 { 724 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 725 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 726 u32 wb_offset; 727 u32 doorbell; 728 u32 doorbell_offset; 729 u64 wptr_gpu_addr; 730 731 wb_offset = (ring->rptr_offs * 4); 732 733 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); 734 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 735 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 736 737 /* Initialize the ring buffer's read and write pointers */ 738 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, 0); 739 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, 0); 740 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, 0); 741 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, 0); 742 743 /* set the wb address whether it's enabled or not */ 744 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_HI, 745 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 746 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_LO, 747 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 748 749 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, 750 RPTR_WRITEBACK_ENABLE, 1); 751 752 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE, ring->gpu_addr >> 8); 753 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 754 755 ring->wptr = 0; 756 757 /* before programing wptr to a less value, need set minor_ptr_update first */ 758 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 1); 759 760 doorbell = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL); 761 doorbell_offset = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET); 762 763 doorbell = REG_SET_FIELD(doorbell, SDMA_PAGE_DOORBELL, ENABLE, 764 ring->use_doorbell); 765 doorbell_offset = REG_SET_FIELD(doorbell_offset, 766 SDMA_PAGE_DOORBELL_OFFSET, 767 OFFSET, ring->doorbell_index); 768 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL, doorbell); 769 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET, doorbell_offset); 770 771 /* paging queue doorbell range is setup at sdma_v4_4_2_gfx_resume */ 772 sdma_v4_4_2_page_ring_set_wptr(ring); 773 774 /* set minor_ptr_update to 0 after wptr programed */ 775 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 0); 776 777 /* setup the wptr shadow polling */ 778 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 779 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_LO, 780 lower_32_bits(wptr_gpu_addr)); 781 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_HI, 782 upper_32_bits(wptr_gpu_addr)); 783 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL); 784 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 785 SDMA_PAGE_RB_WPTR_POLL_CNTL, 786 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 787 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 788 789 /* enable DMA RB */ 790 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, RB_ENABLE, 1); 791 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 792 793 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); 794 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_ENABLE, 1); 795 #ifdef __BIG_ENDIAN 796 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 797 #endif 798 /* enable DMA IBs */ 799 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); 800 } 801 802 static void sdma_v4_4_2_init_pg(struct amdgpu_device *adev) 803 { 804 805 } 806 807 /** 808 * sdma_v4_4_2_inst_rlc_resume - setup and start the async dma engines 809 * 810 * @adev: amdgpu_device pointer 811 * @inst_mask: mask of dma engine instances to be enabled 812 * 813 * Set up the compute DMA queues and enable them. 814 * Returns 0 for success, error for failure. 815 */ 816 static int sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device *adev, 817 uint32_t inst_mask) 818 { 819 sdma_v4_4_2_init_pg(adev); 820 821 return 0; 822 } 823 824 /** 825 * sdma_v4_4_2_inst_load_microcode - load the sDMA ME ucode 826 * 827 * @adev: amdgpu_device pointer 828 * @inst_mask: mask of dma engine instances to be enabled 829 * 830 * Loads the sDMA0/1 ucode. 831 * Returns 0 for success, -EINVAL if the ucode is not available. 832 */ 833 static int sdma_v4_4_2_inst_load_microcode(struct amdgpu_device *adev, 834 uint32_t inst_mask) 835 { 836 const struct sdma_firmware_header_v1_0 *hdr; 837 const __le32 *fw_data; 838 u32 fw_size; 839 int i, j; 840 841 /* halt the MEs */ 842 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 843 844 for_each_inst(i, inst_mask) { 845 if (!adev->sdma.instance[i].fw) 846 return -EINVAL; 847 848 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 849 amdgpu_ucode_print_sdma_hdr(&hdr->header); 850 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 851 852 fw_data = (const __le32 *) 853 (adev->sdma.instance[i].fw->data + 854 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 855 856 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 0); 857 858 for (j = 0; j < fw_size; j++) 859 WREG32_SDMA(i, regSDMA_UCODE_DATA, 860 le32_to_cpup(fw_data++)); 861 862 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 863 adev->sdma.instance[i].fw_version); 864 } 865 866 return 0; 867 } 868 869 /** 870 * sdma_v4_4_2_inst_start - setup and start the async dma engines 871 * 872 * @adev: amdgpu_device pointer 873 * @inst_mask: mask of dma engine instances to be enabled 874 * 875 * Set up the DMA engines and enable them. 876 * Returns 0 for success, error for failure. 877 */ 878 static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev, 879 uint32_t inst_mask) 880 { 881 struct amdgpu_ring *ring; 882 uint32_t tmp_mask; 883 int i, r = 0; 884 885 if (amdgpu_sriov_vf(adev)) { 886 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 887 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 888 } else { 889 /* bypass sdma microcode loading on Gopher */ 890 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP && 891 adev->sdma.instance[0].fw) { 892 r = sdma_v4_4_2_inst_load_microcode(adev, inst_mask); 893 if (r) 894 return r; 895 } 896 897 /* unhalt the MEs */ 898 sdma_v4_4_2_inst_enable(adev, true, inst_mask); 899 /* enable sdma ring preemption */ 900 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask); 901 } 902 903 /* start the gfx rings and rlc compute queues */ 904 tmp_mask = inst_mask; 905 for_each_inst(i, tmp_mask) { 906 uint32_t temp; 907 908 WREG32_SDMA(i, regSDMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); 909 sdma_v4_4_2_gfx_resume(adev, i); 910 if (adev->sdma.has_page_queue) 911 sdma_v4_4_2_page_resume(adev, i); 912 913 /* set utc l1 enable flag always to 1 */ 914 temp = RREG32_SDMA(i, regSDMA_CNTL); 915 temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1); 916 /* enable context empty interrupt during initialization */ 917 temp = REG_SET_FIELD(temp, SDMA_CNTL, CTXEMPTY_INT_ENABLE, 1); 918 WREG32_SDMA(i, regSDMA_CNTL, temp); 919 920 if (!amdgpu_sriov_vf(adev)) { 921 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 922 /* unhalt engine */ 923 temp = RREG32_SDMA(i, regSDMA_F32_CNTL); 924 temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0); 925 WREG32_SDMA(i, regSDMA_F32_CNTL, temp); 926 } 927 } 928 } 929 930 if (amdgpu_sriov_vf(adev)) { 931 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask); 932 sdma_v4_4_2_inst_enable(adev, true, inst_mask); 933 } else { 934 r = sdma_v4_4_2_inst_rlc_resume(adev, inst_mask); 935 if (r) 936 return r; 937 } 938 939 tmp_mask = inst_mask; 940 for_each_inst(i, tmp_mask) { 941 ring = &adev->sdma.instance[i].ring; 942 943 r = amdgpu_ring_test_helper(ring); 944 if (r) 945 return r; 946 947 if (adev->sdma.has_page_queue) { 948 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 949 950 r = amdgpu_ring_test_helper(page); 951 if (r) 952 return r; 953 954 if (adev->mman.buffer_funcs_ring == page) 955 amdgpu_ttm_set_buffer_funcs_status(adev, true); 956 } 957 958 if (adev->mman.buffer_funcs_ring == ring) 959 amdgpu_ttm_set_buffer_funcs_status(adev, true); 960 } 961 962 return r; 963 } 964 965 /** 966 * sdma_v4_4_2_ring_test_ring - simple async dma engine test 967 * 968 * @ring: amdgpu_ring structure holding ring information 969 * 970 * Test the DMA engine by writing using it to write an 971 * value to memory. 972 * Returns 0 for success, error for failure. 973 */ 974 static int sdma_v4_4_2_ring_test_ring(struct amdgpu_ring *ring) 975 { 976 struct amdgpu_device *adev = ring->adev; 977 unsigned i; 978 unsigned index; 979 int r; 980 u32 tmp; 981 u64 gpu_addr; 982 983 r = amdgpu_device_wb_get(adev, &index); 984 if (r) 985 return r; 986 987 gpu_addr = adev->wb.gpu_addr + (index * 4); 988 tmp = 0xCAFEDEAD; 989 adev->wb.wb[index] = cpu_to_le32(tmp); 990 991 r = amdgpu_ring_alloc(ring, 5); 992 if (r) 993 goto error_free_wb; 994 995 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 996 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 997 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 998 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 999 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1000 amdgpu_ring_write(ring, 0xDEADBEEF); 1001 amdgpu_ring_commit(ring); 1002 1003 for (i = 0; i < adev->usec_timeout; i++) { 1004 tmp = le32_to_cpu(adev->wb.wb[index]); 1005 if (tmp == 0xDEADBEEF) 1006 break; 1007 udelay(1); 1008 } 1009 1010 if (i >= adev->usec_timeout) 1011 r = -ETIMEDOUT; 1012 1013 error_free_wb: 1014 amdgpu_device_wb_free(adev, index); 1015 return r; 1016 } 1017 1018 /** 1019 * sdma_v4_4_2_ring_test_ib - test an IB on the DMA engine 1020 * 1021 * @ring: amdgpu_ring structure holding ring information 1022 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1023 * 1024 * Test a simple IB in the DMA ring. 1025 * Returns 0 on success, error on failure. 1026 */ 1027 static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1028 { 1029 struct amdgpu_device *adev = ring->adev; 1030 struct amdgpu_ib ib; 1031 struct dma_fence *f = NULL; 1032 unsigned index; 1033 long r; 1034 u32 tmp = 0; 1035 u64 gpu_addr; 1036 1037 r = amdgpu_device_wb_get(adev, &index); 1038 if (r) 1039 return r; 1040 1041 gpu_addr = adev->wb.gpu_addr + (index * 4); 1042 tmp = 0xCAFEDEAD; 1043 adev->wb.wb[index] = cpu_to_le32(tmp); 1044 memset(&ib, 0, sizeof(ib)); 1045 r = amdgpu_ib_get(adev, NULL, 256, 1046 AMDGPU_IB_POOL_DIRECT, &ib); 1047 if (r) 1048 goto err0; 1049 1050 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1051 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1052 ib.ptr[1] = lower_32_bits(gpu_addr); 1053 ib.ptr[2] = upper_32_bits(gpu_addr); 1054 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1055 ib.ptr[4] = 0xDEADBEEF; 1056 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1057 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1058 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1059 ib.length_dw = 8; 1060 1061 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1062 if (r) 1063 goto err1; 1064 1065 r = dma_fence_wait_timeout(f, false, timeout); 1066 if (r == 0) { 1067 r = -ETIMEDOUT; 1068 goto err1; 1069 } else if (r < 0) { 1070 goto err1; 1071 } 1072 tmp = le32_to_cpu(adev->wb.wb[index]); 1073 if (tmp == 0xDEADBEEF) 1074 r = 0; 1075 else 1076 r = -EINVAL; 1077 1078 err1: 1079 amdgpu_ib_free(adev, &ib, NULL); 1080 dma_fence_put(f); 1081 err0: 1082 amdgpu_device_wb_free(adev, index); 1083 return r; 1084 } 1085 1086 1087 /** 1088 * sdma_v4_4_2_vm_copy_pte - update PTEs by copying them from the GART 1089 * 1090 * @ib: indirect buffer to fill with commands 1091 * @pe: addr of the page entry 1092 * @src: src addr to copy from 1093 * @count: number of page entries to update 1094 * 1095 * Update PTEs by copying them from the GART using sDMA. 1096 */ 1097 static void sdma_v4_4_2_vm_copy_pte(struct amdgpu_ib *ib, 1098 uint64_t pe, uint64_t src, 1099 unsigned count) 1100 { 1101 unsigned bytes = count * 8; 1102 1103 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1104 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1105 ib->ptr[ib->length_dw++] = bytes - 1; 1106 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1107 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1108 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1109 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1110 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1111 1112 } 1113 1114 /** 1115 * sdma_v4_4_2_vm_write_pte - update PTEs by writing them manually 1116 * 1117 * @ib: indirect buffer to fill with commands 1118 * @pe: addr of the page entry 1119 * @value: dst addr to write into pe 1120 * @count: number of page entries to update 1121 * @incr: increase next addr by incr bytes 1122 * 1123 * Update PTEs by writing them manually using sDMA. 1124 */ 1125 static void sdma_v4_4_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1126 uint64_t value, unsigned count, 1127 uint32_t incr) 1128 { 1129 unsigned ndw = count * 2; 1130 1131 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1132 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1133 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1134 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1135 ib->ptr[ib->length_dw++] = ndw - 1; 1136 for (; ndw > 0; ndw -= 2) { 1137 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1138 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1139 value += incr; 1140 } 1141 } 1142 1143 /** 1144 * sdma_v4_4_2_vm_set_pte_pde - update the page tables using sDMA 1145 * 1146 * @ib: indirect buffer to fill with commands 1147 * @pe: addr of the page entry 1148 * @addr: dst addr to write into pe 1149 * @count: number of page entries to update 1150 * @incr: increase next addr by incr bytes 1151 * @flags: access flags 1152 * 1153 * Update the page tables using sDMA. 1154 */ 1155 static void sdma_v4_4_2_vm_set_pte_pde(struct amdgpu_ib *ib, 1156 uint64_t pe, 1157 uint64_t addr, unsigned count, 1158 uint32_t incr, uint64_t flags) 1159 { 1160 /* for physically contiguous pages (vram) */ 1161 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1162 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1163 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1164 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1165 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1166 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1167 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1168 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1169 ib->ptr[ib->length_dw++] = 0; 1170 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1171 } 1172 1173 /** 1174 * sdma_v4_4_2_ring_pad_ib - pad the IB to the required number of dw 1175 * 1176 * @ring: amdgpu_ring structure holding ring information 1177 * @ib: indirect buffer to fill with padding 1178 */ 1179 static void sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1180 { 1181 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1182 u32 pad_count; 1183 int i; 1184 1185 pad_count = (-ib->length_dw) & 7; 1186 for (i = 0; i < pad_count; i++) 1187 if (sdma && sdma->burst_nop && (i == 0)) 1188 ib->ptr[ib->length_dw++] = 1189 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1190 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1191 else 1192 ib->ptr[ib->length_dw++] = 1193 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1194 } 1195 1196 1197 /** 1198 * sdma_v4_4_2_ring_emit_pipeline_sync - sync the pipeline 1199 * 1200 * @ring: amdgpu_ring pointer 1201 * 1202 * Make sure all previous operations are completed (CIK). 1203 */ 1204 static void sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1205 { 1206 uint32_t seq = ring->fence_drv.sync_seq; 1207 uint64_t addr = ring->fence_drv.gpu_addr; 1208 1209 /* wait for idle */ 1210 sdma_v4_4_2_wait_reg_mem(ring, 1, 0, 1211 addr & 0xfffffffc, 1212 upper_32_bits(addr) & 0xffffffff, 1213 seq, 0xffffffff, 4); 1214 } 1215 1216 1217 /** 1218 * sdma_v4_4_2_ring_emit_vm_flush - vm flush using sDMA 1219 * 1220 * @ring: amdgpu_ring pointer 1221 * @vmid: vmid number to use 1222 * @pd_addr: address 1223 * 1224 * Update the page table base and flush the VM TLB 1225 * using sDMA. 1226 */ 1227 static void sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring *ring, 1228 unsigned vmid, uint64_t pd_addr) 1229 { 1230 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1231 } 1232 1233 static void sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring *ring, 1234 uint32_t reg, uint32_t val) 1235 { 1236 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1237 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1238 amdgpu_ring_write(ring, reg); 1239 amdgpu_ring_write(ring, val); 1240 } 1241 1242 static void sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1243 uint32_t val, uint32_t mask) 1244 { 1245 sdma_v4_4_2_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1246 } 1247 1248 static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev) 1249 { 1250 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1251 case IP_VERSION(4, 4, 2): 1252 return false; 1253 default: 1254 return false; 1255 } 1256 } 1257 1258 static int sdma_v4_4_2_early_init(void *handle) 1259 { 1260 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1261 int r; 1262 1263 r = sdma_v4_4_2_init_microcode(adev); 1264 if (r) 1265 return r; 1266 1267 /* TODO: Page queue breaks driver reload under SRIOV */ 1268 if (sdma_v4_4_2_fw_support_paging_queue(adev)) 1269 adev->sdma.has_page_queue = true; 1270 1271 sdma_v4_4_2_set_ring_funcs(adev); 1272 sdma_v4_4_2_set_buffer_funcs(adev); 1273 sdma_v4_4_2_set_vm_pte_funcs(adev); 1274 sdma_v4_4_2_set_irq_funcs(adev); 1275 sdma_v4_4_2_set_ras_funcs(adev); 1276 1277 return 0; 1278 } 1279 1280 #if 0 1281 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, 1282 void *err_data, 1283 struct amdgpu_iv_entry *entry); 1284 #endif 1285 1286 static int sdma_v4_4_2_late_init(void *handle) 1287 { 1288 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1289 #if 0 1290 struct ras_ih_if ih_info = { 1291 .cb = sdma_v4_4_2_process_ras_data_cb, 1292 }; 1293 #endif 1294 if (!amdgpu_persistent_edc_harvesting_supported(adev)) 1295 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__SDMA); 1296 1297 return 0; 1298 } 1299 1300 static int sdma_v4_4_2_sw_init(void *handle) 1301 { 1302 struct amdgpu_ring *ring; 1303 int r, i; 1304 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1305 u32 aid_id; 1306 1307 /* SDMA trap event */ 1308 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1309 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1310 SDMA0_4_0__SRCID__SDMA_TRAP, 1311 &adev->sdma.trap_irq); 1312 if (r) 1313 return r; 1314 } 1315 1316 /* SDMA SRAM ECC event */ 1317 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1318 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1319 SDMA0_4_0__SRCID__SDMA_SRAM_ECC, 1320 &adev->sdma.ecc_irq); 1321 if (r) 1322 return r; 1323 } 1324 1325 /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/ 1326 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1327 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1328 SDMA0_4_0__SRCID__SDMA_VM_HOLE, 1329 &adev->sdma.vm_hole_irq); 1330 if (r) 1331 return r; 1332 1333 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1334 SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID, 1335 &adev->sdma.doorbell_invalid_irq); 1336 if (r) 1337 return r; 1338 1339 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1340 SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT, 1341 &adev->sdma.pool_timeout_irq); 1342 if (r) 1343 return r; 1344 1345 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1346 SDMA0_4_0__SRCID__SDMA_SRBMWRITE, 1347 &adev->sdma.srbm_write_irq); 1348 if (r) 1349 return r; 1350 } 1351 1352 for (i = 0; i < adev->sdma.num_instances; i++) { 1353 ring = &adev->sdma.instance[i].ring; 1354 ring->ring_obj = NULL; 1355 ring->use_doorbell = true; 1356 aid_id = adev->sdma.instance[i].aid_id; 1357 1358 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1359 ring->use_doorbell?"true":"false"); 1360 1361 /* doorbell size is 2 dwords, get DWORD offset */ 1362 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1363 ring->vm_hub = AMDGPU_MMHUB0(aid_id); 1364 1365 sprintf(ring->name, "sdma%d.%d", aid_id, 1366 i % adev->sdma.num_inst_per_aid); 1367 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1368 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1369 AMDGPU_RING_PRIO_DEFAULT, NULL); 1370 if (r) 1371 return r; 1372 1373 if (adev->sdma.has_page_queue) { 1374 ring = &adev->sdma.instance[i].page; 1375 ring->ring_obj = NULL; 1376 ring->use_doorbell = true; 1377 1378 /* doorbell index of page queue is assigned right after 1379 * gfx queue on the same instance 1380 */ 1381 ring->doorbell_index = 1382 (adev->doorbell_index.sdma_engine[i] + 1) << 1; 1383 ring->vm_hub = AMDGPU_MMHUB0(aid_id); 1384 1385 sprintf(ring->name, "page%d.%d", aid_id, 1386 i % adev->sdma.num_inst_per_aid); 1387 r = amdgpu_ring_init(adev, ring, 1024, 1388 &adev->sdma.trap_irq, 1389 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1390 AMDGPU_RING_PRIO_DEFAULT, NULL); 1391 if (r) 1392 return r; 1393 } 1394 } 1395 1396 if (amdgpu_sdma_ras_sw_init(adev)) { 1397 dev_err(adev->dev, "fail to initialize sdma ras block\n"); 1398 return -EINVAL; 1399 } 1400 1401 return r; 1402 } 1403 1404 static int sdma_v4_4_2_sw_fini(void *handle) 1405 { 1406 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1407 int i; 1408 1409 for (i = 0; i < adev->sdma.num_instances; i++) { 1410 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1411 if (adev->sdma.has_page_queue) 1412 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1413 } 1414 1415 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2)) 1416 amdgpu_sdma_destroy_inst_ctx(adev, true); 1417 else 1418 amdgpu_sdma_destroy_inst_ctx(adev, false); 1419 1420 return 0; 1421 } 1422 1423 static int sdma_v4_4_2_hw_init(void *handle) 1424 { 1425 int r; 1426 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1427 uint32_t inst_mask; 1428 1429 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1430 if (!amdgpu_sriov_vf(adev)) 1431 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask); 1432 1433 r = sdma_v4_4_2_inst_start(adev, inst_mask); 1434 1435 return r; 1436 } 1437 1438 static int sdma_v4_4_2_hw_fini(void *handle) 1439 { 1440 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1441 uint32_t inst_mask; 1442 int i; 1443 1444 if (amdgpu_sriov_vf(adev)) 1445 return 0; 1446 1447 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1448 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 1449 for (i = 0; i < adev->sdma.num_instances; i++) { 1450 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 1451 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1452 } 1453 } 1454 1455 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 1456 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 1457 1458 return 0; 1459 } 1460 1461 static int sdma_v4_4_2_set_clockgating_state(void *handle, 1462 enum amd_clockgating_state state); 1463 1464 static int sdma_v4_4_2_suspend(void *handle) 1465 { 1466 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1467 1468 if (amdgpu_in_reset(adev)) 1469 sdma_v4_4_2_set_clockgating_state(adev, AMD_CG_STATE_UNGATE); 1470 1471 return sdma_v4_4_2_hw_fini(adev); 1472 } 1473 1474 static int sdma_v4_4_2_resume(void *handle) 1475 { 1476 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1477 1478 return sdma_v4_4_2_hw_init(adev); 1479 } 1480 1481 static bool sdma_v4_4_2_is_idle(void *handle) 1482 { 1483 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1484 u32 i; 1485 1486 for (i = 0; i < adev->sdma.num_instances; i++) { 1487 u32 tmp = RREG32_SDMA(i, regSDMA_STATUS_REG); 1488 1489 if (!(tmp & SDMA_STATUS_REG__IDLE_MASK)) 1490 return false; 1491 } 1492 1493 return true; 1494 } 1495 1496 static int sdma_v4_4_2_wait_for_idle(void *handle) 1497 { 1498 unsigned i, j; 1499 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; 1500 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1501 1502 for (i = 0; i < adev->usec_timeout; i++) { 1503 for (j = 0; j < adev->sdma.num_instances; j++) { 1504 sdma[j] = RREG32_SDMA(j, regSDMA_STATUS_REG); 1505 if (!(sdma[j] & SDMA_STATUS_REG__IDLE_MASK)) 1506 break; 1507 } 1508 if (j == adev->sdma.num_instances) 1509 return 0; 1510 udelay(1); 1511 } 1512 return -ETIMEDOUT; 1513 } 1514 1515 static int sdma_v4_4_2_soft_reset(void *handle) 1516 { 1517 /* todo */ 1518 1519 return 0; 1520 } 1521 1522 static int sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device *adev, 1523 struct amdgpu_irq_src *source, 1524 unsigned type, 1525 enum amdgpu_interrupt_state state) 1526 { 1527 u32 sdma_cntl; 1528 1529 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); 1530 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE, 1531 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1532 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); 1533 1534 return 0; 1535 } 1536 1537 static int sdma_v4_4_2_process_trap_irq(struct amdgpu_device *adev, 1538 struct amdgpu_irq_src *source, 1539 struct amdgpu_iv_entry *entry) 1540 { 1541 uint32_t instance, i; 1542 1543 DRM_DEBUG("IH: SDMA trap\n"); 1544 instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id); 1545 1546 /* Client id gives the SDMA instance in AID. To know the exact SDMA 1547 * instance, interrupt entry gives the node id which corresponds to the AID instance. 1548 * Match node id with the AID id associated with the SDMA instance. */ 1549 for (i = instance; i < adev->sdma.num_instances; 1550 i += adev->sdma.num_inst_per_aid) { 1551 if (adev->sdma.instance[i].aid_id == 1552 node_id_to_phys_map[entry->node_id]) 1553 break; 1554 } 1555 1556 if (i >= adev->sdma.num_instances) { 1557 dev_WARN_ONCE( 1558 adev->dev, 1, 1559 "Couldn't find the right sdma instance in trap handler"); 1560 return 0; 1561 } 1562 1563 switch (entry->ring_id) { 1564 case 0: 1565 amdgpu_fence_process(&adev->sdma.instance[i].ring); 1566 break; 1567 default: 1568 break; 1569 } 1570 return 0; 1571 } 1572 1573 #if 0 1574 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, 1575 void *err_data, 1576 struct amdgpu_iv_entry *entry) 1577 { 1578 int instance; 1579 1580 /* When “Full RAS” is enabled, the per-IP interrupt sources should 1581 * be disabled and the driver should only look for the aggregated 1582 * interrupt via sync flood 1583 */ 1584 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) 1585 goto out; 1586 1587 instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id); 1588 if (instance < 0) 1589 goto out; 1590 1591 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry); 1592 1593 out: 1594 return AMDGPU_RAS_SUCCESS; 1595 } 1596 #endif 1597 1598 static int sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device *adev, 1599 struct amdgpu_irq_src *source, 1600 struct amdgpu_iv_entry *entry) 1601 { 1602 int instance; 1603 1604 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1605 1606 instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id); 1607 if (instance < 0) 1608 return 0; 1609 1610 switch (entry->ring_id) { 1611 case 0: 1612 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 1613 break; 1614 } 1615 return 0; 1616 } 1617 1618 static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev, 1619 struct amdgpu_irq_src *source, 1620 unsigned type, 1621 enum amdgpu_interrupt_state state) 1622 { 1623 u32 sdma_cntl; 1624 1625 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); 1626 switch (state) { 1627 case AMDGPU_IRQ_STATE_DISABLE: 1628 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, 1629 DRAM_ECC_INT_ENABLE, 0); 1630 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); 1631 break; 1632 /* sdma ecc interrupt is enabled by default 1633 * driver doesn't need to do anything to 1634 * enable the interrupt */ 1635 case AMDGPU_IRQ_STATE_ENABLE: 1636 default: 1637 break; 1638 } 1639 1640 return 0; 1641 } 1642 1643 static int sdma_v4_4_2_print_iv_entry(struct amdgpu_device *adev, 1644 struct amdgpu_iv_entry *entry) 1645 { 1646 int instance; 1647 struct amdgpu_task_info *task_info; 1648 u64 addr; 1649 1650 instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id); 1651 if (instance < 0 || instance >= adev->sdma.num_instances) { 1652 dev_err(adev->dev, "sdma instance invalid %d\n", instance); 1653 return -EINVAL; 1654 } 1655 1656 addr = (u64)entry->src_data[0] << 12; 1657 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 1658 1659 dev_dbg_ratelimited(adev->dev, 1660 "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u pasid:%u\n", 1661 instance, addr, entry->src_id, entry->ring_id, entry->vmid, 1662 entry->pasid); 1663 1664 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 1665 if (task_info) { 1666 dev_dbg_ratelimited(adev->dev, " for process %s pid %d thread %s pid %d\n", 1667 task_info->process_name, task_info->tgid, 1668 task_info->task_name, task_info->pid); 1669 amdgpu_vm_put_task_info(task_info); 1670 } 1671 1672 return 0; 1673 } 1674 1675 static int sdma_v4_4_2_process_vm_hole_irq(struct amdgpu_device *adev, 1676 struct amdgpu_irq_src *source, 1677 struct amdgpu_iv_entry *entry) 1678 { 1679 dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n"); 1680 sdma_v4_4_2_print_iv_entry(adev, entry); 1681 return 0; 1682 } 1683 1684 static int sdma_v4_4_2_process_doorbell_invalid_irq(struct amdgpu_device *adev, 1685 struct amdgpu_irq_src *source, 1686 struct amdgpu_iv_entry *entry) 1687 { 1688 1689 dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n"); 1690 sdma_v4_4_2_print_iv_entry(adev, entry); 1691 return 0; 1692 } 1693 1694 static int sdma_v4_4_2_process_pool_timeout_irq(struct amdgpu_device *adev, 1695 struct amdgpu_irq_src *source, 1696 struct amdgpu_iv_entry *entry) 1697 { 1698 dev_dbg_ratelimited(adev->dev, 1699 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n"); 1700 sdma_v4_4_2_print_iv_entry(adev, entry); 1701 return 0; 1702 } 1703 1704 static int sdma_v4_4_2_process_srbm_write_irq(struct amdgpu_device *adev, 1705 struct amdgpu_irq_src *source, 1706 struct amdgpu_iv_entry *entry) 1707 { 1708 dev_dbg_ratelimited(adev->dev, 1709 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n"); 1710 sdma_v4_4_2_print_iv_entry(adev, entry); 1711 return 0; 1712 } 1713 1714 static void sdma_v4_4_2_inst_update_medium_grain_light_sleep( 1715 struct amdgpu_device *adev, bool enable, uint32_t inst_mask) 1716 { 1717 uint32_t data, def; 1718 int i; 1719 1720 /* leave as default if it is not driver controlled */ 1721 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) 1722 return; 1723 1724 if (enable) { 1725 for_each_inst(i, inst_mask) { 1726 /* 1-not override: enable sdma mem light sleep */ 1727 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL); 1728 data |= SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1729 if (def != data) 1730 WREG32_SDMA(i, regSDMA_POWER_CNTL, data); 1731 } 1732 } else { 1733 for_each_inst(i, inst_mask) { 1734 /* 0-override:disable sdma mem light sleep */ 1735 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL); 1736 data &= ~SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1737 if (def != data) 1738 WREG32_SDMA(i, regSDMA_POWER_CNTL, data); 1739 } 1740 } 1741 } 1742 1743 static void sdma_v4_4_2_inst_update_medium_grain_clock_gating( 1744 struct amdgpu_device *adev, bool enable, uint32_t inst_mask) 1745 { 1746 uint32_t data, def; 1747 int i; 1748 1749 /* leave as default if it is not driver controlled */ 1750 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) 1751 return; 1752 1753 if (enable) { 1754 for_each_inst(i, inst_mask) { 1755 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL); 1756 data &= ~(SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1757 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1758 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1759 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1760 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1761 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1762 if (def != data) 1763 WREG32_SDMA(i, regSDMA_CLK_CTRL, data); 1764 } 1765 } else { 1766 for_each_inst(i, inst_mask) { 1767 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL); 1768 data |= (SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1769 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1770 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1771 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1772 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1773 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1774 if (def != data) 1775 WREG32_SDMA(i, regSDMA_CLK_CTRL, data); 1776 } 1777 } 1778 } 1779 1780 static int sdma_v4_4_2_set_clockgating_state(void *handle, 1781 enum amd_clockgating_state state) 1782 { 1783 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1784 uint32_t inst_mask; 1785 1786 if (amdgpu_sriov_vf(adev)) 1787 return 0; 1788 1789 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1790 1791 sdma_v4_4_2_inst_update_medium_grain_clock_gating( 1792 adev, state == AMD_CG_STATE_GATE, inst_mask); 1793 sdma_v4_4_2_inst_update_medium_grain_light_sleep( 1794 adev, state == AMD_CG_STATE_GATE, inst_mask); 1795 return 0; 1796 } 1797 1798 static int sdma_v4_4_2_set_powergating_state(void *handle, 1799 enum amd_powergating_state state) 1800 { 1801 return 0; 1802 } 1803 1804 static void sdma_v4_4_2_get_clockgating_state(void *handle, u64 *flags) 1805 { 1806 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1807 int data; 1808 1809 if (amdgpu_sriov_vf(adev)) 1810 *flags = 0; 1811 1812 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1813 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL)); 1814 if (!(data & SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK)) 1815 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1816 1817 /* AMD_CG_SUPPORT_SDMA_LS */ 1818 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL)); 1819 if (data & SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1820 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1821 } 1822 1823 const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = { 1824 .name = "sdma_v4_4_2", 1825 .early_init = sdma_v4_4_2_early_init, 1826 .late_init = sdma_v4_4_2_late_init, 1827 .sw_init = sdma_v4_4_2_sw_init, 1828 .sw_fini = sdma_v4_4_2_sw_fini, 1829 .hw_init = sdma_v4_4_2_hw_init, 1830 .hw_fini = sdma_v4_4_2_hw_fini, 1831 .suspend = sdma_v4_4_2_suspend, 1832 .resume = sdma_v4_4_2_resume, 1833 .is_idle = sdma_v4_4_2_is_idle, 1834 .wait_for_idle = sdma_v4_4_2_wait_for_idle, 1835 .soft_reset = sdma_v4_4_2_soft_reset, 1836 .set_clockgating_state = sdma_v4_4_2_set_clockgating_state, 1837 .set_powergating_state = sdma_v4_4_2_set_powergating_state, 1838 .get_clockgating_state = sdma_v4_4_2_get_clockgating_state, 1839 }; 1840 1841 static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = { 1842 .type = AMDGPU_RING_TYPE_SDMA, 1843 .align_mask = 0xff, 1844 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1845 .support_64bit_ptrs = true, 1846 .get_rptr = sdma_v4_4_2_ring_get_rptr, 1847 .get_wptr = sdma_v4_4_2_ring_get_wptr, 1848 .set_wptr = sdma_v4_4_2_ring_set_wptr, 1849 .emit_frame_size = 1850 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */ 1851 3 + /* hdp invalidate */ 1852 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */ 1853 /* sdma_v4_4_2_ring_emit_vm_flush */ 1854 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1855 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1856 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */ 1857 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */ 1858 .emit_ib = sdma_v4_4_2_ring_emit_ib, 1859 .emit_fence = sdma_v4_4_2_ring_emit_fence, 1860 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync, 1861 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush, 1862 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush, 1863 .test_ring = sdma_v4_4_2_ring_test_ring, 1864 .test_ib = sdma_v4_4_2_ring_test_ib, 1865 .insert_nop = sdma_v4_4_2_ring_insert_nop, 1866 .pad_ib = sdma_v4_4_2_ring_pad_ib, 1867 .emit_wreg = sdma_v4_4_2_ring_emit_wreg, 1868 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, 1869 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1870 }; 1871 1872 static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = { 1873 .type = AMDGPU_RING_TYPE_SDMA, 1874 .align_mask = 0xff, 1875 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1876 .support_64bit_ptrs = true, 1877 .get_rptr = sdma_v4_4_2_ring_get_rptr, 1878 .get_wptr = sdma_v4_4_2_page_ring_get_wptr, 1879 .set_wptr = sdma_v4_4_2_page_ring_set_wptr, 1880 .emit_frame_size = 1881 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */ 1882 3 + /* hdp invalidate */ 1883 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */ 1884 /* sdma_v4_4_2_ring_emit_vm_flush */ 1885 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1886 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1887 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */ 1888 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */ 1889 .emit_ib = sdma_v4_4_2_ring_emit_ib, 1890 .emit_fence = sdma_v4_4_2_ring_emit_fence, 1891 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync, 1892 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush, 1893 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush, 1894 .test_ring = sdma_v4_4_2_ring_test_ring, 1895 .test_ib = sdma_v4_4_2_ring_test_ib, 1896 .insert_nop = sdma_v4_4_2_ring_insert_nop, 1897 .pad_ib = sdma_v4_4_2_ring_pad_ib, 1898 .emit_wreg = sdma_v4_4_2_ring_emit_wreg, 1899 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, 1900 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1901 }; 1902 1903 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev) 1904 { 1905 int i, dev_inst; 1906 1907 for (i = 0; i < adev->sdma.num_instances; i++) { 1908 adev->sdma.instance[i].ring.funcs = &sdma_v4_4_2_ring_funcs; 1909 adev->sdma.instance[i].ring.me = i; 1910 if (adev->sdma.has_page_queue) { 1911 adev->sdma.instance[i].page.funcs = 1912 &sdma_v4_4_2_page_ring_funcs; 1913 adev->sdma.instance[i].page.me = i; 1914 } 1915 1916 dev_inst = GET_INST(SDMA0, i); 1917 /* AID to which SDMA belongs depends on physical instance */ 1918 adev->sdma.instance[i].aid_id = 1919 dev_inst / adev->sdma.num_inst_per_aid; 1920 } 1921 } 1922 1923 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_trap_irq_funcs = { 1924 .set = sdma_v4_4_2_set_trap_irq_state, 1925 .process = sdma_v4_4_2_process_trap_irq, 1926 }; 1927 1928 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_illegal_inst_irq_funcs = { 1929 .process = sdma_v4_4_2_process_illegal_inst_irq, 1930 }; 1931 1932 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ecc_irq_funcs = { 1933 .set = sdma_v4_4_2_set_ecc_irq_state, 1934 .process = amdgpu_sdma_process_ecc_irq, 1935 }; 1936 1937 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_vm_hole_irq_funcs = { 1938 .process = sdma_v4_4_2_process_vm_hole_irq, 1939 }; 1940 1941 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_doorbell_invalid_irq_funcs = { 1942 .process = sdma_v4_4_2_process_doorbell_invalid_irq, 1943 }; 1944 1945 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_pool_timeout_irq_funcs = { 1946 .process = sdma_v4_4_2_process_pool_timeout_irq, 1947 }; 1948 1949 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_srbm_write_irq_funcs = { 1950 .process = sdma_v4_4_2_process_srbm_write_irq, 1951 }; 1952 1953 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev) 1954 { 1955 adev->sdma.trap_irq.num_types = adev->sdma.num_instances; 1956 adev->sdma.ecc_irq.num_types = adev->sdma.num_instances; 1957 adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances; 1958 adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances; 1959 adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances; 1960 adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances; 1961 1962 adev->sdma.trap_irq.funcs = &sdma_v4_4_2_trap_irq_funcs; 1963 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_4_2_illegal_inst_irq_funcs; 1964 adev->sdma.ecc_irq.funcs = &sdma_v4_4_2_ecc_irq_funcs; 1965 adev->sdma.vm_hole_irq.funcs = &sdma_v4_4_2_vm_hole_irq_funcs; 1966 adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_4_2_doorbell_invalid_irq_funcs; 1967 adev->sdma.pool_timeout_irq.funcs = &sdma_v4_4_2_pool_timeout_irq_funcs; 1968 adev->sdma.srbm_write_irq.funcs = &sdma_v4_4_2_srbm_write_irq_funcs; 1969 } 1970 1971 /** 1972 * sdma_v4_4_2_emit_copy_buffer - copy buffer using the sDMA engine 1973 * 1974 * @ib: indirect buffer to copy to 1975 * @src_offset: src GPU address 1976 * @dst_offset: dst GPU address 1977 * @byte_count: number of bytes to xfer 1978 * @tmz: if a secure copy should be used 1979 * 1980 * Copy GPU buffers using the DMA engine. 1981 * Used by the amdgpu ttm implementation to move pages if 1982 * registered as the asic copy callback. 1983 */ 1984 static void sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib *ib, 1985 uint64_t src_offset, 1986 uint64_t dst_offset, 1987 uint32_t byte_count, 1988 bool tmz) 1989 { 1990 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1991 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1992 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 1993 ib->ptr[ib->length_dw++] = byte_count - 1; 1994 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1995 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1996 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1997 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1998 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1999 } 2000 2001 /** 2002 * sdma_v4_4_2_emit_fill_buffer - fill buffer using the sDMA engine 2003 * 2004 * @ib: indirect buffer to copy to 2005 * @src_data: value to write to buffer 2006 * @dst_offset: dst GPU address 2007 * @byte_count: number of bytes to xfer 2008 * 2009 * Fill GPU buffers using the DMA engine. 2010 */ 2011 static void sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib *ib, 2012 uint32_t src_data, 2013 uint64_t dst_offset, 2014 uint32_t byte_count) 2015 { 2016 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2017 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2018 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2019 ib->ptr[ib->length_dw++] = src_data; 2020 ib->ptr[ib->length_dw++] = byte_count - 1; 2021 } 2022 2023 static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = { 2024 .copy_max_bytes = 0x400000, 2025 .copy_num_dw = 7, 2026 .emit_copy_buffer = sdma_v4_4_2_emit_copy_buffer, 2027 2028 .fill_max_bytes = 0x400000, 2029 .fill_num_dw = 5, 2030 .emit_fill_buffer = sdma_v4_4_2_emit_fill_buffer, 2031 }; 2032 2033 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev) 2034 { 2035 adev->mman.buffer_funcs = &sdma_v4_4_2_buffer_funcs; 2036 if (adev->sdma.has_page_queue) 2037 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; 2038 else 2039 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2040 } 2041 2042 static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = { 2043 .copy_pte_num_dw = 7, 2044 .copy_pte = sdma_v4_4_2_vm_copy_pte, 2045 2046 .write_pte = sdma_v4_4_2_vm_write_pte, 2047 .set_pte_pde = sdma_v4_4_2_vm_set_pte_pde, 2048 }; 2049 2050 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev) 2051 { 2052 struct drm_gpu_scheduler *sched; 2053 unsigned i; 2054 2055 adev->vm_manager.vm_pte_funcs = &sdma_v4_4_2_vm_pte_funcs; 2056 for (i = 0; i < adev->sdma.num_instances; i++) { 2057 if (adev->sdma.has_page_queue) 2058 sched = &adev->sdma.instance[i].page.sched; 2059 else 2060 sched = &adev->sdma.instance[i].ring.sched; 2061 adev->vm_manager.vm_pte_scheds[i] = sched; 2062 } 2063 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 2064 } 2065 2066 const struct amdgpu_ip_block_version sdma_v4_4_2_ip_block = { 2067 .type = AMD_IP_BLOCK_TYPE_SDMA, 2068 .major = 4, 2069 .minor = 4, 2070 .rev = 2, 2071 .funcs = &sdma_v4_4_2_ip_funcs, 2072 }; 2073 2074 static int sdma_v4_4_2_xcp_resume(void *handle, uint32_t inst_mask) 2075 { 2076 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2077 int r; 2078 2079 if (!amdgpu_sriov_vf(adev)) 2080 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask); 2081 2082 r = sdma_v4_4_2_inst_start(adev, inst_mask); 2083 2084 return r; 2085 } 2086 2087 static int sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask) 2088 { 2089 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2090 uint32_t tmp_mask = inst_mask; 2091 int i; 2092 2093 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2094 for_each_inst(i, tmp_mask) { 2095 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 2096 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 2097 } 2098 } 2099 2100 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 2101 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 2102 2103 return 0; 2104 } 2105 2106 struct amdgpu_xcp_ip_funcs sdma_v4_4_2_xcp_funcs = { 2107 .suspend = &sdma_v4_4_2_xcp_suspend, 2108 .resume = &sdma_v4_4_2_xcp_resume 2109 }; 2110 2111 static const struct amdgpu_ras_err_status_reg_entry sdma_v4_2_2_ue_reg_list[] = { 2112 {AMDGPU_RAS_REG_ENTRY(SDMA0, 0, regSDMA_UE_ERR_STATUS_LO, regSDMA_UE_ERR_STATUS_HI), 2113 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SDMA"}, 2114 }; 2115 2116 static const struct amdgpu_ras_memory_id_entry sdma_v4_4_2_ras_memory_list[] = { 2117 {AMDGPU_SDMA_MBANK_DATA_BUF0, "SDMA_MBANK_DATA_BUF0"}, 2118 {AMDGPU_SDMA_MBANK_DATA_BUF1, "SDMA_MBANK_DATA_BUF1"}, 2119 {AMDGPU_SDMA_MBANK_DATA_BUF2, "SDMA_MBANK_DATA_BUF2"}, 2120 {AMDGPU_SDMA_MBANK_DATA_BUF3, "SDMA_MBANK_DATA_BUF3"}, 2121 {AMDGPU_SDMA_MBANK_DATA_BUF4, "SDMA_MBANK_DATA_BUF4"}, 2122 {AMDGPU_SDMA_MBANK_DATA_BUF5, "SDMA_MBANK_DATA_BUF5"}, 2123 {AMDGPU_SDMA_MBANK_DATA_BUF6, "SDMA_MBANK_DATA_BUF6"}, 2124 {AMDGPU_SDMA_MBANK_DATA_BUF7, "SDMA_MBANK_DATA_BUF7"}, 2125 {AMDGPU_SDMA_MBANK_DATA_BUF8, "SDMA_MBANK_DATA_BUF8"}, 2126 {AMDGPU_SDMA_MBANK_DATA_BUF9, "SDMA_MBANK_DATA_BUF9"}, 2127 {AMDGPU_SDMA_MBANK_DATA_BUF10, "SDMA_MBANK_DATA_BUF10"}, 2128 {AMDGPU_SDMA_MBANK_DATA_BUF11, "SDMA_MBANK_DATA_BUF11"}, 2129 {AMDGPU_SDMA_MBANK_DATA_BUF12, "SDMA_MBANK_DATA_BUF12"}, 2130 {AMDGPU_SDMA_MBANK_DATA_BUF13, "SDMA_MBANK_DATA_BUF13"}, 2131 {AMDGPU_SDMA_MBANK_DATA_BUF14, "SDMA_MBANK_DATA_BUF14"}, 2132 {AMDGPU_SDMA_MBANK_DATA_BUF15, "SDMA_MBANK_DATA_BUF15"}, 2133 {AMDGPU_SDMA_UCODE_BUF, "SDMA_UCODE_BUF"}, 2134 {AMDGPU_SDMA_RB_CMD_BUF, "SDMA_RB_CMD_BUF"}, 2135 {AMDGPU_SDMA_IB_CMD_BUF, "SDMA_IB_CMD_BUF"}, 2136 {AMDGPU_SDMA_UTCL1_RD_FIFO, "SDMA_UTCL1_RD_FIFO"}, 2137 {AMDGPU_SDMA_UTCL1_RDBST_FIFO, "SDMA_UTCL1_RDBST_FIFO"}, 2138 {AMDGPU_SDMA_UTCL1_WR_FIFO, "SDMA_UTCL1_WR_FIFO"}, 2139 {AMDGPU_SDMA_DATA_LUT_FIFO, "SDMA_DATA_LUT_FIFO"}, 2140 {AMDGPU_SDMA_SPLIT_DAT_BUF, "SDMA_SPLIT_DAT_BUF"}, 2141 }; 2142 2143 static void sdma_v4_4_2_inst_query_ras_error_count(struct amdgpu_device *adev, 2144 uint32_t sdma_inst, 2145 void *ras_err_status) 2146 { 2147 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 2148 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); 2149 unsigned long ue_count = 0; 2150 struct amdgpu_smuio_mcm_config_info mcm_info = { 2151 .socket_id = adev->smuio.funcs->get_socket_id(adev), 2152 .die_id = adev->sdma.instance[sdma_inst].aid_id, 2153 }; 2154 2155 /* sdma v4_4_2 doesn't support query ce counts */ 2156 amdgpu_ras_inst_query_ras_error_count(adev, 2157 sdma_v4_2_2_ue_reg_list, 2158 ARRAY_SIZE(sdma_v4_2_2_ue_reg_list), 2159 sdma_v4_4_2_ras_memory_list, 2160 ARRAY_SIZE(sdma_v4_4_2_ras_memory_list), 2161 sdma_dev_inst, 2162 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 2163 &ue_count); 2164 2165 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, NULL, ue_count); 2166 } 2167 2168 static void sdma_v4_4_2_query_ras_error_count(struct amdgpu_device *adev, 2169 void *ras_err_status) 2170 { 2171 uint32_t inst_mask; 2172 int i = 0; 2173 2174 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 2175 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2176 for_each_inst(i, inst_mask) 2177 sdma_v4_4_2_inst_query_ras_error_count(adev, i, ras_err_status); 2178 } else { 2179 dev_warn(adev->dev, "SDMA RAS is not supported\n"); 2180 } 2181 } 2182 2183 static void sdma_v4_4_2_inst_reset_ras_error_count(struct amdgpu_device *adev, 2184 uint32_t sdma_inst) 2185 { 2186 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); 2187 2188 amdgpu_ras_inst_reset_ras_error_count(adev, 2189 sdma_v4_2_2_ue_reg_list, 2190 ARRAY_SIZE(sdma_v4_2_2_ue_reg_list), 2191 sdma_dev_inst); 2192 } 2193 2194 static void sdma_v4_4_2_reset_ras_error_count(struct amdgpu_device *adev) 2195 { 2196 uint32_t inst_mask; 2197 int i = 0; 2198 2199 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 2200 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2201 for_each_inst(i, inst_mask) 2202 sdma_v4_4_2_inst_reset_ras_error_count(adev, i); 2203 } else { 2204 dev_warn(adev->dev, "SDMA RAS is not supported\n"); 2205 } 2206 } 2207 2208 static const struct amdgpu_ras_block_hw_ops sdma_v4_4_2_ras_hw_ops = { 2209 .query_ras_error_count = sdma_v4_4_2_query_ras_error_count, 2210 .reset_ras_error_count = sdma_v4_4_2_reset_ras_error_count, 2211 }; 2212 2213 static int sdma_v4_4_2_aca_bank_generate_report(struct aca_handle *handle, 2214 struct aca_bank *bank, enum aca_error_type type, 2215 struct aca_bank_report *report, void *data) 2216 { 2217 u64 status, misc0; 2218 int ret; 2219 2220 status = bank->regs[ACA_REG_IDX_STATUS]; 2221 if ((type == ACA_ERROR_TYPE_UE && 2222 ACA_REG__STATUS__ERRORCODEEXT(status) == ACA_EXTERROR_CODE_FAULT) || 2223 (type == ACA_ERROR_TYPE_CE && 2224 ACA_REG__STATUS__ERRORCODEEXT(status) == ACA_EXTERROR_CODE_CE)) { 2225 2226 ret = aca_bank_info_decode(bank, &report->info); 2227 if (ret) 2228 return ret; 2229 2230 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 2231 report->count[type] = ACA_REG__MISC0__ERRCNT(misc0); 2232 } 2233 2234 return 0; 2235 } 2236 2237 /* CODE_SDMA0 - CODE_SDMA4, reference to smu driver if header file */ 2238 static int sdma_v4_4_2_err_codes[] = { 33, 34, 35, 36 }; 2239 2240 static bool sdma_v4_4_2_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 2241 enum aca_error_type type, void *data) 2242 { 2243 u32 instlo; 2244 2245 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 2246 instlo &= GENMASK(31, 1); 2247 2248 if (instlo != mmSMNAID_AID0_MCA_SMU) 2249 return false; 2250 2251 if (aca_bank_check_error_codes(handle->adev, bank, 2252 sdma_v4_4_2_err_codes, 2253 ARRAY_SIZE(sdma_v4_4_2_err_codes))) 2254 return false; 2255 2256 return true; 2257 } 2258 2259 static const struct aca_bank_ops sdma_v4_4_2_aca_bank_ops = { 2260 .aca_bank_generate_report = sdma_v4_4_2_aca_bank_generate_report, 2261 .aca_bank_is_valid = sdma_v4_4_2_aca_bank_is_valid, 2262 }; 2263 2264 static const struct aca_info sdma_v4_4_2_aca_info = { 2265 .hwip = ACA_HWIP_TYPE_SMU, 2266 .mask = ACA_ERROR_UE_MASK, 2267 .bank_ops = &sdma_v4_4_2_aca_bank_ops, 2268 }; 2269 2270 static int sdma_v4_4_2_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 2271 { 2272 int r; 2273 2274 r = amdgpu_sdma_ras_late_init(adev, ras_block); 2275 if (r) 2276 return r; 2277 2278 return amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__SDMA, 2279 &sdma_v4_4_2_aca_info, NULL); 2280 } 2281 2282 static struct amdgpu_sdma_ras sdma_v4_4_2_ras = { 2283 .ras_block = { 2284 .hw_ops = &sdma_v4_4_2_ras_hw_ops, 2285 .ras_late_init = sdma_v4_4_2_ras_late_init, 2286 }, 2287 }; 2288 2289 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev) 2290 { 2291 adev->sdma.ras = &sdma_v4_4_2_ras; 2292 } 2293