1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_xcp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_trace.h" 33 #include "amdgpu_reset.h" 34 35 #include "sdma/sdma_4_4_2_offset.h" 36 #include "sdma/sdma_4_4_2_sh_mask.h" 37 38 #include "soc15_common.h" 39 #include "soc15.h" 40 #include "vega10_sdma_pkt_open.h" 41 42 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 43 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 44 45 #include "amdgpu_ras.h" 46 47 MODULE_FIRMWARE("amdgpu/sdma_4_4_2.bin"); 48 MODULE_FIRMWARE("amdgpu/sdma_4_4_4.bin"); 49 MODULE_FIRMWARE("amdgpu/sdma_4_4_5.bin"); 50 51 static const struct amdgpu_hwip_reg_entry sdma_reg_list_4_4_2[] = { 52 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS_REG), 53 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS1_REG), 54 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS2_REG), 55 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS3_REG), 56 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UCODE_CHECKSUM), 57 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH_HI), 58 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH), 59 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_STATUS), 60 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_STATUS), 61 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK0), 62 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK1), 63 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK0), 64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK1), 65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_CNTL), 66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR), 67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR_HI), 68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR), 69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR_HI), 70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_OFFSET), 71 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_LO), 72 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_HI), 73 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_CNTL), 74 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_RPTR), 75 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_SUB_REMAIN), 76 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_DUMMY_REG), 77 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_CNTL), 78 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR), 79 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR_HI), 80 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR), 81 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR_HI), 82 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_OFFSET), 83 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_LO), 84 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_HI), 85 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_DUMMY_REG), 86 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_CNTL), 87 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR), 88 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR_HI), 89 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR), 90 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR_HI), 91 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_OFFSET), 92 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_LO), 93 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_HI), 94 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_DUMMY_REG), 95 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_VM_CNTL) 96 }; 97 98 #define mmSMNAID_AID0_MCA_SMU 0x03b30400 99 100 #define WREG32_SDMA(instance, offset, value) \ 101 WREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)), value) 102 #define RREG32_SDMA(instance, offset) \ 103 RREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset))) 104 105 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev); 106 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev); 107 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev); 108 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev); 109 static void sdma_v4_4_2_update_reset_mask(struct amdgpu_device *adev); 110 static int sdma_v4_4_2_stop_queue(struct amdgpu_ring *ring); 111 static int sdma_v4_4_2_restore_queue(struct amdgpu_ring *ring); 112 static int sdma_v4_4_2_soft_reset_engine(struct amdgpu_device *adev, 113 u32 instance_id); 114 115 static u32 sdma_v4_4_2_get_reg_offset(struct amdgpu_device *adev, 116 u32 instance, u32 offset) 117 { 118 u32 dev_inst = GET_INST(SDMA0, instance); 119 120 return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset); 121 } 122 123 static unsigned sdma_v4_4_2_seq_to_irq_id(int seq_num) 124 { 125 switch (seq_num) { 126 case 0: 127 return SOC15_IH_CLIENTID_SDMA0; 128 case 1: 129 return SOC15_IH_CLIENTID_SDMA1; 130 case 2: 131 return SOC15_IH_CLIENTID_SDMA2; 132 case 3: 133 return SOC15_IH_CLIENTID_SDMA3; 134 default: 135 return -EINVAL; 136 } 137 } 138 139 static int sdma_v4_4_2_irq_id_to_seq(struct amdgpu_device *adev, unsigned client_id) 140 { 141 switch (client_id) { 142 case SOC15_IH_CLIENTID_SDMA0: 143 return 0; 144 case SOC15_IH_CLIENTID_SDMA1: 145 return 1; 146 case SOC15_IH_CLIENTID_SDMA2: 147 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) 148 return 0; 149 else 150 return 2; 151 case SOC15_IH_CLIENTID_SDMA3: 152 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) 153 return 1; 154 else 155 return 3; 156 default: 157 return -EINVAL; 158 } 159 } 160 161 static void sdma_v4_4_2_inst_init_golden_registers(struct amdgpu_device *adev, 162 uint32_t inst_mask) 163 { 164 u32 val; 165 int i; 166 167 for (i = 0; i < adev->sdma.num_instances; i++) { 168 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG); 169 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4); 170 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, 171 PIPE_INTERLEAVE_SIZE, 0); 172 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG, val); 173 174 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ); 175 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS, 176 4); 177 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, 178 PIPE_INTERLEAVE_SIZE, 0); 179 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ, val); 180 } 181 } 182 183 /** 184 * sdma_v4_4_2_init_microcode - load ucode images from disk 185 * 186 * @adev: amdgpu_device pointer 187 * 188 * Use the firmware interface to load the ucode images into 189 * the driver (not loaded into hw). 190 * Returns 0 on success, error on failure. 191 */ 192 static int sdma_v4_4_2_init_microcode(struct amdgpu_device *adev) 193 { 194 int ret, i; 195 196 for (i = 0; i < adev->sdma.num_instances; i++) { 197 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) || 198 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 4) || 199 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) { 200 ret = amdgpu_sdma_init_microcode(adev, 0, true); 201 break; 202 } else { 203 ret = amdgpu_sdma_init_microcode(adev, i, false); 204 if (ret) 205 return ret; 206 } 207 } 208 209 return ret; 210 } 211 212 /** 213 * sdma_v4_4_2_ring_get_rptr - get the current read pointer 214 * 215 * @ring: amdgpu ring pointer 216 * 217 * Get the current rptr from the hardware. 218 */ 219 static uint64_t sdma_v4_4_2_ring_get_rptr(struct amdgpu_ring *ring) 220 { 221 u64 rptr; 222 223 /* XXX check if swapping is necessary on BE */ 224 rptr = READ_ONCE(*((u64 *)&ring->adev->wb.wb[ring->rptr_offs])); 225 226 DRM_DEBUG("rptr before shift == 0x%016llx\n", rptr); 227 return rptr >> 2; 228 } 229 230 /** 231 * sdma_v4_4_2_ring_get_wptr - get the current write pointer 232 * 233 * @ring: amdgpu ring pointer 234 * 235 * Get the current wptr from the hardware. 236 */ 237 static uint64_t sdma_v4_4_2_ring_get_wptr(struct amdgpu_ring *ring) 238 { 239 struct amdgpu_device *adev = ring->adev; 240 u64 wptr; 241 242 if (ring->use_doorbell) { 243 /* XXX check if swapping is necessary on BE */ 244 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 245 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 246 } else { 247 wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI); 248 wptr = wptr << 32; 249 wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR); 250 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 251 ring->me, wptr); 252 } 253 254 return wptr >> 2; 255 } 256 257 /** 258 * sdma_v4_4_2_ring_set_wptr - commit the write pointer 259 * 260 * @ring: amdgpu ring pointer 261 * 262 * Write the wptr back to the hardware. 263 */ 264 static void sdma_v4_4_2_ring_set_wptr(struct amdgpu_ring *ring) 265 { 266 struct amdgpu_device *adev = ring->adev; 267 268 DRM_DEBUG("Setting write pointer\n"); 269 if (ring->use_doorbell) { 270 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 271 272 DRM_DEBUG("Using doorbell -- " 273 "wptr_offs == 0x%08x " 274 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 275 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 276 ring->wptr_offs, 277 lower_32_bits(ring->wptr << 2), 278 upper_32_bits(ring->wptr << 2)); 279 /* XXX check if swapping is necessary on BE */ 280 WRITE_ONCE(*wb, (ring->wptr << 2)); 281 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 282 ring->doorbell_index, ring->wptr << 2); 283 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 284 } else { 285 DRM_DEBUG("Not using doorbell -- " 286 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 287 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 288 ring->me, 289 lower_32_bits(ring->wptr << 2), 290 ring->me, 291 upper_32_bits(ring->wptr << 2)); 292 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR, 293 lower_32_bits(ring->wptr << 2)); 294 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI, 295 upper_32_bits(ring->wptr << 2)); 296 } 297 } 298 299 /** 300 * sdma_v4_4_2_page_ring_get_wptr - get the current write pointer 301 * 302 * @ring: amdgpu ring pointer 303 * 304 * Get the current wptr from the hardware. 305 */ 306 static uint64_t sdma_v4_4_2_page_ring_get_wptr(struct amdgpu_ring *ring) 307 { 308 struct amdgpu_device *adev = ring->adev; 309 u64 wptr; 310 311 if (ring->use_doorbell) { 312 /* XXX check if swapping is necessary on BE */ 313 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 314 } else { 315 wptr = RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI); 316 wptr = wptr << 32; 317 wptr |= RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR); 318 } 319 320 return wptr >> 2; 321 } 322 323 /** 324 * sdma_v4_4_2_page_ring_set_wptr - commit the write pointer 325 * 326 * @ring: amdgpu ring pointer 327 * 328 * Write the wptr back to the hardware. 329 */ 330 static void sdma_v4_4_2_page_ring_set_wptr(struct amdgpu_ring *ring) 331 { 332 struct amdgpu_device *adev = ring->adev; 333 334 if (ring->use_doorbell) { 335 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 336 337 /* XXX check if swapping is necessary on BE */ 338 WRITE_ONCE(*wb, (ring->wptr << 2)); 339 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 340 } else { 341 uint64_t wptr = ring->wptr << 2; 342 343 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR, 344 lower_32_bits(wptr)); 345 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI, 346 upper_32_bits(wptr)); 347 } 348 } 349 350 static void sdma_v4_4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 351 { 352 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 353 int i; 354 355 for (i = 0; i < count; i++) 356 if (sdma && sdma->burst_nop && (i == 0)) 357 amdgpu_ring_write(ring, ring->funcs->nop | 358 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 359 else 360 amdgpu_ring_write(ring, ring->funcs->nop); 361 } 362 363 /** 364 * sdma_v4_4_2_ring_emit_ib - Schedule an IB on the DMA engine 365 * 366 * @ring: amdgpu ring pointer 367 * @job: job to retrieve vmid from 368 * @ib: IB object to schedule 369 * @flags: unused 370 * 371 * Schedule an IB in the DMA ring. 372 */ 373 static void sdma_v4_4_2_ring_emit_ib(struct amdgpu_ring *ring, 374 struct amdgpu_job *job, 375 struct amdgpu_ib *ib, 376 uint32_t flags) 377 { 378 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 379 380 /* IB packet must end on a 8 DW boundary */ 381 sdma_v4_4_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 382 383 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 384 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 385 /* base must be 32 byte aligned */ 386 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 387 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 388 amdgpu_ring_write(ring, ib->length_dw); 389 amdgpu_ring_write(ring, 0); 390 amdgpu_ring_write(ring, 0); 391 392 } 393 394 static void sdma_v4_4_2_wait_reg_mem(struct amdgpu_ring *ring, 395 int mem_space, int hdp, 396 uint32_t addr0, uint32_t addr1, 397 uint32_t ref, uint32_t mask, 398 uint32_t inv) 399 { 400 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 401 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 402 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 403 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 404 if (mem_space) { 405 /* memory */ 406 amdgpu_ring_write(ring, addr0); 407 amdgpu_ring_write(ring, addr1); 408 } else { 409 /* registers */ 410 amdgpu_ring_write(ring, addr0 << 2); 411 amdgpu_ring_write(ring, addr1 << 2); 412 } 413 amdgpu_ring_write(ring, ref); /* reference */ 414 amdgpu_ring_write(ring, mask); /* mask */ 415 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 416 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 417 } 418 419 /** 420 * sdma_v4_4_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 421 * 422 * @ring: amdgpu ring pointer 423 * 424 * Emit an hdp flush packet on the requested DMA ring. 425 */ 426 static void sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 427 { 428 struct amdgpu_device *adev = ring->adev; 429 u32 ref_and_mask = 0; 430 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 431 432 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 433 << (ring->me % adev->sdma.num_inst_per_aid); 434 435 sdma_v4_4_2_wait_reg_mem(ring, 0, 1, 436 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 437 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 438 ref_and_mask, ref_and_mask, 10); 439 } 440 441 /** 442 * sdma_v4_4_2_ring_emit_fence - emit a fence on the DMA ring 443 * 444 * @ring: amdgpu ring pointer 445 * @addr: address 446 * @seq: sequence number 447 * @flags: fence related flags 448 * 449 * Add a DMA fence packet to the ring to write 450 * the fence seq number and DMA trap packet to generate 451 * an interrupt if needed. 452 */ 453 static void sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 454 unsigned flags) 455 { 456 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 457 /* write the fence */ 458 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 459 /* zero in first two bits */ 460 WARN_ON(addr & 0x3); 461 amdgpu_ring_write(ring, lower_32_bits(addr)); 462 amdgpu_ring_write(ring, upper_32_bits(addr)); 463 amdgpu_ring_write(ring, lower_32_bits(seq)); 464 465 /* optionally write high bits as well */ 466 if (write64bit) { 467 addr += 4; 468 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 469 /* zero in first two bits */ 470 WARN_ON(addr & 0x3); 471 amdgpu_ring_write(ring, lower_32_bits(addr)); 472 amdgpu_ring_write(ring, upper_32_bits(addr)); 473 amdgpu_ring_write(ring, upper_32_bits(seq)); 474 } 475 476 /* generate an interrupt */ 477 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 478 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 479 } 480 481 482 /** 483 * sdma_v4_4_2_inst_gfx_stop - stop the gfx async dma engines 484 * 485 * @adev: amdgpu_device pointer 486 * @inst_mask: mask of dma engine instances to be disabled 487 * 488 * Stop the gfx async dma ring buffers. 489 */ 490 static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev, 491 uint32_t inst_mask) 492 { 493 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 494 u32 doorbell_offset, doorbell; 495 u32 rb_cntl, ib_cntl, sdma_cntl; 496 int i; 497 498 for_each_inst(i, inst_mask) { 499 sdma[i] = &adev->sdma.instance[i].ring; 500 501 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); 502 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0); 503 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 504 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 505 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0); 506 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 507 sdma_cntl = RREG32_SDMA(i, regSDMA_CNTL); 508 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, UTC_L1_ENABLE, 0); 509 WREG32_SDMA(i, regSDMA_CNTL, sdma_cntl); 510 511 if (sdma[i]->use_doorbell) { 512 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL); 513 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET); 514 515 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 0); 516 doorbell_offset = REG_SET_FIELD(doorbell_offset, 517 SDMA_GFX_DOORBELL_OFFSET, 518 OFFSET, 0); 519 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell); 520 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset); 521 } 522 } 523 } 524 525 /** 526 * sdma_v4_4_2_inst_rlc_stop - stop the compute async dma engines 527 * 528 * @adev: amdgpu_device pointer 529 * @inst_mask: mask of dma engine instances to be disabled 530 * 531 * Stop the compute async dma queues. 532 */ 533 static void sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device *adev, 534 uint32_t inst_mask) 535 { 536 /* XXX todo */ 537 } 538 539 /** 540 * sdma_v4_4_2_inst_page_stop - stop the page async dma engines 541 * 542 * @adev: amdgpu_device pointer 543 * @inst_mask: mask of dma engine instances to be disabled 544 * 545 * Stop the page async dma ring buffers. 546 */ 547 static void sdma_v4_4_2_inst_page_stop(struct amdgpu_device *adev, 548 uint32_t inst_mask) 549 { 550 u32 rb_cntl, ib_cntl; 551 int i; 552 553 for_each_inst(i, inst_mask) { 554 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); 555 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, 556 RB_ENABLE, 0); 557 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 558 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); 559 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, 560 IB_ENABLE, 0); 561 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); 562 } 563 } 564 565 /** 566 * sdma_v4_4_2_inst_ctx_switch_enable - stop the async dma engines context switch 567 * 568 * @adev: amdgpu_device pointer 569 * @enable: enable/disable the DMA MEs context switch. 570 * @inst_mask: mask of dma engine instances to be enabled 571 * 572 * Halt or unhalt the async dma engines context switch. 573 */ 574 static void sdma_v4_4_2_inst_ctx_switch_enable(struct amdgpu_device *adev, 575 bool enable, uint32_t inst_mask) 576 { 577 u32 f32_cntl, phase_quantum = 0; 578 int i; 579 580 if (amdgpu_sdma_phase_quantum) { 581 unsigned value = amdgpu_sdma_phase_quantum; 582 unsigned unit = 0; 583 584 while (value > (SDMA_PHASE0_QUANTUM__VALUE_MASK >> 585 SDMA_PHASE0_QUANTUM__VALUE__SHIFT)) { 586 value = (value + 1) >> 1; 587 unit++; 588 } 589 if (unit > (SDMA_PHASE0_QUANTUM__UNIT_MASK >> 590 SDMA_PHASE0_QUANTUM__UNIT__SHIFT)) { 591 value = (SDMA_PHASE0_QUANTUM__VALUE_MASK >> 592 SDMA_PHASE0_QUANTUM__VALUE__SHIFT); 593 unit = (SDMA_PHASE0_QUANTUM__UNIT_MASK >> 594 SDMA_PHASE0_QUANTUM__UNIT__SHIFT); 595 WARN_ONCE(1, 596 "clamping sdma_phase_quantum to %uK clock cycles\n", 597 value << unit); 598 } 599 phase_quantum = 600 value << SDMA_PHASE0_QUANTUM__VALUE__SHIFT | 601 unit << SDMA_PHASE0_QUANTUM__UNIT__SHIFT; 602 } 603 604 for_each_inst(i, inst_mask) { 605 f32_cntl = RREG32_SDMA(i, regSDMA_CNTL); 606 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_CNTL, 607 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 608 if (enable && amdgpu_sdma_phase_quantum) { 609 WREG32_SDMA(i, regSDMA_PHASE0_QUANTUM, phase_quantum); 610 WREG32_SDMA(i, regSDMA_PHASE1_QUANTUM, phase_quantum); 611 WREG32_SDMA(i, regSDMA_PHASE2_QUANTUM, phase_quantum); 612 } 613 WREG32_SDMA(i, regSDMA_CNTL, f32_cntl); 614 615 /* Extend page fault timeout to avoid interrupt storm */ 616 WREG32_SDMA(i, regSDMA_UTCL1_TIMEOUT, 0x00800080); 617 } 618 } 619 620 /** 621 * sdma_v4_4_2_inst_enable - stop the async dma engines 622 * 623 * @adev: amdgpu_device pointer 624 * @enable: enable/disable the DMA MEs. 625 * @inst_mask: mask of dma engine instances to be enabled 626 * 627 * Halt or unhalt the async dma engines. 628 */ 629 static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable, 630 uint32_t inst_mask) 631 { 632 u32 f32_cntl; 633 int i; 634 635 if (!enable) { 636 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask); 637 sdma_v4_4_2_inst_rlc_stop(adev, inst_mask); 638 if (adev->sdma.has_page_queue) 639 sdma_v4_4_2_inst_page_stop(adev, inst_mask); 640 641 /* SDMA FW needs to respond to FREEZE requests during reset. 642 * Keep it running during reset */ 643 if (!amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 644 return; 645 } 646 647 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 648 return; 649 650 for_each_inst(i, inst_mask) { 651 f32_cntl = RREG32_SDMA(i, regSDMA_F32_CNTL); 652 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1); 653 WREG32_SDMA(i, regSDMA_F32_CNTL, f32_cntl); 654 } 655 } 656 657 /* 658 * sdma_v4_4_2_rb_cntl - get parameters for rb_cntl 659 */ 660 static uint32_t sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 661 { 662 /* Set ring buffer size in dwords */ 663 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 664 665 barrier(); /* work around https://llvm.org/pr42576 */ 666 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 667 #ifdef __BIG_ENDIAN 668 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 669 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, 670 RPTR_WRITEBACK_SWAP_ENABLE, 1); 671 #endif 672 return rb_cntl; 673 } 674 675 /** 676 * sdma_v4_4_2_gfx_resume - setup and start the async dma engines 677 * 678 * @adev: amdgpu_device pointer 679 * @i: instance to resume 680 * @restore: used to restore wptr when restart 681 * 682 * Set up the gfx DMA ring buffers and enable them. 683 * Returns 0 for success, error for failure. 684 */ 685 static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i, bool restore) 686 { 687 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 688 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 689 u32 wb_offset; 690 u32 doorbell; 691 u32 doorbell_offset; 692 u64 wptr_gpu_addr; 693 u64 rwptr; 694 695 wb_offset = (ring->rptr_offs * 4); 696 697 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); 698 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 699 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 700 701 /* set the wb address whether it's enabled or not */ 702 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_HI, 703 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 704 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_LO, 705 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 706 707 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, 708 RPTR_WRITEBACK_ENABLE, 1); 709 710 WREG32_SDMA(i, regSDMA_GFX_RB_BASE, ring->gpu_addr >> 8); 711 WREG32_SDMA(i, regSDMA_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 712 713 if (!restore) 714 ring->wptr = 0; 715 716 /* before programing wptr to a less value, need set minor_ptr_update first */ 717 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 1); 718 719 /* For the guilty queue, set RPTR to the current wptr to skip bad commands, 720 * It is not a guilty queue, restore cache_rptr and continue execution. 721 */ 722 if (adev->sdma.instance[i].gfx_guilty) 723 rwptr = ring->wptr; 724 else 725 rwptr = ring->cached_rptr; 726 727 /* Initialize the ring buffer's read and write pointers */ 728 if (restore) { 729 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, lower_32_bits(rwptr << 2)); 730 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, upper_32_bits(rwptr << 2)); 731 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, lower_32_bits(rwptr << 2)); 732 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, upper_32_bits(rwptr << 2)); 733 } else { 734 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0); 735 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0); 736 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0); 737 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0); 738 } 739 740 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL); 741 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET); 742 743 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 744 ring->use_doorbell); 745 doorbell_offset = REG_SET_FIELD(doorbell_offset, 746 SDMA_GFX_DOORBELL_OFFSET, 747 OFFSET, ring->doorbell_index); 748 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell); 749 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset); 750 751 sdma_v4_4_2_ring_set_wptr(ring); 752 753 /* set minor_ptr_update to 0 after wptr programed */ 754 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 0); 755 756 /* setup the wptr shadow polling */ 757 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 758 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_LO, 759 lower_32_bits(wptr_gpu_addr)); 760 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_HI, 761 upper_32_bits(wptr_gpu_addr)); 762 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL); 763 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 764 SDMA_GFX_RB_WPTR_POLL_CNTL, 765 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 766 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 767 768 /* enable DMA RB */ 769 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 1); 770 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 771 772 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 773 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 1); 774 #ifdef __BIG_ENDIAN 775 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 776 #endif 777 /* enable DMA IBs */ 778 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 779 } 780 781 /** 782 * sdma_v4_4_2_page_resume - setup and start the async dma engines 783 * 784 * @adev: amdgpu_device pointer 785 * @i: instance to resume 786 * @restore: boolean to say restore needed or not 787 * 788 * Set up the page DMA ring buffers and enable them. 789 * Returns 0 for success, error for failure. 790 */ 791 static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i, bool restore) 792 { 793 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 794 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 795 u32 wb_offset; 796 u32 doorbell; 797 u32 doorbell_offset; 798 u64 wptr_gpu_addr; 799 u64 rwptr; 800 801 wb_offset = (ring->rptr_offs * 4); 802 803 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); 804 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 805 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 806 807 /* For the guilty queue, set RPTR to the current wptr to skip bad commands, 808 * It is not a guilty queue, restore cache_rptr and continue execution. 809 */ 810 if (adev->sdma.instance[i].page_guilty) 811 rwptr = ring->wptr; 812 else 813 rwptr = ring->cached_rptr; 814 815 /* Initialize the ring buffer's read and write pointers */ 816 if (restore) { 817 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, lower_32_bits(rwptr << 2)); 818 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, upper_32_bits(rwptr << 2)); 819 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, lower_32_bits(rwptr << 2)); 820 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, upper_32_bits(rwptr << 2)); 821 } else { 822 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, 0); 823 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, 0); 824 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, 0); 825 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, 0); 826 } 827 828 /* set the wb address whether it's enabled or not */ 829 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_HI, 830 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 831 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_LO, 832 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 833 834 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, 835 RPTR_WRITEBACK_ENABLE, 1); 836 837 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE, ring->gpu_addr >> 8); 838 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 839 840 if (!restore) 841 ring->wptr = 0; 842 843 /* before programing wptr to a less value, need set minor_ptr_update first */ 844 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 1); 845 846 doorbell = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL); 847 doorbell_offset = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET); 848 849 doorbell = REG_SET_FIELD(doorbell, SDMA_PAGE_DOORBELL, ENABLE, 850 ring->use_doorbell); 851 doorbell_offset = REG_SET_FIELD(doorbell_offset, 852 SDMA_PAGE_DOORBELL_OFFSET, 853 OFFSET, ring->doorbell_index); 854 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL, doorbell); 855 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET, doorbell_offset); 856 857 /* paging queue doorbell range is setup at sdma_v4_4_2_gfx_resume */ 858 sdma_v4_4_2_page_ring_set_wptr(ring); 859 860 /* set minor_ptr_update to 0 after wptr programed */ 861 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 0); 862 863 /* setup the wptr shadow polling */ 864 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 865 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_LO, 866 lower_32_bits(wptr_gpu_addr)); 867 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_HI, 868 upper_32_bits(wptr_gpu_addr)); 869 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL); 870 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 871 SDMA_PAGE_RB_WPTR_POLL_CNTL, 872 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 873 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 874 875 /* enable DMA RB */ 876 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, RB_ENABLE, 1); 877 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 878 879 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); 880 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_ENABLE, 1); 881 #ifdef __BIG_ENDIAN 882 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 883 #endif 884 /* enable DMA IBs */ 885 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); 886 } 887 888 static void sdma_v4_4_2_init_pg(struct amdgpu_device *adev) 889 { 890 891 } 892 893 /** 894 * sdma_v4_4_2_inst_rlc_resume - setup and start the async dma engines 895 * 896 * @adev: amdgpu_device pointer 897 * @inst_mask: mask of dma engine instances to be enabled 898 * 899 * Set up the compute DMA queues and enable them. 900 * Returns 0 for success, error for failure. 901 */ 902 static int sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device *adev, 903 uint32_t inst_mask) 904 { 905 sdma_v4_4_2_init_pg(adev); 906 907 return 0; 908 } 909 910 /** 911 * sdma_v4_4_2_inst_load_microcode - load the sDMA ME ucode 912 * 913 * @adev: amdgpu_device pointer 914 * @inst_mask: mask of dma engine instances to be enabled 915 * 916 * Loads the sDMA0/1 ucode. 917 * Returns 0 for success, -EINVAL if the ucode is not available. 918 */ 919 static int sdma_v4_4_2_inst_load_microcode(struct amdgpu_device *adev, 920 uint32_t inst_mask) 921 { 922 const struct sdma_firmware_header_v1_0 *hdr; 923 const __le32 *fw_data; 924 u32 fw_size; 925 int i, j; 926 927 /* halt the MEs */ 928 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 929 930 for_each_inst(i, inst_mask) { 931 if (!adev->sdma.instance[i].fw) 932 return -EINVAL; 933 934 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 935 amdgpu_ucode_print_sdma_hdr(&hdr->header); 936 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 937 938 fw_data = (const __le32 *) 939 (adev->sdma.instance[i].fw->data + 940 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 941 942 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 0); 943 944 for (j = 0; j < fw_size; j++) 945 WREG32_SDMA(i, regSDMA_UCODE_DATA, 946 le32_to_cpup(fw_data++)); 947 948 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 949 adev->sdma.instance[i].fw_version); 950 } 951 952 return 0; 953 } 954 955 /** 956 * sdma_v4_4_2_inst_start - setup and start the async dma engines 957 * 958 * @adev: amdgpu_device pointer 959 * @inst_mask: mask of dma engine instances to be enabled 960 * @restore: boolean to say restore needed or not 961 * 962 * Set up the DMA engines and enable them. 963 * Returns 0 for success, error for failure. 964 */ 965 static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev, 966 uint32_t inst_mask, bool restore) 967 { 968 struct amdgpu_ring *ring; 969 uint32_t tmp_mask; 970 int i, r = 0; 971 972 if (amdgpu_sriov_vf(adev)) { 973 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 974 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 975 } else { 976 /* bypass sdma microcode loading on Gopher */ 977 if (!restore && adev->firmware.load_type != AMDGPU_FW_LOAD_PSP && 978 adev->sdma.instance[0].fw) { 979 r = sdma_v4_4_2_inst_load_microcode(adev, inst_mask); 980 if (r) 981 return r; 982 } 983 984 /* unhalt the MEs */ 985 sdma_v4_4_2_inst_enable(adev, true, inst_mask); 986 /* enable sdma ring preemption */ 987 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask); 988 } 989 990 /* start the gfx rings and rlc compute queues */ 991 tmp_mask = inst_mask; 992 for_each_inst(i, tmp_mask) { 993 uint32_t temp; 994 995 WREG32_SDMA(i, regSDMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); 996 sdma_v4_4_2_gfx_resume(adev, i, restore); 997 if (adev->sdma.has_page_queue) 998 sdma_v4_4_2_page_resume(adev, i, restore); 999 1000 /* set utc l1 enable flag always to 1 */ 1001 temp = RREG32_SDMA(i, regSDMA_CNTL); 1002 temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1); 1003 WREG32_SDMA(i, regSDMA_CNTL, temp); 1004 1005 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) < IP_VERSION(4, 4, 5)) { 1006 /* enable context empty interrupt during initialization */ 1007 temp = REG_SET_FIELD(temp, SDMA_CNTL, CTXEMPTY_INT_ENABLE, 1); 1008 WREG32_SDMA(i, regSDMA_CNTL, temp); 1009 } 1010 if (!amdgpu_sriov_vf(adev)) { 1011 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1012 /* unhalt engine */ 1013 temp = RREG32_SDMA(i, regSDMA_F32_CNTL); 1014 temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0); 1015 WREG32_SDMA(i, regSDMA_F32_CNTL, temp); 1016 } 1017 } 1018 } 1019 1020 if (amdgpu_sriov_vf(adev)) { 1021 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask); 1022 sdma_v4_4_2_inst_enable(adev, true, inst_mask); 1023 } else { 1024 r = sdma_v4_4_2_inst_rlc_resume(adev, inst_mask); 1025 if (r) 1026 return r; 1027 } 1028 1029 tmp_mask = inst_mask; 1030 for_each_inst(i, tmp_mask) { 1031 ring = &adev->sdma.instance[i].ring; 1032 1033 r = amdgpu_ring_test_helper(ring); 1034 if (r) 1035 return r; 1036 1037 if (adev->sdma.has_page_queue) { 1038 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 1039 1040 r = amdgpu_ring_test_helper(page); 1041 if (r) 1042 return r; 1043 } 1044 } 1045 1046 return r; 1047 } 1048 1049 /** 1050 * sdma_v4_4_2_ring_test_ring - simple async dma engine test 1051 * 1052 * @ring: amdgpu_ring structure holding ring information 1053 * 1054 * Test the DMA engine by writing using it to write an 1055 * value to memory. 1056 * Returns 0 for success, error for failure. 1057 */ 1058 static int sdma_v4_4_2_ring_test_ring(struct amdgpu_ring *ring) 1059 { 1060 struct amdgpu_device *adev = ring->adev; 1061 unsigned i; 1062 unsigned index; 1063 int r; 1064 u32 tmp; 1065 u64 gpu_addr; 1066 1067 r = amdgpu_device_wb_get(adev, &index); 1068 if (r) 1069 return r; 1070 1071 gpu_addr = adev->wb.gpu_addr + (index * 4); 1072 tmp = 0xCAFEDEAD; 1073 adev->wb.wb[index] = cpu_to_le32(tmp); 1074 1075 r = amdgpu_ring_alloc(ring, 5); 1076 if (r) 1077 goto error_free_wb; 1078 1079 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1080 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1081 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1082 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1083 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1084 amdgpu_ring_write(ring, 0xDEADBEEF); 1085 amdgpu_ring_commit(ring); 1086 1087 for (i = 0; i < adev->usec_timeout; i++) { 1088 tmp = le32_to_cpu(adev->wb.wb[index]); 1089 if (tmp == 0xDEADBEEF) 1090 break; 1091 udelay(1); 1092 } 1093 1094 if (i >= adev->usec_timeout) 1095 r = -ETIMEDOUT; 1096 1097 error_free_wb: 1098 amdgpu_device_wb_free(adev, index); 1099 return r; 1100 } 1101 1102 /** 1103 * sdma_v4_4_2_ring_test_ib - test an IB on the DMA engine 1104 * 1105 * @ring: amdgpu_ring structure holding ring information 1106 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1107 * 1108 * Test a simple IB in the DMA ring. 1109 * Returns 0 on success, error on failure. 1110 */ 1111 static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1112 { 1113 struct amdgpu_device *adev = ring->adev; 1114 struct amdgpu_ib ib; 1115 struct dma_fence *f = NULL; 1116 unsigned index; 1117 long r; 1118 u32 tmp = 0; 1119 u64 gpu_addr; 1120 1121 r = amdgpu_device_wb_get(adev, &index); 1122 if (r) 1123 return r; 1124 1125 gpu_addr = adev->wb.gpu_addr + (index * 4); 1126 tmp = 0xCAFEDEAD; 1127 adev->wb.wb[index] = cpu_to_le32(tmp); 1128 memset(&ib, 0, sizeof(ib)); 1129 r = amdgpu_ib_get(adev, NULL, 256, 1130 AMDGPU_IB_POOL_DIRECT, &ib); 1131 if (r) 1132 goto err0; 1133 1134 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1135 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1136 ib.ptr[1] = lower_32_bits(gpu_addr); 1137 ib.ptr[2] = upper_32_bits(gpu_addr); 1138 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1139 ib.ptr[4] = 0xDEADBEEF; 1140 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1141 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1142 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1143 ib.length_dw = 8; 1144 1145 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1146 if (r) 1147 goto err1; 1148 1149 r = dma_fence_wait_timeout(f, false, timeout); 1150 if (r == 0) { 1151 r = -ETIMEDOUT; 1152 goto err1; 1153 } else if (r < 0) { 1154 goto err1; 1155 } 1156 tmp = le32_to_cpu(adev->wb.wb[index]); 1157 if (tmp == 0xDEADBEEF) 1158 r = 0; 1159 else 1160 r = -EINVAL; 1161 1162 err1: 1163 amdgpu_ib_free(&ib, NULL); 1164 dma_fence_put(f); 1165 err0: 1166 amdgpu_device_wb_free(adev, index); 1167 return r; 1168 } 1169 1170 1171 /** 1172 * sdma_v4_4_2_vm_copy_pte - update PTEs by copying them from the GART 1173 * 1174 * @ib: indirect buffer to fill with commands 1175 * @pe: addr of the page entry 1176 * @src: src addr to copy from 1177 * @count: number of page entries to update 1178 * 1179 * Update PTEs by copying them from the GART using sDMA. 1180 */ 1181 static void sdma_v4_4_2_vm_copy_pte(struct amdgpu_ib *ib, 1182 uint64_t pe, uint64_t src, 1183 unsigned count) 1184 { 1185 unsigned bytes = count * 8; 1186 1187 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1188 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1189 ib->ptr[ib->length_dw++] = bytes - 1; 1190 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1191 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1192 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1193 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1194 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1195 1196 } 1197 1198 /** 1199 * sdma_v4_4_2_vm_write_pte - update PTEs by writing them manually 1200 * 1201 * @ib: indirect buffer to fill with commands 1202 * @pe: addr of the page entry 1203 * @value: dst addr to write into pe 1204 * @count: number of page entries to update 1205 * @incr: increase next addr by incr bytes 1206 * 1207 * Update PTEs by writing them manually using sDMA. 1208 */ 1209 static void sdma_v4_4_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1210 uint64_t value, unsigned count, 1211 uint32_t incr) 1212 { 1213 unsigned ndw = count * 2; 1214 1215 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1216 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1217 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1218 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1219 ib->ptr[ib->length_dw++] = ndw - 1; 1220 for (; ndw > 0; ndw -= 2) { 1221 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1222 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1223 value += incr; 1224 } 1225 } 1226 1227 /** 1228 * sdma_v4_4_2_vm_set_pte_pde - update the page tables using sDMA 1229 * 1230 * @ib: indirect buffer to fill with commands 1231 * @pe: addr of the page entry 1232 * @addr: dst addr to write into pe 1233 * @count: number of page entries to update 1234 * @incr: increase next addr by incr bytes 1235 * @flags: access flags 1236 * 1237 * Update the page tables using sDMA. 1238 */ 1239 static void sdma_v4_4_2_vm_set_pte_pde(struct amdgpu_ib *ib, 1240 uint64_t pe, 1241 uint64_t addr, unsigned count, 1242 uint32_t incr, uint64_t flags) 1243 { 1244 /* for physically contiguous pages (vram) */ 1245 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1246 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1247 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1248 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1249 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1250 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1251 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1252 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1253 ib->ptr[ib->length_dw++] = 0; 1254 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1255 } 1256 1257 /** 1258 * sdma_v4_4_2_ring_pad_ib - pad the IB to the required number of dw 1259 * 1260 * @ring: amdgpu_ring structure holding ring information 1261 * @ib: indirect buffer to fill with padding 1262 */ 1263 static void sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1264 { 1265 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1266 u32 pad_count; 1267 int i; 1268 1269 pad_count = (-ib->length_dw) & 7; 1270 for (i = 0; i < pad_count; i++) 1271 if (sdma && sdma->burst_nop && (i == 0)) 1272 ib->ptr[ib->length_dw++] = 1273 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1274 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1275 else 1276 ib->ptr[ib->length_dw++] = 1277 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1278 } 1279 1280 1281 /** 1282 * sdma_v4_4_2_ring_emit_pipeline_sync - sync the pipeline 1283 * 1284 * @ring: amdgpu_ring pointer 1285 * 1286 * Make sure all previous operations are completed (CIK). 1287 */ 1288 static void sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1289 { 1290 uint32_t seq = ring->fence_drv.sync_seq; 1291 uint64_t addr = ring->fence_drv.gpu_addr; 1292 1293 /* wait for idle */ 1294 sdma_v4_4_2_wait_reg_mem(ring, 1, 0, 1295 addr & 0xfffffffc, 1296 upper_32_bits(addr) & 0xffffffff, 1297 seq, 0xffffffff, 4); 1298 } 1299 1300 1301 /** 1302 * sdma_v4_4_2_ring_emit_vm_flush - vm flush using sDMA 1303 * 1304 * @ring: amdgpu_ring pointer 1305 * @vmid: vmid number to use 1306 * @pd_addr: address 1307 * 1308 * Update the page table base and flush the VM TLB 1309 * using sDMA. 1310 */ 1311 static void sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring *ring, 1312 unsigned vmid, uint64_t pd_addr) 1313 { 1314 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1315 } 1316 1317 static void sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring *ring, 1318 uint32_t reg, uint32_t val) 1319 { 1320 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1321 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1322 amdgpu_ring_write(ring, reg); 1323 amdgpu_ring_write(ring, val); 1324 } 1325 1326 static void sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1327 uint32_t val, uint32_t mask) 1328 { 1329 sdma_v4_4_2_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1330 } 1331 1332 static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev) 1333 { 1334 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1335 case IP_VERSION(4, 4, 2): 1336 case IP_VERSION(4, 4, 5): 1337 return false; 1338 default: 1339 return false; 1340 } 1341 } 1342 1343 static const struct amdgpu_sdma_funcs sdma_v4_4_2_sdma_funcs = { 1344 .stop_kernel_queue = &sdma_v4_4_2_stop_queue, 1345 .start_kernel_queue = &sdma_v4_4_2_restore_queue, 1346 .soft_reset_kernel_queue = &sdma_v4_4_2_soft_reset_engine, 1347 }; 1348 1349 static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = { 1350 .copy_pte_num_dw = 7, 1351 .copy_pte = sdma_v4_4_2_vm_copy_pte, 1352 1353 .write_pte = sdma_v4_4_2_vm_write_pte, 1354 .set_pte_pde = sdma_v4_4_2_vm_set_pte_pde, 1355 }; 1356 1357 static int sdma_v4_4_2_early_init(struct amdgpu_ip_block *ip_block) 1358 { 1359 struct amdgpu_device *adev = ip_block->adev; 1360 int r; 1361 1362 switch (amdgpu_user_queue) { 1363 case -1: 1364 case 0: 1365 default: 1366 adev->sdma.no_user_submission = false; 1367 adev->sdma.disable_uq = true; 1368 break; 1369 case 2: 1370 adev->sdma.no_user_submission = true; 1371 adev->sdma.disable_uq = true; 1372 break; 1373 } 1374 1375 r = sdma_v4_4_2_init_microcode(adev); 1376 if (r) 1377 return r; 1378 1379 /* TODO: Page queue breaks driver reload under SRIOV */ 1380 if (sdma_v4_4_2_fw_support_paging_queue(adev)) 1381 adev->sdma.has_page_queue = true; 1382 1383 sdma_v4_4_2_set_ring_funcs(adev); 1384 amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v4_4_2_vm_pte_funcs); 1385 sdma_v4_4_2_set_irq_funcs(adev); 1386 sdma_v4_4_2_set_ras_funcs(adev); 1387 return 0; 1388 } 1389 1390 #if 0 1391 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, 1392 void *err_data, 1393 struct amdgpu_iv_entry *entry); 1394 #endif 1395 1396 static int sdma_v4_4_2_late_init(struct amdgpu_ip_block *ip_block) 1397 { 1398 struct amdgpu_device *adev = ip_block->adev; 1399 #if 0 1400 struct ras_ih_if ih_info = { 1401 .cb = sdma_v4_4_2_process_ras_data_cb, 1402 }; 1403 #endif 1404 if (!amdgpu_persistent_edc_harvesting_supported(adev)) 1405 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__SDMA); 1406 1407 /* The initialization is done in the late_init stage to ensure that the SMU 1408 * initialization and capability setup are completed before we check the SDMA 1409 * reset capability 1410 */ 1411 sdma_v4_4_2_update_reset_mask(adev); 1412 1413 return 0; 1414 } 1415 1416 static int sdma_v4_4_2_sw_init(struct amdgpu_ip_block *ip_block) 1417 { 1418 struct amdgpu_ring *ring; 1419 int r, i; 1420 struct amdgpu_device *adev = ip_block->adev; 1421 u32 aid_id; 1422 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); 1423 uint32_t *ptr; 1424 1425 /* SDMA trap event */ 1426 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1427 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1428 SDMA0_4_0__SRCID__SDMA_TRAP, 1429 &adev->sdma.trap_irq); 1430 if (r) 1431 return r; 1432 } 1433 1434 /* SDMA SRAM ECC event */ 1435 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1436 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1437 SDMA0_4_0__SRCID__SDMA_SRAM_ECC, 1438 &adev->sdma.ecc_irq); 1439 if (r) 1440 return r; 1441 } 1442 1443 /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/ 1444 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1445 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1446 SDMA0_4_0__SRCID__SDMA_VM_HOLE, 1447 &adev->sdma.vm_hole_irq); 1448 if (r) 1449 return r; 1450 1451 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1452 SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID, 1453 &adev->sdma.doorbell_invalid_irq); 1454 if (r) 1455 return r; 1456 1457 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1458 SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT, 1459 &adev->sdma.pool_timeout_irq); 1460 if (r) 1461 return r; 1462 1463 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1464 SDMA0_4_0__SRCID__SDMA_SRBMWRITE, 1465 &adev->sdma.srbm_write_irq); 1466 if (r) 1467 return r; 1468 1469 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1470 SDMA0_4_0__SRCID__SDMA_CTXEMPTY, 1471 &adev->sdma.ctxt_empty_irq); 1472 if (r) 1473 return r; 1474 } 1475 1476 for (i = 0; i < adev->sdma.num_instances; i++) { 1477 mutex_init(&adev->sdma.instance[i].engine_reset_mutex); 1478 /* Initialize guilty flags for GFX and PAGE queues */ 1479 adev->sdma.instance[i].gfx_guilty = false; 1480 adev->sdma.instance[i].page_guilty = false; 1481 adev->sdma.instance[i].funcs = &sdma_v4_4_2_sdma_funcs; 1482 1483 ring = &adev->sdma.instance[i].ring; 1484 ring->ring_obj = NULL; 1485 ring->use_doorbell = true; 1486 aid_id = adev->sdma.instance[i].aid_id; 1487 1488 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1489 ring->use_doorbell?"true":"false"); 1490 1491 /* doorbell size is 2 dwords, get DWORD offset */ 1492 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1493 ring->vm_hub = AMDGPU_MMHUB0(aid_id); 1494 ring->no_user_submission = adev->sdma.no_user_submission; 1495 1496 sprintf(ring->name, "sdma%d.%d", aid_id, 1497 i % adev->sdma.num_inst_per_aid); 1498 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1499 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1500 AMDGPU_RING_PRIO_DEFAULT, NULL); 1501 if (r) 1502 return r; 1503 1504 if (adev->sdma.has_page_queue) { 1505 ring = &adev->sdma.instance[i].page; 1506 ring->ring_obj = NULL; 1507 ring->use_doorbell = true; 1508 1509 /* doorbell index of page queue is assigned right after 1510 * gfx queue on the same instance 1511 */ 1512 ring->doorbell_index = 1513 (adev->doorbell_index.sdma_engine[i] + 1) << 1; 1514 ring->vm_hub = AMDGPU_MMHUB0(aid_id); 1515 1516 sprintf(ring->name, "page%d.%d", aid_id, 1517 i % adev->sdma.num_inst_per_aid); 1518 r = amdgpu_ring_init(adev, ring, 1024, 1519 &adev->sdma.trap_irq, 1520 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1521 AMDGPU_RING_PRIO_DEFAULT, NULL); 1522 if (r) 1523 return r; 1524 } 1525 } 1526 1527 adev->sdma.supported_reset = 1528 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); 1529 1530 if (amdgpu_sdma_ras_sw_init(adev)) { 1531 dev_err(adev->dev, "fail to initialize sdma ras block\n"); 1532 return -EINVAL; 1533 } 1534 1535 /* Allocate memory for SDMA IP Dump buffer */ 1536 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); 1537 if (ptr) 1538 adev->sdma.ip_dump = ptr; 1539 else 1540 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n"); 1541 1542 r = amdgpu_sdma_sysfs_reset_mask_init(adev); 1543 if (r) 1544 return r; 1545 1546 return r; 1547 } 1548 1549 static int sdma_v4_4_2_sw_fini(struct amdgpu_ip_block *ip_block) 1550 { 1551 struct amdgpu_device *adev = ip_block->adev; 1552 int i; 1553 1554 for (i = 0; i < adev->sdma.num_instances; i++) { 1555 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1556 if (adev->sdma.has_page_queue) 1557 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1558 } 1559 1560 amdgpu_sdma_sysfs_reset_mask_fini(adev); 1561 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) || 1562 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 4) || 1563 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) 1564 amdgpu_sdma_destroy_inst_ctx(adev, true); 1565 else 1566 amdgpu_sdma_destroy_inst_ctx(adev, false); 1567 1568 kfree(adev->sdma.ip_dump); 1569 1570 return 0; 1571 } 1572 1573 static int sdma_v4_4_2_hw_init(struct amdgpu_ip_block *ip_block) 1574 { 1575 int r; 1576 struct amdgpu_device *adev = ip_block->adev; 1577 uint32_t inst_mask; 1578 1579 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1580 if (!amdgpu_sriov_vf(adev)) 1581 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask); 1582 1583 r = sdma_v4_4_2_inst_start(adev, inst_mask, false); 1584 if (r) 1585 return r; 1586 sdma_v4_4_2_set_buffer_funcs(adev); 1587 1588 return 0; 1589 } 1590 1591 static int sdma_v4_4_2_hw_fini(struct amdgpu_ip_block *ip_block) 1592 { 1593 struct amdgpu_device *adev = ip_block->adev; 1594 uint32_t inst_mask; 1595 int i; 1596 1597 if (amdgpu_sriov_vf(adev)) 1598 return 0; 1599 1600 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1601 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 1602 for (i = 0; i < adev->sdma.num_instances; i++) { 1603 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 1604 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1605 } 1606 } 1607 1608 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 1609 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 1610 1611 return 0; 1612 } 1613 1614 static int sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1615 enum amd_clockgating_state state); 1616 1617 static int sdma_v4_4_2_suspend(struct amdgpu_ip_block *ip_block) 1618 { 1619 struct amdgpu_device *adev = ip_block->adev; 1620 1621 if (amdgpu_in_reset(adev)) 1622 sdma_v4_4_2_set_clockgating_state(ip_block, AMD_CG_STATE_UNGATE); 1623 1624 return sdma_v4_4_2_hw_fini(ip_block); 1625 } 1626 1627 static int sdma_v4_4_2_resume(struct amdgpu_ip_block *ip_block) 1628 { 1629 return sdma_v4_4_2_hw_init(ip_block); 1630 } 1631 1632 static bool sdma_v4_4_2_is_idle(struct amdgpu_ip_block *ip_block) 1633 { 1634 struct amdgpu_device *adev = ip_block->adev; 1635 u32 i; 1636 1637 for (i = 0; i < adev->sdma.num_instances; i++) { 1638 u32 tmp = RREG32_SDMA(i, regSDMA_STATUS_REG); 1639 1640 if (!(tmp & SDMA_STATUS_REG__IDLE_MASK)) 1641 return false; 1642 } 1643 1644 return true; 1645 } 1646 1647 static int sdma_v4_4_2_wait_for_idle(struct amdgpu_ip_block *ip_block) 1648 { 1649 unsigned i, j; 1650 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; 1651 struct amdgpu_device *adev = ip_block->adev; 1652 1653 for (i = 0; i < adev->usec_timeout; i++) { 1654 for (j = 0; j < adev->sdma.num_instances; j++) { 1655 sdma[j] = RREG32_SDMA(j, regSDMA_STATUS_REG); 1656 if (!(sdma[j] & SDMA_STATUS_REG__IDLE_MASK)) 1657 break; 1658 } 1659 if (j == adev->sdma.num_instances) 1660 return 0; 1661 udelay(1); 1662 } 1663 return -ETIMEDOUT; 1664 } 1665 1666 static int sdma_v4_4_2_soft_reset(struct amdgpu_ip_block *ip_block) 1667 { 1668 /* todo */ 1669 1670 return 0; 1671 } 1672 1673 static bool sdma_v4_4_2_is_queue_selected(struct amdgpu_device *adev, uint32_t instance_id, bool is_page_queue) 1674 { 1675 uint32_t reg_offset = is_page_queue ? regSDMA_PAGE_CONTEXT_STATUS : regSDMA_GFX_CONTEXT_STATUS; 1676 uint32_t context_status = RREG32(sdma_v4_4_2_get_reg_offset(adev, instance_id, reg_offset)); 1677 1678 /* Check if the SELECTED bit is set */ 1679 return (context_status & SDMA_GFX_CONTEXT_STATUS__SELECTED_MASK) != 0; 1680 } 1681 1682 static int sdma_v4_4_2_reset_queue(struct amdgpu_ring *ring, 1683 unsigned int vmid, 1684 struct amdgpu_fence *timedout_fence) 1685 { 1686 struct amdgpu_device *adev = ring->adev; 1687 u32 id = ring->me; 1688 int r; 1689 1690 amdgpu_amdkfd_suspend(adev, true); 1691 r = amdgpu_sdma_reset_engine(adev, id, false); 1692 amdgpu_amdkfd_resume(adev, true); 1693 return r; 1694 } 1695 1696 static int sdma_v4_4_2_stop_queue(struct amdgpu_ring *ring) 1697 { 1698 struct amdgpu_device *adev = ring->adev; 1699 u32 instance_id = ring->me; 1700 u32 inst_mask; 1701 uint64_t rptr; 1702 1703 if (amdgpu_sriov_vf(adev)) 1704 return -EINVAL; 1705 1706 /* Check if this queue is the guilty one */ 1707 adev->sdma.instance[instance_id].gfx_guilty = 1708 sdma_v4_4_2_is_queue_selected(adev, instance_id, false); 1709 if (adev->sdma.has_page_queue) 1710 adev->sdma.instance[instance_id].page_guilty = 1711 sdma_v4_4_2_is_queue_selected(adev, instance_id, true); 1712 1713 /* Cache the rptr before reset, after the reset, 1714 * all of the registers will be reset to 0 1715 */ 1716 rptr = amdgpu_ring_get_rptr(ring); 1717 ring->cached_rptr = rptr; 1718 /* Cache the rptr for the page queue if it exists */ 1719 if (adev->sdma.has_page_queue) { 1720 struct amdgpu_ring *page_ring = &adev->sdma.instance[instance_id].page; 1721 rptr = amdgpu_ring_get_rptr(page_ring); 1722 page_ring->cached_rptr = rptr; 1723 } 1724 1725 /* stop queue */ 1726 inst_mask = 1 << ring->me; 1727 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask); 1728 if (adev->sdma.has_page_queue) 1729 sdma_v4_4_2_inst_page_stop(adev, inst_mask); 1730 1731 return 0; 1732 } 1733 1734 static int sdma_v4_4_2_restore_queue(struct amdgpu_ring *ring) 1735 { 1736 struct amdgpu_device *adev = ring->adev; 1737 u32 inst_mask; 1738 int i, r; 1739 1740 inst_mask = 1 << ring->me; 1741 udelay(50); 1742 1743 for (i = 0; i < adev->usec_timeout; i++) { 1744 if (!REG_GET_FIELD(RREG32_SDMA(ring->me, regSDMA_F32_CNTL), SDMA_F32_CNTL, HALT)) 1745 break; 1746 udelay(1); 1747 } 1748 1749 if (i == adev->usec_timeout) { 1750 dev_err(adev->dev, "timed out waiting for SDMA%d unhalt after reset\n", 1751 ring->me); 1752 return -ETIMEDOUT; 1753 } 1754 1755 r = sdma_v4_4_2_inst_start(adev, inst_mask, true); 1756 1757 return r; 1758 } 1759 1760 static int sdma_v4_4_2_soft_reset_engine(struct amdgpu_device *adev, 1761 u32 instance_id) 1762 { 1763 /* For SDMA 4.x, use the existing DPM interface for backward compatibility 1764 * we need to convert the logical instance ID to physical instance ID before reset. 1765 */ 1766 return amdgpu_dpm_reset_sdma(adev, 1 << GET_INST(SDMA0, instance_id)); 1767 } 1768 1769 static int sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device *adev, 1770 struct amdgpu_irq_src *source, 1771 unsigned type, 1772 enum amdgpu_interrupt_state state) 1773 { 1774 u32 sdma_cntl; 1775 1776 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); 1777 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE, 1778 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1779 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); 1780 1781 return 0; 1782 } 1783 1784 static int sdma_v4_4_2_process_trap_irq(struct amdgpu_device *adev, 1785 struct amdgpu_irq_src *source, 1786 struct amdgpu_iv_entry *entry) 1787 { 1788 uint32_t instance, i; 1789 1790 DRM_DEBUG("IH: SDMA trap\n"); 1791 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1792 1793 /* Client id gives the SDMA instance in AID. To know the exact SDMA 1794 * instance, interrupt entry gives the node id which corresponds to the AID instance. 1795 * Match node id with the AID id associated with the SDMA instance. */ 1796 for (i = instance; i < adev->sdma.num_instances; 1797 i += adev->sdma.num_inst_per_aid) { 1798 if (adev->sdma.instance[i].aid_id == 1799 node_id_to_phys_map[entry->node_id]) 1800 break; 1801 } 1802 1803 if (i >= adev->sdma.num_instances) { 1804 dev_WARN_ONCE( 1805 adev->dev, 1, 1806 "Couldn't find the right sdma instance in trap handler"); 1807 return 0; 1808 } 1809 1810 switch (entry->ring_id) { 1811 case 0: 1812 amdgpu_fence_process(&adev->sdma.instance[i].ring); 1813 break; 1814 case 1: 1815 amdgpu_fence_process(&adev->sdma.instance[i].page); 1816 break; 1817 default: 1818 break; 1819 } 1820 return 0; 1821 } 1822 1823 #if 0 1824 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, 1825 void *err_data, 1826 struct amdgpu_iv_entry *entry) 1827 { 1828 int instance; 1829 1830 /* When “Full RAS” is enabled, the per-IP interrupt sources should 1831 * be disabled and the driver should only look for the aggregated 1832 * interrupt via sync flood 1833 */ 1834 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) 1835 goto out; 1836 1837 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1838 if (instance < 0) 1839 goto out; 1840 1841 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry); 1842 1843 out: 1844 return AMDGPU_RAS_SUCCESS; 1845 } 1846 #endif 1847 1848 static int sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device *adev, 1849 struct amdgpu_irq_src *source, 1850 struct amdgpu_iv_entry *entry) 1851 { 1852 int instance; 1853 1854 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1855 1856 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1857 if (instance < 0) 1858 return 0; 1859 1860 switch (entry->ring_id) { 1861 case 0: 1862 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 1863 break; 1864 } 1865 return 0; 1866 } 1867 1868 static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev, 1869 struct amdgpu_irq_src *source, 1870 unsigned type, 1871 enum amdgpu_interrupt_state state) 1872 { 1873 u32 sdma_cntl; 1874 1875 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); 1876 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, DRAM_ECC_INT_ENABLE, 1877 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1878 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); 1879 1880 return 0; 1881 } 1882 1883 static int sdma_v4_4_2_print_iv_entry(struct amdgpu_device *adev, 1884 struct amdgpu_iv_entry *entry) 1885 { 1886 int instance; 1887 struct amdgpu_task_info *task_info; 1888 u64 addr; 1889 1890 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1891 if (instance < 0 || instance >= adev->sdma.num_instances) { 1892 dev_err(adev->dev, "sdma instance invalid %d\n", instance); 1893 return -EINVAL; 1894 } 1895 1896 addr = (u64)entry->src_data[0] << 12; 1897 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 1898 1899 dev_dbg_ratelimited(adev->dev, 1900 "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u pasid:%u\n", 1901 instance, addr, entry->src_id, entry->ring_id, entry->vmid, 1902 entry->pasid); 1903 1904 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 1905 if (task_info) { 1906 dev_dbg_ratelimited(adev->dev, " for process %s pid %d thread %s pid %d\n", 1907 task_info->process_name, task_info->tgid, 1908 task_info->task.comm, task_info->task.pid); 1909 amdgpu_vm_put_task_info(task_info); 1910 } 1911 1912 return 0; 1913 } 1914 1915 static int sdma_v4_4_2_process_vm_hole_irq(struct amdgpu_device *adev, 1916 struct amdgpu_irq_src *source, 1917 struct amdgpu_iv_entry *entry) 1918 { 1919 dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n"); 1920 sdma_v4_4_2_print_iv_entry(adev, entry); 1921 return 0; 1922 } 1923 1924 static int sdma_v4_4_2_process_doorbell_invalid_irq(struct amdgpu_device *adev, 1925 struct amdgpu_irq_src *source, 1926 struct amdgpu_iv_entry *entry) 1927 { 1928 1929 dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n"); 1930 sdma_v4_4_2_print_iv_entry(adev, entry); 1931 return 0; 1932 } 1933 1934 static int sdma_v4_4_2_process_pool_timeout_irq(struct amdgpu_device *adev, 1935 struct amdgpu_irq_src *source, 1936 struct amdgpu_iv_entry *entry) 1937 { 1938 dev_dbg_ratelimited(adev->dev, 1939 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n"); 1940 sdma_v4_4_2_print_iv_entry(adev, entry); 1941 return 0; 1942 } 1943 1944 static int sdma_v4_4_2_process_srbm_write_irq(struct amdgpu_device *adev, 1945 struct amdgpu_irq_src *source, 1946 struct amdgpu_iv_entry *entry) 1947 { 1948 dev_dbg_ratelimited(adev->dev, 1949 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n"); 1950 sdma_v4_4_2_print_iv_entry(adev, entry); 1951 return 0; 1952 } 1953 1954 static int sdma_v4_4_2_process_ctxt_empty_irq(struct amdgpu_device *adev, 1955 struct amdgpu_irq_src *source, 1956 struct amdgpu_iv_entry *entry) 1957 { 1958 /* There is nothing useful to be done here, only kept for debug */ 1959 dev_dbg_ratelimited(adev->dev, "SDMA context empty interrupt"); 1960 sdma_v4_4_2_print_iv_entry(adev, entry); 1961 return 0; 1962 } 1963 1964 static void sdma_v4_4_2_inst_update_medium_grain_light_sleep( 1965 struct amdgpu_device *adev, bool enable, uint32_t inst_mask) 1966 { 1967 uint32_t data, def; 1968 int i; 1969 1970 /* leave as default if it is not driver controlled */ 1971 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) 1972 return; 1973 1974 if (enable) { 1975 for_each_inst(i, inst_mask) { 1976 /* 1-not override: enable sdma mem light sleep */ 1977 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL); 1978 data |= SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1979 if (def != data) 1980 WREG32_SDMA(i, regSDMA_POWER_CNTL, data); 1981 } 1982 } else { 1983 for_each_inst(i, inst_mask) { 1984 /* 0-override:disable sdma mem light sleep */ 1985 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL); 1986 data &= ~SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1987 if (def != data) 1988 WREG32_SDMA(i, regSDMA_POWER_CNTL, data); 1989 } 1990 } 1991 } 1992 1993 static void sdma_v4_4_2_inst_update_medium_grain_clock_gating( 1994 struct amdgpu_device *adev, bool enable, uint32_t inst_mask) 1995 { 1996 uint32_t data, def; 1997 int i; 1998 1999 /* leave as default if it is not driver controlled */ 2000 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) 2001 return; 2002 2003 if (enable) { 2004 for_each_inst(i, inst_mask) { 2005 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL); 2006 data &= ~(SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2007 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2008 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2009 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2010 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2011 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2012 if (def != data) 2013 WREG32_SDMA(i, regSDMA_CLK_CTRL, data); 2014 } 2015 } else { 2016 for_each_inst(i, inst_mask) { 2017 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL); 2018 data |= (SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2019 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2020 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2021 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2022 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2023 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2024 if (def != data) 2025 WREG32_SDMA(i, regSDMA_CLK_CTRL, data); 2026 } 2027 } 2028 } 2029 2030 static int sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2031 enum amd_clockgating_state state) 2032 { 2033 struct amdgpu_device *adev = ip_block->adev; 2034 uint32_t inst_mask; 2035 2036 if (amdgpu_sriov_vf(adev)) 2037 return 0; 2038 2039 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 2040 2041 sdma_v4_4_2_inst_update_medium_grain_clock_gating( 2042 adev, state == AMD_CG_STATE_GATE, inst_mask); 2043 sdma_v4_4_2_inst_update_medium_grain_light_sleep( 2044 adev, state == AMD_CG_STATE_GATE, inst_mask); 2045 return 0; 2046 } 2047 2048 static int sdma_v4_4_2_set_powergating_state(struct amdgpu_ip_block *ip_block, 2049 enum amd_powergating_state state) 2050 { 2051 return 0; 2052 } 2053 2054 static void sdma_v4_4_2_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 2055 { 2056 struct amdgpu_device *adev = ip_block->adev; 2057 int data; 2058 2059 if (amdgpu_sriov_vf(adev)) 2060 *flags = 0; 2061 2062 /* AMD_CG_SUPPORT_SDMA_MGCG */ 2063 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL)); 2064 if (!(data & SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK)) 2065 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 2066 2067 /* AMD_CG_SUPPORT_SDMA_LS */ 2068 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL)); 2069 if (data & SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 2070 *flags |= AMD_CG_SUPPORT_SDMA_LS; 2071 } 2072 2073 static void sdma_v4_4_2_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 2074 { 2075 struct amdgpu_device *adev = ip_block->adev; 2076 int i, j; 2077 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); 2078 uint32_t instance_offset; 2079 2080 if (!adev->sdma.ip_dump) 2081 return; 2082 2083 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances); 2084 for (i = 0; i < adev->sdma.num_instances; i++) { 2085 instance_offset = i * reg_count; 2086 drm_printf(p, "\nInstance:%d\n", i); 2087 2088 for (j = 0; j < reg_count; j++) 2089 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_4_4_2[j].reg_name, 2090 adev->sdma.ip_dump[instance_offset + j]); 2091 } 2092 } 2093 2094 static void sdma_v4_4_2_dump_ip_state(struct amdgpu_ip_block *ip_block) 2095 { 2096 struct amdgpu_device *adev = ip_block->adev; 2097 int i, j; 2098 uint32_t instance_offset; 2099 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); 2100 2101 if (!adev->sdma.ip_dump) 2102 return; 2103 2104 for (i = 0; i < adev->sdma.num_instances; i++) { 2105 instance_offset = i * reg_count; 2106 for (j = 0; j < reg_count; j++) 2107 adev->sdma.ip_dump[instance_offset + j] = 2108 RREG32(sdma_v4_4_2_get_reg_offset(adev, i, 2109 sdma_reg_list_4_4_2[j].reg_offset)); 2110 } 2111 } 2112 2113 const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = { 2114 .name = "sdma_v4_4_2", 2115 .early_init = sdma_v4_4_2_early_init, 2116 .late_init = sdma_v4_4_2_late_init, 2117 .sw_init = sdma_v4_4_2_sw_init, 2118 .sw_fini = sdma_v4_4_2_sw_fini, 2119 .hw_init = sdma_v4_4_2_hw_init, 2120 .hw_fini = sdma_v4_4_2_hw_fini, 2121 .suspend = sdma_v4_4_2_suspend, 2122 .resume = sdma_v4_4_2_resume, 2123 .is_idle = sdma_v4_4_2_is_idle, 2124 .wait_for_idle = sdma_v4_4_2_wait_for_idle, 2125 .soft_reset = sdma_v4_4_2_soft_reset, 2126 .set_clockgating_state = sdma_v4_4_2_set_clockgating_state, 2127 .set_powergating_state = sdma_v4_4_2_set_powergating_state, 2128 .get_clockgating_state = sdma_v4_4_2_get_clockgating_state, 2129 .dump_ip_state = sdma_v4_4_2_dump_ip_state, 2130 .print_ip_state = sdma_v4_4_2_print_ip_state, 2131 }; 2132 2133 static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = { 2134 .type = AMDGPU_RING_TYPE_SDMA, 2135 .align_mask = 0xff, 2136 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2137 .support_64bit_ptrs = true, 2138 .get_rptr = sdma_v4_4_2_ring_get_rptr, 2139 .get_wptr = sdma_v4_4_2_ring_get_wptr, 2140 .set_wptr = sdma_v4_4_2_ring_set_wptr, 2141 .emit_frame_size = 2142 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */ 2143 3 + /* hdp invalidate */ 2144 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */ 2145 /* sdma_v4_4_2_ring_emit_vm_flush */ 2146 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2147 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2148 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */ 2149 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */ 2150 .emit_ib = sdma_v4_4_2_ring_emit_ib, 2151 .emit_fence = sdma_v4_4_2_ring_emit_fence, 2152 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync, 2153 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush, 2154 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush, 2155 .test_ring = sdma_v4_4_2_ring_test_ring, 2156 .test_ib = sdma_v4_4_2_ring_test_ib, 2157 .insert_nop = sdma_v4_4_2_ring_insert_nop, 2158 .pad_ib = sdma_v4_4_2_ring_pad_ib, 2159 .emit_wreg = sdma_v4_4_2_ring_emit_wreg, 2160 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, 2161 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2162 .reset = sdma_v4_4_2_reset_queue, 2163 }; 2164 2165 static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = { 2166 .type = AMDGPU_RING_TYPE_SDMA, 2167 .align_mask = 0xff, 2168 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2169 .support_64bit_ptrs = true, 2170 .get_rptr = sdma_v4_4_2_ring_get_rptr, 2171 .get_wptr = sdma_v4_4_2_page_ring_get_wptr, 2172 .set_wptr = sdma_v4_4_2_page_ring_set_wptr, 2173 .emit_frame_size = 2174 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */ 2175 3 + /* hdp invalidate */ 2176 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */ 2177 /* sdma_v4_4_2_ring_emit_vm_flush */ 2178 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2179 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2180 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */ 2181 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */ 2182 .emit_ib = sdma_v4_4_2_ring_emit_ib, 2183 .emit_fence = sdma_v4_4_2_ring_emit_fence, 2184 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync, 2185 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush, 2186 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush, 2187 .test_ring = sdma_v4_4_2_ring_test_ring, 2188 .test_ib = sdma_v4_4_2_ring_test_ib, 2189 .insert_nop = sdma_v4_4_2_ring_insert_nop, 2190 .pad_ib = sdma_v4_4_2_ring_pad_ib, 2191 .emit_wreg = sdma_v4_4_2_ring_emit_wreg, 2192 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, 2193 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2194 .reset = sdma_v4_4_2_reset_queue, 2195 }; 2196 2197 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev) 2198 { 2199 int i, dev_inst; 2200 2201 for (i = 0; i < adev->sdma.num_instances; i++) { 2202 adev->sdma.instance[i].ring.funcs = &sdma_v4_4_2_ring_funcs; 2203 adev->sdma.instance[i].ring.me = i; 2204 if (adev->sdma.has_page_queue) { 2205 adev->sdma.instance[i].page.funcs = 2206 &sdma_v4_4_2_page_ring_funcs; 2207 adev->sdma.instance[i].page.me = i; 2208 } 2209 2210 dev_inst = GET_INST(SDMA0, i); 2211 /* AID to which SDMA belongs depends on physical instance */ 2212 adev->sdma.instance[i].aid_id = 2213 dev_inst / adev->sdma.num_inst_per_aid; 2214 } 2215 } 2216 2217 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_trap_irq_funcs = { 2218 .set = sdma_v4_4_2_set_trap_irq_state, 2219 .process = sdma_v4_4_2_process_trap_irq, 2220 }; 2221 2222 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_illegal_inst_irq_funcs = { 2223 .process = sdma_v4_4_2_process_illegal_inst_irq, 2224 }; 2225 2226 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ecc_irq_funcs = { 2227 .set = sdma_v4_4_2_set_ecc_irq_state, 2228 .process = amdgpu_sdma_process_ecc_irq, 2229 }; 2230 2231 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_vm_hole_irq_funcs = { 2232 .process = sdma_v4_4_2_process_vm_hole_irq, 2233 }; 2234 2235 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_doorbell_invalid_irq_funcs = { 2236 .process = sdma_v4_4_2_process_doorbell_invalid_irq, 2237 }; 2238 2239 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_pool_timeout_irq_funcs = { 2240 .process = sdma_v4_4_2_process_pool_timeout_irq, 2241 }; 2242 2243 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_srbm_write_irq_funcs = { 2244 .process = sdma_v4_4_2_process_srbm_write_irq, 2245 }; 2246 2247 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ctxt_empty_irq_funcs = { 2248 .process = sdma_v4_4_2_process_ctxt_empty_irq, 2249 }; 2250 2251 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev) 2252 { 2253 adev->sdma.trap_irq.num_types = adev->sdma.num_instances; 2254 adev->sdma.ecc_irq.num_types = adev->sdma.num_instances; 2255 adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances; 2256 adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances; 2257 adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances; 2258 adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances; 2259 adev->sdma.ctxt_empty_irq.num_types = adev->sdma.num_instances; 2260 2261 adev->sdma.trap_irq.funcs = &sdma_v4_4_2_trap_irq_funcs; 2262 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_4_2_illegal_inst_irq_funcs; 2263 adev->sdma.ecc_irq.funcs = &sdma_v4_4_2_ecc_irq_funcs; 2264 adev->sdma.vm_hole_irq.funcs = &sdma_v4_4_2_vm_hole_irq_funcs; 2265 adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_4_2_doorbell_invalid_irq_funcs; 2266 adev->sdma.pool_timeout_irq.funcs = &sdma_v4_4_2_pool_timeout_irq_funcs; 2267 adev->sdma.srbm_write_irq.funcs = &sdma_v4_4_2_srbm_write_irq_funcs; 2268 adev->sdma.ctxt_empty_irq.funcs = &sdma_v4_4_2_ctxt_empty_irq_funcs; 2269 } 2270 2271 /** 2272 * sdma_v4_4_2_emit_copy_buffer - copy buffer using the sDMA engine 2273 * 2274 * @ib: indirect buffer to copy to 2275 * @src_offset: src GPU address 2276 * @dst_offset: dst GPU address 2277 * @byte_count: number of bytes to xfer 2278 * @copy_flags: copy flags for the buffers 2279 * 2280 * Copy GPU buffers using the DMA engine. 2281 * Used by the amdgpu ttm implementation to move pages if 2282 * registered as the asic copy callback. 2283 */ 2284 static void sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib *ib, 2285 uint64_t src_offset, 2286 uint64_t dst_offset, 2287 uint32_t byte_count, 2288 uint32_t copy_flags) 2289 { 2290 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 2291 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 2292 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0); 2293 ib->ptr[ib->length_dw++] = byte_count - 1; 2294 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 2295 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 2296 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 2297 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2298 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2299 } 2300 2301 /** 2302 * sdma_v4_4_2_emit_fill_buffer - fill buffer using the sDMA engine 2303 * 2304 * @ib: indirect buffer to copy to 2305 * @src_data: value to write to buffer 2306 * @dst_offset: dst GPU address 2307 * @byte_count: number of bytes to xfer 2308 * 2309 * Fill GPU buffers using the DMA engine. 2310 */ 2311 static void sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib *ib, 2312 uint32_t src_data, 2313 uint64_t dst_offset, 2314 uint32_t byte_count) 2315 { 2316 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2317 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2318 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2319 ib->ptr[ib->length_dw++] = src_data; 2320 ib->ptr[ib->length_dw++] = byte_count - 1; 2321 } 2322 2323 static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = { 2324 .copy_max_bytes = 1 << 30, 2325 .copy_num_dw = 7, 2326 .emit_copy_buffer = sdma_v4_4_2_emit_copy_buffer, 2327 2328 .fill_max_bytes = 1 << 30, 2329 .fill_num_dw = 5, 2330 .emit_fill_buffer = sdma_v4_4_2_emit_fill_buffer, 2331 }; 2332 2333 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev) 2334 { 2335 amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v4_4_2_buffer_funcs); 2336 } 2337 2338 /** 2339 * sdma_v4_4_2_update_reset_mask - update reset mask for SDMA 2340 * @adev: Pointer to the AMDGPU device structure 2341 * 2342 * This function update reset mask for SDMA and sets the supported 2343 * reset types based on the IP version and firmware versions. 2344 * 2345 */ 2346 static void sdma_v4_4_2_update_reset_mask(struct amdgpu_device *adev) 2347 { 2348 /* per queue reset not supported for SRIOV */ 2349 if (amdgpu_sriov_vf(adev)) 2350 return; 2351 2352 /* 2353 * the user queue relies on MEC fw and pmfw when the sdma queue do reset. 2354 * it needs to check both of them at here to skip old mec and pmfw. 2355 */ 2356 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2357 case IP_VERSION(9, 4, 3): 2358 case IP_VERSION(9, 4, 4): 2359 if ((adev->gfx.mec_fw_version >= 0xb0) && 2360 amdgpu_dpm_reset_sdma_is_supported(adev) && 2361 !adev->debug_disable_gpu_ring_reset) 2362 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 2363 break; 2364 case IP_VERSION(9, 5, 0): 2365 if ((adev->gfx.mec_fw_version >= 0xf) && 2366 amdgpu_dpm_reset_sdma_is_supported(adev) && 2367 !adev->debug_disable_gpu_ring_reset) 2368 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 2369 break; 2370 default: 2371 break; 2372 } 2373 2374 } 2375 2376 const struct amdgpu_ip_block_version sdma_v4_4_2_ip_block = { 2377 .type = AMD_IP_BLOCK_TYPE_SDMA, 2378 .major = 4, 2379 .minor = 4, 2380 .rev = 2, 2381 .funcs = &sdma_v4_4_2_ip_funcs, 2382 }; 2383 2384 static int sdma_v4_4_2_xcp_resume(void *handle, uint32_t inst_mask) 2385 { 2386 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2387 int r; 2388 2389 if (!amdgpu_sriov_vf(adev)) 2390 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask); 2391 2392 r = sdma_v4_4_2_inst_start(adev, inst_mask, false); 2393 2394 return r; 2395 } 2396 2397 static int sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask) 2398 { 2399 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2400 uint32_t tmp_mask = inst_mask; 2401 int i; 2402 2403 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2404 for_each_inst(i, tmp_mask) { 2405 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 2406 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 2407 } 2408 } 2409 2410 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 2411 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 2412 2413 return 0; 2414 } 2415 2416 struct amdgpu_xcp_ip_funcs sdma_v4_4_2_xcp_funcs = { 2417 .suspend = &sdma_v4_4_2_xcp_suspend, 2418 .resume = &sdma_v4_4_2_xcp_resume 2419 }; 2420 2421 static const struct amdgpu_ras_err_status_reg_entry sdma_v4_2_2_ue_reg_list[] = { 2422 {AMDGPU_RAS_REG_ENTRY(SDMA0, 0, regSDMA_UE_ERR_STATUS_LO, regSDMA_UE_ERR_STATUS_HI), 2423 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SDMA"}, 2424 }; 2425 2426 static const struct amdgpu_ras_memory_id_entry sdma_v4_4_2_ras_memory_list[] = { 2427 {AMDGPU_SDMA_MBANK_DATA_BUF0, "SDMA_MBANK_DATA_BUF0"}, 2428 {AMDGPU_SDMA_MBANK_DATA_BUF1, "SDMA_MBANK_DATA_BUF1"}, 2429 {AMDGPU_SDMA_MBANK_DATA_BUF2, "SDMA_MBANK_DATA_BUF2"}, 2430 {AMDGPU_SDMA_MBANK_DATA_BUF3, "SDMA_MBANK_DATA_BUF3"}, 2431 {AMDGPU_SDMA_MBANK_DATA_BUF4, "SDMA_MBANK_DATA_BUF4"}, 2432 {AMDGPU_SDMA_MBANK_DATA_BUF5, "SDMA_MBANK_DATA_BUF5"}, 2433 {AMDGPU_SDMA_MBANK_DATA_BUF6, "SDMA_MBANK_DATA_BUF6"}, 2434 {AMDGPU_SDMA_MBANK_DATA_BUF7, "SDMA_MBANK_DATA_BUF7"}, 2435 {AMDGPU_SDMA_MBANK_DATA_BUF8, "SDMA_MBANK_DATA_BUF8"}, 2436 {AMDGPU_SDMA_MBANK_DATA_BUF9, "SDMA_MBANK_DATA_BUF9"}, 2437 {AMDGPU_SDMA_MBANK_DATA_BUF10, "SDMA_MBANK_DATA_BUF10"}, 2438 {AMDGPU_SDMA_MBANK_DATA_BUF11, "SDMA_MBANK_DATA_BUF11"}, 2439 {AMDGPU_SDMA_MBANK_DATA_BUF12, "SDMA_MBANK_DATA_BUF12"}, 2440 {AMDGPU_SDMA_MBANK_DATA_BUF13, "SDMA_MBANK_DATA_BUF13"}, 2441 {AMDGPU_SDMA_MBANK_DATA_BUF14, "SDMA_MBANK_DATA_BUF14"}, 2442 {AMDGPU_SDMA_MBANK_DATA_BUF15, "SDMA_MBANK_DATA_BUF15"}, 2443 {AMDGPU_SDMA_UCODE_BUF, "SDMA_UCODE_BUF"}, 2444 {AMDGPU_SDMA_RB_CMD_BUF, "SDMA_RB_CMD_BUF"}, 2445 {AMDGPU_SDMA_IB_CMD_BUF, "SDMA_IB_CMD_BUF"}, 2446 {AMDGPU_SDMA_UTCL1_RD_FIFO, "SDMA_UTCL1_RD_FIFO"}, 2447 {AMDGPU_SDMA_UTCL1_RDBST_FIFO, "SDMA_UTCL1_RDBST_FIFO"}, 2448 {AMDGPU_SDMA_UTCL1_WR_FIFO, "SDMA_UTCL1_WR_FIFO"}, 2449 {AMDGPU_SDMA_DATA_LUT_FIFO, "SDMA_DATA_LUT_FIFO"}, 2450 {AMDGPU_SDMA_SPLIT_DAT_BUF, "SDMA_SPLIT_DAT_BUF"}, 2451 }; 2452 2453 static void sdma_v4_4_2_inst_query_ras_error_count(struct amdgpu_device *adev, 2454 uint32_t sdma_inst, 2455 void *ras_err_status) 2456 { 2457 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 2458 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); 2459 unsigned long ue_count = 0; 2460 struct amdgpu_smuio_mcm_config_info mcm_info = { 2461 .socket_id = adev->smuio.funcs->get_socket_id(adev), 2462 .die_id = adev->sdma.instance[sdma_inst].aid_id, 2463 }; 2464 2465 /* sdma v4_4_2 doesn't support query ce counts */ 2466 amdgpu_ras_inst_query_ras_error_count(adev, 2467 sdma_v4_2_2_ue_reg_list, 2468 ARRAY_SIZE(sdma_v4_2_2_ue_reg_list), 2469 sdma_v4_4_2_ras_memory_list, 2470 ARRAY_SIZE(sdma_v4_4_2_ras_memory_list), 2471 sdma_dev_inst, 2472 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 2473 &ue_count); 2474 2475 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count); 2476 } 2477 2478 static void sdma_v4_4_2_query_ras_error_count(struct amdgpu_device *adev, 2479 void *ras_err_status) 2480 { 2481 uint32_t inst_mask; 2482 int i = 0; 2483 2484 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 2485 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2486 for_each_inst(i, inst_mask) 2487 sdma_v4_4_2_inst_query_ras_error_count(adev, i, ras_err_status); 2488 } else { 2489 dev_warn(adev->dev, "SDMA RAS is not supported\n"); 2490 } 2491 } 2492 2493 static void sdma_v4_4_2_inst_reset_ras_error_count(struct amdgpu_device *adev, 2494 uint32_t sdma_inst) 2495 { 2496 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); 2497 2498 amdgpu_ras_inst_reset_ras_error_count(adev, 2499 sdma_v4_2_2_ue_reg_list, 2500 ARRAY_SIZE(sdma_v4_2_2_ue_reg_list), 2501 sdma_dev_inst); 2502 } 2503 2504 static void sdma_v4_4_2_reset_ras_error_count(struct amdgpu_device *adev) 2505 { 2506 uint32_t inst_mask; 2507 int i = 0; 2508 2509 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 2510 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2511 for_each_inst(i, inst_mask) 2512 sdma_v4_4_2_inst_reset_ras_error_count(adev, i); 2513 } else { 2514 dev_warn(adev->dev, "SDMA RAS is not supported\n"); 2515 } 2516 } 2517 2518 static const struct amdgpu_ras_block_hw_ops sdma_v4_4_2_ras_hw_ops = { 2519 .query_ras_error_count = sdma_v4_4_2_query_ras_error_count, 2520 .reset_ras_error_count = sdma_v4_4_2_reset_ras_error_count, 2521 }; 2522 2523 static int sdma_v4_4_2_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, 2524 enum aca_smu_type type, void *data) 2525 { 2526 struct aca_bank_info info; 2527 u64 misc0; 2528 int ret; 2529 2530 ret = aca_bank_info_decode(bank, &info); 2531 if (ret) 2532 return ret; 2533 2534 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 2535 switch (type) { 2536 case ACA_SMU_TYPE_UE: 2537 bank->aca_err_type = ACA_ERROR_TYPE_UE; 2538 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE, 2539 1ULL); 2540 break; 2541 case ACA_SMU_TYPE_CE: 2542 bank->aca_err_type = ACA_ERROR_TYPE_CE; 2543 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 2544 ACA_REG__MISC0__ERRCNT(misc0)); 2545 break; 2546 default: 2547 return -EINVAL; 2548 } 2549 2550 return ret; 2551 } 2552 2553 /* CODE_SDMA0 - CODE_SDMA4, reference to smu driver if header file */ 2554 static int sdma_v4_4_2_err_codes[] = { 33, 34, 35, 36 }; 2555 2556 static bool sdma_v4_4_2_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 2557 enum aca_smu_type type, void *data) 2558 { 2559 u32 instlo; 2560 2561 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 2562 instlo &= GENMASK(31, 1); 2563 2564 if (instlo != mmSMNAID_AID0_MCA_SMU) 2565 return false; 2566 2567 if (aca_bank_check_error_codes(handle->adev, bank, 2568 sdma_v4_4_2_err_codes, 2569 ARRAY_SIZE(sdma_v4_4_2_err_codes))) 2570 return false; 2571 2572 return true; 2573 } 2574 2575 static const struct aca_bank_ops sdma_v4_4_2_aca_bank_ops = { 2576 .aca_bank_parser = sdma_v4_4_2_aca_bank_parser, 2577 .aca_bank_is_valid = sdma_v4_4_2_aca_bank_is_valid, 2578 }; 2579 2580 static const struct aca_info sdma_v4_4_2_aca_info = { 2581 .hwip = ACA_HWIP_TYPE_SMU, 2582 .mask = ACA_ERROR_UE_MASK, 2583 .bank_ops = &sdma_v4_4_2_aca_bank_ops, 2584 }; 2585 2586 static int sdma_v4_4_2_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 2587 { 2588 int r; 2589 2590 r = amdgpu_sdma_ras_late_init(adev, ras_block); 2591 if (r) 2592 return r; 2593 2594 return amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__SDMA, 2595 &sdma_v4_4_2_aca_info, NULL); 2596 } 2597 2598 static struct amdgpu_sdma_ras sdma_v4_4_2_ras = { 2599 .ras_block = { 2600 .hw_ops = &sdma_v4_4_2_ras_hw_ops, 2601 .ras_late_init = sdma_v4_4_2_ras_late_init, 2602 }, 2603 }; 2604 2605 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev) 2606 { 2607 adev->sdma.ras = &sdma_v4_4_2_ras; 2608 } 2609