1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_xcp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_trace.h" 33 #include "amdgpu_reset.h" 34 35 #include "sdma/sdma_4_4_2_offset.h" 36 #include "sdma/sdma_4_4_2_sh_mask.h" 37 38 #include "soc15_common.h" 39 #include "soc15.h" 40 #include "vega10_sdma_pkt_open.h" 41 42 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 43 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 44 45 #include "amdgpu_ras.h" 46 47 MODULE_FIRMWARE("amdgpu/sdma_4_4_2.bin"); 48 MODULE_FIRMWARE("amdgpu/sdma_4_4_5.bin"); 49 50 static const struct amdgpu_hwip_reg_entry sdma_reg_list_4_4_2[] = { 51 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS_REG), 52 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS1_REG), 53 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS2_REG), 54 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS3_REG), 55 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UCODE_CHECKSUM), 56 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH_HI), 57 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH), 58 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_STATUS), 59 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_STATUS), 60 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK0), 61 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK1), 62 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK0), 63 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK1), 64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_CNTL), 65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR), 66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR_HI), 67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR), 68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR_HI), 69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_OFFSET), 70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_LO), 71 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_HI), 72 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_CNTL), 73 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_RPTR), 74 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_SUB_REMAIN), 75 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_DUMMY_REG), 76 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_CNTL), 77 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR), 78 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR_HI), 79 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR), 80 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR_HI), 81 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_OFFSET), 82 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_LO), 83 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_HI), 84 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_DUMMY_REG), 85 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_CNTL), 86 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR), 87 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR_HI), 88 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR), 89 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR_HI), 90 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_OFFSET), 91 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_LO), 92 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_HI), 93 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_DUMMY_REG), 94 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_VM_CNTL) 95 }; 96 97 #define mmSMNAID_AID0_MCA_SMU 0x03b30400 98 99 #define WREG32_SDMA(instance, offset, value) \ 100 WREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)), value) 101 #define RREG32_SDMA(instance, offset) \ 102 RREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset))) 103 104 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev); 105 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev); 106 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev); 107 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev); 108 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev); 109 static void sdma_v4_4_2_update_reset_mask(struct amdgpu_device *adev); 110 static int sdma_v4_4_2_stop_queue(struct amdgpu_ring *ring); 111 static int sdma_v4_4_2_restore_queue(struct amdgpu_ring *ring); 112 static int sdma_v4_4_2_soft_reset_engine(struct amdgpu_device *adev, 113 u32 instance_id); 114 115 static u32 sdma_v4_4_2_get_reg_offset(struct amdgpu_device *adev, 116 u32 instance, u32 offset) 117 { 118 u32 dev_inst = GET_INST(SDMA0, instance); 119 120 return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset); 121 } 122 123 static unsigned sdma_v4_4_2_seq_to_irq_id(int seq_num) 124 { 125 switch (seq_num) { 126 case 0: 127 return SOC15_IH_CLIENTID_SDMA0; 128 case 1: 129 return SOC15_IH_CLIENTID_SDMA1; 130 case 2: 131 return SOC15_IH_CLIENTID_SDMA2; 132 case 3: 133 return SOC15_IH_CLIENTID_SDMA3; 134 default: 135 return -EINVAL; 136 } 137 } 138 139 static int sdma_v4_4_2_irq_id_to_seq(struct amdgpu_device *adev, unsigned client_id) 140 { 141 switch (client_id) { 142 case SOC15_IH_CLIENTID_SDMA0: 143 return 0; 144 case SOC15_IH_CLIENTID_SDMA1: 145 return 1; 146 case SOC15_IH_CLIENTID_SDMA2: 147 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) 148 return 0; 149 else 150 return 2; 151 case SOC15_IH_CLIENTID_SDMA3: 152 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) 153 return 1; 154 else 155 return 3; 156 default: 157 return -EINVAL; 158 } 159 } 160 161 static void sdma_v4_4_2_inst_init_golden_registers(struct amdgpu_device *adev, 162 uint32_t inst_mask) 163 { 164 u32 val; 165 int i; 166 167 for (i = 0; i < adev->sdma.num_instances; i++) { 168 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG); 169 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4); 170 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, 171 PIPE_INTERLEAVE_SIZE, 0); 172 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG, val); 173 174 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ); 175 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS, 176 4); 177 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, 178 PIPE_INTERLEAVE_SIZE, 0); 179 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ, val); 180 } 181 } 182 183 /** 184 * sdma_v4_4_2_init_microcode - load ucode images from disk 185 * 186 * @adev: amdgpu_device pointer 187 * 188 * Use the firmware interface to load the ucode images into 189 * the driver (not loaded into hw). 190 * Returns 0 on success, error on failure. 191 */ 192 static int sdma_v4_4_2_init_microcode(struct amdgpu_device *adev) 193 { 194 int ret, i; 195 196 for (i = 0; i < adev->sdma.num_instances; i++) { 197 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) || 198 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 4) || 199 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) { 200 ret = amdgpu_sdma_init_microcode(adev, 0, true); 201 break; 202 } else { 203 ret = amdgpu_sdma_init_microcode(adev, i, false); 204 if (ret) 205 return ret; 206 } 207 } 208 209 return ret; 210 } 211 212 /** 213 * sdma_v4_4_2_ring_get_rptr - get the current read pointer 214 * 215 * @ring: amdgpu ring pointer 216 * 217 * Get the current rptr from the hardware. 218 */ 219 static uint64_t sdma_v4_4_2_ring_get_rptr(struct amdgpu_ring *ring) 220 { 221 u64 rptr; 222 223 /* XXX check if swapping is necessary on BE */ 224 rptr = READ_ONCE(*((u64 *)&ring->adev->wb.wb[ring->rptr_offs])); 225 226 DRM_DEBUG("rptr before shift == 0x%016llx\n", rptr); 227 return rptr >> 2; 228 } 229 230 /** 231 * sdma_v4_4_2_ring_get_wptr - get the current write pointer 232 * 233 * @ring: amdgpu ring pointer 234 * 235 * Get the current wptr from the hardware. 236 */ 237 static uint64_t sdma_v4_4_2_ring_get_wptr(struct amdgpu_ring *ring) 238 { 239 struct amdgpu_device *adev = ring->adev; 240 u64 wptr; 241 242 if (ring->use_doorbell) { 243 /* XXX check if swapping is necessary on BE */ 244 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 245 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 246 } else { 247 wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI); 248 wptr = wptr << 32; 249 wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR); 250 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 251 ring->me, wptr); 252 } 253 254 return wptr >> 2; 255 } 256 257 /** 258 * sdma_v4_4_2_ring_set_wptr - commit the write pointer 259 * 260 * @ring: amdgpu ring pointer 261 * 262 * Write the wptr back to the hardware. 263 */ 264 static void sdma_v4_4_2_ring_set_wptr(struct amdgpu_ring *ring) 265 { 266 struct amdgpu_device *adev = ring->adev; 267 268 DRM_DEBUG("Setting write pointer\n"); 269 if (ring->use_doorbell) { 270 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 271 272 DRM_DEBUG("Using doorbell -- " 273 "wptr_offs == 0x%08x " 274 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 275 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 276 ring->wptr_offs, 277 lower_32_bits(ring->wptr << 2), 278 upper_32_bits(ring->wptr << 2)); 279 /* XXX check if swapping is necessary on BE */ 280 WRITE_ONCE(*wb, (ring->wptr << 2)); 281 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 282 ring->doorbell_index, ring->wptr << 2); 283 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 284 } else { 285 DRM_DEBUG("Not using doorbell -- " 286 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 287 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 288 ring->me, 289 lower_32_bits(ring->wptr << 2), 290 ring->me, 291 upper_32_bits(ring->wptr << 2)); 292 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR, 293 lower_32_bits(ring->wptr << 2)); 294 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI, 295 upper_32_bits(ring->wptr << 2)); 296 } 297 } 298 299 /** 300 * sdma_v4_4_2_page_ring_get_wptr - get the current write pointer 301 * 302 * @ring: amdgpu ring pointer 303 * 304 * Get the current wptr from the hardware. 305 */ 306 static uint64_t sdma_v4_4_2_page_ring_get_wptr(struct amdgpu_ring *ring) 307 { 308 struct amdgpu_device *adev = ring->adev; 309 u64 wptr; 310 311 if (ring->use_doorbell) { 312 /* XXX check if swapping is necessary on BE */ 313 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 314 } else { 315 wptr = RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI); 316 wptr = wptr << 32; 317 wptr |= RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR); 318 } 319 320 return wptr >> 2; 321 } 322 323 /** 324 * sdma_v4_4_2_page_ring_set_wptr - commit the write pointer 325 * 326 * @ring: amdgpu ring pointer 327 * 328 * Write the wptr back to the hardware. 329 */ 330 static void sdma_v4_4_2_page_ring_set_wptr(struct amdgpu_ring *ring) 331 { 332 struct amdgpu_device *adev = ring->adev; 333 334 if (ring->use_doorbell) { 335 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 336 337 /* XXX check if swapping is necessary on BE */ 338 WRITE_ONCE(*wb, (ring->wptr << 2)); 339 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 340 } else { 341 uint64_t wptr = ring->wptr << 2; 342 343 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR, 344 lower_32_bits(wptr)); 345 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI, 346 upper_32_bits(wptr)); 347 } 348 } 349 350 static void sdma_v4_4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 351 { 352 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 353 int i; 354 355 for (i = 0; i < count; i++) 356 if (sdma && sdma->burst_nop && (i == 0)) 357 amdgpu_ring_write(ring, ring->funcs->nop | 358 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 359 else 360 amdgpu_ring_write(ring, ring->funcs->nop); 361 } 362 363 /** 364 * sdma_v4_4_2_ring_emit_ib - Schedule an IB on the DMA engine 365 * 366 * @ring: amdgpu ring pointer 367 * @job: job to retrieve vmid from 368 * @ib: IB object to schedule 369 * @flags: unused 370 * 371 * Schedule an IB in the DMA ring. 372 */ 373 static void sdma_v4_4_2_ring_emit_ib(struct amdgpu_ring *ring, 374 struct amdgpu_job *job, 375 struct amdgpu_ib *ib, 376 uint32_t flags) 377 { 378 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 379 380 /* IB packet must end on a 8 DW boundary */ 381 sdma_v4_4_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 382 383 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 384 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 385 /* base must be 32 byte aligned */ 386 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 387 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 388 amdgpu_ring_write(ring, ib->length_dw); 389 amdgpu_ring_write(ring, 0); 390 amdgpu_ring_write(ring, 0); 391 392 } 393 394 static void sdma_v4_4_2_wait_reg_mem(struct amdgpu_ring *ring, 395 int mem_space, int hdp, 396 uint32_t addr0, uint32_t addr1, 397 uint32_t ref, uint32_t mask, 398 uint32_t inv) 399 { 400 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 401 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 402 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 403 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 404 if (mem_space) { 405 /* memory */ 406 amdgpu_ring_write(ring, addr0); 407 amdgpu_ring_write(ring, addr1); 408 } else { 409 /* registers */ 410 amdgpu_ring_write(ring, addr0 << 2); 411 amdgpu_ring_write(ring, addr1 << 2); 412 } 413 amdgpu_ring_write(ring, ref); /* reference */ 414 amdgpu_ring_write(ring, mask); /* mask */ 415 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 416 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 417 } 418 419 /** 420 * sdma_v4_4_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 421 * 422 * @ring: amdgpu ring pointer 423 * 424 * Emit an hdp flush packet on the requested DMA ring. 425 */ 426 static void sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 427 { 428 struct amdgpu_device *adev = ring->adev; 429 u32 ref_and_mask = 0; 430 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 431 432 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 433 << (ring->me % adev->sdma.num_inst_per_aid); 434 435 sdma_v4_4_2_wait_reg_mem(ring, 0, 1, 436 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 437 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 438 ref_and_mask, ref_and_mask, 10); 439 } 440 441 /** 442 * sdma_v4_4_2_ring_emit_fence - emit a fence on the DMA ring 443 * 444 * @ring: amdgpu ring pointer 445 * @addr: address 446 * @seq: sequence number 447 * @flags: fence related flags 448 * 449 * Add a DMA fence packet to the ring to write 450 * the fence seq number and DMA trap packet to generate 451 * an interrupt if needed. 452 */ 453 static void sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 454 unsigned flags) 455 { 456 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 457 /* write the fence */ 458 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 459 /* zero in first two bits */ 460 BUG_ON(addr & 0x3); 461 amdgpu_ring_write(ring, lower_32_bits(addr)); 462 amdgpu_ring_write(ring, upper_32_bits(addr)); 463 amdgpu_ring_write(ring, lower_32_bits(seq)); 464 465 /* optionally write high bits as well */ 466 if (write64bit) { 467 addr += 4; 468 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 469 /* zero in first two bits */ 470 BUG_ON(addr & 0x3); 471 amdgpu_ring_write(ring, lower_32_bits(addr)); 472 amdgpu_ring_write(ring, upper_32_bits(addr)); 473 amdgpu_ring_write(ring, upper_32_bits(seq)); 474 } 475 476 /* generate an interrupt */ 477 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 478 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 479 } 480 481 482 /** 483 * sdma_v4_4_2_inst_gfx_stop - stop the gfx async dma engines 484 * 485 * @adev: amdgpu_device pointer 486 * @inst_mask: mask of dma engine instances to be disabled 487 * 488 * Stop the gfx async dma ring buffers. 489 */ 490 static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev, 491 uint32_t inst_mask) 492 { 493 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 494 u32 doorbell_offset, doorbell; 495 u32 rb_cntl, ib_cntl; 496 int i; 497 498 for_each_inst(i, inst_mask) { 499 sdma[i] = &adev->sdma.instance[i].ring; 500 501 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); 502 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0); 503 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 504 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 505 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0); 506 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 507 508 if (sdma[i]->use_doorbell) { 509 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL); 510 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET); 511 512 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 0); 513 doorbell_offset = REG_SET_FIELD(doorbell_offset, 514 SDMA_GFX_DOORBELL_OFFSET, 515 OFFSET, 0); 516 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell); 517 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset); 518 } 519 } 520 } 521 522 /** 523 * sdma_v4_4_2_inst_rlc_stop - stop the compute async dma engines 524 * 525 * @adev: amdgpu_device pointer 526 * @inst_mask: mask of dma engine instances to be disabled 527 * 528 * Stop the compute async dma queues. 529 */ 530 static void sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device *adev, 531 uint32_t inst_mask) 532 { 533 /* XXX todo */ 534 } 535 536 /** 537 * sdma_v4_4_2_inst_page_stop - stop the page async dma engines 538 * 539 * @adev: amdgpu_device pointer 540 * @inst_mask: mask of dma engine instances to be disabled 541 * 542 * Stop the page async dma ring buffers. 543 */ 544 static void sdma_v4_4_2_inst_page_stop(struct amdgpu_device *adev, 545 uint32_t inst_mask) 546 { 547 u32 rb_cntl, ib_cntl; 548 int i; 549 550 for_each_inst(i, inst_mask) { 551 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); 552 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, 553 RB_ENABLE, 0); 554 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 555 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); 556 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, 557 IB_ENABLE, 0); 558 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); 559 } 560 } 561 562 /** 563 * sdma_v4_4_2_inst_ctx_switch_enable - stop the async dma engines context switch 564 * 565 * @adev: amdgpu_device pointer 566 * @enable: enable/disable the DMA MEs context switch. 567 * @inst_mask: mask of dma engine instances to be enabled 568 * 569 * Halt or unhalt the async dma engines context switch. 570 */ 571 static void sdma_v4_4_2_inst_ctx_switch_enable(struct amdgpu_device *adev, 572 bool enable, uint32_t inst_mask) 573 { 574 u32 f32_cntl, phase_quantum = 0; 575 int i; 576 577 if (amdgpu_sdma_phase_quantum) { 578 unsigned value = amdgpu_sdma_phase_quantum; 579 unsigned unit = 0; 580 581 while (value > (SDMA_PHASE0_QUANTUM__VALUE_MASK >> 582 SDMA_PHASE0_QUANTUM__VALUE__SHIFT)) { 583 value = (value + 1) >> 1; 584 unit++; 585 } 586 if (unit > (SDMA_PHASE0_QUANTUM__UNIT_MASK >> 587 SDMA_PHASE0_QUANTUM__UNIT__SHIFT)) { 588 value = (SDMA_PHASE0_QUANTUM__VALUE_MASK >> 589 SDMA_PHASE0_QUANTUM__VALUE__SHIFT); 590 unit = (SDMA_PHASE0_QUANTUM__UNIT_MASK >> 591 SDMA_PHASE0_QUANTUM__UNIT__SHIFT); 592 WARN_ONCE(1, 593 "clamping sdma_phase_quantum to %uK clock cycles\n", 594 value << unit); 595 } 596 phase_quantum = 597 value << SDMA_PHASE0_QUANTUM__VALUE__SHIFT | 598 unit << SDMA_PHASE0_QUANTUM__UNIT__SHIFT; 599 } 600 601 for_each_inst(i, inst_mask) { 602 f32_cntl = RREG32_SDMA(i, regSDMA_CNTL); 603 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_CNTL, 604 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 605 if (enable && amdgpu_sdma_phase_quantum) { 606 WREG32_SDMA(i, regSDMA_PHASE0_QUANTUM, phase_quantum); 607 WREG32_SDMA(i, regSDMA_PHASE1_QUANTUM, phase_quantum); 608 WREG32_SDMA(i, regSDMA_PHASE2_QUANTUM, phase_quantum); 609 } 610 WREG32_SDMA(i, regSDMA_CNTL, f32_cntl); 611 612 /* Extend page fault timeout to avoid interrupt storm */ 613 WREG32_SDMA(i, regSDMA_UTCL1_TIMEOUT, 0x00800080); 614 } 615 } 616 617 /** 618 * sdma_v4_4_2_inst_enable - stop the async dma engines 619 * 620 * @adev: amdgpu_device pointer 621 * @enable: enable/disable the DMA MEs. 622 * @inst_mask: mask of dma engine instances to be enabled 623 * 624 * Halt or unhalt the async dma engines. 625 */ 626 static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable, 627 uint32_t inst_mask) 628 { 629 u32 f32_cntl; 630 int i; 631 632 if (!enable) { 633 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask); 634 sdma_v4_4_2_inst_rlc_stop(adev, inst_mask); 635 if (adev->sdma.has_page_queue) 636 sdma_v4_4_2_inst_page_stop(adev, inst_mask); 637 638 /* SDMA FW needs to respond to FREEZE requests during reset. 639 * Keep it running during reset */ 640 if (!amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 641 return; 642 } 643 644 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 645 return; 646 647 for_each_inst(i, inst_mask) { 648 f32_cntl = RREG32_SDMA(i, regSDMA_F32_CNTL); 649 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1); 650 WREG32_SDMA(i, regSDMA_F32_CNTL, f32_cntl); 651 } 652 } 653 654 /* 655 * sdma_v4_4_2_rb_cntl - get parameters for rb_cntl 656 */ 657 static uint32_t sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 658 { 659 /* Set ring buffer size in dwords */ 660 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 661 662 barrier(); /* work around https://llvm.org/pr42576 */ 663 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 664 #ifdef __BIG_ENDIAN 665 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 666 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, 667 RPTR_WRITEBACK_SWAP_ENABLE, 1); 668 #endif 669 return rb_cntl; 670 } 671 672 /** 673 * sdma_v4_4_2_gfx_resume - setup and start the async dma engines 674 * 675 * @adev: amdgpu_device pointer 676 * @i: instance to resume 677 * @restore: used to restore wptr when restart 678 * 679 * Set up the gfx DMA ring buffers and enable them. 680 * Returns 0 for success, error for failure. 681 */ 682 static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i, bool restore) 683 { 684 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 685 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 686 u32 wb_offset; 687 u32 doorbell; 688 u32 doorbell_offset; 689 u64 wptr_gpu_addr; 690 u64 rwptr; 691 692 wb_offset = (ring->rptr_offs * 4); 693 694 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); 695 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 696 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 697 698 /* set the wb address whether it's enabled or not */ 699 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_HI, 700 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 701 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_LO, 702 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 703 704 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, 705 RPTR_WRITEBACK_ENABLE, 1); 706 707 WREG32_SDMA(i, regSDMA_GFX_RB_BASE, ring->gpu_addr >> 8); 708 WREG32_SDMA(i, regSDMA_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 709 710 if (!restore) 711 ring->wptr = 0; 712 713 /* before programing wptr to a less value, need set minor_ptr_update first */ 714 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 1); 715 716 /* For the guilty queue, set RPTR to the current wptr to skip bad commands, 717 * It is not a guilty queue, restore cache_rptr and continue execution. 718 */ 719 if (adev->sdma.instance[i].gfx_guilty) 720 rwptr = ring->wptr; 721 else 722 rwptr = ring->cached_rptr; 723 724 /* Initialize the ring buffer's read and write pointers */ 725 if (restore) { 726 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, lower_32_bits(rwptr << 2)); 727 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, upper_32_bits(rwptr << 2)); 728 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, lower_32_bits(rwptr << 2)); 729 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, upper_32_bits(rwptr << 2)); 730 } else { 731 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0); 732 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0); 733 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0); 734 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0); 735 } 736 737 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL); 738 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET); 739 740 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 741 ring->use_doorbell); 742 doorbell_offset = REG_SET_FIELD(doorbell_offset, 743 SDMA_GFX_DOORBELL_OFFSET, 744 OFFSET, ring->doorbell_index); 745 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell); 746 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset); 747 748 sdma_v4_4_2_ring_set_wptr(ring); 749 750 /* set minor_ptr_update to 0 after wptr programed */ 751 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 0); 752 753 /* setup the wptr shadow polling */ 754 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 755 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_LO, 756 lower_32_bits(wptr_gpu_addr)); 757 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_HI, 758 upper_32_bits(wptr_gpu_addr)); 759 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL); 760 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 761 SDMA_GFX_RB_WPTR_POLL_CNTL, 762 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 763 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 764 765 /* enable DMA RB */ 766 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 1); 767 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 768 769 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 770 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 1); 771 #ifdef __BIG_ENDIAN 772 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 773 #endif 774 /* enable DMA IBs */ 775 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 776 } 777 778 /** 779 * sdma_v4_4_2_page_resume - setup and start the async dma engines 780 * 781 * @adev: amdgpu_device pointer 782 * @i: instance to resume 783 * @restore: boolean to say restore needed or not 784 * 785 * Set up the page DMA ring buffers and enable them. 786 * Returns 0 for success, error for failure. 787 */ 788 static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i, bool restore) 789 { 790 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 791 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 792 u32 wb_offset; 793 u32 doorbell; 794 u32 doorbell_offset; 795 u64 wptr_gpu_addr; 796 u64 rwptr; 797 798 wb_offset = (ring->rptr_offs * 4); 799 800 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); 801 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 802 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 803 804 /* For the guilty queue, set RPTR to the current wptr to skip bad commands, 805 * It is not a guilty queue, restore cache_rptr and continue execution. 806 */ 807 if (adev->sdma.instance[i].page_guilty) 808 rwptr = ring->wptr; 809 else 810 rwptr = ring->cached_rptr; 811 812 /* Initialize the ring buffer's read and write pointers */ 813 if (restore) { 814 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, lower_32_bits(rwptr << 2)); 815 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, upper_32_bits(rwptr << 2)); 816 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, lower_32_bits(rwptr << 2)); 817 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, upper_32_bits(rwptr << 2)); 818 } else { 819 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, 0); 820 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, 0); 821 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, 0); 822 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, 0); 823 } 824 825 /* set the wb address whether it's enabled or not */ 826 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_HI, 827 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 828 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_LO, 829 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 830 831 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, 832 RPTR_WRITEBACK_ENABLE, 1); 833 834 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE, ring->gpu_addr >> 8); 835 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 836 837 if (!restore) 838 ring->wptr = 0; 839 840 /* before programing wptr to a less value, need set minor_ptr_update first */ 841 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 1); 842 843 doorbell = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL); 844 doorbell_offset = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET); 845 846 doorbell = REG_SET_FIELD(doorbell, SDMA_PAGE_DOORBELL, ENABLE, 847 ring->use_doorbell); 848 doorbell_offset = REG_SET_FIELD(doorbell_offset, 849 SDMA_PAGE_DOORBELL_OFFSET, 850 OFFSET, ring->doorbell_index); 851 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL, doorbell); 852 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET, doorbell_offset); 853 854 /* paging queue doorbell range is setup at sdma_v4_4_2_gfx_resume */ 855 sdma_v4_4_2_page_ring_set_wptr(ring); 856 857 /* set minor_ptr_update to 0 after wptr programed */ 858 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 0); 859 860 /* setup the wptr shadow polling */ 861 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 862 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_LO, 863 lower_32_bits(wptr_gpu_addr)); 864 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_HI, 865 upper_32_bits(wptr_gpu_addr)); 866 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL); 867 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 868 SDMA_PAGE_RB_WPTR_POLL_CNTL, 869 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 870 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 871 872 /* enable DMA RB */ 873 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, RB_ENABLE, 1); 874 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 875 876 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); 877 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_ENABLE, 1); 878 #ifdef __BIG_ENDIAN 879 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 880 #endif 881 /* enable DMA IBs */ 882 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); 883 } 884 885 static void sdma_v4_4_2_init_pg(struct amdgpu_device *adev) 886 { 887 888 } 889 890 /** 891 * sdma_v4_4_2_inst_rlc_resume - setup and start the async dma engines 892 * 893 * @adev: amdgpu_device pointer 894 * @inst_mask: mask of dma engine instances to be enabled 895 * 896 * Set up the compute DMA queues and enable them. 897 * Returns 0 for success, error for failure. 898 */ 899 static int sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device *adev, 900 uint32_t inst_mask) 901 { 902 sdma_v4_4_2_init_pg(adev); 903 904 return 0; 905 } 906 907 /** 908 * sdma_v4_4_2_inst_load_microcode - load the sDMA ME ucode 909 * 910 * @adev: amdgpu_device pointer 911 * @inst_mask: mask of dma engine instances to be enabled 912 * 913 * Loads the sDMA0/1 ucode. 914 * Returns 0 for success, -EINVAL if the ucode is not available. 915 */ 916 static int sdma_v4_4_2_inst_load_microcode(struct amdgpu_device *adev, 917 uint32_t inst_mask) 918 { 919 const struct sdma_firmware_header_v1_0 *hdr; 920 const __le32 *fw_data; 921 u32 fw_size; 922 int i, j; 923 924 /* halt the MEs */ 925 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 926 927 for_each_inst(i, inst_mask) { 928 if (!adev->sdma.instance[i].fw) 929 return -EINVAL; 930 931 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 932 amdgpu_ucode_print_sdma_hdr(&hdr->header); 933 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 934 935 fw_data = (const __le32 *) 936 (adev->sdma.instance[i].fw->data + 937 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 938 939 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 0); 940 941 for (j = 0; j < fw_size; j++) 942 WREG32_SDMA(i, regSDMA_UCODE_DATA, 943 le32_to_cpup(fw_data++)); 944 945 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 946 adev->sdma.instance[i].fw_version); 947 } 948 949 return 0; 950 } 951 952 /** 953 * sdma_v4_4_2_inst_start - setup and start the async dma engines 954 * 955 * @adev: amdgpu_device pointer 956 * @inst_mask: mask of dma engine instances to be enabled 957 * @restore: boolean to say restore needed or not 958 * 959 * Set up the DMA engines and enable them. 960 * Returns 0 for success, error for failure. 961 */ 962 static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev, 963 uint32_t inst_mask, bool restore) 964 { 965 struct amdgpu_ring *ring; 966 uint32_t tmp_mask; 967 int i, r = 0; 968 969 if (amdgpu_sriov_vf(adev)) { 970 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 971 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 972 } else { 973 /* bypass sdma microcode loading on Gopher */ 974 if (!restore && adev->firmware.load_type != AMDGPU_FW_LOAD_PSP && 975 adev->sdma.instance[0].fw) { 976 r = sdma_v4_4_2_inst_load_microcode(adev, inst_mask); 977 if (r) 978 return r; 979 } 980 981 /* unhalt the MEs */ 982 sdma_v4_4_2_inst_enable(adev, true, inst_mask); 983 /* enable sdma ring preemption */ 984 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask); 985 } 986 987 /* start the gfx rings and rlc compute queues */ 988 tmp_mask = inst_mask; 989 for_each_inst(i, tmp_mask) { 990 uint32_t temp; 991 992 WREG32_SDMA(i, regSDMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); 993 sdma_v4_4_2_gfx_resume(adev, i, restore); 994 if (adev->sdma.has_page_queue) 995 sdma_v4_4_2_page_resume(adev, i, restore); 996 997 /* set utc l1 enable flag always to 1 */ 998 temp = RREG32_SDMA(i, regSDMA_CNTL); 999 temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1); 1000 1001 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) < IP_VERSION(4, 4, 5)) { 1002 /* enable context empty interrupt during initialization */ 1003 temp = REG_SET_FIELD(temp, SDMA_CNTL, CTXEMPTY_INT_ENABLE, 1); 1004 WREG32_SDMA(i, regSDMA_CNTL, temp); 1005 } 1006 if (!amdgpu_sriov_vf(adev)) { 1007 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1008 /* unhalt engine */ 1009 temp = RREG32_SDMA(i, regSDMA_F32_CNTL); 1010 temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0); 1011 WREG32_SDMA(i, regSDMA_F32_CNTL, temp); 1012 } 1013 } 1014 } 1015 1016 if (amdgpu_sriov_vf(adev)) { 1017 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask); 1018 sdma_v4_4_2_inst_enable(adev, true, inst_mask); 1019 } else { 1020 r = sdma_v4_4_2_inst_rlc_resume(adev, inst_mask); 1021 if (r) 1022 return r; 1023 } 1024 1025 tmp_mask = inst_mask; 1026 for_each_inst(i, tmp_mask) { 1027 ring = &adev->sdma.instance[i].ring; 1028 1029 r = amdgpu_ring_test_helper(ring); 1030 if (r) 1031 return r; 1032 1033 if (adev->sdma.has_page_queue) { 1034 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 1035 1036 r = amdgpu_ring_test_helper(page); 1037 if (r) 1038 return r; 1039 } 1040 } 1041 1042 return r; 1043 } 1044 1045 /** 1046 * sdma_v4_4_2_ring_test_ring - simple async dma engine test 1047 * 1048 * @ring: amdgpu_ring structure holding ring information 1049 * 1050 * Test the DMA engine by writing using it to write an 1051 * value to memory. 1052 * Returns 0 for success, error for failure. 1053 */ 1054 static int sdma_v4_4_2_ring_test_ring(struct amdgpu_ring *ring) 1055 { 1056 struct amdgpu_device *adev = ring->adev; 1057 unsigned i; 1058 unsigned index; 1059 int r; 1060 u32 tmp; 1061 u64 gpu_addr; 1062 1063 r = amdgpu_device_wb_get(adev, &index); 1064 if (r) 1065 return r; 1066 1067 gpu_addr = adev->wb.gpu_addr + (index * 4); 1068 tmp = 0xCAFEDEAD; 1069 adev->wb.wb[index] = cpu_to_le32(tmp); 1070 1071 r = amdgpu_ring_alloc(ring, 5); 1072 if (r) 1073 goto error_free_wb; 1074 1075 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1076 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1077 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1078 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1079 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1080 amdgpu_ring_write(ring, 0xDEADBEEF); 1081 amdgpu_ring_commit(ring); 1082 1083 for (i = 0; i < adev->usec_timeout; i++) { 1084 tmp = le32_to_cpu(adev->wb.wb[index]); 1085 if (tmp == 0xDEADBEEF) 1086 break; 1087 udelay(1); 1088 } 1089 1090 if (i >= adev->usec_timeout) 1091 r = -ETIMEDOUT; 1092 1093 error_free_wb: 1094 amdgpu_device_wb_free(adev, index); 1095 return r; 1096 } 1097 1098 /** 1099 * sdma_v4_4_2_ring_test_ib - test an IB on the DMA engine 1100 * 1101 * @ring: amdgpu_ring structure holding ring information 1102 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1103 * 1104 * Test a simple IB in the DMA ring. 1105 * Returns 0 on success, error on failure. 1106 */ 1107 static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1108 { 1109 struct amdgpu_device *adev = ring->adev; 1110 struct amdgpu_ib ib; 1111 struct dma_fence *f = NULL; 1112 unsigned index; 1113 long r; 1114 u32 tmp = 0; 1115 u64 gpu_addr; 1116 1117 r = amdgpu_device_wb_get(adev, &index); 1118 if (r) 1119 return r; 1120 1121 gpu_addr = adev->wb.gpu_addr + (index * 4); 1122 tmp = 0xCAFEDEAD; 1123 adev->wb.wb[index] = cpu_to_le32(tmp); 1124 memset(&ib, 0, sizeof(ib)); 1125 r = amdgpu_ib_get(adev, NULL, 256, 1126 AMDGPU_IB_POOL_DIRECT, &ib); 1127 if (r) 1128 goto err0; 1129 1130 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1131 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1132 ib.ptr[1] = lower_32_bits(gpu_addr); 1133 ib.ptr[2] = upper_32_bits(gpu_addr); 1134 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1135 ib.ptr[4] = 0xDEADBEEF; 1136 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1137 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1138 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1139 ib.length_dw = 8; 1140 1141 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1142 if (r) 1143 goto err1; 1144 1145 r = dma_fence_wait_timeout(f, false, timeout); 1146 if (r == 0) { 1147 r = -ETIMEDOUT; 1148 goto err1; 1149 } else if (r < 0) { 1150 goto err1; 1151 } 1152 tmp = le32_to_cpu(adev->wb.wb[index]); 1153 if (tmp == 0xDEADBEEF) 1154 r = 0; 1155 else 1156 r = -EINVAL; 1157 1158 err1: 1159 amdgpu_ib_free(&ib, NULL); 1160 dma_fence_put(f); 1161 err0: 1162 amdgpu_device_wb_free(adev, index); 1163 return r; 1164 } 1165 1166 1167 /** 1168 * sdma_v4_4_2_vm_copy_pte - update PTEs by copying them from the GART 1169 * 1170 * @ib: indirect buffer to fill with commands 1171 * @pe: addr of the page entry 1172 * @src: src addr to copy from 1173 * @count: number of page entries to update 1174 * 1175 * Update PTEs by copying them from the GART using sDMA. 1176 */ 1177 static void sdma_v4_4_2_vm_copy_pte(struct amdgpu_ib *ib, 1178 uint64_t pe, uint64_t src, 1179 unsigned count) 1180 { 1181 unsigned bytes = count * 8; 1182 1183 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1184 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1185 ib->ptr[ib->length_dw++] = bytes - 1; 1186 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1187 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1188 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1189 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1190 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1191 1192 } 1193 1194 /** 1195 * sdma_v4_4_2_vm_write_pte - update PTEs by writing them manually 1196 * 1197 * @ib: indirect buffer to fill with commands 1198 * @pe: addr of the page entry 1199 * @value: dst addr to write into pe 1200 * @count: number of page entries to update 1201 * @incr: increase next addr by incr bytes 1202 * 1203 * Update PTEs by writing them manually using sDMA. 1204 */ 1205 static void sdma_v4_4_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1206 uint64_t value, unsigned count, 1207 uint32_t incr) 1208 { 1209 unsigned ndw = count * 2; 1210 1211 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1212 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1213 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1214 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1215 ib->ptr[ib->length_dw++] = ndw - 1; 1216 for (; ndw > 0; ndw -= 2) { 1217 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1218 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1219 value += incr; 1220 } 1221 } 1222 1223 /** 1224 * sdma_v4_4_2_vm_set_pte_pde - update the page tables using sDMA 1225 * 1226 * @ib: indirect buffer to fill with commands 1227 * @pe: addr of the page entry 1228 * @addr: dst addr to write into pe 1229 * @count: number of page entries to update 1230 * @incr: increase next addr by incr bytes 1231 * @flags: access flags 1232 * 1233 * Update the page tables using sDMA. 1234 */ 1235 static void sdma_v4_4_2_vm_set_pte_pde(struct amdgpu_ib *ib, 1236 uint64_t pe, 1237 uint64_t addr, unsigned count, 1238 uint32_t incr, uint64_t flags) 1239 { 1240 /* for physically contiguous pages (vram) */ 1241 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1242 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1243 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1244 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1245 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1246 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1247 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1248 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1249 ib->ptr[ib->length_dw++] = 0; 1250 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1251 } 1252 1253 /** 1254 * sdma_v4_4_2_ring_pad_ib - pad the IB to the required number of dw 1255 * 1256 * @ring: amdgpu_ring structure holding ring information 1257 * @ib: indirect buffer to fill with padding 1258 */ 1259 static void sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1260 { 1261 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1262 u32 pad_count; 1263 int i; 1264 1265 pad_count = (-ib->length_dw) & 7; 1266 for (i = 0; i < pad_count; i++) 1267 if (sdma && sdma->burst_nop && (i == 0)) 1268 ib->ptr[ib->length_dw++] = 1269 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1270 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1271 else 1272 ib->ptr[ib->length_dw++] = 1273 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1274 } 1275 1276 1277 /** 1278 * sdma_v4_4_2_ring_emit_pipeline_sync - sync the pipeline 1279 * 1280 * @ring: amdgpu_ring pointer 1281 * 1282 * Make sure all previous operations are completed (CIK). 1283 */ 1284 static void sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1285 { 1286 uint32_t seq = ring->fence_drv.sync_seq; 1287 uint64_t addr = ring->fence_drv.gpu_addr; 1288 1289 /* wait for idle */ 1290 sdma_v4_4_2_wait_reg_mem(ring, 1, 0, 1291 addr & 0xfffffffc, 1292 upper_32_bits(addr) & 0xffffffff, 1293 seq, 0xffffffff, 4); 1294 } 1295 1296 1297 /** 1298 * sdma_v4_4_2_ring_emit_vm_flush - vm flush using sDMA 1299 * 1300 * @ring: amdgpu_ring pointer 1301 * @vmid: vmid number to use 1302 * @pd_addr: address 1303 * 1304 * Update the page table base and flush the VM TLB 1305 * using sDMA. 1306 */ 1307 static void sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring *ring, 1308 unsigned vmid, uint64_t pd_addr) 1309 { 1310 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1311 } 1312 1313 static void sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring *ring, 1314 uint32_t reg, uint32_t val) 1315 { 1316 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1317 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1318 amdgpu_ring_write(ring, reg); 1319 amdgpu_ring_write(ring, val); 1320 } 1321 1322 static void sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1323 uint32_t val, uint32_t mask) 1324 { 1325 sdma_v4_4_2_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1326 } 1327 1328 static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev) 1329 { 1330 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1331 case IP_VERSION(4, 4, 2): 1332 case IP_VERSION(4, 4, 5): 1333 return false; 1334 default: 1335 return false; 1336 } 1337 } 1338 1339 static const struct amdgpu_sdma_funcs sdma_v4_4_2_sdma_funcs = { 1340 .stop_kernel_queue = &sdma_v4_4_2_stop_queue, 1341 .start_kernel_queue = &sdma_v4_4_2_restore_queue, 1342 .soft_reset_kernel_queue = &sdma_v4_4_2_soft_reset_engine, 1343 }; 1344 1345 static int sdma_v4_4_2_early_init(struct amdgpu_ip_block *ip_block) 1346 { 1347 struct amdgpu_device *adev = ip_block->adev; 1348 int r; 1349 1350 r = sdma_v4_4_2_init_microcode(adev); 1351 if (r) 1352 return r; 1353 1354 /* TODO: Page queue breaks driver reload under SRIOV */ 1355 if (sdma_v4_4_2_fw_support_paging_queue(adev)) 1356 adev->sdma.has_page_queue = true; 1357 1358 sdma_v4_4_2_set_ring_funcs(adev); 1359 sdma_v4_4_2_set_buffer_funcs(adev); 1360 sdma_v4_4_2_set_vm_pte_funcs(adev); 1361 sdma_v4_4_2_set_irq_funcs(adev); 1362 sdma_v4_4_2_set_ras_funcs(adev); 1363 return 0; 1364 } 1365 1366 #if 0 1367 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, 1368 void *err_data, 1369 struct amdgpu_iv_entry *entry); 1370 #endif 1371 1372 static int sdma_v4_4_2_late_init(struct amdgpu_ip_block *ip_block) 1373 { 1374 struct amdgpu_device *adev = ip_block->adev; 1375 #if 0 1376 struct ras_ih_if ih_info = { 1377 .cb = sdma_v4_4_2_process_ras_data_cb, 1378 }; 1379 #endif 1380 if (!amdgpu_persistent_edc_harvesting_supported(adev)) 1381 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__SDMA); 1382 1383 /* The initialization is done in the late_init stage to ensure that the SMU 1384 * initialization and capability setup are completed before we check the SDMA 1385 * reset capability 1386 */ 1387 sdma_v4_4_2_update_reset_mask(adev); 1388 1389 return 0; 1390 } 1391 1392 static int sdma_v4_4_2_sw_init(struct amdgpu_ip_block *ip_block) 1393 { 1394 struct amdgpu_ring *ring; 1395 int r, i; 1396 struct amdgpu_device *adev = ip_block->adev; 1397 u32 aid_id; 1398 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); 1399 uint32_t *ptr; 1400 1401 /* SDMA trap event */ 1402 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1403 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1404 SDMA0_4_0__SRCID__SDMA_TRAP, 1405 &adev->sdma.trap_irq); 1406 if (r) 1407 return r; 1408 } 1409 1410 /* SDMA SRAM ECC event */ 1411 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1412 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1413 SDMA0_4_0__SRCID__SDMA_SRAM_ECC, 1414 &adev->sdma.ecc_irq); 1415 if (r) 1416 return r; 1417 } 1418 1419 /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/ 1420 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1421 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1422 SDMA0_4_0__SRCID__SDMA_VM_HOLE, 1423 &adev->sdma.vm_hole_irq); 1424 if (r) 1425 return r; 1426 1427 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1428 SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID, 1429 &adev->sdma.doorbell_invalid_irq); 1430 if (r) 1431 return r; 1432 1433 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1434 SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT, 1435 &adev->sdma.pool_timeout_irq); 1436 if (r) 1437 return r; 1438 1439 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1440 SDMA0_4_0__SRCID__SDMA_SRBMWRITE, 1441 &adev->sdma.srbm_write_irq); 1442 if (r) 1443 return r; 1444 1445 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1446 SDMA0_4_0__SRCID__SDMA_CTXEMPTY, 1447 &adev->sdma.ctxt_empty_irq); 1448 if (r) 1449 return r; 1450 } 1451 1452 for (i = 0; i < adev->sdma.num_instances; i++) { 1453 mutex_init(&adev->sdma.instance[i].engine_reset_mutex); 1454 /* Initialize guilty flags for GFX and PAGE queues */ 1455 adev->sdma.instance[i].gfx_guilty = false; 1456 adev->sdma.instance[i].page_guilty = false; 1457 adev->sdma.instance[i].funcs = &sdma_v4_4_2_sdma_funcs; 1458 1459 ring = &adev->sdma.instance[i].ring; 1460 ring->ring_obj = NULL; 1461 ring->use_doorbell = true; 1462 aid_id = adev->sdma.instance[i].aid_id; 1463 1464 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1465 ring->use_doorbell?"true":"false"); 1466 1467 /* doorbell size is 2 dwords, get DWORD offset */ 1468 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1469 ring->vm_hub = AMDGPU_MMHUB0(aid_id); 1470 1471 sprintf(ring->name, "sdma%d.%d", aid_id, 1472 i % adev->sdma.num_inst_per_aid); 1473 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1474 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1475 AMDGPU_RING_PRIO_DEFAULT, NULL); 1476 if (r) 1477 return r; 1478 1479 if (adev->sdma.has_page_queue) { 1480 ring = &adev->sdma.instance[i].page; 1481 ring->ring_obj = NULL; 1482 ring->use_doorbell = true; 1483 1484 /* doorbell index of page queue is assigned right after 1485 * gfx queue on the same instance 1486 */ 1487 ring->doorbell_index = 1488 (adev->doorbell_index.sdma_engine[i] + 1) << 1; 1489 ring->vm_hub = AMDGPU_MMHUB0(aid_id); 1490 1491 sprintf(ring->name, "page%d.%d", aid_id, 1492 i % adev->sdma.num_inst_per_aid); 1493 r = amdgpu_ring_init(adev, ring, 1024, 1494 &adev->sdma.trap_irq, 1495 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1496 AMDGPU_RING_PRIO_DEFAULT, NULL); 1497 if (r) 1498 return r; 1499 } 1500 } 1501 1502 adev->sdma.supported_reset = 1503 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); 1504 1505 if (amdgpu_sdma_ras_sw_init(adev)) { 1506 dev_err(adev->dev, "fail to initialize sdma ras block\n"); 1507 return -EINVAL; 1508 } 1509 1510 /* Allocate memory for SDMA IP Dump buffer */ 1511 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); 1512 if (ptr) 1513 adev->sdma.ip_dump = ptr; 1514 else 1515 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n"); 1516 1517 r = amdgpu_sdma_sysfs_reset_mask_init(adev); 1518 if (r) 1519 return r; 1520 1521 return r; 1522 } 1523 1524 static int sdma_v4_4_2_sw_fini(struct amdgpu_ip_block *ip_block) 1525 { 1526 struct amdgpu_device *adev = ip_block->adev; 1527 int i; 1528 1529 for (i = 0; i < adev->sdma.num_instances; i++) { 1530 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1531 if (adev->sdma.has_page_queue) 1532 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1533 } 1534 1535 amdgpu_sdma_sysfs_reset_mask_fini(adev); 1536 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) || 1537 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 4) || 1538 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) 1539 amdgpu_sdma_destroy_inst_ctx(adev, true); 1540 else 1541 amdgpu_sdma_destroy_inst_ctx(adev, false); 1542 1543 kfree(adev->sdma.ip_dump); 1544 1545 return 0; 1546 } 1547 1548 static int sdma_v4_4_2_hw_init(struct amdgpu_ip_block *ip_block) 1549 { 1550 int r; 1551 struct amdgpu_device *adev = ip_block->adev; 1552 uint32_t inst_mask; 1553 1554 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1555 if (!amdgpu_sriov_vf(adev)) 1556 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask); 1557 1558 r = sdma_v4_4_2_inst_start(adev, inst_mask, false); 1559 1560 return r; 1561 } 1562 1563 static int sdma_v4_4_2_hw_fini(struct amdgpu_ip_block *ip_block) 1564 { 1565 struct amdgpu_device *adev = ip_block->adev; 1566 uint32_t inst_mask; 1567 int i; 1568 1569 if (amdgpu_sriov_vf(adev)) 1570 return 0; 1571 1572 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1573 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 1574 for (i = 0; i < adev->sdma.num_instances; i++) { 1575 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 1576 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1577 } 1578 } 1579 1580 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 1581 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 1582 1583 return 0; 1584 } 1585 1586 static int sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1587 enum amd_clockgating_state state); 1588 1589 static int sdma_v4_4_2_suspend(struct amdgpu_ip_block *ip_block) 1590 { 1591 struct amdgpu_device *adev = ip_block->adev; 1592 1593 if (amdgpu_in_reset(adev)) 1594 sdma_v4_4_2_set_clockgating_state(ip_block, AMD_CG_STATE_UNGATE); 1595 1596 return sdma_v4_4_2_hw_fini(ip_block); 1597 } 1598 1599 static int sdma_v4_4_2_resume(struct amdgpu_ip_block *ip_block) 1600 { 1601 return sdma_v4_4_2_hw_init(ip_block); 1602 } 1603 1604 static bool sdma_v4_4_2_is_idle(struct amdgpu_ip_block *ip_block) 1605 { 1606 struct amdgpu_device *adev = ip_block->adev; 1607 u32 i; 1608 1609 for (i = 0; i < adev->sdma.num_instances; i++) { 1610 u32 tmp = RREG32_SDMA(i, regSDMA_STATUS_REG); 1611 1612 if (!(tmp & SDMA_STATUS_REG__IDLE_MASK)) 1613 return false; 1614 } 1615 1616 return true; 1617 } 1618 1619 static int sdma_v4_4_2_wait_for_idle(struct amdgpu_ip_block *ip_block) 1620 { 1621 unsigned i, j; 1622 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; 1623 struct amdgpu_device *adev = ip_block->adev; 1624 1625 for (i = 0; i < adev->usec_timeout; i++) { 1626 for (j = 0; j < adev->sdma.num_instances; j++) { 1627 sdma[j] = RREG32_SDMA(j, regSDMA_STATUS_REG); 1628 if (!(sdma[j] & SDMA_STATUS_REG__IDLE_MASK)) 1629 break; 1630 } 1631 if (j == adev->sdma.num_instances) 1632 return 0; 1633 udelay(1); 1634 } 1635 return -ETIMEDOUT; 1636 } 1637 1638 static int sdma_v4_4_2_soft_reset(struct amdgpu_ip_block *ip_block) 1639 { 1640 /* todo */ 1641 1642 return 0; 1643 } 1644 1645 static bool sdma_v4_4_2_is_queue_selected(struct amdgpu_device *adev, uint32_t instance_id, bool is_page_queue) 1646 { 1647 uint32_t reg_offset = is_page_queue ? regSDMA_PAGE_CONTEXT_STATUS : regSDMA_GFX_CONTEXT_STATUS; 1648 uint32_t context_status = RREG32(sdma_v4_4_2_get_reg_offset(adev, instance_id, reg_offset)); 1649 1650 /* Check if the SELECTED bit is set */ 1651 return (context_status & SDMA_GFX_CONTEXT_STATUS__SELECTED_MASK) != 0; 1652 } 1653 1654 static bool sdma_v4_4_2_ring_is_guilty(struct amdgpu_ring *ring) 1655 { 1656 struct amdgpu_device *adev = ring->adev; 1657 uint32_t instance_id = ring->me; 1658 1659 return sdma_v4_4_2_is_queue_selected(adev, instance_id, false); 1660 } 1661 1662 static bool sdma_v4_4_2_page_ring_is_guilty(struct amdgpu_ring *ring) 1663 { 1664 struct amdgpu_device *adev = ring->adev; 1665 uint32_t instance_id = ring->me; 1666 1667 if (!adev->sdma.has_page_queue) 1668 return false; 1669 1670 return sdma_v4_4_2_is_queue_selected(adev, instance_id, true); 1671 } 1672 1673 static int sdma_v4_4_2_reset_queue(struct amdgpu_ring *ring, unsigned int vmid) 1674 { 1675 struct amdgpu_device *adev = ring->adev; 1676 u32 id = ring->me; 1677 int r; 1678 1679 if (!(adev->sdma.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) 1680 return -EOPNOTSUPP; 1681 1682 amdgpu_amdkfd_suspend(adev, true); 1683 r = amdgpu_sdma_reset_engine(adev, id); 1684 amdgpu_amdkfd_resume(adev, true); 1685 1686 return r; 1687 } 1688 1689 static int sdma_v4_4_2_stop_queue(struct amdgpu_ring *ring) 1690 { 1691 struct amdgpu_device *adev = ring->adev; 1692 u32 instance_id = ring->me; 1693 u32 inst_mask; 1694 uint64_t rptr; 1695 1696 if (amdgpu_sriov_vf(adev)) 1697 return -EINVAL; 1698 1699 /* Check if this queue is the guilty one */ 1700 adev->sdma.instance[instance_id].gfx_guilty = 1701 sdma_v4_4_2_is_queue_selected(adev, instance_id, false); 1702 if (adev->sdma.has_page_queue) 1703 adev->sdma.instance[instance_id].page_guilty = 1704 sdma_v4_4_2_is_queue_selected(adev, instance_id, true); 1705 1706 /* Cache the rptr before reset, after the reset, 1707 * all of the registers will be reset to 0 1708 */ 1709 rptr = amdgpu_ring_get_rptr(ring); 1710 ring->cached_rptr = rptr; 1711 /* Cache the rptr for the page queue if it exists */ 1712 if (adev->sdma.has_page_queue) { 1713 struct amdgpu_ring *page_ring = &adev->sdma.instance[instance_id].page; 1714 rptr = amdgpu_ring_get_rptr(page_ring); 1715 page_ring->cached_rptr = rptr; 1716 } 1717 1718 /* stop queue */ 1719 inst_mask = 1 << ring->me; 1720 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask); 1721 if (adev->sdma.has_page_queue) 1722 sdma_v4_4_2_inst_page_stop(adev, inst_mask); 1723 1724 return 0; 1725 } 1726 1727 static int sdma_v4_4_2_restore_queue(struct amdgpu_ring *ring) 1728 { 1729 struct amdgpu_device *adev = ring->adev; 1730 u32 inst_mask; 1731 int i; 1732 1733 inst_mask = 1 << ring->me; 1734 udelay(50); 1735 1736 for (i = 0; i < adev->usec_timeout; i++) { 1737 if (!REG_GET_FIELD(RREG32_SDMA(ring->me, regSDMA_F32_CNTL), SDMA_F32_CNTL, HALT)) 1738 break; 1739 udelay(1); 1740 } 1741 1742 if (i == adev->usec_timeout) { 1743 dev_err(adev->dev, "timed out waiting for SDMA%d unhalt after reset\n", 1744 ring->me); 1745 return -ETIMEDOUT; 1746 } 1747 1748 return sdma_v4_4_2_inst_start(adev, inst_mask, true); 1749 } 1750 1751 static int sdma_v4_4_2_soft_reset_engine(struct amdgpu_device *adev, 1752 u32 instance_id) 1753 { 1754 /* For SDMA 4.x, use the existing DPM interface for backward compatibility 1755 * we need to convert the logical instance ID to physical instance ID before reset. 1756 */ 1757 return amdgpu_dpm_reset_sdma(adev, 1 << GET_INST(SDMA0, instance_id)); 1758 } 1759 1760 static int sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device *adev, 1761 struct amdgpu_irq_src *source, 1762 unsigned type, 1763 enum amdgpu_interrupt_state state) 1764 { 1765 u32 sdma_cntl; 1766 1767 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); 1768 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE, 1769 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1770 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); 1771 1772 return 0; 1773 } 1774 1775 static int sdma_v4_4_2_process_trap_irq(struct amdgpu_device *adev, 1776 struct amdgpu_irq_src *source, 1777 struct amdgpu_iv_entry *entry) 1778 { 1779 uint32_t instance, i; 1780 1781 DRM_DEBUG("IH: SDMA trap\n"); 1782 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1783 1784 /* Client id gives the SDMA instance in AID. To know the exact SDMA 1785 * instance, interrupt entry gives the node id which corresponds to the AID instance. 1786 * Match node id with the AID id associated with the SDMA instance. */ 1787 for (i = instance; i < adev->sdma.num_instances; 1788 i += adev->sdma.num_inst_per_aid) { 1789 if (adev->sdma.instance[i].aid_id == 1790 node_id_to_phys_map[entry->node_id]) 1791 break; 1792 } 1793 1794 if (i >= adev->sdma.num_instances) { 1795 dev_WARN_ONCE( 1796 adev->dev, 1, 1797 "Couldn't find the right sdma instance in trap handler"); 1798 return 0; 1799 } 1800 1801 switch (entry->ring_id) { 1802 case 0: 1803 amdgpu_fence_process(&adev->sdma.instance[i].ring); 1804 break; 1805 case 1: 1806 amdgpu_fence_process(&adev->sdma.instance[i].page); 1807 break; 1808 default: 1809 break; 1810 } 1811 return 0; 1812 } 1813 1814 #if 0 1815 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, 1816 void *err_data, 1817 struct amdgpu_iv_entry *entry) 1818 { 1819 int instance; 1820 1821 /* When “Full RAS” is enabled, the per-IP interrupt sources should 1822 * be disabled and the driver should only look for the aggregated 1823 * interrupt via sync flood 1824 */ 1825 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) 1826 goto out; 1827 1828 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1829 if (instance < 0) 1830 goto out; 1831 1832 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry); 1833 1834 out: 1835 return AMDGPU_RAS_SUCCESS; 1836 } 1837 #endif 1838 1839 static int sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device *adev, 1840 struct amdgpu_irq_src *source, 1841 struct amdgpu_iv_entry *entry) 1842 { 1843 int instance; 1844 1845 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1846 1847 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1848 if (instance < 0) 1849 return 0; 1850 1851 switch (entry->ring_id) { 1852 case 0: 1853 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 1854 break; 1855 } 1856 return 0; 1857 } 1858 1859 static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev, 1860 struct amdgpu_irq_src *source, 1861 unsigned type, 1862 enum amdgpu_interrupt_state state) 1863 { 1864 u32 sdma_cntl; 1865 1866 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); 1867 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, DRAM_ECC_INT_ENABLE, 1868 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1869 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); 1870 1871 return 0; 1872 } 1873 1874 static int sdma_v4_4_2_print_iv_entry(struct amdgpu_device *adev, 1875 struct amdgpu_iv_entry *entry) 1876 { 1877 int instance; 1878 struct amdgpu_task_info *task_info; 1879 u64 addr; 1880 1881 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1882 if (instance < 0 || instance >= adev->sdma.num_instances) { 1883 dev_err(adev->dev, "sdma instance invalid %d\n", instance); 1884 return -EINVAL; 1885 } 1886 1887 addr = (u64)entry->src_data[0] << 12; 1888 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 1889 1890 dev_dbg_ratelimited(adev->dev, 1891 "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u pasid:%u\n", 1892 instance, addr, entry->src_id, entry->ring_id, entry->vmid, 1893 entry->pasid); 1894 1895 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 1896 if (task_info) { 1897 dev_dbg_ratelimited(adev->dev, " for process %s pid %d thread %s pid %d\n", 1898 task_info->process_name, task_info->tgid, 1899 task_info->task_name, task_info->pid); 1900 amdgpu_vm_put_task_info(task_info); 1901 } 1902 1903 return 0; 1904 } 1905 1906 static int sdma_v4_4_2_process_vm_hole_irq(struct amdgpu_device *adev, 1907 struct amdgpu_irq_src *source, 1908 struct amdgpu_iv_entry *entry) 1909 { 1910 dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n"); 1911 sdma_v4_4_2_print_iv_entry(adev, entry); 1912 return 0; 1913 } 1914 1915 static int sdma_v4_4_2_process_doorbell_invalid_irq(struct amdgpu_device *adev, 1916 struct amdgpu_irq_src *source, 1917 struct amdgpu_iv_entry *entry) 1918 { 1919 1920 dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n"); 1921 sdma_v4_4_2_print_iv_entry(adev, entry); 1922 return 0; 1923 } 1924 1925 static int sdma_v4_4_2_process_pool_timeout_irq(struct amdgpu_device *adev, 1926 struct amdgpu_irq_src *source, 1927 struct amdgpu_iv_entry *entry) 1928 { 1929 dev_dbg_ratelimited(adev->dev, 1930 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n"); 1931 sdma_v4_4_2_print_iv_entry(adev, entry); 1932 return 0; 1933 } 1934 1935 static int sdma_v4_4_2_process_srbm_write_irq(struct amdgpu_device *adev, 1936 struct amdgpu_irq_src *source, 1937 struct amdgpu_iv_entry *entry) 1938 { 1939 dev_dbg_ratelimited(adev->dev, 1940 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n"); 1941 sdma_v4_4_2_print_iv_entry(adev, entry); 1942 return 0; 1943 } 1944 1945 static int sdma_v4_4_2_process_ctxt_empty_irq(struct amdgpu_device *adev, 1946 struct amdgpu_irq_src *source, 1947 struct amdgpu_iv_entry *entry) 1948 { 1949 /* There is nothing useful to be done here, only kept for debug */ 1950 dev_dbg_ratelimited(adev->dev, "SDMA context empty interrupt"); 1951 sdma_v4_4_2_print_iv_entry(adev, entry); 1952 return 0; 1953 } 1954 1955 static void sdma_v4_4_2_inst_update_medium_grain_light_sleep( 1956 struct amdgpu_device *adev, bool enable, uint32_t inst_mask) 1957 { 1958 uint32_t data, def; 1959 int i; 1960 1961 /* leave as default if it is not driver controlled */ 1962 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) 1963 return; 1964 1965 if (enable) { 1966 for_each_inst(i, inst_mask) { 1967 /* 1-not override: enable sdma mem light sleep */ 1968 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL); 1969 data |= SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1970 if (def != data) 1971 WREG32_SDMA(i, regSDMA_POWER_CNTL, data); 1972 } 1973 } else { 1974 for_each_inst(i, inst_mask) { 1975 /* 0-override:disable sdma mem light sleep */ 1976 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL); 1977 data &= ~SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1978 if (def != data) 1979 WREG32_SDMA(i, regSDMA_POWER_CNTL, data); 1980 } 1981 } 1982 } 1983 1984 static void sdma_v4_4_2_inst_update_medium_grain_clock_gating( 1985 struct amdgpu_device *adev, bool enable, uint32_t inst_mask) 1986 { 1987 uint32_t data, def; 1988 int i; 1989 1990 /* leave as default if it is not driver controlled */ 1991 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) 1992 return; 1993 1994 if (enable) { 1995 for_each_inst(i, inst_mask) { 1996 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL); 1997 data &= ~(SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1998 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1999 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2000 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2001 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2002 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2003 if (def != data) 2004 WREG32_SDMA(i, regSDMA_CLK_CTRL, data); 2005 } 2006 } else { 2007 for_each_inst(i, inst_mask) { 2008 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL); 2009 data |= (SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2010 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2011 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2012 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2013 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2014 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2015 if (def != data) 2016 WREG32_SDMA(i, regSDMA_CLK_CTRL, data); 2017 } 2018 } 2019 } 2020 2021 static int sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2022 enum amd_clockgating_state state) 2023 { 2024 struct amdgpu_device *adev = ip_block->adev; 2025 uint32_t inst_mask; 2026 2027 if (amdgpu_sriov_vf(adev)) 2028 return 0; 2029 2030 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 2031 2032 sdma_v4_4_2_inst_update_medium_grain_clock_gating( 2033 adev, state == AMD_CG_STATE_GATE, inst_mask); 2034 sdma_v4_4_2_inst_update_medium_grain_light_sleep( 2035 adev, state == AMD_CG_STATE_GATE, inst_mask); 2036 return 0; 2037 } 2038 2039 static int sdma_v4_4_2_set_powergating_state(struct amdgpu_ip_block *ip_block, 2040 enum amd_powergating_state state) 2041 { 2042 return 0; 2043 } 2044 2045 static void sdma_v4_4_2_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 2046 { 2047 struct amdgpu_device *adev = ip_block->adev; 2048 int data; 2049 2050 if (amdgpu_sriov_vf(adev)) 2051 *flags = 0; 2052 2053 /* AMD_CG_SUPPORT_SDMA_MGCG */ 2054 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL)); 2055 if (!(data & SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK)) 2056 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 2057 2058 /* AMD_CG_SUPPORT_SDMA_LS */ 2059 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL)); 2060 if (data & SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 2061 *flags |= AMD_CG_SUPPORT_SDMA_LS; 2062 } 2063 2064 static void sdma_v4_4_2_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 2065 { 2066 struct amdgpu_device *adev = ip_block->adev; 2067 int i, j; 2068 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); 2069 uint32_t instance_offset; 2070 2071 if (!adev->sdma.ip_dump) 2072 return; 2073 2074 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances); 2075 for (i = 0; i < adev->sdma.num_instances; i++) { 2076 instance_offset = i * reg_count; 2077 drm_printf(p, "\nInstance:%d\n", i); 2078 2079 for (j = 0; j < reg_count; j++) 2080 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_4_4_2[j].reg_name, 2081 adev->sdma.ip_dump[instance_offset + j]); 2082 } 2083 } 2084 2085 static void sdma_v4_4_2_dump_ip_state(struct amdgpu_ip_block *ip_block) 2086 { 2087 struct amdgpu_device *adev = ip_block->adev; 2088 int i, j; 2089 uint32_t instance_offset; 2090 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); 2091 2092 if (!adev->sdma.ip_dump) 2093 return; 2094 2095 for (i = 0; i < adev->sdma.num_instances; i++) { 2096 instance_offset = i * reg_count; 2097 for (j = 0; j < reg_count; j++) 2098 adev->sdma.ip_dump[instance_offset + j] = 2099 RREG32(sdma_v4_4_2_get_reg_offset(adev, i, 2100 sdma_reg_list_4_4_2[j].reg_offset)); 2101 } 2102 } 2103 2104 const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = { 2105 .name = "sdma_v4_4_2", 2106 .early_init = sdma_v4_4_2_early_init, 2107 .late_init = sdma_v4_4_2_late_init, 2108 .sw_init = sdma_v4_4_2_sw_init, 2109 .sw_fini = sdma_v4_4_2_sw_fini, 2110 .hw_init = sdma_v4_4_2_hw_init, 2111 .hw_fini = sdma_v4_4_2_hw_fini, 2112 .suspend = sdma_v4_4_2_suspend, 2113 .resume = sdma_v4_4_2_resume, 2114 .is_idle = sdma_v4_4_2_is_idle, 2115 .wait_for_idle = sdma_v4_4_2_wait_for_idle, 2116 .soft_reset = sdma_v4_4_2_soft_reset, 2117 .set_clockgating_state = sdma_v4_4_2_set_clockgating_state, 2118 .set_powergating_state = sdma_v4_4_2_set_powergating_state, 2119 .get_clockgating_state = sdma_v4_4_2_get_clockgating_state, 2120 .dump_ip_state = sdma_v4_4_2_dump_ip_state, 2121 .print_ip_state = sdma_v4_4_2_print_ip_state, 2122 }; 2123 2124 static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = { 2125 .type = AMDGPU_RING_TYPE_SDMA, 2126 .align_mask = 0xff, 2127 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2128 .support_64bit_ptrs = true, 2129 .get_rptr = sdma_v4_4_2_ring_get_rptr, 2130 .get_wptr = sdma_v4_4_2_ring_get_wptr, 2131 .set_wptr = sdma_v4_4_2_ring_set_wptr, 2132 .emit_frame_size = 2133 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */ 2134 3 + /* hdp invalidate */ 2135 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */ 2136 /* sdma_v4_4_2_ring_emit_vm_flush */ 2137 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2138 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2139 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */ 2140 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */ 2141 .emit_ib = sdma_v4_4_2_ring_emit_ib, 2142 .emit_fence = sdma_v4_4_2_ring_emit_fence, 2143 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync, 2144 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush, 2145 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush, 2146 .test_ring = sdma_v4_4_2_ring_test_ring, 2147 .test_ib = sdma_v4_4_2_ring_test_ib, 2148 .insert_nop = sdma_v4_4_2_ring_insert_nop, 2149 .pad_ib = sdma_v4_4_2_ring_pad_ib, 2150 .emit_wreg = sdma_v4_4_2_ring_emit_wreg, 2151 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, 2152 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2153 .reset = sdma_v4_4_2_reset_queue, 2154 .is_guilty = sdma_v4_4_2_ring_is_guilty, 2155 }; 2156 2157 static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = { 2158 .type = AMDGPU_RING_TYPE_SDMA, 2159 .align_mask = 0xff, 2160 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2161 .support_64bit_ptrs = true, 2162 .get_rptr = sdma_v4_4_2_ring_get_rptr, 2163 .get_wptr = sdma_v4_4_2_page_ring_get_wptr, 2164 .set_wptr = sdma_v4_4_2_page_ring_set_wptr, 2165 .emit_frame_size = 2166 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */ 2167 3 + /* hdp invalidate */ 2168 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */ 2169 /* sdma_v4_4_2_ring_emit_vm_flush */ 2170 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2171 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2172 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */ 2173 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */ 2174 .emit_ib = sdma_v4_4_2_ring_emit_ib, 2175 .emit_fence = sdma_v4_4_2_ring_emit_fence, 2176 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync, 2177 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush, 2178 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush, 2179 .test_ring = sdma_v4_4_2_ring_test_ring, 2180 .test_ib = sdma_v4_4_2_ring_test_ib, 2181 .insert_nop = sdma_v4_4_2_ring_insert_nop, 2182 .pad_ib = sdma_v4_4_2_ring_pad_ib, 2183 .emit_wreg = sdma_v4_4_2_ring_emit_wreg, 2184 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, 2185 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2186 .reset = sdma_v4_4_2_reset_queue, 2187 .is_guilty = sdma_v4_4_2_page_ring_is_guilty, 2188 }; 2189 2190 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev) 2191 { 2192 int i, dev_inst; 2193 2194 for (i = 0; i < adev->sdma.num_instances; i++) { 2195 adev->sdma.instance[i].ring.funcs = &sdma_v4_4_2_ring_funcs; 2196 adev->sdma.instance[i].ring.me = i; 2197 if (adev->sdma.has_page_queue) { 2198 adev->sdma.instance[i].page.funcs = 2199 &sdma_v4_4_2_page_ring_funcs; 2200 adev->sdma.instance[i].page.me = i; 2201 } 2202 2203 dev_inst = GET_INST(SDMA0, i); 2204 /* AID to which SDMA belongs depends on physical instance */ 2205 adev->sdma.instance[i].aid_id = 2206 dev_inst / adev->sdma.num_inst_per_aid; 2207 } 2208 } 2209 2210 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_trap_irq_funcs = { 2211 .set = sdma_v4_4_2_set_trap_irq_state, 2212 .process = sdma_v4_4_2_process_trap_irq, 2213 }; 2214 2215 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_illegal_inst_irq_funcs = { 2216 .process = sdma_v4_4_2_process_illegal_inst_irq, 2217 }; 2218 2219 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ecc_irq_funcs = { 2220 .set = sdma_v4_4_2_set_ecc_irq_state, 2221 .process = amdgpu_sdma_process_ecc_irq, 2222 }; 2223 2224 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_vm_hole_irq_funcs = { 2225 .process = sdma_v4_4_2_process_vm_hole_irq, 2226 }; 2227 2228 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_doorbell_invalid_irq_funcs = { 2229 .process = sdma_v4_4_2_process_doorbell_invalid_irq, 2230 }; 2231 2232 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_pool_timeout_irq_funcs = { 2233 .process = sdma_v4_4_2_process_pool_timeout_irq, 2234 }; 2235 2236 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_srbm_write_irq_funcs = { 2237 .process = sdma_v4_4_2_process_srbm_write_irq, 2238 }; 2239 2240 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ctxt_empty_irq_funcs = { 2241 .process = sdma_v4_4_2_process_ctxt_empty_irq, 2242 }; 2243 2244 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev) 2245 { 2246 adev->sdma.trap_irq.num_types = adev->sdma.num_instances; 2247 adev->sdma.ecc_irq.num_types = adev->sdma.num_instances; 2248 adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances; 2249 adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances; 2250 adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances; 2251 adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances; 2252 adev->sdma.ctxt_empty_irq.num_types = adev->sdma.num_instances; 2253 2254 adev->sdma.trap_irq.funcs = &sdma_v4_4_2_trap_irq_funcs; 2255 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_4_2_illegal_inst_irq_funcs; 2256 adev->sdma.ecc_irq.funcs = &sdma_v4_4_2_ecc_irq_funcs; 2257 adev->sdma.vm_hole_irq.funcs = &sdma_v4_4_2_vm_hole_irq_funcs; 2258 adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_4_2_doorbell_invalid_irq_funcs; 2259 adev->sdma.pool_timeout_irq.funcs = &sdma_v4_4_2_pool_timeout_irq_funcs; 2260 adev->sdma.srbm_write_irq.funcs = &sdma_v4_4_2_srbm_write_irq_funcs; 2261 adev->sdma.ctxt_empty_irq.funcs = &sdma_v4_4_2_ctxt_empty_irq_funcs; 2262 } 2263 2264 /** 2265 * sdma_v4_4_2_emit_copy_buffer - copy buffer using the sDMA engine 2266 * 2267 * @ib: indirect buffer to copy to 2268 * @src_offset: src GPU address 2269 * @dst_offset: dst GPU address 2270 * @byte_count: number of bytes to xfer 2271 * @copy_flags: copy flags for the buffers 2272 * 2273 * Copy GPU buffers using the DMA engine. 2274 * Used by the amdgpu ttm implementation to move pages if 2275 * registered as the asic copy callback. 2276 */ 2277 static void sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib *ib, 2278 uint64_t src_offset, 2279 uint64_t dst_offset, 2280 uint32_t byte_count, 2281 uint32_t copy_flags) 2282 { 2283 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 2284 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 2285 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0); 2286 ib->ptr[ib->length_dw++] = byte_count - 1; 2287 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 2288 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 2289 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 2290 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2291 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2292 } 2293 2294 /** 2295 * sdma_v4_4_2_emit_fill_buffer - fill buffer using the sDMA engine 2296 * 2297 * @ib: indirect buffer to copy to 2298 * @src_data: value to write to buffer 2299 * @dst_offset: dst GPU address 2300 * @byte_count: number of bytes to xfer 2301 * 2302 * Fill GPU buffers using the DMA engine. 2303 */ 2304 static void sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib *ib, 2305 uint32_t src_data, 2306 uint64_t dst_offset, 2307 uint32_t byte_count) 2308 { 2309 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2310 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2311 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2312 ib->ptr[ib->length_dw++] = src_data; 2313 ib->ptr[ib->length_dw++] = byte_count - 1; 2314 } 2315 2316 static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = { 2317 .copy_max_bytes = 0x400000, 2318 .copy_num_dw = 7, 2319 .emit_copy_buffer = sdma_v4_4_2_emit_copy_buffer, 2320 2321 .fill_max_bytes = 0x400000, 2322 .fill_num_dw = 5, 2323 .emit_fill_buffer = sdma_v4_4_2_emit_fill_buffer, 2324 }; 2325 2326 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev) 2327 { 2328 adev->mman.buffer_funcs = &sdma_v4_4_2_buffer_funcs; 2329 if (adev->sdma.has_page_queue) 2330 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; 2331 else 2332 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2333 } 2334 2335 static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = { 2336 .copy_pte_num_dw = 7, 2337 .copy_pte = sdma_v4_4_2_vm_copy_pte, 2338 2339 .write_pte = sdma_v4_4_2_vm_write_pte, 2340 .set_pte_pde = sdma_v4_4_2_vm_set_pte_pde, 2341 }; 2342 2343 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev) 2344 { 2345 struct drm_gpu_scheduler *sched; 2346 unsigned i; 2347 2348 adev->vm_manager.vm_pte_funcs = &sdma_v4_4_2_vm_pte_funcs; 2349 for (i = 0; i < adev->sdma.num_instances; i++) { 2350 if (adev->sdma.has_page_queue) 2351 sched = &adev->sdma.instance[i].page.sched; 2352 else 2353 sched = &adev->sdma.instance[i].ring.sched; 2354 adev->vm_manager.vm_pte_scheds[i] = sched; 2355 } 2356 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 2357 } 2358 2359 /** 2360 * sdma_v4_4_2_update_reset_mask - update reset mask for SDMA 2361 * @adev: Pointer to the AMDGPU device structure 2362 * 2363 * This function update reset mask for SDMA and sets the supported 2364 * reset types based on the IP version and firmware versions. 2365 * 2366 */ 2367 static void sdma_v4_4_2_update_reset_mask(struct amdgpu_device *adev) 2368 { 2369 /* per queue reset not supported for SRIOV */ 2370 if (amdgpu_sriov_vf(adev)) 2371 return; 2372 2373 /* 2374 * the user queue relies on MEC fw and pmfw when the sdma queue do reset. 2375 * it needs to check both of them at here to skip old mec and pmfw. 2376 */ 2377 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2378 case IP_VERSION(9, 4, 3): 2379 case IP_VERSION(9, 4, 4): 2380 if ((adev->gfx.mec_fw_version >= 0xb0) && amdgpu_dpm_reset_sdma_is_supported(adev)) 2381 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 2382 break; 2383 case IP_VERSION(9, 5, 0): 2384 if ((adev->gfx.mec_fw_version >= 0xf) && amdgpu_dpm_reset_sdma_is_supported(adev)) 2385 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 2386 break; 2387 default: 2388 break; 2389 } 2390 2391 } 2392 2393 const struct amdgpu_ip_block_version sdma_v4_4_2_ip_block = { 2394 .type = AMD_IP_BLOCK_TYPE_SDMA, 2395 .major = 4, 2396 .minor = 4, 2397 .rev = 2, 2398 .funcs = &sdma_v4_4_2_ip_funcs, 2399 }; 2400 2401 static int sdma_v4_4_2_xcp_resume(void *handle, uint32_t inst_mask) 2402 { 2403 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2404 int r; 2405 2406 if (!amdgpu_sriov_vf(adev)) 2407 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask); 2408 2409 r = sdma_v4_4_2_inst_start(adev, inst_mask, false); 2410 2411 return r; 2412 } 2413 2414 static int sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask) 2415 { 2416 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2417 uint32_t tmp_mask = inst_mask; 2418 int i; 2419 2420 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2421 for_each_inst(i, tmp_mask) { 2422 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 2423 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 2424 } 2425 } 2426 2427 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 2428 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 2429 2430 return 0; 2431 } 2432 2433 struct amdgpu_xcp_ip_funcs sdma_v4_4_2_xcp_funcs = { 2434 .suspend = &sdma_v4_4_2_xcp_suspend, 2435 .resume = &sdma_v4_4_2_xcp_resume 2436 }; 2437 2438 static const struct amdgpu_ras_err_status_reg_entry sdma_v4_2_2_ue_reg_list[] = { 2439 {AMDGPU_RAS_REG_ENTRY(SDMA0, 0, regSDMA_UE_ERR_STATUS_LO, regSDMA_UE_ERR_STATUS_HI), 2440 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SDMA"}, 2441 }; 2442 2443 static const struct amdgpu_ras_memory_id_entry sdma_v4_4_2_ras_memory_list[] = { 2444 {AMDGPU_SDMA_MBANK_DATA_BUF0, "SDMA_MBANK_DATA_BUF0"}, 2445 {AMDGPU_SDMA_MBANK_DATA_BUF1, "SDMA_MBANK_DATA_BUF1"}, 2446 {AMDGPU_SDMA_MBANK_DATA_BUF2, "SDMA_MBANK_DATA_BUF2"}, 2447 {AMDGPU_SDMA_MBANK_DATA_BUF3, "SDMA_MBANK_DATA_BUF3"}, 2448 {AMDGPU_SDMA_MBANK_DATA_BUF4, "SDMA_MBANK_DATA_BUF4"}, 2449 {AMDGPU_SDMA_MBANK_DATA_BUF5, "SDMA_MBANK_DATA_BUF5"}, 2450 {AMDGPU_SDMA_MBANK_DATA_BUF6, "SDMA_MBANK_DATA_BUF6"}, 2451 {AMDGPU_SDMA_MBANK_DATA_BUF7, "SDMA_MBANK_DATA_BUF7"}, 2452 {AMDGPU_SDMA_MBANK_DATA_BUF8, "SDMA_MBANK_DATA_BUF8"}, 2453 {AMDGPU_SDMA_MBANK_DATA_BUF9, "SDMA_MBANK_DATA_BUF9"}, 2454 {AMDGPU_SDMA_MBANK_DATA_BUF10, "SDMA_MBANK_DATA_BUF10"}, 2455 {AMDGPU_SDMA_MBANK_DATA_BUF11, "SDMA_MBANK_DATA_BUF11"}, 2456 {AMDGPU_SDMA_MBANK_DATA_BUF12, "SDMA_MBANK_DATA_BUF12"}, 2457 {AMDGPU_SDMA_MBANK_DATA_BUF13, "SDMA_MBANK_DATA_BUF13"}, 2458 {AMDGPU_SDMA_MBANK_DATA_BUF14, "SDMA_MBANK_DATA_BUF14"}, 2459 {AMDGPU_SDMA_MBANK_DATA_BUF15, "SDMA_MBANK_DATA_BUF15"}, 2460 {AMDGPU_SDMA_UCODE_BUF, "SDMA_UCODE_BUF"}, 2461 {AMDGPU_SDMA_RB_CMD_BUF, "SDMA_RB_CMD_BUF"}, 2462 {AMDGPU_SDMA_IB_CMD_BUF, "SDMA_IB_CMD_BUF"}, 2463 {AMDGPU_SDMA_UTCL1_RD_FIFO, "SDMA_UTCL1_RD_FIFO"}, 2464 {AMDGPU_SDMA_UTCL1_RDBST_FIFO, "SDMA_UTCL1_RDBST_FIFO"}, 2465 {AMDGPU_SDMA_UTCL1_WR_FIFO, "SDMA_UTCL1_WR_FIFO"}, 2466 {AMDGPU_SDMA_DATA_LUT_FIFO, "SDMA_DATA_LUT_FIFO"}, 2467 {AMDGPU_SDMA_SPLIT_DAT_BUF, "SDMA_SPLIT_DAT_BUF"}, 2468 }; 2469 2470 static void sdma_v4_4_2_inst_query_ras_error_count(struct amdgpu_device *adev, 2471 uint32_t sdma_inst, 2472 void *ras_err_status) 2473 { 2474 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 2475 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); 2476 unsigned long ue_count = 0; 2477 struct amdgpu_smuio_mcm_config_info mcm_info = { 2478 .socket_id = adev->smuio.funcs->get_socket_id(adev), 2479 .die_id = adev->sdma.instance[sdma_inst].aid_id, 2480 }; 2481 2482 /* sdma v4_4_2 doesn't support query ce counts */ 2483 amdgpu_ras_inst_query_ras_error_count(adev, 2484 sdma_v4_2_2_ue_reg_list, 2485 ARRAY_SIZE(sdma_v4_2_2_ue_reg_list), 2486 sdma_v4_4_2_ras_memory_list, 2487 ARRAY_SIZE(sdma_v4_4_2_ras_memory_list), 2488 sdma_dev_inst, 2489 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 2490 &ue_count); 2491 2492 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count); 2493 } 2494 2495 static void sdma_v4_4_2_query_ras_error_count(struct amdgpu_device *adev, 2496 void *ras_err_status) 2497 { 2498 uint32_t inst_mask; 2499 int i = 0; 2500 2501 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 2502 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2503 for_each_inst(i, inst_mask) 2504 sdma_v4_4_2_inst_query_ras_error_count(adev, i, ras_err_status); 2505 } else { 2506 dev_warn(adev->dev, "SDMA RAS is not supported\n"); 2507 } 2508 } 2509 2510 static void sdma_v4_4_2_inst_reset_ras_error_count(struct amdgpu_device *adev, 2511 uint32_t sdma_inst) 2512 { 2513 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); 2514 2515 amdgpu_ras_inst_reset_ras_error_count(adev, 2516 sdma_v4_2_2_ue_reg_list, 2517 ARRAY_SIZE(sdma_v4_2_2_ue_reg_list), 2518 sdma_dev_inst); 2519 } 2520 2521 static void sdma_v4_4_2_reset_ras_error_count(struct amdgpu_device *adev) 2522 { 2523 uint32_t inst_mask; 2524 int i = 0; 2525 2526 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 2527 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2528 for_each_inst(i, inst_mask) 2529 sdma_v4_4_2_inst_reset_ras_error_count(adev, i); 2530 } else { 2531 dev_warn(adev->dev, "SDMA RAS is not supported\n"); 2532 } 2533 } 2534 2535 static const struct amdgpu_ras_block_hw_ops sdma_v4_4_2_ras_hw_ops = { 2536 .query_ras_error_count = sdma_v4_4_2_query_ras_error_count, 2537 .reset_ras_error_count = sdma_v4_4_2_reset_ras_error_count, 2538 }; 2539 2540 static int sdma_v4_4_2_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, 2541 enum aca_smu_type type, void *data) 2542 { 2543 struct aca_bank_info info; 2544 u64 misc0; 2545 int ret; 2546 2547 ret = aca_bank_info_decode(bank, &info); 2548 if (ret) 2549 return ret; 2550 2551 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 2552 switch (type) { 2553 case ACA_SMU_TYPE_UE: 2554 bank->aca_err_type = ACA_ERROR_TYPE_UE; 2555 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE, 2556 1ULL); 2557 break; 2558 case ACA_SMU_TYPE_CE: 2559 bank->aca_err_type = ACA_ERROR_TYPE_CE; 2560 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 2561 ACA_REG__MISC0__ERRCNT(misc0)); 2562 break; 2563 default: 2564 return -EINVAL; 2565 } 2566 2567 return ret; 2568 } 2569 2570 /* CODE_SDMA0 - CODE_SDMA4, reference to smu driver if header file */ 2571 static int sdma_v4_4_2_err_codes[] = { 33, 34, 35, 36 }; 2572 2573 static bool sdma_v4_4_2_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 2574 enum aca_smu_type type, void *data) 2575 { 2576 u32 instlo; 2577 2578 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 2579 instlo &= GENMASK(31, 1); 2580 2581 if (instlo != mmSMNAID_AID0_MCA_SMU) 2582 return false; 2583 2584 if (aca_bank_check_error_codes(handle->adev, bank, 2585 sdma_v4_4_2_err_codes, 2586 ARRAY_SIZE(sdma_v4_4_2_err_codes))) 2587 return false; 2588 2589 return true; 2590 } 2591 2592 static const struct aca_bank_ops sdma_v4_4_2_aca_bank_ops = { 2593 .aca_bank_parser = sdma_v4_4_2_aca_bank_parser, 2594 .aca_bank_is_valid = sdma_v4_4_2_aca_bank_is_valid, 2595 }; 2596 2597 static const struct aca_info sdma_v4_4_2_aca_info = { 2598 .hwip = ACA_HWIP_TYPE_SMU, 2599 .mask = ACA_ERROR_UE_MASK, 2600 .bank_ops = &sdma_v4_4_2_aca_bank_ops, 2601 }; 2602 2603 static int sdma_v4_4_2_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 2604 { 2605 int r; 2606 2607 r = amdgpu_sdma_ras_late_init(adev, ras_block); 2608 if (r) 2609 return r; 2610 2611 return amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__SDMA, 2612 &sdma_v4_4_2_aca_info, NULL); 2613 } 2614 2615 static struct amdgpu_sdma_ras sdma_v4_4_2_ras = { 2616 .ras_block = { 2617 .hw_ops = &sdma_v4_4_2_ras_hw_ops, 2618 .ras_late_init = sdma_v4_4_2_ras_late_init, 2619 }, 2620 }; 2621 2622 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev) 2623 { 2624 adev->sdma.ras = &sdma_v4_4_2_ras; 2625 } 2626