1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_xcp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_trace.h" 33 34 #include "sdma/sdma_4_4_2_offset.h" 35 #include "sdma/sdma_4_4_2_sh_mask.h" 36 37 #include "soc15_common.h" 38 #include "soc15.h" 39 #include "vega10_sdma_pkt_open.h" 40 41 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 42 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 43 44 #include "amdgpu_ras.h" 45 46 MODULE_FIRMWARE("amdgpu/sdma_4_4_2.bin"); 47 48 #define WREG32_SDMA(instance, offset, value) \ 49 WREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)), value) 50 #define RREG32_SDMA(instance, offset) \ 51 RREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset))) 52 53 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev); 54 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev); 55 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev); 56 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev); 57 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev); 58 59 static u32 sdma_v4_4_2_get_reg_offset(struct amdgpu_device *adev, 60 u32 instance, u32 offset) 61 { 62 u32 dev_inst = GET_INST(SDMA0, instance); 63 64 return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset); 65 } 66 67 static unsigned sdma_v4_4_2_seq_to_irq_id(int seq_num) 68 { 69 switch (seq_num) { 70 case 0: 71 return SOC15_IH_CLIENTID_SDMA0; 72 case 1: 73 return SOC15_IH_CLIENTID_SDMA1; 74 case 2: 75 return SOC15_IH_CLIENTID_SDMA2; 76 case 3: 77 return SOC15_IH_CLIENTID_SDMA3; 78 default: 79 return -EINVAL; 80 } 81 } 82 83 static int sdma_v4_4_2_irq_id_to_seq(unsigned client_id) 84 { 85 switch (client_id) { 86 case SOC15_IH_CLIENTID_SDMA0: 87 return 0; 88 case SOC15_IH_CLIENTID_SDMA1: 89 return 1; 90 case SOC15_IH_CLIENTID_SDMA2: 91 return 2; 92 case SOC15_IH_CLIENTID_SDMA3: 93 return 3; 94 default: 95 return -EINVAL; 96 } 97 } 98 99 static void sdma_v4_4_2_inst_init_golden_registers(struct amdgpu_device *adev, 100 uint32_t inst_mask) 101 { 102 u32 val; 103 int i; 104 105 for (i = 0; i < adev->sdma.num_instances; i++) { 106 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG); 107 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4); 108 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, 109 PIPE_INTERLEAVE_SIZE, 0); 110 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG, val); 111 112 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ); 113 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS, 114 4); 115 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, 116 PIPE_INTERLEAVE_SIZE, 0); 117 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ, val); 118 } 119 } 120 121 /** 122 * sdma_v4_4_2_init_microcode - load ucode images from disk 123 * 124 * @adev: amdgpu_device pointer 125 * 126 * Use the firmware interface to load the ucode images into 127 * the driver (not loaded into hw). 128 * Returns 0 on success, error on failure. 129 */ 130 static int sdma_v4_4_2_init_microcode(struct amdgpu_device *adev) 131 { 132 int ret, i; 133 134 for (i = 0; i < adev->sdma.num_instances; i++) { 135 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == 136 IP_VERSION(4, 4, 2)) { 137 ret = amdgpu_sdma_init_microcode(adev, 0, true); 138 break; 139 } else { 140 ret = amdgpu_sdma_init_microcode(adev, i, false); 141 if (ret) 142 return ret; 143 } 144 } 145 146 return ret; 147 } 148 149 /** 150 * sdma_v4_4_2_ring_get_rptr - get the current read pointer 151 * 152 * @ring: amdgpu ring pointer 153 * 154 * Get the current rptr from the hardware. 155 */ 156 static uint64_t sdma_v4_4_2_ring_get_rptr(struct amdgpu_ring *ring) 157 { 158 u64 rptr; 159 160 /* XXX check if swapping is necessary on BE */ 161 rptr = READ_ONCE(*((u64 *)&ring->adev->wb.wb[ring->rptr_offs])); 162 163 DRM_DEBUG("rptr before shift == 0x%016llx\n", rptr); 164 return rptr >> 2; 165 } 166 167 /** 168 * sdma_v4_4_2_ring_get_wptr - get the current write pointer 169 * 170 * @ring: amdgpu ring pointer 171 * 172 * Get the current wptr from the hardware. 173 */ 174 static uint64_t sdma_v4_4_2_ring_get_wptr(struct amdgpu_ring *ring) 175 { 176 struct amdgpu_device *adev = ring->adev; 177 u64 wptr; 178 179 if (ring->use_doorbell) { 180 /* XXX check if swapping is necessary on BE */ 181 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 182 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 183 } else { 184 wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI); 185 wptr = wptr << 32; 186 wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR); 187 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 188 ring->me, wptr); 189 } 190 191 return wptr >> 2; 192 } 193 194 /** 195 * sdma_v4_4_2_ring_set_wptr - commit the write pointer 196 * 197 * @ring: amdgpu ring pointer 198 * 199 * Write the wptr back to the hardware. 200 */ 201 static void sdma_v4_4_2_ring_set_wptr(struct amdgpu_ring *ring) 202 { 203 struct amdgpu_device *adev = ring->adev; 204 205 DRM_DEBUG("Setting write pointer\n"); 206 if (ring->use_doorbell) { 207 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 208 209 DRM_DEBUG("Using doorbell -- " 210 "wptr_offs == 0x%08x " 211 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 212 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 213 ring->wptr_offs, 214 lower_32_bits(ring->wptr << 2), 215 upper_32_bits(ring->wptr << 2)); 216 /* XXX check if swapping is necessary on BE */ 217 WRITE_ONCE(*wb, (ring->wptr << 2)); 218 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 219 ring->doorbell_index, ring->wptr << 2); 220 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 221 } else { 222 DRM_DEBUG("Not using doorbell -- " 223 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 224 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 225 ring->me, 226 lower_32_bits(ring->wptr << 2), 227 ring->me, 228 upper_32_bits(ring->wptr << 2)); 229 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR, 230 lower_32_bits(ring->wptr << 2)); 231 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI, 232 upper_32_bits(ring->wptr << 2)); 233 } 234 } 235 236 /** 237 * sdma_v4_4_2_page_ring_get_wptr - get the current write pointer 238 * 239 * @ring: amdgpu ring pointer 240 * 241 * Get the current wptr from the hardware. 242 */ 243 static uint64_t sdma_v4_4_2_page_ring_get_wptr(struct amdgpu_ring *ring) 244 { 245 struct amdgpu_device *adev = ring->adev; 246 u64 wptr; 247 248 if (ring->use_doorbell) { 249 /* XXX check if swapping is necessary on BE */ 250 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 251 } else { 252 wptr = RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI); 253 wptr = wptr << 32; 254 wptr |= RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR); 255 } 256 257 return wptr >> 2; 258 } 259 260 /** 261 * sdma_v4_4_2_page_ring_set_wptr - commit the write pointer 262 * 263 * @ring: amdgpu ring pointer 264 * 265 * Write the wptr back to the hardware. 266 */ 267 static void sdma_v4_4_2_page_ring_set_wptr(struct amdgpu_ring *ring) 268 { 269 struct amdgpu_device *adev = ring->adev; 270 271 if (ring->use_doorbell) { 272 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 273 274 /* XXX check if swapping is necessary on BE */ 275 WRITE_ONCE(*wb, (ring->wptr << 2)); 276 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 277 } else { 278 uint64_t wptr = ring->wptr << 2; 279 280 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR, 281 lower_32_bits(wptr)); 282 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI, 283 upper_32_bits(wptr)); 284 } 285 } 286 287 static void sdma_v4_4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 288 { 289 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 290 int i; 291 292 for (i = 0; i < count; i++) 293 if (sdma && sdma->burst_nop && (i == 0)) 294 amdgpu_ring_write(ring, ring->funcs->nop | 295 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 296 else 297 amdgpu_ring_write(ring, ring->funcs->nop); 298 } 299 300 /** 301 * sdma_v4_4_2_ring_emit_ib - Schedule an IB on the DMA engine 302 * 303 * @ring: amdgpu ring pointer 304 * @job: job to retrieve vmid from 305 * @ib: IB object to schedule 306 * @flags: unused 307 * 308 * Schedule an IB in the DMA ring. 309 */ 310 static void sdma_v4_4_2_ring_emit_ib(struct amdgpu_ring *ring, 311 struct amdgpu_job *job, 312 struct amdgpu_ib *ib, 313 uint32_t flags) 314 { 315 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 316 317 /* IB packet must end on a 8 DW boundary */ 318 sdma_v4_4_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 319 320 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 321 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 322 /* base must be 32 byte aligned */ 323 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 324 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 325 amdgpu_ring_write(ring, ib->length_dw); 326 amdgpu_ring_write(ring, 0); 327 amdgpu_ring_write(ring, 0); 328 329 } 330 331 static void sdma_v4_4_2_wait_reg_mem(struct amdgpu_ring *ring, 332 int mem_space, int hdp, 333 uint32_t addr0, uint32_t addr1, 334 uint32_t ref, uint32_t mask, 335 uint32_t inv) 336 { 337 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 338 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 339 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 340 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 341 if (mem_space) { 342 /* memory */ 343 amdgpu_ring_write(ring, addr0); 344 amdgpu_ring_write(ring, addr1); 345 } else { 346 /* registers */ 347 amdgpu_ring_write(ring, addr0 << 2); 348 amdgpu_ring_write(ring, addr1 << 2); 349 } 350 amdgpu_ring_write(ring, ref); /* reference */ 351 amdgpu_ring_write(ring, mask); /* mask */ 352 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 353 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 354 } 355 356 /** 357 * sdma_v4_4_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 358 * 359 * @ring: amdgpu ring pointer 360 * 361 * Emit an hdp flush packet on the requested DMA ring. 362 */ 363 static void sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 364 { 365 struct amdgpu_device *adev = ring->adev; 366 u32 ref_and_mask = 0; 367 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 368 369 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 370 371 sdma_v4_4_2_wait_reg_mem(ring, 0, 1, 372 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 373 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 374 ref_and_mask, ref_and_mask, 10); 375 } 376 377 /** 378 * sdma_v4_4_2_ring_emit_fence - emit a fence on the DMA ring 379 * 380 * @ring: amdgpu ring pointer 381 * @addr: address 382 * @seq: sequence number 383 * @flags: fence related flags 384 * 385 * Add a DMA fence packet to the ring to write 386 * the fence seq number and DMA trap packet to generate 387 * an interrupt if needed. 388 */ 389 static void sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 390 unsigned flags) 391 { 392 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 393 /* write the fence */ 394 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 395 /* zero in first two bits */ 396 BUG_ON(addr & 0x3); 397 amdgpu_ring_write(ring, lower_32_bits(addr)); 398 amdgpu_ring_write(ring, upper_32_bits(addr)); 399 amdgpu_ring_write(ring, lower_32_bits(seq)); 400 401 /* optionally write high bits as well */ 402 if (write64bit) { 403 addr += 4; 404 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 405 /* zero in first two bits */ 406 BUG_ON(addr & 0x3); 407 amdgpu_ring_write(ring, lower_32_bits(addr)); 408 amdgpu_ring_write(ring, upper_32_bits(addr)); 409 amdgpu_ring_write(ring, upper_32_bits(seq)); 410 } 411 412 /* generate an interrupt */ 413 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 414 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 415 } 416 417 418 /** 419 * sdma_v4_4_2_inst_gfx_stop - stop the gfx async dma engines 420 * 421 * @adev: amdgpu_device pointer 422 * @inst_mask: mask of dma engine instances to be disabled 423 * 424 * Stop the gfx async dma ring buffers. 425 */ 426 static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev, 427 uint32_t inst_mask) 428 { 429 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 430 u32 rb_cntl, ib_cntl; 431 int i, unset = 0; 432 433 for_each_inst(i, inst_mask) { 434 sdma[i] = &adev->sdma.instance[i].ring; 435 436 if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) { 437 amdgpu_ttm_set_buffer_funcs_status(adev, false); 438 unset = 1; 439 } 440 441 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); 442 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0); 443 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 444 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 445 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0); 446 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 447 } 448 } 449 450 /** 451 * sdma_v4_4_2_inst_rlc_stop - stop the compute async dma engines 452 * 453 * @adev: amdgpu_device pointer 454 * @inst_mask: mask of dma engine instances to be disabled 455 * 456 * Stop the compute async dma queues. 457 */ 458 static void sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device *adev, 459 uint32_t inst_mask) 460 { 461 /* XXX todo */ 462 } 463 464 /** 465 * sdma_v4_4_2_inst_page_stop - stop the page async dma engines 466 * 467 * @adev: amdgpu_device pointer 468 * @inst_mask: mask of dma engine instances to be disabled 469 * 470 * Stop the page async dma ring buffers. 471 */ 472 static void sdma_v4_4_2_inst_page_stop(struct amdgpu_device *adev, 473 uint32_t inst_mask) 474 { 475 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 476 u32 rb_cntl, ib_cntl; 477 int i; 478 bool unset = false; 479 480 for_each_inst(i, inst_mask) { 481 sdma[i] = &adev->sdma.instance[i].page; 482 483 if ((adev->mman.buffer_funcs_ring == sdma[i]) && 484 (!unset)) { 485 amdgpu_ttm_set_buffer_funcs_status(adev, false); 486 unset = true; 487 } 488 489 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); 490 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, 491 RB_ENABLE, 0); 492 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 493 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); 494 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, 495 IB_ENABLE, 0); 496 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); 497 } 498 } 499 500 /** 501 * sdma_v4_4_2_inst_ctx_switch_enable - stop the async dma engines context switch 502 * 503 * @adev: amdgpu_device pointer 504 * @enable: enable/disable the DMA MEs context switch. 505 * @inst_mask: mask of dma engine instances to be enabled 506 * 507 * Halt or unhalt the async dma engines context switch. 508 */ 509 static void sdma_v4_4_2_inst_ctx_switch_enable(struct amdgpu_device *adev, 510 bool enable, uint32_t inst_mask) 511 { 512 u32 f32_cntl, phase_quantum = 0; 513 int i; 514 515 if (amdgpu_sdma_phase_quantum) { 516 unsigned value = amdgpu_sdma_phase_quantum; 517 unsigned unit = 0; 518 519 while (value > (SDMA_PHASE0_QUANTUM__VALUE_MASK >> 520 SDMA_PHASE0_QUANTUM__VALUE__SHIFT)) { 521 value = (value + 1) >> 1; 522 unit++; 523 } 524 if (unit > (SDMA_PHASE0_QUANTUM__UNIT_MASK >> 525 SDMA_PHASE0_QUANTUM__UNIT__SHIFT)) { 526 value = (SDMA_PHASE0_QUANTUM__VALUE_MASK >> 527 SDMA_PHASE0_QUANTUM__VALUE__SHIFT); 528 unit = (SDMA_PHASE0_QUANTUM__UNIT_MASK >> 529 SDMA_PHASE0_QUANTUM__UNIT__SHIFT); 530 WARN_ONCE(1, 531 "clamping sdma_phase_quantum to %uK clock cycles\n", 532 value << unit); 533 } 534 phase_quantum = 535 value << SDMA_PHASE0_QUANTUM__VALUE__SHIFT | 536 unit << SDMA_PHASE0_QUANTUM__UNIT__SHIFT; 537 } 538 539 for_each_inst(i, inst_mask) { 540 f32_cntl = RREG32_SDMA(i, regSDMA_CNTL); 541 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_CNTL, 542 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 543 if (enable && amdgpu_sdma_phase_quantum) { 544 WREG32_SDMA(i, regSDMA_PHASE0_QUANTUM, phase_quantum); 545 WREG32_SDMA(i, regSDMA_PHASE1_QUANTUM, phase_quantum); 546 WREG32_SDMA(i, regSDMA_PHASE2_QUANTUM, phase_quantum); 547 } 548 WREG32_SDMA(i, regSDMA_CNTL, f32_cntl); 549 550 /* Extend page fault timeout to avoid interrupt storm */ 551 WREG32_SDMA(i, regSDMA_UTCL1_TIMEOUT, 0x00800080); 552 } 553 } 554 555 /** 556 * sdma_v4_4_2_inst_enable - stop the async dma engines 557 * 558 * @adev: amdgpu_device pointer 559 * @enable: enable/disable the DMA MEs. 560 * @inst_mask: mask of dma engine instances to be enabled 561 * 562 * Halt or unhalt the async dma engines. 563 */ 564 static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable, 565 uint32_t inst_mask) 566 { 567 u32 f32_cntl; 568 int i; 569 570 if (!enable) { 571 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask); 572 sdma_v4_4_2_inst_rlc_stop(adev, inst_mask); 573 if (adev->sdma.has_page_queue) 574 sdma_v4_4_2_inst_page_stop(adev, inst_mask); 575 576 /* SDMA FW needs to respond to FREEZE requests during reset. 577 * Keep it running during reset */ 578 if (!amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 579 return; 580 } 581 582 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 583 return; 584 585 for_each_inst(i, inst_mask) { 586 f32_cntl = RREG32_SDMA(i, regSDMA_F32_CNTL); 587 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1); 588 WREG32_SDMA(i, regSDMA_F32_CNTL, f32_cntl); 589 } 590 } 591 592 /* 593 * sdma_v4_4_2_rb_cntl - get parameters for rb_cntl 594 */ 595 static uint32_t sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 596 { 597 /* Set ring buffer size in dwords */ 598 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 599 600 barrier(); /* work around https://bugs.llvm.org/show_bug.cgi?id=42576 */ 601 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 602 #ifdef __BIG_ENDIAN 603 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 604 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, 605 RPTR_WRITEBACK_SWAP_ENABLE, 1); 606 #endif 607 return rb_cntl; 608 } 609 610 /** 611 * sdma_v4_4_2_gfx_resume - setup and start the async dma engines 612 * 613 * @adev: amdgpu_device pointer 614 * @i: instance to resume 615 * 616 * Set up the gfx DMA ring buffers and enable them. 617 * Returns 0 for success, error for failure. 618 */ 619 static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i) 620 { 621 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 622 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 623 u32 wb_offset; 624 u32 doorbell; 625 u32 doorbell_offset; 626 u64 wptr_gpu_addr; 627 628 wb_offset = (ring->rptr_offs * 4); 629 630 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); 631 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 632 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 633 634 /* Initialize the ring buffer's read and write pointers */ 635 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0); 636 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0); 637 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0); 638 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0); 639 640 /* set the wb address whether it's enabled or not */ 641 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_HI, 642 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 643 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_LO, 644 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 645 646 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, 647 RPTR_WRITEBACK_ENABLE, 1); 648 649 WREG32_SDMA(i, regSDMA_GFX_RB_BASE, ring->gpu_addr >> 8); 650 WREG32_SDMA(i, regSDMA_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 651 652 ring->wptr = 0; 653 654 /* before programing wptr to a less value, need set minor_ptr_update first */ 655 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 1); 656 657 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL); 658 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET); 659 660 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 661 ring->use_doorbell); 662 doorbell_offset = REG_SET_FIELD(doorbell_offset, 663 SDMA_GFX_DOORBELL_OFFSET, 664 OFFSET, ring->doorbell_index); 665 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell); 666 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset); 667 668 sdma_v4_4_2_ring_set_wptr(ring); 669 670 /* set minor_ptr_update to 0 after wptr programed */ 671 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 0); 672 673 /* setup the wptr shadow polling */ 674 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 675 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_LO, 676 lower_32_bits(wptr_gpu_addr)); 677 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_HI, 678 upper_32_bits(wptr_gpu_addr)); 679 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL); 680 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 681 SDMA_GFX_RB_WPTR_POLL_CNTL, 682 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 683 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 684 685 /* enable DMA RB */ 686 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 1); 687 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 688 689 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 690 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 1); 691 #ifdef __BIG_ENDIAN 692 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 693 #endif 694 /* enable DMA IBs */ 695 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 696 } 697 698 /** 699 * sdma_v4_4_2_page_resume - setup and start the async dma engines 700 * 701 * @adev: amdgpu_device pointer 702 * @i: instance to resume 703 * 704 * Set up the page DMA ring buffers and enable them. 705 * Returns 0 for success, error for failure. 706 */ 707 static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i) 708 { 709 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 710 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 711 u32 wb_offset; 712 u32 doorbell; 713 u32 doorbell_offset; 714 u64 wptr_gpu_addr; 715 716 wb_offset = (ring->rptr_offs * 4); 717 718 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); 719 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 720 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 721 722 /* Initialize the ring buffer's read and write pointers */ 723 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, 0); 724 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, 0); 725 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, 0); 726 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, 0); 727 728 /* set the wb address whether it's enabled or not */ 729 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_HI, 730 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 731 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_LO, 732 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 733 734 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, 735 RPTR_WRITEBACK_ENABLE, 1); 736 737 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE, ring->gpu_addr >> 8); 738 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 739 740 ring->wptr = 0; 741 742 /* before programing wptr to a less value, need set minor_ptr_update first */ 743 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 1); 744 745 doorbell = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL); 746 doorbell_offset = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET); 747 748 doorbell = REG_SET_FIELD(doorbell, SDMA_PAGE_DOORBELL, ENABLE, 749 ring->use_doorbell); 750 doorbell_offset = REG_SET_FIELD(doorbell_offset, 751 SDMA_PAGE_DOORBELL_OFFSET, 752 OFFSET, ring->doorbell_index); 753 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL, doorbell); 754 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET, doorbell_offset); 755 756 /* paging queue doorbell range is setup at sdma_v4_4_2_gfx_resume */ 757 sdma_v4_4_2_page_ring_set_wptr(ring); 758 759 /* set minor_ptr_update to 0 after wptr programed */ 760 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 0); 761 762 /* setup the wptr shadow polling */ 763 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 764 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_LO, 765 lower_32_bits(wptr_gpu_addr)); 766 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_HI, 767 upper_32_bits(wptr_gpu_addr)); 768 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL); 769 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 770 SDMA_PAGE_RB_WPTR_POLL_CNTL, 771 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 772 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 773 774 /* enable DMA RB */ 775 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, RB_ENABLE, 1); 776 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 777 778 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); 779 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_ENABLE, 1); 780 #ifdef __BIG_ENDIAN 781 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 782 #endif 783 /* enable DMA IBs */ 784 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); 785 } 786 787 static void sdma_v4_4_2_init_pg(struct amdgpu_device *adev) 788 { 789 790 } 791 792 /** 793 * sdma_v4_4_2_inst_rlc_resume - setup and start the async dma engines 794 * 795 * @adev: amdgpu_device pointer 796 * @inst_mask: mask of dma engine instances to be enabled 797 * 798 * Set up the compute DMA queues and enable them. 799 * Returns 0 for success, error for failure. 800 */ 801 static int sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device *adev, 802 uint32_t inst_mask) 803 { 804 sdma_v4_4_2_init_pg(adev); 805 806 return 0; 807 } 808 809 /** 810 * sdma_v4_4_2_inst_load_microcode - load the sDMA ME ucode 811 * 812 * @adev: amdgpu_device pointer 813 * @inst_mask: mask of dma engine instances to be enabled 814 * 815 * Loads the sDMA0/1 ucode. 816 * Returns 0 for success, -EINVAL if the ucode is not available. 817 */ 818 static int sdma_v4_4_2_inst_load_microcode(struct amdgpu_device *adev, 819 uint32_t inst_mask) 820 { 821 const struct sdma_firmware_header_v1_0 *hdr; 822 const __le32 *fw_data; 823 u32 fw_size; 824 int i, j; 825 826 /* halt the MEs */ 827 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 828 829 for_each_inst(i, inst_mask) { 830 if (!adev->sdma.instance[i].fw) 831 return -EINVAL; 832 833 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 834 amdgpu_ucode_print_sdma_hdr(&hdr->header); 835 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 836 837 fw_data = (const __le32 *) 838 (adev->sdma.instance[i].fw->data + 839 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 840 841 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 0); 842 843 for (j = 0; j < fw_size; j++) 844 WREG32_SDMA(i, regSDMA_UCODE_DATA, 845 le32_to_cpup(fw_data++)); 846 847 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 848 adev->sdma.instance[i].fw_version); 849 } 850 851 return 0; 852 } 853 854 /** 855 * sdma_v4_4_2_inst_start - setup and start the async dma engines 856 * 857 * @adev: amdgpu_device pointer 858 * @inst_mask: mask of dma engine instances to be enabled 859 * 860 * Set up the DMA engines and enable them. 861 * Returns 0 for success, error for failure. 862 */ 863 static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev, 864 uint32_t inst_mask) 865 { 866 struct amdgpu_ring *ring; 867 uint32_t tmp_mask; 868 int i, r = 0; 869 870 if (amdgpu_sriov_vf(adev)) { 871 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 872 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 873 } else { 874 /* bypass sdma microcode loading on Gopher */ 875 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP && 876 adev->sdma.instance[0].fw) { 877 r = sdma_v4_4_2_inst_load_microcode(adev, inst_mask); 878 if (r) 879 return r; 880 } 881 882 /* unhalt the MEs */ 883 sdma_v4_4_2_inst_enable(adev, true, inst_mask); 884 /* enable sdma ring preemption */ 885 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask); 886 } 887 888 /* start the gfx rings and rlc compute queues */ 889 tmp_mask = inst_mask; 890 for_each_inst(i, tmp_mask) { 891 uint32_t temp; 892 893 WREG32_SDMA(i, regSDMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); 894 sdma_v4_4_2_gfx_resume(adev, i); 895 if (adev->sdma.has_page_queue) 896 sdma_v4_4_2_page_resume(adev, i); 897 898 /* set utc l1 enable flag always to 1 */ 899 temp = RREG32_SDMA(i, regSDMA_CNTL); 900 temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1); 901 /* enable context empty interrupt during initialization */ 902 temp = REG_SET_FIELD(temp, SDMA_CNTL, CTXEMPTY_INT_ENABLE, 1); 903 WREG32_SDMA(i, regSDMA_CNTL, temp); 904 905 if (!amdgpu_sriov_vf(adev)) { 906 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 907 /* unhalt engine */ 908 temp = RREG32_SDMA(i, regSDMA_F32_CNTL); 909 temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0); 910 WREG32_SDMA(i, regSDMA_F32_CNTL, temp); 911 } 912 } 913 } 914 915 if (amdgpu_sriov_vf(adev)) { 916 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask); 917 sdma_v4_4_2_inst_enable(adev, true, inst_mask); 918 } else { 919 r = sdma_v4_4_2_inst_rlc_resume(adev, inst_mask); 920 if (r) 921 return r; 922 } 923 924 tmp_mask = inst_mask; 925 for_each_inst(i, tmp_mask) { 926 ring = &adev->sdma.instance[i].ring; 927 928 r = amdgpu_ring_test_helper(ring); 929 if (r) 930 return r; 931 932 if (adev->sdma.has_page_queue) { 933 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 934 935 r = amdgpu_ring_test_helper(page); 936 if (r) 937 return r; 938 939 if (adev->mman.buffer_funcs_ring == page) 940 amdgpu_ttm_set_buffer_funcs_status(adev, true); 941 } 942 943 if (adev->mman.buffer_funcs_ring == ring) 944 amdgpu_ttm_set_buffer_funcs_status(adev, true); 945 } 946 947 return r; 948 } 949 950 /** 951 * sdma_v4_4_2_ring_test_ring - simple async dma engine test 952 * 953 * @ring: amdgpu_ring structure holding ring information 954 * 955 * Test the DMA engine by writing using it to write an 956 * value to memory. 957 * Returns 0 for success, error for failure. 958 */ 959 static int sdma_v4_4_2_ring_test_ring(struct amdgpu_ring *ring) 960 { 961 struct amdgpu_device *adev = ring->adev; 962 unsigned i; 963 unsigned index; 964 int r; 965 u32 tmp; 966 u64 gpu_addr; 967 968 r = amdgpu_device_wb_get(adev, &index); 969 if (r) 970 return r; 971 972 gpu_addr = adev->wb.gpu_addr + (index * 4); 973 tmp = 0xCAFEDEAD; 974 adev->wb.wb[index] = cpu_to_le32(tmp); 975 976 r = amdgpu_ring_alloc(ring, 5); 977 if (r) 978 goto error_free_wb; 979 980 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 981 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 982 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 983 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 984 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 985 amdgpu_ring_write(ring, 0xDEADBEEF); 986 amdgpu_ring_commit(ring); 987 988 for (i = 0; i < adev->usec_timeout; i++) { 989 tmp = le32_to_cpu(adev->wb.wb[index]); 990 if (tmp == 0xDEADBEEF) 991 break; 992 udelay(1); 993 } 994 995 if (i >= adev->usec_timeout) 996 r = -ETIMEDOUT; 997 998 error_free_wb: 999 amdgpu_device_wb_free(adev, index); 1000 return r; 1001 } 1002 1003 /** 1004 * sdma_v4_4_2_ring_test_ib - test an IB on the DMA engine 1005 * 1006 * @ring: amdgpu_ring structure holding ring information 1007 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1008 * 1009 * Test a simple IB in the DMA ring. 1010 * Returns 0 on success, error on failure. 1011 */ 1012 static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1013 { 1014 struct amdgpu_device *adev = ring->adev; 1015 struct amdgpu_ib ib; 1016 struct dma_fence *f = NULL; 1017 unsigned index; 1018 long r; 1019 u32 tmp = 0; 1020 u64 gpu_addr; 1021 1022 r = amdgpu_device_wb_get(adev, &index); 1023 if (r) 1024 return r; 1025 1026 gpu_addr = adev->wb.gpu_addr + (index * 4); 1027 tmp = 0xCAFEDEAD; 1028 adev->wb.wb[index] = cpu_to_le32(tmp); 1029 memset(&ib, 0, sizeof(ib)); 1030 r = amdgpu_ib_get(adev, NULL, 256, 1031 AMDGPU_IB_POOL_DIRECT, &ib); 1032 if (r) 1033 goto err0; 1034 1035 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1036 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1037 ib.ptr[1] = lower_32_bits(gpu_addr); 1038 ib.ptr[2] = upper_32_bits(gpu_addr); 1039 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1040 ib.ptr[4] = 0xDEADBEEF; 1041 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1042 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1043 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1044 ib.length_dw = 8; 1045 1046 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1047 if (r) 1048 goto err1; 1049 1050 r = dma_fence_wait_timeout(f, false, timeout); 1051 if (r == 0) { 1052 r = -ETIMEDOUT; 1053 goto err1; 1054 } else if (r < 0) { 1055 goto err1; 1056 } 1057 tmp = le32_to_cpu(adev->wb.wb[index]); 1058 if (tmp == 0xDEADBEEF) 1059 r = 0; 1060 else 1061 r = -EINVAL; 1062 1063 err1: 1064 amdgpu_ib_free(adev, &ib, NULL); 1065 dma_fence_put(f); 1066 err0: 1067 amdgpu_device_wb_free(adev, index); 1068 return r; 1069 } 1070 1071 1072 /** 1073 * sdma_v4_4_2_vm_copy_pte - update PTEs by copying them from the GART 1074 * 1075 * @ib: indirect buffer to fill with commands 1076 * @pe: addr of the page entry 1077 * @src: src addr to copy from 1078 * @count: number of page entries to update 1079 * 1080 * Update PTEs by copying them from the GART using sDMA. 1081 */ 1082 static void sdma_v4_4_2_vm_copy_pte(struct amdgpu_ib *ib, 1083 uint64_t pe, uint64_t src, 1084 unsigned count) 1085 { 1086 unsigned bytes = count * 8; 1087 1088 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1089 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1090 ib->ptr[ib->length_dw++] = bytes - 1; 1091 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1092 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1093 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1094 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1095 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1096 1097 } 1098 1099 /** 1100 * sdma_v4_4_2_vm_write_pte - update PTEs by writing them manually 1101 * 1102 * @ib: indirect buffer to fill with commands 1103 * @pe: addr of the page entry 1104 * @value: dst addr to write into pe 1105 * @count: number of page entries to update 1106 * @incr: increase next addr by incr bytes 1107 * 1108 * Update PTEs by writing them manually using sDMA. 1109 */ 1110 static void sdma_v4_4_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1111 uint64_t value, unsigned count, 1112 uint32_t incr) 1113 { 1114 unsigned ndw = count * 2; 1115 1116 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1117 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1118 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1119 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1120 ib->ptr[ib->length_dw++] = ndw - 1; 1121 for (; ndw > 0; ndw -= 2) { 1122 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1123 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1124 value += incr; 1125 } 1126 } 1127 1128 /** 1129 * sdma_v4_4_2_vm_set_pte_pde - update the page tables using sDMA 1130 * 1131 * @ib: indirect buffer to fill with commands 1132 * @pe: addr of the page entry 1133 * @addr: dst addr to write into pe 1134 * @count: number of page entries to update 1135 * @incr: increase next addr by incr bytes 1136 * @flags: access flags 1137 * 1138 * Update the page tables using sDMA. 1139 */ 1140 static void sdma_v4_4_2_vm_set_pte_pde(struct amdgpu_ib *ib, 1141 uint64_t pe, 1142 uint64_t addr, unsigned count, 1143 uint32_t incr, uint64_t flags) 1144 { 1145 /* for physically contiguous pages (vram) */ 1146 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1147 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1148 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1149 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1150 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1151 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1152 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1153 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1154 ib->ptr[ib->length_dw++] = 0; 1155 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1156 } 1157 1158 /** 1159 * sdma_v4_4_2_ring_pad_ib - pad the IB to the required number of dw 1160 * 1161 * @ring: amdgpu_ring structure holding ring information 1162 * @ib: indirect buffer to fill with padding 1163 */ 1164 static void sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1165 { 1166 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1167 u32 pad_count; 1168 int i; 1169 1170 pad_count = (-ib->length_dw) & 7; 1171 for (i = 0; i < pad_count; i++) 1172 if (sdma && sdma->burst_nop && (i == 0)) 1173 ib->ptr[ib->length_dw++] = 1174 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1175 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1176 else 1177 ib->ptr[ib->length_dw++] = 1178 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1179 } 1180 1181 1182 /** 1183 * sdma_v4_4_2_ring_emit_pipeline_sync - sync the pipeline 1184 * 1185 * @ring: amdgpu_ring pointer 1186 * 1187 * Make sure all previous operations are completed (CIK). 1188 */ 1189 static void sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1190 { 1191 uint32_t seq = ring->fence_drv.sync_seq; 1192 uint64_t addr = ring->fence_drv.gpu_addr; 1193 1194 /* wait for idle */ 1195 sdma_v4_4_2_wait_reg_mem(ring, 1, 0, 1196 addr & 0xfffffffc, 1197 upper_32_bits(addr) & 0xffffffff, 1198 seq, 0xffffffff, 4); 1199 } 1200 1201 1202 /** 1203 * sdma_v4_4_2_ring_emit_vm_flush - vm flush using sDMA 1204 * 1205 * @ring: amdgpu_ring pointer 1206 * @vmid: vmid number to use 1207 * @pd_addr: address 1208 * 1209 * Update the page table base and flush the VM TLB 1210 * using sDMA. 1211 */ 1212 static void sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring *ring, 1213 unsigned vmid, uint64_t pd_addr) 1214 { 1215 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1216 } 1217 1218 static void sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring *ring, 1219 uint32_t reg, uint32_t val) 1220 { 1221 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1222 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1223 amdgpu_ring_write(ring, reg); 1224 amdgpu_ring_write(ring, val); 1225 } 1226 1227 static void sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1228 uint32_t val, uint32_t mask) 1229 { 1230 sdma_v4_4_2_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1231 } 1232 1233 static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev) 1234 { 1235 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1236 case IP_VERSION(4, 4, 2): 1237 return false; 1238 default: 1239 return false; 1240 } 1241 } 1242 1243 static int sdma_v4_4_2_early_init(void *handle) 1244 { 1245 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1246 int r; 1247 1248 r = sdma_v4_4_2_init_microcode(adev); 1249 if (r) 1250 return r; 1251 1252 /* TODO: Page queue breaks driver reload under SRIOV */ 1253 if (sdma_v4_4_2_fw_support_paging_queue(adev)) 1254 adev->sdma.has_page_queue = true; 1255 1256 sdma_v4_4_2_set_ring_funcs(adev); 1257 sdma_v4_4_2_set_buffer_funcs(adev); 1258 sdma_v4_4_2_set_vm_pte_funcs(adev); 1259 sdma_v4_4_2_set_irq_funcs(adev); 1260 sdma_v4_4_2_set_ras_funcs(adev); 1261 1262 return 0; 1263 } 1264 1265 #if 0 1266 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, 1267 void *err_data, 1268 struct amdgpu_iv_entry *entry); 1269 #endif 1270 1271 static int sdma_v4_4_2_late_init(void *handle) 1272 { 1273 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1274 #if 0 1275 struct ras_ih_if ih_info = { 1276 .cb = sdma_v4_4_2_process_ras_data_cb, 1277 }; 1278 #endif 1279 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1280 if (adev->sdma.ras && adev->sdma.ras->ras_block.hw_ops && 1281 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count) 1282 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count(adev); 1283 } 1284 1285 return 0; 1286 } 1287 1288 static int sdma_v4_4_2_sw_init(void *handle) 1289 { 1290 struct amdgpu_ring *ring; 1291 int r, i; 1292 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1293 u32 aid_id; 1294 1295 /* SDMA trap event */ 1296 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1297 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1298 SDMA0_4_0__SRCID__SDMA_TRAP, 1299 &adev->sdma.trap_irq); 1300 if (r) 1301 return r; 1302 } 1303 1304 /* SDMA SRAM ECC event */ 1305 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1306 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1307 SDMA0_4_0__SRCID__SDMA_SRAM_ECC, 1308 &adev->sdma.ecc_irq); 1309 if (r) 1310 return r; 1311 } 1312 1313 /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/ 1314 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1315 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1316 SDMA0_4_0__SRCID__SDMA_VM_HOLE, 1317 &adev->sdma.vm_hole_irq); 1318 if (r) 1319 return r; 1320 1321 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1322 SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID, 1323 &adev->sdma.doorbell_invalid_irq); 1324 if (r) 1325 return r; 1326 1327 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1328 SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT, 1329 &adev->sdma.pool_timeout_irq); 1330 if (r) 1331 return r; 1332 1333 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1334 SDMA0_4_0__SRCID__SDMA_SRBMWRITE, 1335 &adev->sdma.srbm_write_irq); 1336 if (r) 1337 return r; 1338 } 1339 1340 for (i = 0; i < adev->sdma.num_instances; i++) { 1341 ring = &adev->sdma.instance[i].ring; 1342 ring->ring_obj = NULL; 1343 ring->use_doorbell = true; 1344 aid_id = adev->sdma.instance[i].aid_id; 1345 1346 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1347 ring->use_doorbell?"true":"false"); 1348 1349 /* doorbell size is 2 dwords, get DWORD offset */ 1350 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1351 ring->vm_hub = AMDGPU_MMHUB0(aid_id); 1352 1353 sprintf(ring->name, "sdma%d.%d", aid_id, 1354 i % adev->sdma.num_inst_per_aid); 1355 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1356 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1357 AMDGPU_RING_PRIO_DEFAULT, NULL); 1358 if (r) 1359 return r; 1360 1361 if (adev->sdma.has_page_queue) { 1362 ring = &adev->sdma.instance[i].page; 1363 ring->ring_obj = NULL; 1364 ring->use_doorbell = true; 1365 1366 /* doorbell index of page queue is assigned right after 1367 * gfx queue on the same instance 1368 */ 1369 ring->doorbell_index = 1370 (adev->doorbell_index.sdma_engine[i] + 1) << 1; 1371 ring->vm_hub = AMDGPU_MMHUB0(aid_id); 1372 1373 sprintf(ring->name, "page%d.%d", aid_id, 1374 i % adev->sdma.num_inst_per_aid); 1375 r = amdgpu_ring_init(adev, ring, 1024, 1376 &adev->sdma.trap_irq, 1377 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1378 AMDGPU_RING_PRIO_DEFAULT, NULL); 1379 if (r) 1380 return r; 1381 } 1382 } 1383 1384 if (amdgpu_sdma_ras_sw_init(adev)) { 1385 dev_err(adev->dev, "fail to initialize sdma ras block\n"); 1386 return -EINVAL; 1387 } 1388 1389 return r; 1390 } 1391 1392 static int sdma_v4_4_2_sw_fini(void *handle) 1393 { 1394 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1395 int i; 1396 1397 for (i = 0; i < adev->sdma.num_instances; i++) { 1398 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1399 if (adev->sdma.has_page_queue) 1400 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1401 } 1402 1403 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2)) 1404 amdgpu_sdma_destroy_inst_ctx(adev, true); 1405 else 1406 amdgpu_sdma_destroy_inst_ctx(adev, false); 1407 1408 return 0; 1409 } 1410 1411 static int sdma_v4_4_2_hw_init(void *handle) 1412 { 1413 int r; 1414 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1415 uint32_t inst_mask; 1416 1417 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1418 if (!amdgpu_sriov_vf(adev)) 1419 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask); 1420 1421 r = sdma_v4_4_2_inst_start(adev, inst_mask); 1422 1423 return r; 1424 } 1425 1426 static int sdma_v4_4_2_hw_fini(void *handle) 1427 { 1428 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1429 uint32_t inst_mask; 1430 int i; 1431 1432 if (amdgpu_sriov_vf(adev)) 1433 return 0; 1434 1435 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1436 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 1437 for (i = 0; i < adev->sdma.num_instances; i++) { 1438 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 1439 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1440 } 1441 } 1442 1443 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 1444 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 1445 1446 return 0; 1447 } 1448 1449 static int sdma_v4_4_2_set_clockgating_state(void *handle, 1450 enum amd_clockgating_state state); 1451 1452 static int sdma_v4_4_2_suspend(void *handle) 1453 { 1454 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1455 1456 if (amdgpu_in_reset(adev)) 1457 sdma_v4_4_2_set_clockgating_state(adev, AMD_CG_STATE_UNGATE); 1458 1459 return sdma_v4_4_2_hw_fini(adev); 1460 } 1461 1462 static int sdma_v4_4_2_resume(void *handle) 1463 { 1464 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1465 1466 return sdma_v4_4_2_hw_init(adev); 1467 } 1468 1469 static bool sdma_v4_4_2_is_idle(void *handle) 1470 { 1471 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1472 u32 i; 1473 1474 for (i = 0; i < adev->sdma.num_instances; i++) { 1475 u32 tmp = RREG32_SDMA(i, regSDMA_STATUS_REG); 1476 1477 if (!(tmp & SDMA_STATUS_REG__IDLE_MASK)) 1478 return false; 1479 } 1480 1481 return true; 1482 } 1483 1484 static int sdma_v4_4_2_wait_for_idle(void *handle) 1485 { 1486 unsigned i, j; 1487 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; 1488 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1489 1490 for (i = 0; i < adev->usec_timeout; i++) { 1491 for (j = 0; j < adev->sdma.num_instances; j++) { 1492 sdma[j] = RREG32_SDMA(j, regSDMA_STATUS_REG); 1493 if (!(sdma[j] & SDMA_STATUS_REG__IDLE_MASK)) 1494 break; 1495 } 1496 if (j == adev->sdma.num_instances) 1497 return 0; 1498 udelay(1); 1499 } 1500 return -ETIMEDOUT; 1501 } 1502 1503 static int sdma_v4_4_2_soft_reset(void *handle) 1504 { 1505 /* todo */ 1506 1507 return 0; 1508 } 1509 1510 static int sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device *adev, 1511 struct amdgpu_irq_src *source, 1512 unsigned type, 1513 enum amdgpu_interrupt_state state) 1514 { 1515 u32 sdma_cntl; 1516 1517 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); 1518 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE, 1519 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1520 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); 1521 1522 return 0; 1523 } 1524 1525 static int sdma_v4_4_2_process_trap_irq(struct amdgpu_device *adev, 1526 struct amdgpu_irq_src *source, 1527 struct amdgpu_iv_entry *entry) 1528 { 1529 uint32_t instance, i; 1530 1531 DRM_DEBUG("IH: SDMA trap\n"); 1532 instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id); 1533 1534 /* Client id gives the SDMA instance in AID. To know the exact SDMA 1535 * instance, interrupt entry gives the node id which corresponds to the AID instance. 1536 * Match node id with the AID id associated with the SDMA instance. */ 1537 for (i = instance; i < adev->sdma.num_instances; 1538 i += adev->sdma.num_inst_per_aid) { 1539 if (adev->sdma.instance[i].aid_id == 1540 node_id_to_phys_map[entry->node_id]) 1541 break; 1542 } 1543 1544 if (i >= adev->sdma.num_instances) { 1545 dev_WARN_ONCE( 1546 adev->dev, 1, 1547 "Couldn't find the right sdma instance in trap handler"); 1548 return 0; 1549 } 1550 1551 switch (entry->ring_id) { 1552 case 0: 1553 amdgpu_fence_process(&adev->sdma.instance[i].ring); 1554 break; 1555 default: 1556 break; 1557 } 1558 return 0; 1559 } 1560 1561 #if 0 1562 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, 1563 void *err_data, 1564 struct amdgpu_iv_entry *entry) 1565 { 1566 int instance; 1567 1568 /* When “Full RAS” is enabled, the per-IP interrupt sources should 1569 * be disabled and the driver should only look for the aggregated 1570 * interrupt via sync flood 1571 */ 1572 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) 1573 goto out; 1574 1575 instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id); 1576 if (instance < 0) 1577 goto out; 1578 1579 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry); 1580 1581 out: 1582 return AMDGPU_RAS_SUCCESS; 1583 } 1584 #endif 1585 1586 static int sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device *adev, 1587 struct amdgpu_irq_src *source, 1588 struct amdgpu_iv_entry *entry) 1589 { 1590 int instance; 1591 1592 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1593 1594 instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id); 1595 if (instance < 0) 1596 return 0; 1597 1598 switch (entry->ring_id) { 1599 case 0: 1600 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 1601 break; 1602 } 1603 return 0; 1604 } 1605 1606 static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev, 1607 struct amdgpu_irq_src *source, 1608 unsigned type, 1609 enum amdgpu_interrupt_state state) 1610 { 1611 u32 sdma_cntl; 1612 1613 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); 1614 switch (state) { 1615 case AMDGPU_IRQ_STATE_DISABLE: 1616 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, 1617 DRAM_ECC_INT_ENABLE, 0); 1618 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); 1619 break; 1620 /* sdma ecc interrupt is enabled by default 1621 * driver doesn't need to do anything to 1622 * enable the interrupt */ 1623 case AMDGPU_IRQ_STATE_ENABLE: 1624 default: 1625 break; 1626 } 1627 1628 return 0; 1629 } 1630 1631 static int sdma_v4_4_2_print_iv_entry(struct amdgpu_device *adev, 1632 struct amdgpu_iv_entry *entry) 1633 { 1634 int instance; 1635 struct amdgpu_task_info task_info; 1636 u64 addr; 1637 1638 instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id); 1639 if (instance < 0 || instance >= adev->sdma.num_instances) { 1640 dev_err(adev->dev, "sdma instance invalid %d\n", instance); 1641 return -EINVAL; 1642 } 1643 1644 addr = (u64)entry->src_data[0] << 12; 1645 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 1646 1647 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 1648 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 1649 1650 dev_dbg_ratelimited(adev->dev, 1651 "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u " 1652 "pasid:%u, for process %s pid %d thread %s pid %d\n", 1653 instance, addr, entry->src_id, entry->ring_id, entry->vmid, 1654 entry->pasid, task_info.process_name, task_info.tgid, 1655 task_info.task_name, task_info.pid); 1656 return 0; 1657 } 1658 1659 static int sdma_v4_4_2_process_vm_hole_irq(struct amdgpu_device *adev, 1660 struct amdgpu_irq_src *source, 1661 struct amdgpu_iv_entry *entry) 1662 { 1663 dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n"); 1664 sdma_v4_4_2_print_iv_entry(adev, entry); 1665 return 0; 1666 } 1667 1668 static int sdma_v4_4_2_process_doorbell_invalid_irq(struct amdgpu_device *adev, 1669 struct amdgpu_irq_src *source, 1670 struct amdgpu_iv_entry *entry) 1671 { 1672 1673 dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n"); 1674 sdma_v4_4_2_print_iv_entry(adev, entry); 1675 return 0; 1676 } 1677 1678 static int sdma_v4_4_2_process_pool_timeout_irq(struct amdgpu_device *adev, 1679 struct amdgpu_irq_src *source, 1680 struct amdgpu_iv_entry *entry) 1681 { 1682 dev_dbg_ratelimited(adev->dev, 1683 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n"); 1684 sdma_v4_4_2_print_iv_entry(adev, entry); 1685 return 0; 1686 } 1687 1688 static int sdma_v4_4_2_process_srbm_write_irq(struct amdgpu_device *adev, 1689 struct amdgpu_irq_src *source, 1690 struct amdgpu_iv_entry *entry) 1691 { 1692 dev_dbg_ratelimited(adev->dev, 1693 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n"); 1694 sdma_v4_4_2_print_iv_entry(adev, entry); 1695 return 0; 1696 } 1697 1698 static void sdma_v4_4_2_inst_update_medium_grain_light_sleep( 1699 struct amdgpu_device *adev, bool enable, uint32_t inst_mask) 1700 { 1701 uint32_t data, def; 1702 int i; 1703 1704 /* leave as default if it is not driver controlled */ 1705 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) 1706 return; 1707 1708 if (enable) { 1709 for_each_inst(i, inst_mask) { 1710 /* 1-not override: enable sdma mem light sleep */ 1711 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL); 1712 data |= SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1713 if (def != data) 1714 WREG32_SDMA(i, regSDMA_POWER_CNTL, data); 1715 } 1716 } else { 1717 for_each_inst(i, inst_mask) { 1718 /* 0-override:disable sdma mem light sleep */ 1719 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL); 1720 data &= ~SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1721 if (def != data) 1722 WREG32_SDMA(i, regSDMA_POWER_CNTL, data); 1723 } 1724 } 1725 } 1726 1727 static void sdma_v4_4_2_inst_update_medium_grain_clock_gating( 1728 struct amdgpu_device *adev, bool enable, uint32_t inst_mask) 1729 { 1730 uint32_t data, def; 1731 int i; 1732 1733 /* leave as default if it is not driver controlled */ 1734 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) 1735 return; 1736 1737 if (enable) { 1738 for_each_inst(i, inst_mask) { 1739 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL); 1740 data &= ~(SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1741 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1742 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1743 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1744 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1745 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1746 if (def != data) 1747 WREG32_SDMA(i, regSDMA_CLK_CTRL, data); 1748 } 1749 } else { 1750 for_each_inst(i, inst_mask) { 1751 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL); 1752 data |= (SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1753 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1754 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1755 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1756 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1757 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1758 if (def != data) 1759 WREG32_SDMA(i, regSDMA_CLK_CTRL, data); 1760 } 1761 } 1762 } 1763 1764 static int sdma_v4_4_2_set_clockgating_state(void *handle, 1765 enum amd_clockgating_state state) 1766 { 1767 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1768 uint32_t inst_mask; 1769 1770 if (amdgpu_sriov_vf(adev)) 1771 return 0; 1772 1773 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1774 1775 sdma_v4_4_2_inst_update_medium_grain_clock_gating( 1776 adev, state == AMD_CG_STATE_GATE, inst_mask); 1777 sdma_v4_4_2_inst_update_medium_grain_light_sleep( 1778 adev, state == AMD_CG_STATE_GATE, inst_mask); 1779 return 0; 1780 } 1781 1782 static int sdma_v4_4_2_set_powergating_state(void *handle, 1783 enum amd_powergating_state state) 1784 { 1785 return 0; 1786 } 1787 1788 static void sdma_v4_4_2_get_clockgating_state(void *handle, u64 *flags) 1789 { 1790 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1791 int data; 1792 1793 if (amdgpu_sriov_vf(adev)) 1794 *flags = 0; 1795 1796 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1797 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL)); 1798 if (!(data & SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK)) 1799 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1800 1801 /* AMD_CG_SUPPORT_SDMA_LS */ 1802 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL)); 1803 if (data & SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1804 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1805 } 1806 1807 const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = { 1808 .name = "sdma_v4_4_2", 1809 .early_init = sdma_v4_4_2_early_init, 1810 .late_init = sdma_v4_4_2_late_init, 1811 .sw_init = sdma_v4_4_2_sw_init, 1812 .sw_fini = sdma_v4_4_2_sw_fini, 1813 .hw_init = sdma_v4_4_2_hw_init, 1814 .hw_fini = sdma_v4_4_2_hw_fini, 1815 .suspend = sdma_v4_4_2_suspend, 1816 .resume = sdma_v4_4_2_resume, 1817 .is_idle = sdma_v4_4_2_is_idle, 1818 .wait_for_idle = sdma_v4_4_2_wait_for_idle, 1819 .soft_reset = sdma_v4_4_2_soft_reset, 1820 .set_clockgating_state = sdma_v4_4_2_set_clockgating_state, 1821 .set_powergating_state = sdma_v4_4_2_set_powergating_state, 1822 .get_clockgating_state = sdma_v4_4_2_get_clockgating_state, 1823 }; 1824 1825 static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = { 1826 .type = AMDGPU_RING_TYPE_SDMA, 1827 .align_mask = 0xff, 1828 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1829 .support_64bit_ptrs = true, 1830 .get_rptr = sdma_v4_4_2_ring_get_rptr, 1831 .get_wptr = sdma_v4_4_2_ring_get_wptr, 1832 .set_wptr = sdma_v4_4_2_ring_set_wptr, 1833 .emit_frame_size = 1834 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */ 1835 3 + /* hdp invalidate */ 1836 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */ 1837 /* sdma_v4_4_2_ring_emit_vm_flush */ 1838 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1839 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1840 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */ 1841 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */ 1842 .emit_ib = sdma_v4_4_2_ring_emit_ib, 1843 .emit_fence = sdma_v4_4_2_ring_emit_fence, 1844 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync, 1845 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush, 1846 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush, 1847 .test_ring = sdma_v4_4_2_ring_test_ring, 1848 .test_ib = sdma_v4_4_2_ring_test_ib, 1849 .insert_nop = sdma_v4_4_2_ring_insert_nop, 1850 .pad_ib = sdma_v4_4_2_ring_pad_ib, 1851 .emit_wreg = sdma_v4_4_2_ring_emit_wreg, 1852 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, 1853 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1854 }; 1855 1856 static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = { 1857 .type = AMDGPU_RING_TYPE_SDMA, 1858 .align_mask = 0xff, 1859 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1860 .support_64bit_ptrs = true, 1861 .get_rptr = sdma_v4_4_2_ring_get_rptr, 1862 .get_wptr = sdma_v4_4_2_page_ring_get_wptr, 1863 .set_wptr = sdma_v4_4_2_page_ring_set_wptr, 1864 .emit_frame_size = 1865 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */ 1866 3 + /* hdp invalidate */ 1867 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */ 1868 /* sdma_v4_4_2_ring_emit_vm_flush */ 1869 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1870 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1871 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */ 1872 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */ 1873 .emit_ib = sdma_v4_4_2_ring_emit_ib, 1874 .emit_fence = sdma_v4_4_2_ring_emit_fence, 1875 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync, 1876 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush, 1877 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush, 1878 .test_ring = sdma_v4_4_2_ring_test_ring, 1879 .test_ib = sdma_v4_4_2_ring_test_ib, 1880 .insert_nop = sdma_v4_4_2_ring_insert_nop, 1881 .pad_ib = sdma_v4_4_2_ring_pad_ib, 1882 .emit_wreg = sdma_v4_4_2_ring_emit_wreg, 1883 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, 1884 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1885 }; 1886 1887 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev) 1888 { 1889 int i, dev_inst; 1890 1891 for (i = 0; i < adev->sdma.num_instances; i++) { 1892 adev->sdma.instance[i].ring.funcs = &sdma_v4_4_2_ring_funcs; 1893 adev->sdma.instance[i].ring.me = i; 1894 if (adev->sdma.has_page_queue) { 1895 adev->sdma.instance[i].page.funcs = 1896 &sdma_v4_4_2_page_ring_funcs; 1897 adev->sdma.instance[i].page.me = i; 1898 } 1899 1900 dev_inst = GET_INST(SDMA0, i); 1901 /* AID to which SDMA belongs depends on physical instance */ 1902 adev->sdma.instance[i].aid_id = 1903 dev_inst / adev->sdma.num_inst_per_aid; 1904 } 1905 } 1906 1907 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_trap_irq_funcs = { 1908 .set = sdma_v4_4_2_set_trap_irq_state, 1909 .process = sdma_v4_4_2_process_trap_irq, 1910 }; 1911 1912 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_illegal_inst_irq_funcs = { 1913 .process = sdma_v4_4_2_process_illegal_inst_irq, 1914 }; 1915 1916 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ecc_irq_funcs = { 1917 .set = sdma_v4_4_2_set_ecc_irq_state, 1918 .process = amdgpu_sdma_process_ecc_irq, 1919 }; 1920 1921 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_vm_hole_irq_funcs = { 1922 .process = sdma_v4_4_2_process_vm_hole_irq, 1923 }; 1924 1925 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_doorbell_invalid_irq_funcs = { 1926 .process = sdma_v4_4_2_process_doorbell_invalid_irq, 1927 }; 1928 1929 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_pool_timeout_irq_funcs = { 1930 .process = sdma_v4_4_2_process_pool_timeout_irq, 1931 }; 1932 1933 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_srbm_write_irq_funcs = { 1934 .process = sdma_v4_4_2_process_srbm_write_irq, 1935 }; 1936 1937 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev) 1938 { 1939 adev->sdma.trap_irq.num_types = adev->sdma.num_instances; 1940 adev->sdma.ecc_irq.num_types = adev->sdma.num_instances; 1941 adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances; 1942 adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances; 1943 adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances; 1944 adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances; 1945 1946 adev->sdma.trap_irq.funcs = &sdma_v4_4_2_trap_irq_funcs; 1947 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_4_2_illegal_inst_irq_funcs; 1948 adev->sdma.ecc_irq.funcs = &sdma_v4_4_2_ecc_irq_funcs; 1949 adev->sdma.vm_hole_irq.funcs = &sdma_v4_4_2_vm_hole_irq_funcs; 1950 adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_4_2_doorbell_invalid_irq_funcs; 1951 adev->sdma.pool_timeout_irq.funcs = &sdma_v4_4_2_pool_timeout_irq_funcs; 1952 adev->sdma.srbm_write_irq.funcs = &sdma_v4_4_2_srbm_write_irq_funcs; 1953 } 1954 1955 /** 1956 * sdma_v4_4_2_emit_copy_buffer - copy buffer using the sDMA engine 1957 * 1958 * @ib: indirect buffer to copy to 1959 * @src_offset: src GPU address 1960 * @dst_offset: dst GPU address 1961 * @byte_count: number of bytes to xfer 1962 * @tmz: if a secure copy should be used 1963 * 1964 * Copy GPU buffers using the DMA engine. 1965 * Used by the amdgpu ttm implementation to move pages if 1966 * registered as the asic copy callback. 1967 */ 1968 static void sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib *ib, 1969 uint64_t src_offset, 1970 uint64_t dst_offset, 1971 uint32_t byte_count, 1972 bool tmz) 1973 { 1974 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1975 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1976 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 1977 ib->ptr[ib->length_dw++] = byte_count - 1; 1978 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1979 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1980 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1981 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1982 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1983 } 1984 1985 /** 1986 * sdma_v4_4_2_emit_fill_buffer - fill buffer using the sDMA engine 1987 * 1988 * @ib: indirect buffer to copy to 1989 * @src_data: value to write to buffer 1990 * @dst_offset: dst GPU address 1991 * @byte_count: number of bytes to xfer 1992 * 1993 * Fill GPU buffers using the DMA engine. 1994 */ 1995 static void sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib *ib, 1996 uint32_t src_data, 1997 uint64_t dst_offset, 1998 uint32_t byte_count) 1999 { 2000 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2001 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2002 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2003 ib->ptr[ib->length_dw++] = src_data; 2004 ib->ptr[ib->length_dw++] = byte_count - 1; 2005 } 2006 2007 static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = { 2008 .copy_max_bytes = 0x400000, 2009 .copy_num_dw = 7, 2010 .emit_copy_buffer = sdma_v4_4_2_emit_copy_buffer, 2011 2012 .fill_max_bytes = 0x400000, 2013 .fill_num_dw = 5, 2014 .emit_fill_buffer = sdma_v4_4_2_emit_fill_buffer, 2015 }; 2016 2017 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev) 2018 { 2019 adev->mman.buffer_funcs = &sdma_v4_4_2_buffer_funcs; 2020 if (adev->sdma.has_page_queue) 2021 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; 2022 else 2023 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2024 } 2025 2026 static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = { 2027 .copy_pte_num_dw = 7, 2028 .copy_pte = sdma_v4_4_2_vm_copy_pte, 2029 2030 .write_pte = sdma_v4_4_2_vm_write_pte, 2031 .set_pte_pde = sdma_v4_4_2_vm_set_pte_pde, 2032 }; 2033 2034 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev) 2035 { 2036 struct drm_gpu_scheduler *sched; 2037 unsigned i; 2038 2039 adev->vm_manager.vm_pte_funcs = &sdma_v4_4_2_vm_pte_funcs; 2040 for (i = 0; i < adev->sdma.num_instances; i++) { 2041 if (adev->sdma.has_page_queue) 2042 sched = &adev->sdma.instance[i].page.sched; 2043 else 2044 sched = &adev->sdma.instance[i].ring.sched; 2045 adev->vm_manager.vm_pte_scheds[i] = sched; 2046 } 2047 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 2048 } 2049 2050 const struct amdgpu_ip_block_version sdma_v4_4_2_ip_block = { 2051 .type = AMD_IP_BLOCK_TYPE_SDMA, 2052 .major = 4, 2053 .minor = 4, 2054 .rev = 0, 2055 .funcs = &sdma_v4_4_2_ip_funcs, 2056 }; 2057 2058 static int sdma_v4_4_2_xcp_resume(void *handle, uint32_t inst_mask) 2059 { 2060 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2061 int r; 2062 2063 if (!amdgpu_sriov_vf(adev)) 2064 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask); 2065 2066 r = sdma_v4_4_2_inst_start(adev, inst_mask); 2067 2068 return r; 2069 } 2070 2071 static int sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask) 2072 { 2073 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2074 uint32_t tmp_mask = inst_mask; 2075 int i; 2076 2077 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2078 for_each_inst(i, tmp_mask) { 2079 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 2080 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 2081 } 2082 } 2083 2084 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 2085 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 2086 2087 return 0; 2088 } 2089 2090 struct amdgpu_xcp_ip_funcs sdma_v4_4_2_xcp_funcs = { 2091 .suspend = &sdma_v4_4_2_xcp_suspend, 2092 .resume = &sdma_v4_4_2_xcp_resume 2093 }; 2094 2095 static const struct amdgpu_ras_err_status_reg_entry sdma_v4_2_2_ue_reg_list[] = { 2096 {AMDGPU_RAS_REG_ENTRY(SDMA0, 0, regSDMA_UE_ERR_STATUS_LO, regSDMA_UE_ERR_STATUS_HI), 2097 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SDMA"}, 2098 }; 2099 2100 static const struct amdgpu_ras_memory_id_entry sdma_v4_4_2_ras_memory_list[] = { 2101 {AMDGPU_SDMA_MBANK_DATA_BUF0, "SDMA_MBANK_DATA_BUF0"}, 2102 {AMDGPU_SDMA_MBANK_DATA_BUF1, "SDMA_MBANK_DATA_BUF1"}, 2103 {AMDGPU_SDMA_MBANK_DATA_BUF2, "SDMA_MBANK_DATA_BUF2"}, 2104 {AMDGPU_SDMA_MBANK_DATA_BUF3, "SDMA_MBANK_DATA_BUF3"}, 2105 {AMDGPU_SDMA_MBANK_DATA_BUF4, "SDMA_MBANK_DATA_BUF4"}, 2106 {AMDGPU_SDMA_MBANK_DATA_BUF5, "SDMA_MBANK_DATA_BUF5"}, 2107 {AMDGPU_SDMA_MBANK_DATA_BUF6, "SDMA_MBANK_DATA_BUF6"}, 2108 {AMDGPU_SDMA_MBANK_DATA_BUF7, "SDMA_MBANK_DATA_BUF7"}, 2109 {AMDGPU_SDMA_MBANK_DATA_BUF8, "SDMA_MBANK_DATA_BUF8"}, 2110 {AMDGPU_SDMA_MBANK_DATA_BUF9, "SDMA_MBANK_DATA_BUF9"}, 2111 {AMDGPU_SDMA_MBANK_DATA_BUF10, "SDMA_MBANK_DATA_BUF10"}, 2112 {AMDGPU_SDMA_MBANK_DATA_BUF11, "SDMA_MBANK_DATA_BUF11"}, 2113 {AMDGPU_SDMA_MBANK_DATA_BUF12, "SDMA_MBANK_DATA_BUF12"}, 2114 {AMDGPU_SDMA_MBANK_DATA_BUF13, "SDMA_MBANK_DATA_BUF13"}, 2115 {AMDGPU_SDMA_MBANK_DATA_BUF14, "SDMA_MBANK_DATA_BUF14"}, 2116 {AMDGPU_SDMA_MBANK_DATA_BUF15, "SDMA_MBANK_DATA_BUF15"}, 2117 {AMDGPU_SDMA_UCODE_BUF, "SDMA_UCODE_BUF"}, 2118 {AMDGPU_SDMA_RB_CMD_BUF, "SDMA_RB_CMD_BUF"}, 2119 {AMDGPU_SDMA_IB_CMD_BUF, "SDMA_IB_CMD_BUF"}, 2120 {AMDGPU_SDMA_UTCL1_RD_FIFO, "SDMA_UTCL1_RD_FIFO"}, 2121 {AMDGPU_SDMA_UTCL1_RDBST_FIFO, "SDMA_UTCL1_RDBST_FIFO"}, 2122 {AMDGPU_SDMA_UTCL1_WR_FIFO, "SDMA_UTCL1_WR_FIFO"}, 2123 {AMDGPU_SDMA_DATA_LUT_FIFO, "SDMA_DATA_LUT_FIFO"}, 2124 {AMDGPU_SDMA_SPLIT_DAT_BUF, "SDMA_SPLIT_DAT_BUF"}, 2125 }; 2126 2127 static void sdma_v4_4_2_inst_query_ras_error_count(struct amdgpu_device *adev, 2128 uint32_t sdma_inst, 2129 void *ras_err_status) 2130 { 2131 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 2132 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); 2133 2134 /* sdma v4_4_2 doesn't support query ce counts */ 2135 amdgpu_ras_inst_query_ras_error_count(adev, 2136 sdma_v4_2_2_ue_reg_list, 2137 ARRAY_SIZE(sdma_v4_2_2_ue_reg_list), 2138 sdma_v4_4_2_ras_memory_list, 2139 ARRAY_SIZE(sdma_v4_4_2_ras_memory_list), 2140 sdma_dev_inst, 2141 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 2142 &err_data->ue_count); 2143 } 2144 2145 static void sdma_v4_4_2_query_ras_error_count(struct amdgpu_device *adev, 2146 void *ras_err_status) 2147 { 2148 uint32_t inst_mask; 2149 int i = 0; 2150 2151 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 2152 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2153 for_each_inst(i, inst_mask) 2154 sdma_v4_4_2_inst_query_ras_error_count(adev, i, ras_err_status); 2155 } else { 2156 dev_warn(adev->dev, "SDMA RAS is not supported\n"); 2157 } 2158 } 2159 2160 static void sdma_v4_4_2_inst_reset_ras_error_count(struct amdgpu_device *adev, 2161 uint32_t sdma_inst) 2162 { 2163 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); 2164 2165 amdgpu_ras_inst_reset_ras_error_count(adev, 2166 sdma_v4_2_2_ue_reg_list, 2167 ARRAY_SIZE(sdma_v4_2_2_ue_reg_list), 2168 sdma_dev_inst); 2169 } 2170 2171 static void sdma_v4_4_2_reset_ras_error_count(struct amdgpu_device *adev) 2172 { 2173 uint32_t inst_mask; 2174 int i = 0; 2175 2176 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 2177 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2178 for_each_inst(i, inst_mask) 2179 sdma_v4_4_2_inst_reset_ras_error_count(adev, i); 2180 } else { 2181 dev_warn(adev->dev, "SDMA RAS is not supported\n"); 2182 } 2183 } 2184 2185 static const struct amdgpu_ras_block_hw_ops sdma_v4_4_2_ras_hw_ops = { 2186 .query_ras_error_count = sdma_v4_4_2_query_ras_error_count, 2187 .reset_ras_error_count = sdma_v4_4_2_reset_ras_error_count, 2188 }; 2189 2190 static struct amdgpu_sdma_ras sdma_v4_4_2_ras = { 2191 .ras_block = { 2192 .hw_ops = &sdma_v4_4_2_ras_hw_ops, 2193 }, 2194 }; 2195 2196 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev) 2197 { 2198 adev->sdma.ras = &sdma_v4_4_2_ras; 2199 } 2200