1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_xcp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_trace.h" 33 34 #include "sdma/sdma_4_4_2_offset.h" 35 #include "sdma/sdma_4_4_2_sh_mask.h" 36 37 #include "soc15_common.h" 38 #include "soc15.h" 39 #include "vega10_sdma_pkt_open.h" 40 41 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 42 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 43 44 #include "amdgpu_ras.h" 45 46 MODULE_FIRMWARE("amdgpu/sdma_4_4_2.bin"); 47 MODULE_FIRMWARE("amdgpu/sdma_4_4_5.bin"); 48 49 static const struct amdgpu_hwip_reg_entry sdma_reg_list_4_4_2[] = { 50 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS_REG), 51 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS1_REG), 52 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS2_REG), 53 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS3_REG), 54 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UCODE_CHECKSUM), 55 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH_HI), 56 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH), 57 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_STATUS), 58 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_STATUS), 59 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK0), 60 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK1), 61 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK0), 62 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK1), 63 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_CNTL), 64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR), 65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR_HI), 66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR), 67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR_HI), 68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_OFFSET), 69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_LO), 70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_HI), 71 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_CNTL), 72 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_RPTR), 73 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_SUB_REMAIN), 74 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_DUMMY_REG), 75 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_CNTL), 76 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR), 77 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR_HI), 78 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR), 79 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR_HI), 80 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_OFFSET), 81 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_LO), 82 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_HI), 83 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_DUMMY_REG), 84 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_CNTL), 85 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR), 86 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR_HI), 87 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR), 88 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR_HI), 89 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_OFFSET), 90 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_LO), 91 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_HI), 92 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_DUMMY_REG), 93 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_VM_CNTL) 94 }; 95 96 #define mmSMNAID_AID0_MCA_SMU 0x03b30400 97 98 #define WREG32_SDMA(instance, offset, value) \ 99 WREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)), value) 100 #define RREG32_SDMA(instance, offset) \ 101 RREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset))) 102 103 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev); 104 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev); 105 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev); 106 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev); 107 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev); 108 109 static u32 sdma_v4_4_2_get_reg_offset(struct amdgpu_device *adev, 110 u32 instance, u32 offset) 111 { 112 u32 dev_inst = GET_INST(SDMA0, instance); 113 114 return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset); 115 } 116 117 static unsigned sdma_v4_4_2_seq_to_irq_id(int seq_num) 118 { 119 switch (seq_num) { 120 case 0: 121 return SOC15_IH_CLIENTID_SDMA0; 122 case 1: 123 return SOC15_IH_CLIENTID_SDMA1; 124 case 2: 125 return SOC15_IH_CLIENTID_SDMA2; 126 case 3: 127 return SOC15_IH_CLIENTID_SDMA3; 128 default: 129 return -EINVAL; 130 } 131 } 132 133 static int sdma_v4_4_2_irq_id_to_seq(struct amdgpu_device *adev, unsigned client_id) 134 { 135 switch (client_id) { 136 case SOC15_IH_CLIENTID_SDMA0: 137 return 0; 138 case SOC15_IH_CLIENTID_SDMA1: 139 return 1; 140 case SOC15_IH_CLIENTID_SDMA2: 141 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) 142 return 0; 143 else 144 return 2; 145 case SOC15_IH_CLIENTID_SDMA3: 146 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) 147 return 1; 148 else 149 return 3; 150 default: 151 return -EINVAL; 152 } 153 } 154 155 static void sdma_v4_4_2_inst_init_golden_registers(struct amdgpu_device *adev, 156 uint32_t inst_mask) 157 { 158 u32 val; 159 int i; 160 161 for (i = 0; i < adev->sdma.num_instances; i++) { 162 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG); 163 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4); 164 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, 165 PIPE_INTERLEAVE_SIZE, 0); 166 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG, val); 167 168 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ); 169 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS, 170 4); 171 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, 172 PIPE_INTERLEAVE_SIZE, 0); 173 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ, val); 174 } 175 } 176 177 /** 178 * sdma_v4_4_2_init_microcode - load ucode images from disk 179 * 180 * @adev: amdgpu_device pointer 181 * 182 * Use the firmware interface to load the ucode images into 183 * the driver (not loaded into hw). 184 * Returns 0 on success, error on failure. 185 */ 186 static int sdma_v4_4_2_init_microcode(struct amdgpu_device *adev) 187 { 188 int ret, i; 189 190 for (i = 0; i < adev->sdma.num_instances; i++) { 191 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) || 192 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) { 193 ret = amdgpu_sdma_init_microcode(adev, 0, true); 194 break; 195 } else { 196 ret = amdgpu_sdma_init_microcode(adev, i, false); 197 if (ret) 198 return ret; 199 } 200 } 201 202 return ret; 203 } 204 205 /** 206 * sdma_v4_4_2_ring_get_rptr - get the current read pointer 207 * 208 * @ring: amdgpu ring pointer 209 * 210 * Get the current rptr from the hardware. 211 */ 212 static uint64_t sdma_v4_4_2_ring_get_rptr(struct amdgpu_ring *ring) 213 { 214 u64 rptr; 215 216 /* XXX check if swapping is necessary on BE */ 217 rptr = READ_ONCE(*((u64 *)&ring->adev->wb.wb[ring->rptr_offs])); 218 219 DRM_DEBUG("rptr before shift == 0x%016llx\n", rptr); 220 return rptr >> 2; 221 } 222 223 /** 224 * sdma_v4_4_2_ring_get_wptr - get the current write pointer 225 * 226 * @ring: amdgpu ring pointer 227 * 228 * Get the current wptr from the hardware. 229 */ 230 static uint64_t sdma_v4_4_2_ring_get_wptr(struct amdgpu_ring *ring) 231 { 232 struct amdgpu_device *adev = ring->adev; 233 u64 wptr; 234 235 if (ring->use_doorbell) { 236 /* XXX check if swapping is necessary on BE */ 237 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 238 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 239 } else { 240 wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI); 241 wptr = wptr << 32; 242 wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR); 243 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 244 ring->me, wptr); 245 } 246 247 return wptr >> 2; 248 } 249 250 /** 251 * sdma_v4_4_2_ring_set_wptr - commit the write pointer 252 * 253 * @ring: amdgpu ring pointer 254 * 255 * Write the wptr back to the hardware. 256 */ 257 static void sdma_v4_4_2_ring_set_wptr(struct amdgpu_ring *ring) 258 { 259 struct amdgpu_device *adev = ring->adev; 260 261 DRM_DEBUG("Setting write pointer\n"); 262 if (ring->use_doorbell) { 263 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 264 265 DRM_DEBUG("Using doorbell -- " 266 "wptr_offs == 0x%08x " 267 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 268 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 269 ring->wptr_offs, 270 lower_32_bits(ring->wptr << 2), 271 upper_32_bits(ring->wptr << 2)); 272 /* XXX check if swapping is necessary on BE */ 273 WRITE_ONCE(*wb, (ring->wptr << 2)); 274 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 275 ring->doorbell_index, ring->wptr << 2); 276 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 277 } else { 278 DRM_DEBUG("Not using doorbell -- " 279 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 280 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 281 ring->me, 282 lower_32_bits(ring->wptr << 2), 283 ring->me, 284 upper_32_bits(ring->wptr << 2)); 285 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR, 286 lower_32_bits(ring->wptr << 2)); 287 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI, 288 upper_32_bits(ring->wptr << 2)); 289 } 290 } 291 292 /** 293 * sdma_v4_4_2_page_ring_get_wptr - get the current write pointer 294 * 295 * @ring: amdgpu ring pointer 296 * 297 * Get the current wptr from the hardware. 298 */ 299 static uint64_t sdma_v4_4_2_page_ring_get_wptr(struct amdgpu_ring *ring) 300 { 301 struct amdgpu_device *adev = ring->adev; 302 u64 wptr; 303 304 if (ring->use_doorbell) { 305 /* XXX check if swapping is necessary on BE */ 306 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 307 } else { 308 wptr = RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI); 309 wptr = wptr << 32; 310 wptr |= RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR); 311 } 312 313 return wptr >> 2; 314 } 315 316 /** 317 * sdma_v4_4_2_page_ring_set_wptr - commit the write pointer 318 * 319 * @ring: amdgpu ring pointer 320 * 321 * Write the wptr back to the hardware. 322 */ 323 static void sdma_v4_4_2_page_ring_set_wptr(struct amdgpu_ring *ring) 324 { 325 struct amdgpu_device *adev = ring->adev; 326 327 if (ring->use_doorbell) { 328 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 329 330 /* XXX check if swapping is necessary on BE */ 331 WRITE_ONCE(*wb, (ring->wptr << 2)); 332 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 333 } else { 334 uint64_t wptr = ring->wptr << 2; 335 336 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR, 337 lower_32_bits(wptr)); 338 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI, 339 upper_32_bits(wptr)); 340 } 341 } 342 343 static void sdma_v4_4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 344 { 345 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 346 int i; 347 348 for (i = 0; i < count; i++) 349 if (sdma && sdma->burst_nop && (i == 0)) 350 amdgpu_ring_write(ring, ring->funcs->nop | 351 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 352 else 353 amdgpu_ring_write(ring, ring->funcs->nop); 354 } 355 356 /** 357 * sdma_v4_4_2_ring_emit_ib - Schedule an IB on the DMA engine 358 * 359 * @ring: amdgpu ring pointer 360 * @job: job to retrieve vmid from 361 * @ib: IB object to schedule 362 * @flags: unused 363 * 364 * Schedule an IB in the DMA ring. 365 */ 366 static void sdma_v4_4_2_ring_emit_ib(struct amdgpu_ring *ring, 367 struct amdgpu_job *job, 368 struct amdgpu_ib *ib, 369 uint32_t flags) 370 { 371 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 372 373 /* IB packet must end on a 8 DW boundary */ 374 sdma_v4_4_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 375 376 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 377 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 378 /* base must be 32 byte aligned */ 379 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 380 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 381 amdgpu_ring_write(ring, ib->length_dw); 382 amdgpu_ring_write(ring, 0); 383 amdgpu_ring_write(ring, 0); 384 385 } 386 387 static void sdma_v4_4_2_wait_reg_mem(struct amdgpu_ring *ring, 388 int mem_space, int hdp, 389 uint32_t addr0, uint32_t addr1, 390 uint32_t ref, uint32_t mask, 391 uint32_t inv) 392 { 393 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 394 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 395 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 396 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 397 if (mem_space) { 398 /* memory */ 399 amdgpu_ring_write(ring, addr0); 400 amdgpu_ring_write(ring, addr1); 401 } else { 402 /* registers */ 403 amdgpu_ring_write(ring, addr0 << 2); 404 amdgpu_ring_write(ring, addr1 << 2); 405 } 406 amdgpu_ring_write(ring, ref); /* reference */ 407 amdgpu_ring_write(ring, mask); /* mask */ 408 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 409 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 410 } 411 412 /** 413 * sdma_v4_4_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 414 * 415 * @ring: amdgpu ring pointer 416 * 417 * Emit an hdp flush packet on the requested DMA ring. 418 */ 419 static void sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 420 { 421 struct amdgpu_device *adev = ring->adev; 422 u32 ref_and_mask = 0; 423 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 424 425 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 426 << (ring->me % adev->sdma.num_inst_per_aid); 427 428 sdma_v4_4_2_wait_reg_mem(ring, 0, 1, 429 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 430 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 431 ref_and_mask, ref_and_mask, 10); 432 } 433 434 /** 435 * sdma_v4_4_2_ring_emit_fence - emit a fence on the DMA ring 436 * 437 * @ring: amdgpu ring pointer 438 * @addr: address 439 * @seq: sequence number 440 * @flags: fence related flags 441 * 442 * Add a DMA fence packet to the ring to write 443 * the fence seq number and DMA trap packet to generate 444 * an interrupt if needed. 445 */ 446 static void sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 447 unsigned flags) 448 { 449 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 450 /* write the fence */ 451 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 452 /* zero in first two bits */ 453 BUG_ON(addr & 0x3); 454 amdgpu_ring_write(ring, lower_32_bits(addr)); 455 amdgpu_ring_write(ring, upper_32_bits(addr)); 456 amdgpu_ring_write(ring, lower_32_bits(seq)); 457 458 /* optionally write high bits as well */ 459 if (write64bit) { 460 addr += 4; 461 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 462 /* zero in first two bits */ 463 BUG_ON(addr & 0x3); 464 amdgpu_ring_write(ring, lower_32_bits(addr)); 465 amdgpu_ring_write(ring, upper_32_bits(addr)); 466 amdgpu_ring_write(ring, upper_32_bits(seq)); 467 } 468 469 /* generate an interrupt */ 470 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 471 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 472 } 473 474 475 /** 476 * sdma_v4_4_2_inst_gfx_stop - stop the gfx async dma engines 477 * 478 * @adev: amdgpu_device pointer 479 * @inst_mask: mask of dma engine instances to be disabled 480 * 481 * Stop the gfx async dma ring buffers. 482 */ 483 static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev, 484 uint32_t inst_mask) 485 { 486 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 487 u32 doorbell_offset, doorbell; 488 u32 rb_cntl, ib_cntl; 489 int i; 490 491 for_each_inst(i, inst_mask) { 492 sdma[i] = &adev->sdma.instance[i].ring; 493 494 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); 495 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0); 496 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 497 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 498 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0); 499 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 500 501 if (sdma[i]->use_doorbell) { 502 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL); 503 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET); 504 505 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 0); 506 doorbell_offset = REG_SET_FIELD(doorbell_offset, 507 SDMA_GFX_DOORBELL_OFFSET, 508 OFFSET, 0); 509 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell); 510 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset); 511 } 512 } 513 } 514 515 /** 516 * sdma_v4_4_2_inst_rlc_stop - stop the compute async dma engines 517 * 518 * @adev: amdgpu_device pointer 519 * @inst_mask: mask of dma engine instances to be disabled 520 * 521 * Stop the compute async dma queues. 522 */ 523 static void sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device *adev, 524 uint32_t inst_mask) 525 { 526 /* XXX todo */ 527 } 528 529 /** 530 * sdma_v4_4_2_inst_page_stop - stop the page async dma engines 531 * 532 * @adev: amdgpu_device pointer 533 * @inst_mask: mask of dma engine instances to be disabled 534 * 535 * Stop the page async dma ring buffers. 536 */ 537 static void sdma_v4_4_2_inst_page_stop(struct amdgpu_device *adev, 538 uint32_t inst_mask) 539 { 540 u32 rb_cntl, ib_cntl; 541 int i; 542 543 for_each_inst(i, inst_mask) { 544 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); 545 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, 546 RB_ENABLE, 0); 547 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 548 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); 549 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, 550 IB_ENABLE, 0); 551 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); 552 } 553 } 554 555 /** 556 * sdma_v4_4_2_inst_ctx_switch_enable - stop the async dma engines context switch 557 * 558 * @adev: amdgpu_device pointer 559 * @enable: enable/disable the DMA MEs context switch. 560 * @inst_mask: mask of dma engine instances to be enabled 561 * 562 * Halt or unhalt the async dma engines context switch. 563 */ 564 static void sdma_v4_4_2_inst_ctx_switch_enable(struct amdgpu_device *adev, 565 bool enable, uint32_t inst_mask) 566 { 567 u32 f32_cntl, phase_quantum = 0; 568 int i; 569 570 if (amdgpu_sdma_phase_quantum) { 571 unsigned value = amdgpu_sdma_phase_quantum; 572 unsigned unit = 0; 573 574 while (value > (SDMA_PHASE0_QUANTUM__VALUE_MASK >> 575 SDMA_PHASE0_QUANTUM__VALUE__SHIFT)) { 576 value = (value + 1) >> 1; 577 unit++; 578 } 579 if (unit > (SDMA_PHASE0_QUANTUM__UNIT_MASK >> 580 SDMA_PHASE0_QUANTUM__UNIT__SHIFT)) { 581 value = (SDMA_PHASE0_QUANTUM__VALUE_MASK >> 582 SDMA_PHASE0_QUANTUM__VALUE__SHIFT); 583 unit = (SDMA_PHASE0_QUANTUM__UNIT_MASK >> 584 SDMA_PHASE0_QUANTUM__UNIT__SHIFT); 585 WARN_ONCE(1, 586 "clamping sdma_phase_quantum to %uK clock cycles\n", 587 value << unit); 588 } 589 phase_quantum = 590 value << SDMA_PHASE0_QUANTUM__VALUE__SHIFT | 591 unit << SDMA_PHASE0_QUANTUM__UNIT__SHIFT; 592 } 593 594 for_each_inst(i, inst_mask) { 595 f32_cntl = RREG32_SDMA(i, regSDMA_CNTL); 596 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_CNTL, 597 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 598 if (enable && amdgpu_sdma_phase_quantum) { 599 WREG32_SDMA(i, regSDMA_PHASE0_QUANTUM, phase_quantum); 600 WREG32_SDMA(i, regSDMA_PHASE1_QUANTUM, phase_quantum); 601 WREG32_SDMA(i, regSDMA_PHASE2_QUANTUM, phase_quantum); 602 } 603 WREG32_SDMA(i, regSDMA_CNTL, f32_cntl); 604 605 /* Extend page fault timeout to avoid interrupt storm */ 606 WREG32_SDMA(i, regSDMA_UTCL1_TIMEOUT, 0x00800080); 607 } 608 } 609 610 /** 611 * sdma_v4_4_2_inst_enable - stop the async dma engines 612 * 613 * @adev: amdgpu_device pointer 614 * @enable: enable/disable the DMA MEs. 615 * @inst_mask: mask of dma engine instances to be enabled 616 * 617 * Halt or unhalt the async dma engines. 618 */ 619 static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable, 620 uint32_t inst_mask) 621 { 622 u32 f32_cntl; 623 int i; 624 625 if (!enable) { 626 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask); 627 sdma_v4_4_2_inst_rlc_stop(adev, inst_mask); 628 if (adev->sdma.has_page_queue) 629 sdma_v4_4_2_inst_page_stop(adev, inst_mask); 630 631 /* SDMA FW needs to respond to FREEZE requests during reset. 632 * Keep it running during reset */ 633 if (!amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 634 return; 635 } 636 637 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 638 return; 639 640 for_each_inst(i, inst_mask) { 641 f32_cntl = RREG32_SDMA(i, regSDMA_F32_CNTL); 642 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1); 643 WREG32_SDMA(i, regSDMA_F32_CNTL, f32_cntl); 644 } 645 } 646 647 /* 648 * sdma_v4_4_2_rb_cntl - get parameters for rb_cntl 649 */ 650 static uint32_t sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 651 { 652 /* Set ring buffer size in dwords */ 653 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 654 655 barrier(); /* work around https://llvm.org/pr42576 */ 656 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 657 #ifdef __BIG_ENDIAN 658 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 659 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, 660 RPTR_WRITEBACK_SWAP_ENABLE, 1); 661 #endif 662 return rb_cntl; 663 } 664 665 /** 666 * sdma_v4_4_2_gfx_resume - setup and start the async dma engines 667 * 668 * @adev: amdgpu_device pointer 669 * @i: instance to resume 670 * 671 * Set up the gfx DMA ring buffers and enable them. 672 * Returns 0 for success, error for failure. 673 */ 674 static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i) 675 { 676 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 677 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 678 u32 wb_offset; 679 u32 doorbell; 680 u32 doorbell_offset; 681 u64 wptr_gpu_addr; 682 683 wb_offset = (ring->rptr_offs * 4); 684 685 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); 686 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 687 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 688 689 /* set the wb address whether it's enabled or not */ 690 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_HI, 691 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 692 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_LO, 693 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 694 695 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, 696 RPTR_WRITEBACK_ENABLE, 1); 697 698 WREG32_SDMA(i, regSDMA_GFX_RB_BASE, ring->gpu_addr >> 8); 699 WREG32_SDMA(i, regSDMA_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 700 701 ring->wptr = 0; 702 703 /* before programing wptr to a less value, need set minor_ptr_update first */ 704 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 1); 705 706 /* Initialize the ring buffer's read and write pointers */ 707 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0); 708 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0); 709 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0); 710 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0); 711 712 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL); 713 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET); 714 715 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 716 ring->use_doorbell); 717 doorbell_offset = REG_SET_FIELD(doorbell_offset, 718 SDMA_GFX_DOORBELL_OFFSET, 719 OFFSET, ring->doorbell_index); 720 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell); 721 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset); 722 723 sdma_v4_4_2_ring_set_wptr(ring); 724 725 /* set minor_ptr_update to 0 after wptr programed */ 726 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 0); 727 728 /* setup the wptr shadow polling */ 729 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 730 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_LO, 731 lower_32_bits(wptr_gpu_addr)); 732 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_HI, 733 upper_32_bits(wptr_gpu_addr)); 734 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL); 735 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 736 SDMA_GFX_RB_WPTR_POLL_CNTL, 737 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 738 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 739 740 /* enable DMA RB */ 741 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 1); 742 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 743 744 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 745 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 1); 746 #ifdef __BIG_ENDIAN 747 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 748 #endif 749 /* enable DMA IBs */ 750 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 751 } 752 753 /** 754 * sdma_v4_4_2_page_resume - setup and start the async dma engines 755 * 756 * @adev: amdgpu_device pointer 757 * @i: instance to resume 758 * 759 * Set up the page DMA ring buffers and enable them. 760 * Returns 0 for success, error for failure. 761 */ 762 static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i) 763 { 764 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 765 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 766 u32 wb_offset; 767 u32 doorbell; 768 u32 doorbell_offset; 769 u64 wptr_gpu_addr; 770 771 wb_offset = (ring->rptr_offs * 4); 772 773 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); 774 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 775 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 776 777 /* Initialize the ring buffer's read and write pointers */ 778 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, 0); 779 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, 0); 780 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, 0); 781 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, 0); 782 783 /* set the wb address whether it's enabled or not */ 784 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_HI, 785 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 786 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_LO, 787 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 788 789 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, 790 RPTR_WRITEBACK_ENABLE, 1); 791 792 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE, ring->gpu_addr >> 8); 793 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 794 795 ring->wptr = 0; 796 797 /* before programing wptr to a less value, need set minor_ptr_update first */ 798 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 1); 799 800 doorbell = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL); 801 doorbell_offset = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET); 802 803 doorbell = REG_SET_FIELD(doorbell, SDMA_PAGE_DOORBELL, ENABLE, 804 ring->use_doorbell); 805 doorbell_offset = REG_SET_FIELD(doorbell_offset, 806 SDMA_PAGE_DOORBELL_OFFSET, 807 OFFSET, ring->doorbell_index); 808 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL, doorbell); 809 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET, doorbell_offset); 810 811 /* paging queue doorbell range is setup at sdma_v4_4_2_gfx_resume */ 812 sdma_v4_4_2_page_ring_set_wptr(ring); 813 814 /* set minor_ptr_update to 0 after wptr programed */ 815 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 0); 816 817 /* setup the wptr shadow polling */ 818 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 819 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_LO, 820 lower_32_bits(wptr_gpu_addr)); 821 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_HI, 822 upper_32_bits(wptr_gpu_addr)); 823 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL); 824 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 825 SDMA_PAGE_RB_WPTR_POLL_CNTL, 826 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 827 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 828 829 /* enable DMA RB */ 830 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, RB_ENABLE, 1); 831 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 832 833 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); 834 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_ENABLE, 1); 835 #ifdef __BIG_ENDIAN 836 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 837 #endif 838 /* enable DMA IBs */ 839 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); 840 } 841 842 static void sdma_v4_4_2_init_pg(struct amdgpu_device *adev) 843 { 844 845 } 846 847 /** 848 * sdma_v4_4_2_inst_rlc_resume - setup and start the async dma engines 849 * 850 * @adev: amdgpu_device pointer 851 * @inst_mask: mask of dma engine instances to be enabled 852 * 853 * Set up the compute DMA queues and enable them. 854 * Returns 0 for success, error for failure. 855 */ 856 static int sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device *adev, 857 uint32_t inst_mask) 858 { 859 sdma_v4_4_2_init_pg(adev); 860 861 return 0; 862 } 863 864 /** 865 * sdma_v4_4_2_inst_load_microcode - load the sDMA ME ucode 866 * 867 * @adev: amdgpu_device pointer 868 * @inst_mask: mask of dma engine instances to be enabled 869 * 870 * Loads the sDMA0/1 ucode. 871 * Returns 0 for success, -EINVAL if the ucode is not available. 872 */ 873 static int sdma_v4_4_2_inst_load_microcode(struct amdgpu_device *adev, 874 uint32_t inst_mask) 875 { 876 const struct sdma_firmware_header_v1_0 *hdr; 877 const __le32 *fw_data; 878 u32 fw_size; 879 int i, j; 880 881 /* halt the MEs */ 882 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 883 884 for_each_inst(i, inst_mask) { 885 if (!adev->sdma.instance[i].fw) 886 return -EINVAL; 887 888 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 889 amdgpu_ucode_print_sdma_hdr(&hdr->header); 890 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 891 892 fw_data = (const __le32 *) 893 (adev->sdma.instance[i].fw->data + 894 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 895 896 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 0); 897 898 for (j = 0; j < fw_size; j++) 899 WREG32_SDMA(i, regSDMA_UCODE_DATA, 900 le32_to_cpup(fw_data++)); 901 902 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 903 adev->sdma.instance[i].fw_version); 904 } 905 906 return 0; 907 } 908 909 /** 910 * sdma_v4_4_2_inst_start - setup and start the async dma engines 911 * 912 * @adev: amdgpu_device pointer 913 * @inst_mask: mask of dma engine instances to be enabled 914 * 915 * Set up the DMA engines and enable them. 916 * Returns 0 for success, error for failure. 917 */ 918 static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev, 919 uint32_t inst_mask) 920 { 921 struct amdgpu_ring *ring; 922 uint32_t tmp_mask; 923 int i, r = 0; 924 925 if (amdgpu_sriov_vf(adev)) { 926 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 927 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 928 } else { 929 /* bypass sdma microcode loading on Gopher */ 930 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP && 931 adev->sdma.instance[0].fw) { 932 r = sdma_v4_4_2_inst_load_microcode(adev, inst_mask); 933 if (r) 934 return r; 935 } 936 937 /* unhalt the MEs */ 938 sdma_v4_4_2_inst_enable(adev, true, inst_mask); 939 /* enable sdma ring preemption */ 940 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask); 941 } 942 943 /* start the gfx rings and rlc compute queues */ 944 tmp_mask = inst_mask; 945 for_each_inst(i, tmp_mask) { 946 uint32_t temp; 947 948 WREG32_SDMA(i, regSDMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); 949 sdma_v4_4_2_gfx_resume(adev, i); 950 if (adev->sdma.has_page_queue) 951 sdma_v4_4_2_page_resume(adev, i); 952 953 /* set utc l1 enable flag always to 1 */ 954 temp = RREG32_SDMA(i, regSDMA_CNTL); 955 temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1); 956 /* enable context empty interrupt during initialization */ 957 temp = REG_SET_FIELD(temp, SDMA_CNTL, CTXEMPTY_INT_ENABLE, 1); 958 WREG32_SDMA(i, regSDMA_CNTL, temp); 959 960 if (!amdgpu_sriov_vf(adev)) { 961 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 962 /* unhalt engine */ 963 temp = RREG32_SDMA(i, regSDMA_F32_CNTL); 964 temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0); 965 WREG32_SDMA(i, regSDMA_F32_CNTL, temp); 966 } 967 } 968 } 969 970 if (amdgpu_sriov_vf(adev)) { 971 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask); 972 sdma_v4_4_2_inst_enable(adev, true, inst_mask); 973 } else { 974 r = sdma_v4_4_2_inst_rlc_resume(adev, inst_mask); 975 if (r) 976 return r; 977 } 978 979 tmp_mask = inst_mask; 980 for_each_inst(i, tmp_mask) { 981 ring = &adev->sdma.instance[i].ring; 982 983 r = amdgpu_ring_test_helper(ring); 984 if (r) 985 return r; 986 987 if (adev->sdma.has_page_queue) { 988 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 989 990 r = amdgpu_ring_test_helper(page); 991 if (r) 992 return r; 993 } 994 } 995 996 return r; 997 } 998 999 /** 1000 * sdma_v4_4_2_ring_test_ring - simple async dma engine test 1001 * 1002 * @ring: amdgpu_ring structure holding ring information 1003 * 1004 * Test the DMA engine by writing using it to write an 1005 * value to memory. 1006 * Returns 0 for success, error for failure. 1007 */ 1008 static int sdma_v4_4_2_ring_test_ring(struct amdgpu_ring *ring) 1009 { 1010 struct amdgpu_device *adev = ring->adev; 1011 unsigned i; 1012 unsigned index; 1013 int r; 1014 u32 tmp; 1015 u64 gpu_addr; 1016 1017 r = amdgpu_device_wb_get(adev, &index); 1018 if (r) 1019 return r; 1020 1021 gpu_addr = adev->wb.gpu_addr + (index * 4); 1022 tmp = 0xCAFEDEAD; 1023 adev->wb.wb[index] = cpu_to_le32(tmp); 1024 1025 r = amdgpu_ring_alloc(ring, 5); 1026 if (r) 1027 goto error_free_wb; 1028 1029 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1030 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1031 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1032 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1033 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1034 amdgpu_ring_write(ring, 0xDEADBEEF); 1035 amdgpu_ring_commit(ring); 1036 1037 for (i = 0; i < adev->usec_timeout; i++) { 1038 tmp = le32_to_cpu(adev->wb.wb[index]); 1039 if (tmp == 0xDEADBEEF) 1040 break; 1041 udelay(1); 1042 } 1043 1044 if (i >= adev->usec_timeout) 1045 r = -ETIMEDOUT; 1046 1047 error_free_wb: 1048 amdgpu_device_wb_free(adev, index); 1049 return r; 1050 } 1051 1052 /** 1053 * sdma_v4_4_2_ring_test_ib - test an IB on the DMA engine 1054 * 1055 * @ring: amdgpu_ring structure holding ring information 1056 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1057 * 1058 * Test a simple IB in the DMA ring. 1059 * Returns 0 on success, error on failure. 1060 */ 1061 static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1062 { 1063 struct amdgpu_device *adev = ring->adev; 1064 struct amdgpu_ib ib; 1065 struct dma_fence *f = NULL; 1066 unsigned index; 1067 long r; 1068 u32 tmp = 0; 1069 u64 gpu_addr; 1070 1071 r = amdgpu_device_wb_get(adev, &index); 1072 if (r) 1073 return r; 1074 1075 gpu_addr = adev->wb.gpu_addr + (index * 4); 1076 tmp = 0xCAFEDEAD; 1077 adev->wb.wb[index] = cpu_to_le32(tmp); 1078 memset(&ib, 0, sizeof(ib)); 1079 r = amdgpu_ib_get(adev, NULL, 256, 1080 AMDGPU_IB_POOL_DIRECT, &ib); 1081 if (r) 1082 goto err0; 1083 1084 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1085 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1086 ib.ptr[1] = lower_32_bits(gpu_addr); 1087 ib.ptr[2] = upper_32_bits(gpu_addr); 1088 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1089 ib.ptr[4] = 0xDEADBEEF; 1090 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1091 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1092 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1093 ib.length_dw = 8; 1094 1095 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1096 if (r) 1097 goto err1; 1098 1099 r = dma_fence_wait_timeout(f, false, timeout); 1100 if (r == 0) { 1101 r = -ETIMEDOUT; 1102 goto err1; 1103 } else if (r < 0) { 1104 goto err1; 1105 } 1106 tmp = le32_to_cpu(adev->wb.wb[index]); 1107 if (tmp == 0xDEADBEEF) 1108 r = 0; 1109 else 1110 r = -EINVAL; 1111 1112 err1: 1113 amdgpu_ib_free(adev, &ib, NULL); 1114 dma_fence_put(f); 1115 err0: 1116 amdgpu_device_wb_free(adev, index); 1117 return r; 1118 } 1119 1120 1121 /** 1122 * sdma_v4_4_2_vm_copy_pte - update PTEs by copying them from the GART 1123 * 1124 * @ib: indirect buffer to fill with commands 1125 * @pe: addr of the page entry 1126 * @src: src addr to copy from 1127 * @count: number of page entries to update 1128 * 1129 * Update PTEs by copying them from the GART using sDMA. 1130 */ 1131 static void sdma_v4_4_2_vm_copy_pte(struct amdgpu_ib *ib, 1132 uint64_t pe, uint64_t src, 1133 unsigned count) 1134 { 1135 unsigned bytes = count * 8; 1136 1137 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1138 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1139 ib->ptr[ib->length_dw++] = bytes - 1; 1140 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1141 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1142 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1143 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1144 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1145 1146 } 1147 1148 /** 1149 * sdma_v4_4_2_vm_write_pte - update PTEs by writing them manually 1150 * 1151 * @ib: indirect buffer to fill with commands 1152 * @pe: addr of the page entry 1153 * @value: dst addr to write into pe 1154 * @count: number of page entries to update 1155 * @incr: increase next addr by incr bytes 1156 * 1157 * Update PTEs by writing them manually using sDMA. 1158 */ 1159 static void sdma_v4_4_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1160 uint64_t value, unsigned count, 1161 uint32_t incr) 1162 { 1163 unsigned ndw = count * 2; 1164 1165 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1166 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1167 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1168 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1169 ib->ptr[ib->length_dw++] = ndw - 1; 1170 for (; ndw > 0; ndw -= 2) { 1171 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1172 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1173 value += incr; 1174 } 1175 } 1176 1177 /** 1178 * sdma_v4_4_2_vm_set_pte_pde - update the page tables using sDMA 1179 * 1180 * @ib: indirect buffer to fill with commands 1181 * @pe: addr of the page entry 1182 * @addr: dst addr to write into pe 1183 * @count: number of page entries to update 1184 * @incr: increase next addr by incr bytes 1185 * @flags: access flags 1186 * 1187 * Update the page tables using sDMA. 1188 */ 1189 static void sdma_v4_4_2_vm_set_pte_pde(struct amdgpu_ib *ib, 1190 uint64_t pe, 1191 uint64_t addr, unsigned count, 1192 uint32_t incr, uint64_t flags) 1193 { 1194 /* for physically contiguous pages (vram) */ 1195 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1196 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1197 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1198 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1199 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1200 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1201 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1202 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1203 ib->ptr[ib->length_dw++] = 0; 1204 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1205 } 1206 1207 /** 1208 * sdma_v4_4_2_ring_pad_ib - pad the IB to the required number of dw 1209 * 1210 * @ring: amdgpu_ring structure holding ring information 1211 * @ib: indirect buffer to fill with padding 1212 */ 1213 static void sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1214 { 1215 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1216 u32 pad_count; 1217 int i; 1218 1219 pad_count = (-ib->length_dw) & 7; 1220 for (i = 0; i < pad_count; i++) 1221 if (sdma && sdma->burst_nop && (i == 0)) 1222 ib->ptr[ib->length_dw++] = 1223 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1224 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1225 else 1226 ib->ptr[ib->length_dw++] = 1227 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1228 } 1229 1230 1231 /** 1232 * sdma_v4_4_2_ring_emit_pipeline_sync - sync the pipeline 1233 * 1234 * @ring: amdgpu_ring pointer 1235 * 1236 * Make sure all previous operations are completed (CIK). 1237 */ 1238 static void sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1239 { 1240 uint32_t seq = ring->fence_drv.sync_seq; 1241 uint64_t addr = ring->fence_drv.gpu_addr; 1242 1243 /* wait for idle */ 1244 sdma_v4_4_2_wait_reg_mem(ring, 1, 0, 1245 addr & 0xfffffffc, 1246 upper_32_bits(addr) & 0xffffffff, 1247 seq, 0xffffffff, 4); 1248 } 1249 1250 1251 /** 1252 * sdma_v4_4_2_ring_emit_vm_flush - vm flush using sDMA 1253 * 1254 * @ring: amdgpu_ring pointer 1255 * @vmid: vmid number to use 1256 * @pd_addr: address 1257 * 1258 * Update the page table base and flush the VM TLB 1259 * using sDMA. 1260 */ 1261 static void sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring *ring, 1262 unsigned vmid, uint64_t pd_addr) 1263 { 1264 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1265 } 1266 1267 static void sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring *ring, 1268 uint32_t reg, uint32_t val) 1269 { 1270 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1271 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1272 amdgpu_ring_write(ring, reg); 1273 amdgpu_ring_write(ring, val); 1274 } 1275 1276 static void sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1277 uint32_t val, uint32_t mask) 1278 { 1279 sdma_v4_4_2_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1280 } 1281 1282 static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev) 1283 { 1284 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1285 case IP_VERSION(4, 4, 2): 1286 case IP_VERSION(4, 4, 5): 1287 return false; 1288 default: 1289 return false; 1290 } 1291 } 1292 1293 static int sdma_v4_4_2_early_init(struct amdgpu_ip_block *ip_block) 1294 { 1295 struct amdgpu_device *adev = ip_block->adev; 1296 int r; 1297 1298 r = sdma_v4_4_2_init_microcode(adev); 1299 if (r) 1300 return r; 1301 1302 /* TODO: Page queue breaks driver reload under SRIOV */ 1303 if (sdma_v4_4_2_fw_support_paging_queue(adev)) 1304 adev->sdma.has_page_queue = true; 1305 1306 sdma_v4_4_2_set_ring_funcs(adev); 1307 sdma_v4_4_2_set_buffer_funcs(adev); 1308 sdma_v4_4_2_set_vm_pte_funcs(adev); 1309 sdma_v4_4_2_set_irq_funcs(adev); 1310 sdma_v4_4_2_set_ras_funcs(adev); 1311 1312 return 0; 1313 } 1314 1315 #if 0 1316 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, 1317 void *err_data, 1318 struct amdgpu_iv_entry *entry); 1319 #endif 1320 1321 static int sdma_v4_4_2_late_init(struct amdgpu_ip_block *ip_block) 1322 { 1323 struct amdgpu_device *adev = ip_block->adev; 1324 #if 0 1325 struct ras_ih_if ih_info = { 1326 .cb = sdma_v4_4_2_process_ras_data_cb, 1327 }; 1328 #endif 1329 if (!amdgpu_persistent_edc_harvesting_supported(adev)) 1330 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__SDMA); 1331 1332 return 0; 1333 } 1334 1335 static int sdma_v4_4_2_sw_init(struct amdgpu_ip_block *ip_block) 1336 { 1337 struct amdgpu_ring *ring; 1338 int r, i; 1339 struct amdgpu_device *adev = ip_block->adev; 1340 u32 aid_id; 1341 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); 1342 uint32_t *ptr; 1343 1344 /* SDMA trap event */ 1345 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1346 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1347 SDMA0_4_0__SRCID__SDMA_TRAP, 1348 &adev->sdma.trap_irq); 1349 if (r) 1350 return r; 1351 } 1352 1353 /* SDMA SRAM ECC event */ 1354 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1355 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1356 SDMA0_4_0__SRCID__SDMA_SRAM_ECC, 1357 &adev->sdma.ecc_irq); 1358 if (r) 1359 return r; 1360 } 1361 1362 /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/ 1363 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1364 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1365 SDMA0_4_0__SRCID__SDMA_VM_HOLE, 1366 &adev->sdma.vm_hole_irq); 1367 if (r) 1368 return r; 1369 1370 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1371 SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID, 1372 &adev->sdma.doorbell_invalid_irq); 1373 if (r) 1374 return r; 1375 1376 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1377 SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT, 1378 &adev->sdma.pool_timeout_irq); 1379 if (r) 1380 return r; 1381 1382 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1383 SDMA0_4_0__SRCID__SDMA_SRBMWRITE, 1384 &adev->sdma.srbm_write_irq); 1385 if (r) 1386 return r; 1387 } 1388 1389 for (i = 0; i < adev->sdma.num_instances; i++) { 1390 ring = &adev->sdma.instance[i].ring; 1391 ring->ring_obj = NULL; 1392 ring->use_doorbell = true; 1393 aid_id = adev->sdma.instance[i].aid_id; 1394 1395 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1396 ring->use_doorbell?"true":"false"); 1397 1398 /* doorbell size is 2 dwords, get DWORD offset */ 1399 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1400 ring->vm_hub = AMDGPU_MMHUB0(aid_id); 1401 1402 sprintf(ring->name, "sdma%d.%d", aid_id, 1403 i % adev->sdma.num_inst_per_aid); 1404 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1405 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1406 AMDGPU_RING_PRIO_DEFAULT, NULL); 1407 if (r) 1408 return r; 1409 1410 if (adev->sdma.has_page_queue) { 1411 ring = &adev->sdma.instance[i].page; 1412 ring->ring_obj = NULL; 1413 ring->use_doorbell = true; 1414 1415 /* doorbell index of page queue is assigned right after 1416 * gfx queue on the same instance 1417 */ 1418 ring->doorbell_index = 1419 (adev->doorbell_index.sdma_engine[i] + 1) << 1; 1420 ring->vm_hub = AMDGPU_MMHUB0(aid_id); 1421 1422 sprintf(ring->name, "page%d.%d", aid_id, 1423 i % adev->sdma.num_inst_per_aid); 1424 r = amdgpu_ring_init(adev, ring, 1024, 1425 &adev->sdma.trap_irq, 1426 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1427 AMDGPU_RING_PRIO_DEFAULT, NULL); 1428 if (r) 1429 return r; 1430 } 1431 } 1432 1433 /* TODO: Add queue reset mask when FW fully supports it */ 1434 adev->sdma.supported_reset = 1435 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); 1436 1437 if (amdgpu_sdma_ras_sw_init(adev)) { 1438 dev_err(adev->dev, "fail to initialize sdma ras block\n"); 1439 return -EINVAL; 1440 } 1441 1442 /* Allocate memory for SDMA IP Dump buffer */ 1443 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); 1444 if (ptr) 1445 adev->sdma.ip_dump = ptr; 1446 else 1447 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n"); 1448 1449 r = amdgpu_sdma_sysfs_reset_mask_init(adev); 1450 if (r) 1451 return r; 1452 1453 return r; 1454 } 1455 1456 static int sdma_v4_4_2_sw_fini(struct amdgpu_ip_block *ip_block) 1457 { 1458 struct amdgpu_device *adev = ip_block->adev; 1459 int i; 1460 1461 for (i = 0; i < adev->sdma.num_instances; i++) { 1462 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1463 if (adev->sdma.has_page_queue) 1464 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1465 } 1466 1467 amdgpu_sdma_sysfs_reset_mask_fini(adev); 1468 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) || 1469 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) 1470 amdgpu_sdma_destroy_inst_ctx(adev, true); 1471 else 1472 amdgpu_sdma_destroy_inst_ctx(adev, false); 1473 1474 kfree(adev->sdma.ip_dump); 1475 1476 return 0; 1477 } 1478 1479 static int sdma_v4_4_2_hw_init(struct amdgpu_ip_block *ip_block) 1480 { 1481 int r; 1482 struct amdgpu_device *adev = ip_block->adev; 1483 uint32_t inst_mask; 1484 1485 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1486 if (!amdgpu_sriov_vf(adev)) 1487 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask); 1488 1489 r = sdma_v4_4_2_inst_start(adev, inst_mask); 1490 1491 return r; 1492 } 1493 1494 static int sdma_v4_4_2_hw_fini(struct amdgpu_ip_block *ip_block) 1495 { 1496 struct amdgpu_device *adev = ip_block->adev; 1497 uint32_t inst_mask; 1498 int i; 1499 1500 if (amdgpu_sriov_vf(adev)) 1501 return 0; 1502 1503 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1504 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 1505 for (i = 0; i < adev->sdma.num_instances; i++) { 1506 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 1507 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1508 } 1509 } 1510 1511 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 1512 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 1513 1514 return 0; 1515 } 1516 1517 static int sdma_v4_4_2_set_clockgating_state(void *handle, 1518 enum amd_clockgating_state state); 1519 1520 static int sdma_v4_4_2_suspend(struct amdgpu_ip_block *ip_block) 1521 { 1522 struct amdgpu_device *adev = ip_block->adev; 1523 1524 if (amdgpu_in_reset(adev)) 1525 sdma_v4_4_2_set_clockgating_state(adev, AMD_CG_STATE_UNGATE); 1526 1527 return sdma_v4_4_2_hw_fini(ip_block); 1528 } 1529 1530 static int sdma_v4_4_2_resume(struct amdgpu_ip_block *ip_block) 1531 { 1532 return sdma_v4_4_2_hw_init(ip_block); 1533 } 1534 1535 static bool sdma_v4_4_2_is_idle(void *handle) 1536 { 1537 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1538 u32 i; 1539 1540 for (i = 0; i < adev->sdma.num_instances; i++) { 1541 u32 tmp = RREG32_SDMA(i, regSDMA_STATUS_REG); 1542 1543 if (!(tmp & SDMA_STATUS_REG__IDLE_MASK)) 1544 return false; 1545 } 1546 1547 return true; 1548 } 1549 1550 static int sdma_v4_4_2_wait_for_idle(struct amdgpu_ip_block *ip_block) 1551 { 1552 unsigned i, j; 1553 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; 1554 struct amdgpu_device *adev = ip_block->adev; 1555 1556 for (i = 0; i < adev->usec_timeout; i++) { 1557 for (j = 0; j < adev->sdma.num_instances; j++) { 1558 sdma[j] = RREG32_SDMA(j, regSDMA_STATUS_REG); 1559 if (!(sdma[j] & SDMA_STATUS_REG__IDLE_MASK)) 1560 break; 1561 } 1562 if (j == adev->sdma.num_instances) 1563 return 0; 1564 udelay(1); 1565 } 1566 return -ETIMEDOUT; 1567 } 1568 1569 static int sdma_v4_4_2_soft_reset(struct amdgpu_ip_block *ip_block) 1570 { 1571 /* todo */ 1572 1573 return 0; 1574 } 1575 1576 static int sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device *adev, 1577 struct amdgpu_irq_src *source, 1578 unsigned type, 1579 enum amdgpu_interrupt_state state) 1580 { 1581 u32 sdma_cntl; 1582 1583 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); 1584 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE, 1585 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1586 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); 1587 1588 return 0; 1589 } 1590 1591 static int sdma_v4_4_2_process_trap_irq(struct amdgpu_device *adev, 1592 struct amdgpu_irq_src *source, 1593 struct amdgpu_iv_entry *entry) 1594 { 1595 uint32_t instance, i; 1596 1597 DRM_DEBUG("IH: SDMA trap\n"); 1598 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1599 1600 /* Client id gives the SDMA instance in AID. To know the exact SDMA 1601 * instance, interrupt entry gives the node id which corresponds to the AID instance. 1602 * Match node id with the AID id associated with the SDMA instance. */ 1603 for (i = instance; i < adev->sdma.num_instances; 1604 i += adev->sdma.num_inst_per_aid) { 1605 if (adev->sdma.instance[i].aid_id == 1606 node_id_to_phys_map[entry->node_id]) 1607 break; 1608 } 1609 1610 if (i >= adev->sdma.num_instances) { 1611 dev_WARN_ONCE( 1612 adev->dev, 1, 1613 "Couldn't find the right sdma instance in trap handler"); 1614 return 0; 1615 } 1616 1617 switch (entry->ring_id) { 1618 case 0: 1619 amdgpu_fence_process(&adev->sdma.instance[i].ring); 1620 break; 1621 default: 1622 break; 1623 } 1624 return 0; 1625 } 1626 1627 #if 0 1628 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, 1629 void *err_data, 1630 struct amdgpu_iv_entry *entry) 1631 { 1632 int instance; 1633 1634 /* When “Full RAS” is enabled, the per-IP interrupt sources should 1635 * be disabled and the driver should only look for the aggregated 1636 * interrupt via sync flood 1637 */ 1638 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) 1639 goto out; 1640 1641 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1642 if (instance < 0) 1643 goto out; 1644 1645 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry); 1646 1647 out: 1648 return AMDGPU_RAS_SUCCESS; 1649 } 1650 #endif 1651 1652 static int sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device *adev, 1653 struct amdgpu_irq_src *source, 1654 struct amdgpu_iv_entry *entry) 1655 { 1656 int instance; 1657 1658 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1659 1660 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1661 if (instance < 0) 1662 return 0; 1663 1664 switch (entry->ring_id) { 1665 case 0: 1666 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 1667 break; 1668 } 1669 return 0; 1670 } 1671 1672 static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev, 1673 struct amdgpu_irq_src *source, 1674 unsigned type, 1675 enum amdgpu_interrupt_state state) 1676 { 1677 u32 sdma_cntl; 1678 1679 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); 1680 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, DRAM_ECC_INT_ENABLE, 1681 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1682 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); 1683 1684 return 0; 1685 } 1686 1687 static int sdma_v4_4_2_print_iv_entry(struct amdgpu_device *adev, 1688 struct amdgpu_iv_entry *entry) 1689 { 1690 int instance; 1691 struct amdgpu_task_info *task_info; 1692 u64 addr; 1693 1694 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1695 if (instance < 0 || instance >= adev->sdma.num_instances) { 1696 dev_err(adev->dev, "sdma instance invalid %d\n", instance); 1697 return -EINVAL; 1698 } 1699 1700 addr = (u64)entry->src_data[0] << 12; 1701 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 1702 1703 dev_dbg_ratelimited(adev->dev, 1704 "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u pasid:%u\n", 1705 instance, addr, entry->src_id, entry->ring_id, entry->vmid, 1706 entry->pasid); 1707 1708 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 1709 if (task_info) { 1710 dev_dbg_ratelimited(adev->dev, " for process %s pid %d thread %s pid %d\n", 1711 task_info->process_name, task_info->tgid, 1712 task_info->task_name, task_info->pid); 1713 amdgpu_vm_put_task_info(task_info); 1714 } 1715 1716 return 0; 1717 } 1718 1719 static int sdma_v4_4_2_process_vm_hole_irq(struct amdgpu_device *adev, 1720 struct amdgpu_irq_src *source, 1721 struct amdgpu_iv_entry *entry) 1722 { 1723 dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n"); 1724 sdma_v4_4_2_print_iv_entry(adev, entry); 1725 return 0; 1726 } 1727 1728 static int sdma_v4_4_2_process_doorbell_invalid_irq(struct amdgpu_device *adev, 1729 struct amdgpu_irq_src *source, 1730 struct amdgpu_iv_entry *entry) 1731 { 1732 1733 dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n"); 1734 sdma_v4_4_2_print_iv_entry(adev, entry); 1735 return 0; 1736 } 1737 1738 static int sdma_v4_4_2_process_pool_timeout_irq(struct amdgpu_device *adev, 1739 struct amdgpu_irq_src *source, 1740 struct amdgpu_iv_entry *entry) 1741 { 1742 dev_dbg_ratelimited(adev->dev, 1743 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n"); 1744 sdma_v4_4_2_print_iv_entry(adev, entry); 1745 return 0; 1746 } 1747 1748 static int sdma_v4_4_2_process_srbm_write_irq(struct amdgpu_device *adev, 1749 struct amdgpu_irq_src *source, 1750 struct amdgpu_iv_entry *entry) 1751 { 1752 dev_dbg_ratelimited(adev->dev, 1753 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n"); 1754 sdma_v4_4_2_print_iv_entry(adev, entry); 1755 return 0; 1756 } 1757 1758 static void sdma_v4_4_2_inst_update_medium_grain_light_sleep( 1759 struct amdgpu_device *adev, bool enable, uint32_t inst_mask) 1760 { 1761 uint32_t data, def; 1762 int i; 1763 1764 /* leave as default if it is not driver controlled */ 1765 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) 1766 return; 1767 1768 if (enable) { 1769 for_each_inst(i, inst_mask) { 1770 /* 1-not override: enable sdma mem light sleep */ 1771 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL); 1772 data |= SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1773 if (def != data) 1774 WREG32_SDMA(i, regSDMA_POWER_CNTL, data); 1775 } 1776 } else { 1777 for_each_inst(i, inst_mask) { 1778 /* 0-override:disable sdma mem light sleep */ 1779 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL); 1780 data &= ~SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1781 if (def != data) 1782 WREG32_SDMA(i, regSDMA_POWER_CNTL, data); 1783 } 1784 } 1785 } 1786 1787 static void sdma_v4_4_2_inst_update_medium_grain_clock_gating( 1788 struct amdgpu_device *adev, bool enable, uint32_t inst_mask) 1789 { 1790 uint32_t data, def; 1791 int i; 1792 1793 /* leave as default if it is not driver controlled */ 1794 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) 1795 return; 1796 1797 if (enable) { 1798 for_each_inst(i, inst_mask) { 1799 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL); 1800 data &= ~(SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1801 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1802 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1803 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1804 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1805 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1806 if (def != data) 1807 WREG32_SDMA(i, regSDMA_CLK_CTRL, data); 1808 } 1809 } else { 1810 for_each_inst(i, inst_mask) { 1811 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL); 1812 data |= (SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1813 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1814 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1815 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1816 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1817 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1818 if (def != data) 1819 WREG32_SDMA(i, regSDMA_CLK_CTRL, data); 1820 } 1821 } 1822 } 1823 1824 static int sdma_v4_4_2_set_clockgating_state(void *handle, 1825 enum amd_clockgating_state state) 1826 { 1827 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1828 uint32_t inst_mask; 1829 1830 if (amdgpu_sriov_vf(adev)) 1831 return 0; 1832 1833 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1834 1835 sdma_v4_4_2_inst_update_medium_grain_clock_gating( 1836 adev, state == AMD_CG_STATE_GATE, inst_mask); 1837 sdma_v4_4_2_inst_update_medium_grain_light_sleep( 1838 adev, state == AMD_CG_STATE_GATE, inst_mask); 1839 return 0; 1840 } 1841 1842 static int sdma_v4_4_2_set_powergating_state(void *handle, 1843 enum amd_powergating_state state) 1844 { 1845 return 0; 1846 } 1847 1848 static void sdma_v4_4_2_get_clockgating_state(void *handle, u64 *flags) 1849 { 1850 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1851 int data; 1852 1853 if (amdgpu_sriov_vf(adev)) 1854 *flags = 0; 1855 1856 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1857 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL)); 1858 if (!(data & SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK)) 1859 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1860 1861 /* AMD_CG_SUPPORT_SDMA_LS */ 1862 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL)); 1863 if (data & SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1864 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1865 } 1866 1867 static void sdma_v4_4_2_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 1868 { 1869 struct amdgpu_device *adev = ip_block->adev; 1870 int i, j; 1871 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); 1872 uint32_t instance_offset; 1873 1874 if (!adev->sdma.ip_dump) 1875 return; 1876 1877 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances); 1878 for (i = 0; i < adev->sdma.num_instances; i++) { 1879 instance_offset = i * reg_count; 1880 drm_printf(p, "\nInstance:%d\n", i); 1881 1882 for (j = 0; j < reg_count; j++) 1883 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_4_4_2[j].reg_name, 1884 adev->sdma.ip_dump[instance_offset + j]); 1885 } 1886 } 1887 1888 static void sdma_v4_4_2_dump_ip_state(struct amdgpu_ip_block *ip_block) 1889 { 1890 struct amdgpu_device *adev = ip_block->adev; 1891 int i, j; 1892 uint32_t instance_offset; 1893 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); 1894 1895 if (!adev->sdma.ip_dump) 1896 return; 1897 1898 amdgpu_gfx_off_ctrl(adev, false); 1899 for (i = 0; i < adev->sdma.num_instances; i++) { 1900 instance_offset = i * reg_count; 1901 for (j = 0; j < reg_count; j++) 1902 adev->sdma.ip_dump[instance_offset + j] = 1903 RREG32(sdma_v4_4_2_get_reg_offset(adev, i, 1904 sdma_reg_list_4_4_2[j].reg_offset)); 1905 } 1906 amdgpu_gfx_off_ctrl(adev, true); 1907 } 1908 1909 const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = { 1910 .name = "sdma_v4_4_2", 1911 .early_init = sdma_v4_4_2_early_init, 1912 .late_init = sdma_v4_4_2_late_init, 1913 .sw_init = sdma_v4_4_2_sw_init, 1914 .sw_fini = sdma_v4_4_2_sw_fini, 1915 .hw_init = sdma_v4_4_2_hw_init, 1916 .hw_fini = sdma_v4_4_2_hw_fini, 1917 .suspend = sdma_v4_4_2_suspend, 1918 .resume = sdma_v4_4_2_resume, 1919 .is_idle = sdma_v4_4_2_is_idle, 1920 .wait_for_idle = sdma_v4_4_2_wait_for_idle, 1921 .soft_reset = sdma_v4_4_2_soft_reset, 1922 .set_clockgating_state = sdma_v4_4_2_set_clockgating_state, 1923 .set_powergating_state = sdma_v4_4_2_set_powergating_state, 1924 .get_clockgating_state = sdma_v4_4_2_get_clockgating_state, 1925 .dump_ip_state = sdma_v4_4_2_dump_ip_state, 1926 .print_ip_state = sdma_v4_4_2_print_ip_state, 1927 }; 1928 1929 static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = { 1930 .type = AMDGPU_RING_TYPE_SDMA, 1931 .align_mask = 0xff, 1932 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1933 .support_64bit_ptrs = true, 1934 .get_rptr = sdma_v4_4_2_ring_get_rptr, 1935 .get_wptr = sdma_v4_4_2_ring_get_wptr, 1936 .set_wptr = sdma_v4_4_2_ring_set_wptr, 1937 .emit_frame_size = 1938 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */ 1939 3 + /* hdp invalidate */ 1940 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */ 1941 /* sdma_v4_4_2_ring_emit_vm_flush */ 1942 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1943 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1944 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */ 1945 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */ 1946 .emit_ib = sdma_v4_4_2_ring_emit_ib, 1947 .emit_fence = sdma_v4_4_2_ring_emit_fence, 1948 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync, 1949 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush, 1950 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush, 1951 .test_ring = sdma_v4_4_2_ring_test_ring, 1952 .test_ib = sdma_v4_4_2_ring_test_ib, 1953 .insert_nop = sdma_v4_4_2_ring_insert_nop, 1954 .pad_ib = sdma_v4_4_2_ring_pad_ib, 1955 .emit_wreg = sdma_v4_4_2_ring_emit_wreg, 1956 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, 1957 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1958 }; 1959 1960 static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = { 1961 .type = AMDGPU_RING_TYPE_SDMA, 1962 .align_mask = 0xff, 1963 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1964 .support_64bit_ptrs = true, 1965 .get_rptr = sdma_v4_4_2_ring_get_rptr, 1966 .get_wptr = sdma_v4_4_2_page_ring_get_wptr, 1967 .set_wptr = sdma_v4_4_2_page_ring_set_wptr, 1968 .emit_frame_size = 1969 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */ 1970 3 + /* hdp invalidate */ 1971 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */ 1972 /* sdma_v4_4_2_ring_emit_vm_flush */ 1973 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1974 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1975 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */ 1976 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */ 1977 .emit_ib = sdma_v4_4_2_ring_emit_ib, 1978 .emit_fence = sdma_v4_4_2_ring_emit_fence, 1979 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync, 1980 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush, 1981 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush, 1982 .test_ring = sdma_v4_4_2_ring_test_ring, 1983 .test_ib = sdma_v4_4_2_ring_test_ib, 1984 .insert_nop = sdma_v4_4_2_ring_insert_nop, 1985 .pad_ib = sdma_v4_4_2_ring_pad_ib, 1986 .emit_wreg = sdma_v4_4_2_ring_emit_wreg, 1987 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, 1988 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1989 }; 1990 1991 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev) 1992 { 1993 int i, dev_inst; 1994 1995 for (i = 0; i < adev->sdma.num_instances; i++) { 1996 adev->sdma.instance[i].ring.funcs = &sdma_v4_4_2_ring_funcs; 1997 adev->sdma.instance[i].ring.me = i; 1998 if (adev->sdma.has_page_queue) { 1999 adev->sdma.instance[i].page.funcs = 2000 &sdma_v4_4_2_page_ring_funcs; 2001 adev->sdma.instance[i].page.me = i; 2002 } 2003 2004 dev_inst = GET_INST(SDMA0, i); 2005 /* AID to which SDMA belongs depends on physical instance */ 2006 adev->sdma.instance[i].aid_id = 2007 dev_inst / adev->sdma.num_inst_per_aid; 2008 } 2009 } 2010 2011 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_trap_irq_funcs = { 2012 .set = sdma_v4_4_2_set_trap_irq_state, 2013 .process = sdma_v4_4_2_process_trap_irq, 2014 }; 2015 2016 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_illegal_inst_irq_funcs = { 2017 .process = sdma_v4_4_2_process_illegal_inst_irq, 2018 }; 2019 2020 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ecc_irq_funcs = { 2021 .set = sdma_v4_4_2_set_ecc_irq_state, 2022 .process = amdgpu_sdma_process_ecc_irq, 2023 }; 2024 2025 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_vm_hole_irq_funcs = { 2026 .process = sdma_v4_4_2_process_vm_hole_irq, 2027 }; 2028 2029 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_doorbell_invalid_irq_funcs = { 2030 .process = sdma_v4_4_2_process_doorbell_invalid_irq, 2031 }; 2032 2033 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_pool_timeout_irq_funcs = { 2034 .process = sdma_v4_4_2_process_pool_timeout_irq, 2035 }; 2036 2037 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_srbm_write_irq_funcs = { 2038 .process = sdma_v4_4_2_process_srbm_write_irq, 2039 }; 2040 2041 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev) 2042 { 2043 adev->sdma.trap_irq.num_types = adev->sdma.num_instances; 2044 adev->sdma.ecc_irq.num_types = adev->sdma.num_instances; 2045 adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances; 2046 adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances; 2047 adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances; 2048 adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances; 2049 2050 adev->sdma.trap_irq.funcs = &sdma_v4_4_2_trap_irq_funcs; 2051 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_4_2_illegal_inst_irq_funcs; 2052 adev->sdma.ecc_irq.funcs = &sdma_v4_4_2_ecc_irq_funcs; 2053 adev->sdma.vm_hole_irq.funcs = &sdma_v4_4_2_vm_hole_irq_funcs; 2054 adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_4_2_doorbell_invalid_irq_funcs; 2055 adev->sdma.pool_timeout_irq.funcs = &sdma_v4_4_2_pool_timeout_irq_funcs; 2056 adev->sdma.srbm_write_irq.funcs = &sdma_v4_4_2_srbm_write_irq_funcs; 2057 } 2058 2059 /** 2060 * sdma_v4_4_2_emit_copy_buffer - copy buffer using the sDMA engine 2061 * 2062 * @ib: indirect buffer to copy to 2063 * @src_offset: src GPU address 2064 * @dst_offset: dst GPU address 2065 * @byte_count: number of bytes to xfer 2066 * @copy_flags: copy flags for the buffers 2067 * 2068 * Copy GPU buffers using the DMA engine. 2069 * Used by the amdgpu ttm implementation to move pages if 2070 * registered as the asic copy callback. 2071 */ 2072 static void sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib *ib, 2073 uint64_t src_offset, 2074 uint64_t dst_offset, 2075 uint32_t byte_count, 2076 uint32_t copy_flags) 2077 { 2078 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 2079 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 2080 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0); 2081 ib->ptr[ib->length_dw++] = byte_count - 1; 2082 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 2083 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 2084 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 2085 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2086 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2087 } 2088 2089 /** 2090 * sdma_v4_4_2_emit_fill_buffer - fill buffer using the sDMA engine 2091 * 2092 * @ib: indirect buffer to copy to 2093 * @src_data: value to write to buffer 2094 * @dst_offset: dst GPU address 2095 * @byte_count: number of bytes to xfer 2096 * 2097 * Fill GPU buffers using the DMA engine. 2098 */ 2099 static void sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib *ib, 2100 uint32_t src_data, 2101 uint64_t dst_offset, 2102 uint32_t byte_count) 2103 { 2104 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2105 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2106 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2107 ib->ptr[ib->length_dw++] = src_data; 2108 ib->ptr[ib->length_dw++] = byte_count - 1; 2109 } 2110 2111 static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = { 2112 .copy_max_bytes = 0x400000, 2113 .copy_num_dw = 7, 2114 .emit_copy_buffer = sdma_v4_4_2_emit_copy_buffer, 2115 2116 .fill_max_bytes = 0x400000, 2117 .fill_num_dw = 5, 2118 .emit_fill_buffer = sdma_v4_4_2_emit_fill_buffer, 2119 }; 2120 2121 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev) 2122 { 2123 adev->mman.buffer_funcs = &sdma_v4_4_2_buffer_funcs; 2124 if (adev->sdma.has_page_queue) 2125 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; 2126 else 2127 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2128 } 2129 2130 static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = { 2131 .copy_pte_num_dw = 7, 2132 .copy_pte = sdma_v4_4_2_vm_copy_pte, 2133 2134 .write_pte = sdma_v4_4_2_vm_write_pte, 2135 .set_pte_pde = sdma_v4_4_2_vm_set_pte_pde, 2136 }; 2137 2138 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev) 2139 { 2140 struct drm_gpu_scheduler *sched; 2141 unsigned i; 2142 2143 adev->vm_manager.vm_pte_funcs = &sdma_v4_4_2_vm_pte_funcs; 2144 for (i = 0; i < adev->sdma.num_instances; i++) { 2145 if (adev->sdma.has_page_queue) 2146 sched = &adev->sdma.instance[i].page.sched; 2147 else 2148 sched = &adev->sdma.instance[i].ring.sched; 2149 adev->vm_manager.vm_pte_scheds[i] = sched; 2150 } 2151 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 2152 } 2153 2154 const struct amdgpu_ip_block_version sdma_v4_4_2_ip_block = { 2155 .type = AMD_IP_BLOCK_TYPE_SDMA, 2156 .major = 4, 2157 .minor = 4, 2158 .rev = 2, 2159 .funcs = &sdma_v4_4_2_ip_funcs, 2160 }; 2161 2162 static int sdma_v4_4_2_xcp_resume(void *handle, uint32_t inst_mask) 2163 { 2164 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2165 int r; 2166 2167 if (!amdgpu_sriov_vf(adev)) 2168 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask); 2169 2170 r = sdma_v4_4_2_inst_start(adev, inst_mask); 2171 2172 return r; 2173 } 2174 2175 static int sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask) 2176 { 2177 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2178 uint32_t tmp_mask = inst_mask; 2179 int i; 2180 2181 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2182 for_each_inst(i, tmp_mask) { 2183 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 2184 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 2185 } 2186 } 2187 2188 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 2189 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 2190 2191 return 0; 2192 } 2193 2194 struct amdgpu_xcp_ip_funcs sdma_v4_4_2_xcp_funcs = { 2195 .suspend = &sdma_v4_4_2_xcp_suspend, 2196 .resume = &sdma_v4_4_2_xcp_resume 2197 }; 2198 2199 static const struct amdgpu_ras_err_status_reg_entry sdma_v4_2_2_ue_reg_list[] = { 2200 {AMDGPU_RAS_REG_ENTRY(SDMA0, 0, regSDMA_UE_ERR_STATUS_LO, regSDMA_UE_ERR_STATUS_HI), 2201 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SDMA"}, 2202 }; 2203 2204 static const struct amdgpu_ras_memory_id_entry sdma_v4_4_2_ras_memory_list[] = { 2205 {AMDGPU_SDMA_MBANK_DATA_BUF0, "SDMA_MBANK_DATA_BUF0"}, 2206 {AMDGPU_SDMA_MBANK_DATA_BUF1, "SDMA_MBANK_DATA_BUF1"}, 2207 {AMDGPU_SDMA_MBANK_DATA_BUF2, "SDMA_MBANK_DATA_BUF2"}, 2208 {AMDGPU_SDMA_MBANK_DATA_BUF3, "SDMA_MBANK_DATA_BUF3"}, 2209 {AMDGPU_SDMA_MBANK_DATA_BUF4, "SDMA_MBANK_DATA_BUF4"}, 2210 {AMDGPU_SDMA_MBANK_DATA_BUF5, "SDMA_MBANK_DATA_BUF5"}, 2211 {AMDGPU_SDMA_MBANK_DATA_BUF6, "SDMA_MBANK_DATA_BUF6"}, 2212 {AMDGPU_SDMA_MBANK_DATA_BUF7, "SDMA_MBANK_DATA_BUF7"}, 2213 {AMDGPU_SDMA_MBANK_DATA_BUF8, "SDMA_MBANK_DATA_BUF8"}, 2214 {AMDGPU_SDMA_MBANK_DATA_BUF9, "SDMA_MBANK_DATA_BUF9"}, 2215 {AMDGPU_SDMA_MBANK_DATA_BUF10, "SDMA_MBANK_DATA_BUF10"}, 2216 {AMDGPU_SDMA_MBANK_DATA_BUF11, "SDMA_MBANK_DATA_BUF11"}, 2217 {AMDGPU_SDMA_MBANK_DATA_BUF12, "SDMA_MBANK_DATA_BUF12"}, 2218 {AMDGPU_SDMA_MBANK_DATA_BUF13, "SDMA_MBANK_DATA_BUF13"}, 2219 {AMDGPU_SDMA_MBANK_DATA_BUF14, "SDMA_MBANK_DATA_BUF14"}, 2220 {AMDGPU_SDMA_MBANK_DATA_BUF15, "SDMA_MBANK_DATA_BUF15"}, 2221 {AMDGPU_SDMA_UCODE_BUF, "SDMA_UCODE_BUF"}, 2222 {AMDGPU_SDMA_RB_CMD_BUF, "SDMA_RB_CMD_BUF"}, 2223 {AMDGPU_SDMA_IB_CMD_BUF, "SDMA_IB_CMD_BUF"}, 2224 {AMDGPU_SDMA_UTCL1_RD_FIFO, "SDMA_UTCL1_RD_FIFO"}, 2225 {AMDGPU_SDMA_UTCL1_RDBST_FIFO, "SDMA_UTCL1_RDBST_FIFO"}, 2226 {AMDGPU_SDMA_UTCL1_WR_FIFO, "SDMA_UTCL1_WR_FIFO"}, 2227 {AMDGPU_SDMA_DATA_LUT_FIFO, "SDMA_DATA_LUT_FIFO"}, 2228 {AMDGPU_SDMA_SPLIT_DAT_BUF, "SDMA_SPLIT_DAT_BUF"}, 2229 }; 2230 2231 static void sdma_v4_4_2_inst_query_ras_error_count(struct amdgpu_device *adev, 2232 uint32_t sdma_inst, 2233 void *ras_err_status) 2234 { 2235 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 2236 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); 2237 unsigned long ue_count = 0; 2238 struct amdgpu_smuio_mcm_config_info mcm_info = { 2239 .socket_id = adev->smuio.funcs->get_socket_id(adev), 2240 .die_id = adev->sdma.instance[sdma_inst].aid_id, 2241 }; 2242 2243 /* sdma v4_4_2 doesn't support query ce counts */ 2244 amdgpu_ras_inst_query_ras_error_count(adev, 2245 sdma_v4_2_2_ue_reg_list, 2246 ARRAY_SIZE(sdma_v4_2_2_ue_reg_list), 2247 sdma_v4_4_2_ras_memory_list, 2248 ARRAY_SIZE(sdma_v4_4_2_ras_memory_list), 2249 sdma_dev_inst, 2250 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 2251 &ue_count); 2252 2253 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count); 2254 } 2255 2256 static void sdma_v4_4_2_query_ras_error_count(struct amdgpu_device *adev, 2257 void *ras_err_status) 2258 { 2259 uint32_t inst_mask; 2260 int i = 0; 2261 2262 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 2263 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2264 for_each_inst(i, inst_mask) 2265 sdma_v4_4_2_inst_query_ras_error_count(adev, i, ras_err_status); 2266 } else { 2267 dev_warn(adev->dev, "SDMA RAS is not supported\n"); 2268 } 2269 } 2270 2271 static void sdma_v4_4_2_inst_reset_ras_error_count(struct amdgpu_device *adev, 2272 uint32_t sdma_inst) 2273 { 2274 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); 2275 2276 amdgpu_ras_inst_reset_ras_error_count(adev, 2277 sdma_v4_2_2_ue_reg_list, 2278 ARRAY_SIZE(sdma_v4_2_2_ue_reg_list), 2279 sdma_dev_inst); 2280 } 2281 2282 static void sdma_v4_4_2_reset_ras_error_count(struct amdgpu_device *adev) 2283 { 2284 uint32_t inst_mask; 2285 int i = 0; 2286 2287 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 2288 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2289 for_each_inst(i, inst_mask) 2290 sdma_v4_4_2_inst_reset_ras_error_count(adev, i); 2291 } else { 2292 dev_warn(adev->dev, "SDMA RAS is not supported\n"); 2293 } 2294 } 2295 2296 static const struct amdgpu_ras_block_hw_ops sdma_v4_4_2_ras_hw_ops = { 2297 .query_ras_error_count = sdma_v4_4_2_query_ras_error_count, 2298 .reset_ras_error_count = sdma_v4_4_2_reset_ras_error_count, 2299 }; 2300 2301 static int sdma_v4_4_2_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, 2302 enum aca_smu_type type, void *data) 2303 { 2304 struct aca_bank_info info; 2305 u64 misc0; 2306 int ret; 2307 2308 ret = aca_bank_info_decode(bank, &info); 2309 if (ret) 2310 return ret; 2311 2312 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 2313 switch (type) { 2314 case ACA_SMU_TYPE_UE: 2315 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE, 2316 1ULL); 2317 break; 2318 case ACA_SMU_TYPE_CE: 2319 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_CE, 2320 ACA_REG__MISC0__ERRCNT(misc0)); 2321 break; 2322 default: 2323 return -EINVAL; 2324 } 2325 2326 return ret; 2327 } 2328 2329 /* CODE_SDMA0 - CODE_SDMA4, reference to smu driver if header file */ 2330 static int sdma_v4_4_2_err_codes[] = { 33, 34, 35, 36 }; 2331 2332 static bool sdma_v4_4_2_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 2333 enum aca_smu_type type, void *data) 2334 { 2335 u32 instlo; 2336 2337 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 2338 instlo &= GENMASK(31, 1); 2339 2340 if (instlo != mmSMNAID_AID0_MCA_SMU) 2341 return false; 2342 2343 if (aca_bank_check_error_codes(handle->adev, bank, 2344 sdma_v4_4_2_err_codes, 2345 ARRAY_SIZE(sdma_v4_4_2_err_codes))) 2346 return false; 2347 2348 return true; 2349 } 2350 2351 static const struct aca_bank_ops sdma_v4_4_2_aca_bank_ops = { 2352 .aca_bank_parser = sdma_v4_4_2_aca_bank_parser, 2353 .aca_bank_is_valid = sdma_v4_4_2_aca_bank_is_valid, 2354 }; 2355 2356 static const struct aca_info sdma_v4_4_2_aca_info = { 2357 .hwip = ACA_HWIP_TYPE_SMU, 2358 .mask = ACA_ERROR_UE_MASK, 2359 .bank_ops = &sdma_v4_4_2_aca_bank_ops, 2360 }; 2361 2362 static int sdma_v4_4_2_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 2363 { 2364 int r; 2365 2366 r = amdgpu_sdma_ras_late_init(adev, ras_block); 2367 if (r) 2368 return r; 2369 2370 return amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__SDMA, 2371 &sdma_v4_4_2_aca_info, NULL); 2372 } 2373 2374 static struct amdgpu_sdma_ras sdma_v4_4_2_ras = { 2375 .ras_block = { 2376 .hw_ops = &sdma_v4_4_2_ras_hw_ops, 2377 .ras_late_init = sdma_v4_4_2_ras_late_init, 2378 }, 2379 }; 2380 2381 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev) 2382 { 2383 adev->sdma.ras = &sdma_v4_4_2_ras; 2384 } 2385