1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_xcp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_trace.h" 33 34 #include "sdma/sdma_4_4_2_offset.h" 35 #include "sdma/sdma_4_4_2_sh_mask.h" 36 37 #include "soc15_common.h" 38 #include "soc15.h" 39 #include "vega10_sdma_pkt_open.h" 40 41 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 42 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 43 44 #include "amdgpu_ras.h" 45 46 MODULE_FIRMWARE("amdgpu/sdma_4_4_2.bin"); 47 MODULE_FIRMWARE("amdgpu/sdma_4_4_5.bin"); 48 49 #define mmSMNAID_AID0_MCA_SMU 0x03b30400 50 51 #define WREG32_SDMA(instance, offset, value) \ 52 WREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)), value) 53 #define RREG32_SDMA(instance, offset) \ 54 RREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset))) 55 56 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev); 57 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev); 58 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev); 59 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev); 60 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev); 61 62 static u32 sdma_v4_4_2_get_reg_offset(struct amdgpu_device *adev, 63 u32 instance, u32 offset) 64 { 65 u32 dev_inst = GET_INST(SDMA0, instance); 66 67 return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset); 68 } 69 70 static unsigned sdma_v4_4_2_seq_to_irq_id(int seq_num) 71 { 72 switch (seq_num) { 73 case 0: 74 return SOC15_IH_CLIENTID_SDMA0; 75 case 1: 76 return SOC15_IH_CLIENTID_SDMA1; 77 case 2: 78 return SOC15_IH_CLIENTID_SDMA2; 79 case 3: 80 return SOC15_IH_CLIENTID_SDMA3; 81 default: 82 return -EINVAL; 83 } 84 } 85 86 static int sdma_v4_4_2_irq_id_to_seq(unsigned client_id) 87 { 88 switch (client_id) { 89 case SOC15_IH_CLIENTID_SDMA0: 90 return 0; 91 case SOC15_IH_CLIENTID_SDMA1: 92 return 1; 93 case SOC15_IH_CLIENTID_SDMA2: 94 return 2; 95 case SOC15_IH_CLIENTID_SDMA3: 96 return 3; 97 default: 98 return -EINVAL; 99 } 100 } 101 102 static void sdma_v4_4_2_inst_init_golden_registers(struct amdgpu_device *adev, 103 uint32_t inst_mask) 104 { 105 u32 val; 106 int i; 107 108 for (i = 0; i < adev->sdma.num_instances; i++) { 109 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG); 110 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4); 111 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, 112 PIPE_INTERLEAVE_SIZE, 0); 113 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG, val); 114 115 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ); 116 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS, 117 4); 118 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, 119 PIPE_INTERLEAVE_SIZE, 0); 120 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ, val); 121 } 122 } 123 124 /** 125 * sdma_v4_4_2_init_microcode - load ucode images from disk 126 * 127 * @adev: amdgpu_device pointer 128 * 129 * Use the firmware interface to load the ucode images into 130 * the driver (not loaded into hw). 131 * Returns 0 on success, error on failure. 132 */ 133 static int sdma_v4_4_2_init_microcode(struct amdgpu_device *adev) 134 { 135 int ret, i; 136 137 for (i = 0; i < adev->sdma.num_instances; i++) { 138 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) || 139 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) { 140 ret = amdgpu_sdma_init_microcode(adev, 0, true); 141 break; 142 } else { 143 ret = amdgpu_sdma_init_microcode(adev, i, false); 144 if (ret) 145 return ret; 146 } 147 } 148 149 return ret; 150 } 151 152 /** 153 * sdma_v4_4_2_ring_get_rptr - get the current read pointer 154 * 155 * @ring: amdgpu ring pointer 156 * 157 * Get the current rptr from the hardware. 158 */ 159 static uint64_t sdma_v4_4_2_ring_get_rptr(struct amdgpu_ring *ring) 160 { 161 u64 rptr; 162 163 /* XXX check if swapping is necessary on BE */ 164 rptr = READ_ONCE(*((u64 *)&ring->adev->wb.wb[ring->rptr_offs])); 165 166 DRM_DEBUG("rptr before shift == 0x%016llx\n", rptr); 167 return rptr >> 2; 168 } 169 170 /** 171 * sdma_v4_4_2_ring_get_wptr - get the current write pointer 172 * 173 * @ring: amdgpu ring pointer 174 * 175 * Get the current wptr from the hardware. 176 */ 177 static uint64_t sdma_v4_4_2_ring_get_wptr(struct amdgpu_ring *ring) 178 { 179 struct amdgpu_device *adev = ring->adev; 180 u64 wptr; 181 182 if (ring->use_doorbell) { 183 /* XXX check if swapping is necessary on BE */ 184 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 185 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 186 } else { 187 wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI); 188 wptr = wptr << 32; 189 wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR); 190 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 191 ring->me, wptr); 192 } 193 194 return wptr >> 2; 195 } 196 197 /** 198 * sdma_v4_4_2_ring_set_wptr - commit the write pointer 199 * 200 * @ring: amdgpu ring pointer 201 * 202 * Write the wptr back to the hardware. 203 */ 204 static void sdma_v4_4_2_ring_set_wptr(struct amdgpu_ring *ring) 205 { 206 struct amdgpu_device *adev = ring->adev; 207 208 DRM_DEBUG("Setting write pointer\n"); 209 if (ring->use_doorbell) { 210 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 211 212 DRM_DEBUG("Using doorbell -- " 213 "wptr_offs == 0x%08x " 214 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 215 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 216 ring->wptr_offs, 217 lower_32_bits(ring->wptr << 2), 218 upper_32_bits(ring->wptr << 2)); 219 /* XXX check if swapping is necessary on BE */ 220 WRITE_ONCE(*wb, (ring->wptr << 2)); 221 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 222 ring->doorbell_index, ring->wptr << 2); 223 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 224 } else { 225 DRM_DEBUG("Not using doorbell -- " 226 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 227 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 228 ring->me, 229 lower_32_bits(ring->wptr << 2), 230 ring->me, 231 upper_32_bits(ring->wptr << 2)); 232 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR, 233 lower_32_bits(ring->wptr << 2)); 234 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI, 235 upper_32_bits(ring->wptr << 2)); 236 } 237 } 238 239 /** 240 * sdma_v4_4_2_page_ring_get_wptr - get the current write pointer 241 * 242 * @ring: amdgpu ring pointer 243 * 244 * Get the current wptr from the hardware. 245 */ 246 static uint64_t sdma_v4_4_2_page_ring_get_wptr(struct amdgpu_ring *ring) 247 { 248 struct amdgpu_device *adev = ring->adev; 249 u64 wptr; 250 251 if (ring->use_doorbell) { 252 /* XXX check if swapping is necessary on BE */ 253 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 254 } else { 255 wptr = RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI); 256 wptr = wptr << 32; 257 wptr |= RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR); 258 } 259 260 return wptr >> 2; 261 } 262 263 /** 264 * sdma_v4_4_2_page_ring_set_wptr - commit the write pointer 265 * 266 * @ring: amdgpu ring pointer 267 * 268 * Write the wptr back to the hardware. 269 */ 270 static void sdma_v4_4_2_page_ring_set_wptr(struct amdgpu_ring *ring) 271 { 272 struct amdgpu_device *adev = ring->adev; 273 274 if (ring->use_doorbell) { 275 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 276 277 /* XXX check if swapping is necessary on BE */ 278 WRITE_ONCE(*wb, (ring->wptr << 2)); 279 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 280 } else { 281 uint64_t wptr = ring->wptr << 2; 282 283 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR, 284 lower_32_bits(wptr)); 285 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI, 286 upper_32_bits(wptr)); 287 } 288 } 289 290 static void sdma_v4_4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 291 { 292 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 293 int i; 294 295 for (i = 0; i < count; i++) 296 if (sdma && sdma->burst_nop && (i == 0)) 297 amdgpu_ring_write(ring, ring->funcs->nop | 298 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 299 else 300 amdgpu_ring_write(ring, ring->funcs->nop); 301 } 302 303 /** 304 * sdma_v4_4_2_ring_emit_ib - Schedule an IB on the DMA engine 305 * 306 * @ring: amdgpu ring pointer 307 * @job: job to retrieve vmid from 308 * @ib: IB object to schedule 309 * @flags: unused 310 * 311 * Schedule an IB in the DMA ring. 312 */ 313 static void sdma_v4_4_2_ring_emit_ib(struct amdgpu_ring *ring, 314 struct amdgpu_job *job, 315 struct amdgpu_ib *ib, 316 uint32_t flags) 317 { 318 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 319 320 /* IB packet must end on a 8 DW boundary */ 321 sdma_v4_4_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 322 323 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 324 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 325 /* base must be 32 byte aligned */ 326 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 327 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 328 amdgpu_ring_write(ring, ib->length_dw); 329 amdgpu_ring_write(ring, 0); 330 amdgpu_ring_write(ring, 0); 331 332 } 333 334 static void sdma_v4_4_2_wait_reg_mem(struct amdgpu_ring *ring, 335 int mem_space, int hdp, 336 uint32_t addr0, uint32_t addr1, 337 uint32_t ref, uint32_t mask, 338 uint32_t inv) 339 { 340 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 341 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 342 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 343 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 344 if (mem_space) { 345 /* memory */ 346 amdgpu_ring_write(ring, addr0); 347 amdgpu_ring_write(ring, addr1); 348 } else { 349 /* registers */ 350 amdgpu_ring_write(ring, addr0 << 2); 351 amdgpu_ring_write(ring, addr1 << 2); 352 } 353 amdgpu_ring_write(ring, ref); /* reference */ 354 amdgpu_ring_write(ring, mask); /* mask */ 355 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 356 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 357 } 358 359 /** 360 * sdma_v4_4_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 361 * 362 * @ring: amdgpu ring pointer 363 * 364 * Emit an hdp flush packet on the requested DMA ring. 365 */ 366 static void sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 367 { 368 struct amdgpu_device *adev = ring->adev; 369 u32 ref_and_mask = 0; 370 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 371 372 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 373 << (ring->me % adev->sdma.num_inst_per_aid); 374 375 sdma_v4_4_2_wait_reg_mem(ring, 0, 1, 376 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 377 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 378 ref_and_mask, ref_and_mask, 10); 379 } 380 381 /** 382 * sdma_v4_4_2_ring_emit_fence - emit a fence on the DMA ring 383 * 384 * @ring: amdgpu ring pointer 385 * @addr: address 386 * @seq: sequence number 387 * @flags: fence related flags 388 * 389 * Add a DMA fence packet to the ring to write 390 * the fence seq number and DMA trap packet to generate 391 * an interrupt if needed. 392 */ 393 static void sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 394 unsigned flags) 395 { 396 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 397 /* write the fence */ 398 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 399 /* zero in first two bits */ 400 BUG_ON(addr & 0x3); 401 amdgpu_ring_write(ring, lower_32_bits(addr)); 402 amdgpu_ring_write(ring, upper_32_bits(addr)); 403 amdgpu_ring_write(ring, lower_32_bits(seq)); 404 405 /* optionally write high bits as well */ 406 if (write64bit) { 407 addr += 4; 408 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 409 /* zero in first two bits */ 410 BUG_ON(addr & 0x3); 411 amdgpu_ring_write(ring, lower_32_bits(addr)); 412 amdgpu_ring_write(ring, upper_32_bits(addr)); 413 amdgpu_ring_write(ring, upper_32_bits(seq)); 414 } 415 416 /* generate an interrupt */ 417 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 418 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 419 } 420 421 422 /** 423 * sdma_v4_4_2_inst_gfx_stop - stop the gfx async dma engines 424 * 425 * @adev: amdgpu_device pointer 426 * @inst_mask: mask of dma engine instances to be disabled 427 * 428 * Stop the gfx async dma ring buffers. 429 */ 430 static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev, 431 uint32_t inst_mask) 432 { 433 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 434 u32 doorbell_offset, doorbell; 435 u32 rb_cntl, ib_cntl; 436 int i; 437 438 for_each_inst(i, inst_mask) { 439 sdma[i] = &adev->sdma.instance[i].ring; 440 441 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); 442 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0); 443 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 444 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 445 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0); 446 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 447 448 if (sdma[i]->use_doorbell) { 449 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL); 450 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET); 451 452 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 0); 453 doorbell_offset = REG_SET_FIELD(doorbell_offset, 454 SDMA_GFX_DOORBELL_OFFSET, 455 OFFSET, 0); 456 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell); 457 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset); 458 } 459 } 460 } 461 462 /** 463 * sdma_v4_4_2_inst_rlc_stop - stop the compute async dma engines 464 * 465 * @adev: amdgpu_device pointer 466 * @inst_mask: mask of dma engine instances to be disabled 467 * 468 * Stop the compute async dma queues. 469 */ 470 static void sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device *adev, 471 uint32_t inst_mask) 472 { 473 /* XXX todo */ 474 } 475 476 /** 477 * sdma_v4_4_2_inst_page_stop - stop the page async dma engines 478 * 479 * @adev: amdgpu_device pointer 480 * @inst_mask: mask of dma engine instances to be disabled 481 * 482 * Stop the page async dma ring buffers. 483 */ 484 static void sdma_v4_4_2_inst_page_stop(struct amdgpu_device *adev, 485 uint32_t inst_mask) 486 { 487 u32 rb_cntl, ib_cntl; 488 int i; 489 490 for_each_inst(i, inst_mask) { 491 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); 492 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, 493 RB_ENABLE, 0); 494 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 495 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); 496 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, 497 IB_ENABLE, 0); 498 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); 499 } 500 } 501 502 /** 503 * sdma_v4_4_2_inst_ctx_switch_enable - stop the async dma engines context switch 504 * 505 * @adev: amdgpu_device pointer 506 * @enable: enable/disable the DMA MEs context switch. 507 * @inst_mask: mask of dma engine instances to be enabled 508 * 509 * Halt or unhalt the async dma engines context switch. 510 */ 511 static void sdma_v4_4_2_inst_ctx_switch_enable(struct amdgpu_device *adev, 512 bool enable, uint32_t inst_mask) 513 { 514 u32 f32_cntl, phase_quantum = 0; 515 int i; 516 517 if (amdgpu_sdma_phase_quantum) { 518 unsigned value = amdgpu_sdma_phase_quantum; 519 unsigned unit = 0; 520 521 while (value > (SDMA_PHASE0_QUANTUM__VALUE_MASK >> 522 SDMA_PHASE0_QUANTUM__VALUE__SHIFT)) { 523 value = (value + 1) >> 1; 524 unit++; 525 } 526 if (unit > (SDMA_PHASE0_QUANTUM__UNIT_MASK >> 527 SDMA_PHASE0_QUANTUM__UNIT__SHIFT)) { 528 value = (SDMA_PHASE0_QUANTUM__VALUE_MASK >> 529 SDMA_PHASE0_QUANTUM__VALUE__SHIFT); 530 unit = (SDMA_PHASE0_QUANTUM__UNIT_MASK >> 531 SDMA_PHASE0_QUANTUM__UNIT__SHIFT); 532 WARN_ONCE(1, 533 "clamping sdma_phase_quantum to %uK clock cycles\n", 534 value << unit); 535 } 536 phase_quantum = 537 value << SDMA_PHASE0_QUANTUM__VALUE__SHIFT | 538 unit << SDMA_PHASE0_QUANTUM__UNIT__SHIFT; 539 } 540 541 for_each_inst(i, inst_mask) { 542 f32_cntl = RREG32_SDMA(i, regSDMA_CNTL); 543 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_CNTL, 544 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 545 if (enable && amdgpu_sdma_phase_quantum) { 546 WREG32_SDMA(i, regSDMA_PHASE0_QUANTUM, phase_quantum); 547 WREG32_SDMA(i, regSDMA_PHASE1_QUANTUM, phase_quantum); 548 WREG32_SDMA(i, regSDMA_PHASE2_QUANTUM, phase_quantum); 549 } 550 WREG32_SDMA(i, regSDMA_CNTL, f32_cntl); 551 552 /* Extend page fault timeout to avoid interrupt storm */ 553 WREG32_SDMA(i, regSDMA_UTCL1_TIMEOUT, 0x00800080); 554 } 555 } 556 557 /** 558 * sdma_v4_4_2_inst_enable - stop the async dma engines 559 * 560 * @adev: amdgpu_device pointer 561 * @enable: enable/disable the DMA MEs. 562 * @inst_mask: mask of dma engine instances to be enabled 563 * 564 * Halt or unhalt the async dma engines. 565 */ 566 static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable, 567 uint32_t inst_mask) 568 { 569 u32 f32_cntl; 570 int i; 571 572 if (!enable) { 573 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask); 574 sdma_v4_4_2_inst_rlc_stop(adev, inst_mask); 575 if (adev->sdma.has_page_queue) 576 sdma_v4_4_2_inst_page_stop(adev, inst_mask); 577 578 /* SDMA FW needs to respond to FREEZE requests during reset. 579 * Keep it running during reset */ 580 if (!amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 581 return; 582 } 583 584 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 585 return; 586 587 for_each_inst(i, inst_mask) { 588 f32_cntl = RREG32_SDMA(i, regSDMA_F32_CNTL); 589 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1); 590 WREG32_SDMA(i, regSDMA_F32_CNTL, f32_cntl); 591 } 592 } 593 594 /* 595 * sdma_v4_4_2_rb_cntl - get parameters for rb_cntl 596 */ 597 static uint32_t sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 598 { 599 /* Set ring buffer size in dwords */ 600 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 601 602 barrier(); /* work around https://llvm.org/pr42576 */ 603 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 604 #ifdef __BIG_ENDIAN 605 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 606 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, 607 RPTR_WRITEBACK_SWAP_ENABLE, 1); 608 #endif 609 return rb_cntl; 610 } 611 612 /** 613 * sdma_v4_4_2_gfx_resume - setup and start the async dma engines 614 * 615 * @adev: amdgpu_device pointer 616 * @i: instance to resume 617 * 618 * Set up the gfx DMA ring buffers and enable them. 619 * Returns 0 for success, error for failure. 620 */ 621 static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i) 622 { 623 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 624 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 625 u32 wb_offset; 626 u32 doorbell; 627 u32 doorbell_offset; 628 u64 wptr_gpu_addr; 629 630 wb_offset = (ring->rptr_offs * 4); 631 632 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); 633 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 634 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 635 636 /* set the wb address whether it's enabled or not */ 637 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_HI, 638 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 639 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_LO, 640 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 641 642 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, 643 RPTR_WRITEBACK_ENABLE, 1); 644 645 WREG32_SDMA(i, regSDMA_GFX_RB_BASE, ring->gpu_addr >> 8); 646 WREG32_SDMA(i, regSDMA_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 647 648 ring->wptr = 0; 649 650 /* before programing wptr to a less value, need set minor_ptr_update first */ 651 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 1); 652 653 /* Initialize the ring buffer's read and write pointers */ 654 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0); 655 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0); 656 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0); 657 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0); 658 659 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL); 660 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET); 661 662 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 663 ring->use_doorbell); 664 doorbell_offset = REG_SET_FIELD(doorbell_offset, 665 SDMA_GFX_DOORBELL_OFFSET, 666 OFFSET, ring->doorbell_index); 667 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell); 668 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset); 669 670 sdma_v4_4_2_ring_set_wptr(ring); 671 672 /* set minor_ptr_update to 0 after wptr programed */ 673 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 0); 674 675 /* setup the wptr shadow polling */ 676 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 677 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_LO, 678 lower_32_bits(wptr_gpu_addr)); 679 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_HI, 680 upper_32_bits(wptr_gpu_addr)); 681 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL); 682 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 683 SDMA_GFX_RB_WPTR_POLL_CNTL, 684 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 685 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 686 687 /* enable DMA RB */ 688 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 1); 689 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 690 691 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 692 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 1); 693 #ifdef __BIG_ENDIAN 694 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 695 #endif 696 /* enable DMA IBs */ 697 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 698 } 699 700 /** 701 * sdma_v4_4_2_page_resume - setup and start the async dma engines 702 * 703 * @adev: amdgpu_device pointer 704 * @i: instance to resume 705 * 706 * Set up the page DMA ring buffers and enable them. 707 * Returns 0 for success, error for failure. 708 */ 709 static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i) 710 { 711 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 712 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 713 u32 wb_offset; 714 u32 doorbell; 715 u32 doorbell_offset; 716 u64 wptr_gpu_addr; 717 718 wb_offset = (ring->rptr_offs * 4); 719 720 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); 721 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 722 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 723 724 /* Initialize the ring buffer's read and write pointers */ 725 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, 0); 726 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, 0); 727 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, 0); 728 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, 0); 729 730 /* set the wb address whether it's enabled or not */ 731 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_HI, 732 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 733 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_LO, 734 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 735 736 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, 737 RPTR_WRITEBACK_ENABLE, 1); 738 739 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE, ring->gpu_addr >> 8); 740 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 741 742 ring->wptr = 0; 743 744 /* before programing wptr to a less value, need set minor_ptr_update first */ 745 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 1); 746 747 doorbell = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL); 748 doorbell_offset = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET); 749 750 doorbell = REG_SET_FIELD(doorbell, SDMA_PAGE_DOORBELL, ENABLE, 751 ring->use_doorbell); 752 doorbell_offset = REG_SET_FIELD(doorbell_offset, 753 SDMA_PAGE_DOORBELL_OFFSET, 754 OFFSET, ring->doorbell_index); 755 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL, doorbell); 756 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET, doorbell_offset); 757 758 /* paging queue doorbell range is setup at sdma_v4_4_2_gfx_resume */ 759 sdma_v4_4_2_page_ring_set_wptr(ring); 760 761 /* set minor_ptr_update to 0 after wptr programed */ 762 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 0); 763 764 /* setup the wptr shadow polling */ 765 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 766 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_LO, 767 lower_32_bits(wptr_gpu_addr)); 768 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_HI, 769 upper_32_bits(wptr_gpu_addr)); 770 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL); 771 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 772 SDMA_PAGE_RB_WPTR_POLL_CNTL, 773 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 774 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 775 776 /* enable DMA RB */ 777 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, RB_ENABLE, 1); 778 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 779 780 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); 781 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_ENABLE, 1); 782 #ifdef __BIG_ENDIAN 783 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 784 #endif 785 /* enable DMA IBs */ 786 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); 787 } 788 789 static void sdma_v4_4_2_init_pg(struct amdgpu_device *adev) 790 { 791 792 } 793 794 /** 795 * sdma_v4_4_2_inst_rlc_resume - setup and start the async dma engines 796 * 797 * @adev: amdgpu_device pointer 798 * @inst_mask: mask of dma engine instances to be enabled 799 * 800 * Set up the compute DMA queues and enable them. 801 * Returns 0 for success, error for failure. 802 */ 803 static int sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device *adev, 804 uint32_t inst_mask) 805 { 806 sdma_v4_4_2_init_pg(adev); 807 808 return 0; 809 } 810 811 /** 812 * sdma_v4_4_2_inst_load_microcode - load the sDMA ME ucode 813 * 814 * @adev: amdgpu_device pointer 815 * @inst_mask: mask of dma engine instances to be enabled 816 * 817 * Loads the sDMA0/1 ucode. 818 * Returns 0 for success, -EINVAL if the ucode is not available. 819 */ 820 static int sdma_v4_4_2_inst_load_microcode(struct amdgpu_device *adev, 821 uint32_t inst_mask) 822 { 823 const struct sdma_firmware_header_v1_0 *hdr; 824 const __le32 *fw_data; 825 u32 fw_size; 826 int i, j; 827 828 /* halt the MEs */ 829 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 830 831 for_each_inst(i, inst_mask) { 832 if (!adev->sdma.instance[i].fw) 833 return -EINVAL; 834 835 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 836 amdgpu_ucode_print_sdma_hdr(&hdr->header); 837 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 838 839 fw_data = (const __le32 *) 840 (adev->sdma.instance[i].fw->data + 841 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 842 843 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 0); 844 845 for (j = 0; j < fw_size; j++) 846 WREG32_SDMA(i, regSDMA_UCODE_DATA, 847 le32_to_cpup(fw_data++)); 848 849 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 850 adev->sdma.instance[i].fw_version); 851 } 852 853 return 0; 854 } 855 856 /** 857 * sdma_v4_4_2_inst_start - setup and start the async dma engines 858 * 859 * @adev: amdgpu_device pointer 860 * @inst_mask: mask of dma engine instances to be enabled 861 * 862 * Set up the DMA engines and enable them. 863 * Returns 0 for success, error for failure. 864 */ 865 static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev, 866 uint32_t inst_mask) 867 { 868 struct amdgpu_ring *ring; 869 uint32_t tmp_mask; 870 int i, r = 0; 871 872 if (amdgpu_sriov_vf(adev)) { 873 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 874 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 875 } else { 876 /* bypass sdma microcode loading on Gopher */ 877 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP && 878 adev->sdma.instance[0].fw) { 879 r = sdma_v4_4_2_inst_load_microcode(adev, inst_mask); 880 if (r) 881 return r; 882 } 883 884 /* unhalt the MEs */ 885 sdma_v4_4_2_inst_enable(adev, true, inst_mask); 886 /* enable sdma ring preemption */ 887 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask); 888 } 889 890 /* start the gfx rings and rlc compute queues */ 891 tmp_mask = inst_mask; 892 for_each_inst(i, tmp_mask) { 893 uint32_t temp; 894 895 WREG32_SDMA(i, regSDMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); 896 sdma_v4_4_2_gfx_resume(adev, i); 897 if (adev->sdma.has_page_queue) 898 sdma_v4_4_2_page_resume(adev, i); 899 900 /* set utc l1 enable flag always to 1 */ 901 temp = RREG32_SDMA(i, regSDMA_CNTL); 902 temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1); 903 /* enable context empty interrupt during initialization */ 904 temp = REG_SET_FIELD(temp, SDMA_CNTL, CTXEMPTY_INT_ENABLE, 1); 905 WREG32_SDMA(i, regSDMA_CNTL, temp); 906 907 if (!amdgpu_sriov_vf(adev)) { 908 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 909 /* unhalt engine */ 910 temp = RREG32_SDMA(i, regSDMA_F32_CNTL); 911 temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0); 912 WREG32_SDMA(i, regSDMA_F32_CNTL, temp); 913 } 914 } 915 } 916 917 if (amdgpu_sriov_vf(adev)) { 918 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask); 919 sdma_v4_4_2_inst_enable(adev, true, inst_mask); 920 } else { 921 r = sdma_v4_4_2_inst_rlc_resume(adev, inst_mask); 922 if (r) 923 return r; 924 } 925 926 tmp_mask = inst_mask; 927 for_each_inst(i, tmp_mask) { 928 ring = &adev->sdma.instance[i].ring; 929 930 r = amdgpu_ring_test_helper(ring); 931 if (r) 932 return r; 933 934 if (adev->sdma.has_page_queue) { 935 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 936 937 r = amdgpu_ring_test_helper(page); 938 if (r) 939 return r; 940 } 941 } 942 943 return r; 944 } 945 946 /** 947 * sdma_v4_4_2_ring_test_ring - simple async dma engine test 948 * 949 * @ring: amdgpu_ring structure holding ring information 950 * 951 * Test the DMA engine by writing using it to write an 952 * value to memory. 953 * Returns 0 for success, error for failure. 954 */ 955 static int sdma_v4_4_2_ring_test_ring(struct amdgpu_ring *ring) 956 { 957 struct amdgpu_device *adev = ring->adev; 958 unsigned i; 959 unsigned index; 960 int r; 961 u32 tmp; 962 u64 gpu_addr; 963 964 r = amdgpu_device_wb_get(adev, &index); 965 if (r) 966 return r; 967 968 gpu_addr = adev->wb.gpu_addr + (index * 4); 969 tmp = 0xCAFEDEAD; 970 adev->wb.wb[index] = cpu_to_le32(tmp); 971 972 r = amdgpu_ring_alloc(ring, 5); 973 if (r) 974 goto error_free_wb; 975 976 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 977 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 978 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 979 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 980 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 981 amdgpu_ring_write(ring, 0xDEADBEEF); 982 amdgpu_ring_commit(ring); 983 984 for (i = 0; i < adev->usec_timeout; i++) { 985 tmp = le32_to_cpu(adev->wb.wb[index]); 986 if (tmp == 0xDEADBEEF) 987 break; 988 udelay(1); 989 } 990 991 if (i >= adev->usec_timeout) 992 r = -ETIMEDOUT; 993 994 error_free_wb: 995 amdgpu_device_wb_free(adev, index); 996 return r; 997 } 998 999 /** 1000 * sdma_v4_4_2_ring_test_ib - test an IB on the DMA engine 1001 * 1002 * @ring: amdgpu_ring structure holding ring information 1003 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1004 * 1005 * Test a simple IB in the DMA ring. 1006 * Returns 0 on success, error on failure. 1007 */ 1008 static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1009 { 1010 struct amdgpu_device *adev = ring->adev; 1011 struct amdgpu_ib ib; 1012 struct dma_fence *f = NULL; 1013 unsigned index; 1014 long r; 1015 u32 tmp = 0; 1016 u64 gpu_addr; 1017 1018 r = amdgpu_device_wb_get(adev, &index); 1019 if (r) 1020 return r; 1021 1022 gpu_addr = adev->wb.gpu_addr + (index * 4); 1023 tmp = 0xCAFEDEAD; 1024 adev->wb.wb[index] = cpu_to_le32(tmp); 1025 memset(&ib, 0, sizeof(ib)); 1026 r = amdgpu_ib_get(adev, NULL, 256, 1027 AMDGPU_IB_POOL_DIRECT, &ib); 1028 if (r) 1029 goto err0; 1030 1031 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1032 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1033 ib.ptr[1] = lower_32_bits(gpu_addr); 1034 ib.ptr[2] = upper_32_bits(gpu_addr); 1035 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1036 ib.ptr[4] = 0xDEADBEEF; 1037 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1038 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1039 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1040 ib.length_dw = 8; 1041 1042 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1043 if (r) 1044 goto err1; 1045 1046 r = dma_fence_wait_timeout(f, false, timeout); 1047 if (r == 0) { 1048 r = -ETIMEDOUT; 1049 goto err1; 1050 } else if (r < 0) { 1051 goto err1; 1052 } 1053 tmp = le32_to_cpu(adev->wb.wb[index]); 1054 if (tmp == 0xDEADBEEF) 1055 r = 0; 1056 else 1057 r = -EINVAL; 1058 1059 err1: 1060 amdgpu_ib_free(adev, &ib, NULL); 1061 dma_fence_put(f); 1062 err0: 1063 amdgpu_device_wb_free(adev, index); 1064 return r; 1065 } 1066 1067 1068 /** 1069 * sdma_v4_4_2_vm_copy_pte - update PTEs by copying them from the GART 1070 * 1071 * @ib: indirect buffer to fill with commands 1072 * @pe: addr of the page entry 1073 * @src: src addr to copy from 1074 * @count: number of page entries to update 1075 * 1076 * Update PTEs by copying them from the GART using sDMA. 1077 */ 1078 static void sdma_v4_4_2_vm_copy_pte(struct amdgpu_ib *ib, 1079 uint64_t pe, uint64_t src, 1080 unsigned count) 1081 { 1082 unsigned bytes = count * 8; 1083 1084 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1085 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1086 ib->ptr[ib->length_dw++] = bytes - 1; 1087 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1088 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1089 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1090 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1091 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1092 1093 } 1094 1095 /** 1096 * sdma_v4_4_2_vm_write_pte - update PTEs by writing them manually 1097 * 1098 * @ib: indirect buffer to fill with commands 1099 * @pe: addr of the page entry 1100 * @value: dst addr to write into pe 1101 * @count: number of page entries to update 1102 * @incr: increase next addr by incr bytes 1103 * 1104 * Update PTEs by writing them manually using sDMA. 1105 */ 1106 static void sdma_v4_4_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1107 uint64_t value, unsigned count, 1108 uint32_t incr) 1109 { 1110 unsigned ndw = count * 2; 1111 1112 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1113 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1114 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1115 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1116 ib->ptr[ib->length_dw++] = ndw - 1; 1117 for (; ndw > 0; ndw -= 2) { 1118 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1119 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1120 value += incr; 1121 } 1122 } 1123 1124 /** 1125 * sdma_v4_4_2_vm_set_pte_pde - update the page tables using sDMA 1126 * 1127 * @ib: indirect buffer to fill with commands 1128 * @pe: addr of the page entry 1129 * @addr: dst addr to write into pe 1130 * @count: number of page entries to update 1131 * @incr: increase next addr by incr bytes 1132 * @flags: access flags 1133 * 1134 * Update the page tables using sDMA. 1135 */ 1136 static void sdma_v4_4_2_vm_set_pte_pde(struct amdgpu_ib *ib, 1137 uint64_t pe, 1138 uint64_t addr, unsigned count, 1139 uint32_t incr, uint64_t flags) 1140 { 1141 /* for physically contiguous pages (vram) */ 1142 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1143 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1144 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1145 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1146 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1147 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1148 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1149 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1150 ib->ptr[ib->length_dw++] = 0; 1151 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1152 } 1153 1154 /** 1155 * sdma_v4_4_2_ring_pad_ib - pad the IB to the required number of dw 1156 * 1157 * @ring: amdgpu_ring structure holding ring information 1158 * @ib: indirect buffer to fill with padding 1159 */ 1160 static void sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1161 { 1162 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1163 u32 pad_count; 1164 int i; 1165 1166 pad_count = (-ib->length_dw) & 7; 1167 for (i = 0; i < pad_count; i++) 1168 if (sdma && sdma->burst_nop && (i == 0)) 1169 ib->ptr[ib->length_dw++] = 1170 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1171 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1172 else 1173 ib->ptr[ib->length_dw++] = 1174 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1175 } 1176 1177 1178 /** 1179 * sdma_v4_4_2_ring_emit_pipeline_sync - sync the pipeline 1180 * 1181 * @ring: amdgpu_ring pointer 1182 * 1183 * Make sure all previous operations are completed (CIK). 1184 */ 1185 static void sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1186 { 1187 uint32_t seq = ring->fence_drv.sync_seq; 1188 uint64_t addr = ring->fence_drv.gpu_addr; 1189 1190 /* wait for idle */ 1191 sdma_v4_4_2_wait_reg_mem(ring, 1, 0, 1192 addr & 0xfffffffc, 1193 upper_32_bits(addr) & 0xffffffff, 1194 seq, 0xffffffff, 4); 1195 } 1196 1197 1198 /** 1199 * sdma_v4_4_2_ring_emit_vm_flush - vm flush using sDMA 1200 * 1201 * @ring: amdgpu_ring pointer 1202 * @vmid: vmid number to use 1203 * @pd_addr: address 1204 * 1205 * Update the page table base and flush the VM TLB 1206 * using sDMA. 1207 */ 1208 static void sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring *ring, 1209 unsigned vmid, uint64_t pd_addr) 1210 { 1211 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1212 } 1213 1214 static void sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring *ring, 1215 uint32_t reg, uint32_t val) 1216 { 1217 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1218 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1219 amdgpu_ring_write(ring, reg); 1220 amdgpu_ring_write(ring, val); 1221 } 1222 1223 static void sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1224 uint32_t val, uint32_t mask) 1225 { 1226 sdma_v4_4_2_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1227 } 1228 1229 static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev) 1230 { 1231 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1232 case IP_VERSION(4, 4, 2): 1233 case IP_VERSION(4, 4, 5): 1234 return false; 1235 default: 1236 return false; 1237 } 1238 } 1239 1240 static int sdma_v4_4_2_early_init(void *handle) 1241 { 1242 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1243 int r; 1244 1245 r = sdma_v4_4_2_init_microcode(adev); 1246 if (r) 1247 return r; 1248 1249 /* TODO: Page queue breaks driver reload under SRIOV */ 1250 if (sdma_v4_4_2_fw_support_paging_queue(adev)) 1251 adev->sdma.has_page_queue = true; 1252 1253 sdma_v4_4_2_set_ring_funcs(adev); 1254 sdma_v4_4_2_set_buffer_funcs(adev); 1255 sdma_v4_4_2_set_vm_pte_funcs(adev); 1256 sdma_v4_4_2_set_irq_funcs(adev); 1257 sdma_v4_4_2_set_ras_funcs(adev); 1258 1259 return 0; 1260 } 1261 1262 #if 0 1263 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, 1264 void *err_data, 1265 struct amdgpu_iv_entry *entry); 1266 #endif 1267 1268 static int sdma_v4_4_2_late_init(void *handle) 1269 { 1270 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1271 #if 0 1272 struct ras_ih_if ih_info = { 1273 .cb = sdma_v4_4_2_process_ras_data_cb, 1274 }; 1275 #endif 1276 if (!amdgpu_persistent_edc_harvesting_supported(adev)) 1277 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__SDMA); 1278 1279 return 0; 1280 } 1281 1282 static int sdma_v4_4_2_sw_init(void *handle) 1283 { 1284 struct amdgpu_ring *ring; 1285 int r, i; 1286 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1287 u32 aid_id; 1288 1289 /* SDMA trap event */ 1290 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1291 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1292 SDMA0_4_0__SRCID__SDMA_TRAP, 1293 &adev->sdma.trap_irq); 1294 if (r) 1295 return r; 1296 } 1297 1298 /* SDMA SRAM ECC event */ 1299 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1300 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1301 SDMA0_4_0__SRCID__SDMA_SRAM_ECC, 1302 &adev->sdma.ecc_irq); 1303 if (r) 1304 return r; 1305 } 1306 1307 /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/ 1308 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1309 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1310 SDMA0_4_0__SRCID__SDMA_VM_HOLE, 1311 &adev->sdma.vm_hole_irq); 1312 if (r) 1313 return r; 1314 1315 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1316 SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID, 1317 &adev->sdma.doorbell_invalid_irq); 1318 if (r) 1319 return r; 1320 1321 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1322 SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT, 1323 &adev->sdma.pool_timeout_irq); 1324 if (r) 1325 return r; 1326 1327 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1328 SDMA0_4_0__SRCID__SDMA_SRBMWRITE, 1329 &adev->sdma.srbm_write_irq); 1330 if (r) 1331 return r; 1332 } 1333 1334 for (i = 0; i < adev->sdma.num_instances; i++) { 1335 ring = &adev->sdma.instance[i].ring; 1336 ring->ring_obj = NULL; 1337 ring->use_doorbell = true; 1338 aid_id = adev->sdma.instance[i].aid_id; 1339 1340 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1341 ring->use_doorbell?"true":"false"); 1342 1343 /* doorbell size is 2 dwords, get DWORD offset */ 1344 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1345 ring->vm_hub = AMDGPU_MMHUB0(aid_id); 1346 1347 sprintf(ring->name, "sdma%d.%d", aid_id, 1348 i % adev->sdma.num_inst_per_aid); 1349 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1350 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1351 AMDGPU_RING_PRIO_DEFAULT, NULL); 1352 if (r) 1353 return r; 1354 1355 if (adev->sdma.has_page_queue) { 1356 ring = &adev->sdma.instance[i].page; 1357 ring->ring_obj = NULL; 1358 ring->use_doorbell = true; 1359 1360 /* doorbell index of page queue is assigned right after 1361 * gfx queue on the same instance 1362 */ 1363 ring->doorbell_index = 1364 (adev->doorbell_index.sdma_engine[i] + 1) << 1; 1365 ring->vm_hub = AMDGPU_MMHUB0(aid_id); 1366 1367 sprintf(ring->name, "page%d.%d", aid_id, 1368 i % adev->sdma.num_inst_per_aid); 1369 r = amdgpu_ring_init(adev, ring, 1024, 1370 &adev->sdma.trap_irq, 1371 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1372 AMDGPU_RING_PRIO_DEFAULT, NULL); 1373 if (r) 1374 return r; 1375 } 1376 } 1377 1378 if (amdgpu_sdma_ras_sw_init(adev)) { 1379 dev_err(adev->dev, "fail to initialize sdma ras block\n"); 1380 return -EINVAL; 1381 } 1382 1383 return r; 1384 } 1385 1386 static int sdma_v4_4_2_sw_fini(void *handle) 1387 { 1388 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1389 int i; 1390 1391 for (i = 0; i < adev->sdma.num_instances; i++) { 1392 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1393 if (adev->sdma.has_page_queue) 1394 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1395 } 1396 1397 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) || 1398 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) 1399 amdgpu_sdma_destroy_inst_ctx(adev, true); 1400 else 1401 amdgpu_sdma_destroy_inst_ctx(adev, false); 1402 1403 return 0; 1404 } 1405 1406 static int sdma_v4_4_2_hw_init(void *handle) 1407 { 1408 int r; 1409 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1410 uint32_t inst_mask; 1411 1412 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1413 if (!amdgpu_sriov_vf(adev)) 1414 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask); 1415 1416 r = sdma_v4_4_2_inst_start(adev, inst_mask); 1417 1418 return r; 1419 } 1420 1421 static int sdma_v4_4_2_hw_fini(void *handle) 1422 { 1423 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1424 uint32_t inst_mask; 1425 int i; 1426 1427 if (amdgpu_sriov_vf(adev)) 1428 return 0; 1429 1430 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1431 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 1432 for (i = 0; i < adev->sdma.num_instances; i++) { 1433 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 1434 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1435 } 1436 } 1437 1438 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 1439 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 1440 1441 return 0; 1442 } 1443 1444 static int sdma_v4_4_2_set_clockgating_state(void *handle, 1445 enum amd_clockgating_state state); 1446 1447 static int sdma_v4_4_2_suspend(void *handle) 1448 { 1449 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1450 1451 if (amdgpu_in_reset(adev)) 1452 sdma_v4_4_2_set_clockgating_state(adev, AMD_CG_STATE_UNGATE); 1453 1454 return sdma_v4_4_2_hw_fini(adev); 1455 } 1456 1457 static int sdma_v4_4_2_resume(void *handle) 1458 { 1459 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1460 1461 return sdma_v4_4_2_hw_init(adev); 1462 } 1463 1464 static bool sdma_v4_4_2_is_idle(void *handle) 1465 { 1466 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1467 u32 i; 1468 1469 for (i = 0; i < adev->sdma.num_instances; i++) { 1470 u32 tmp = RREG32_SDMA(i, regSDMA_STATUS_REG); 1471 1472 if (!(tmp & SDMA_STATUS_REG__IDLE_MASK)) 1473 return false; 1474 } 1475 1476 return true; 1477 } 1478 1479 static int sdma_v4_4_2_wait_for_idle(void *handle) 1480 { 1481 unsigned i, j; 1482 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; 1483 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1484 1485 for (i = 0; i < adev->usec_timeout; i++) { 1486 for (j = 0; j < adev->sdma.num_instances; j++) { 1487 sdma[j] = RREG32_SDMA(j, regSDMA_STATUS_REG); 1488 if (!(sdma[j] & SDMA_STATUS_REG__IDLE_MASK)) 1489 break; 1490 } 1491 if (j == adev->sdma.num_instances) 1492 return 0; 1493 udelay(1); 1494 } 1495 return -ETIMEDOUT; 1496 } 1497 1498 static int sdma_v4_4_2_soft_reset(void *handle) 1499 { 1500 /* todo */ 1501 1502 return 0; 1503 } 1504 1505 static int sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device *adev, 1506 struct amdgpu_irq_src *source, 1507 unsigned type, 1508 enum amdgpu_interrupt_state state) 1509 { 1510 u32 sdma_cntl; 1511 1512 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); 1513 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE, 1514 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1515 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); 1516 1517 return 0; 1518 } 1519 1520 static int sdma_v4_4_2_process_trap_irq(struct amdgpu_device *adev, 1521 struct amdgpu_irq_src *source, 1522 struct amdgpu_iv_entry *entry) 1523 { 1524 uint32_t instance, i; 1525 1526 DRM_DEBUG("IH: SDMA trap\n"); 1527 instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id); 1528 1529 /* Client id gives the SDMA instance in AID. To know the exact SDMA 1530 * instance, interrupt entry gives the node id which corresponds to the AID instance. 1531 * Match node id with the AID id associated with the SDMA instance. */ 1532 for (i = instance; i < adev->sdma.num_instances; 1533 i += adev->sdma.num_inst_per_aid) { 1534 if (adev->sdma.instance[i].aid_id == 1535 node_id_to_phys_map[entry->node_id]) 1536 break; 1537 } 1538 1539 if (i >= adev->sdma.num_instances) { 1540 dev_WARN_ONCE( 1541 adev->dev, 1, 1542 "Couldn't find the right sdma instance in trap handler"); 1543 return 0; 1544 } 1545 1546 switch (entry->ring_id) { 1547 case 0: 1548 amdgpu_fence_process(&adev->sdma.instance[i].ring); 1549 break; 1550 default: 1551 break; 1552 } 1553 return 0; 1554 } 1555 1556 #if 0 1557 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, 1558 void *err_data, 1559 struct amdgpu_iv_entry *entry) 1560 { 1561 int instance; 1562 1563 /* When “Full RAS” is enabled, the per-IP interrupt sources should 1564 * be disabled and the driver should only look for the aggregated 1565 * interrupt via sync flood 1566 */ 1567 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) 1568 goto out; 1569 1570 instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id); 1571 if (instance < 0) 1572 goto out; 1573 1574 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry); 1575 1576 out: 1577 return AMDGPU_RAS_SUCCESS; 1578 } 1579 #endif 1580 1581 static int sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device *adev, 1582 struct amdgpu_irq_src *source, 1583 struct amdgpu_iv_entry *entry) 1584 { 1585 int instance; 1586 1587 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1588 1589 instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id); 1590 if (instance < 0) 1591 return 0; 1592 1593 switch (entry->ring_id) { 1594 case 0: 1595 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 1596 break; 1597 } 1598 return 0; 1599 } 1600 1601 static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev, 1602 struct amdgpu_irq_src *source, 1603 unsigned type, 1604 enum amdgpu_interrupt_state state) 1605 { 1606 u32 sdma_cntl; 1607 1608 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); 1609 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, DRAM_ECC_INT_ENABLE, 1610 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1611 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); 1612 1613 return 0; 1614 } 1615 1616 static int sdma_v4_4_2_print_iv_entry(struct amdgpu_device *adev, 1617 struct amdgpu_iv_entry *entry) 1618 { 1619 int instance; 1620 struct amdgpu_task_info *task_info; 1621 u64 addr; 1622 1623 instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id); 1624 if (instance < 0 || instance >= adev->sdma.num_instances) { 1625 dev_err(adev->dev, "sdma instance invalid %d\n", instance); 1626 return -EINVAL; 1627 } 1628 1629 addr = (u64)entry->src_data[0] << 12; 1630 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 1631 1632 dev_dbg_ratelimited(adev->dev, 1633 "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u pasid:%u\n", 1634 instance, addr, entry->src_id, entry->ring_id, entry->vmid, 1635 entry->pasid); 1636 1637 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 1638 if (task_info) { 1639 dev_dbg_ratelimited(adev->dev, " for process %s pid %d thread %s pid %d\n", 1640 task_info->process_name, task_info->tgid, 1641 task_info->task_name, task_info->pid); 1642 amdgpu_vm_put_task_info(task_info); 1643 } 1644 1645 return 0; 1646 } 1647 1648 static int sdma_v4_4_2_process_vm_hole_irq(struct amdgpu_device *adev, 1649 struct amdgpu_irq_src *source, 1650 struct amdgpu_iv_entry *entry) 1651 { 1652 dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n"); 1653 sdma_v4_4_2_print_iv_entry(adev, entry); 1654 return 0; 1655 } 1656 1657 static int sdma_v4_4_2_process_doorbell_invalid_irq(struct amdgpu_device *adev, 1658 struct amdgpu_irq_src *source, 1659 struct amdgpu_iv_entry *entry) 1660 { 1661 1662 dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n"); 1663 sdma_v4_4_2_print_iv_entry(adev, entry); 1664 return 0; 1665 } 1666 1667 static int sdma_v4_4_2_process_pool_timeout_irq(struct amdgpu_device *adev, 1668 struct amdgpu_irq_src *source, 1669 struct amdgpu_iv_entry *entry) 1670 { 1671 dev_dbg_ratelimited(adev->dev, 1672 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n"); 1673 sdma_v4_4_2_print_iv_entry(adev, entry); 1674 return 0; 1675 } 1676 1677 static int sdma_v4_4_2_process_srbm_write_irq(struct amdgpu_device *adev, 1678 struct amdgpu_irq_src *source, 1679 struct amdgpu_iv_entry *entry) 1680 { 1681 dev_dbg_ratelimited(adev->dev, 1682 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n"); 1683 sdma_v4_4_2_print_iv_entry(adev, entry); 1684 return 0; 1685 } 1686 1687 static void sdma_v4_4_2_inst_update_medium_grain_light_sleep( 1688 struct amdgpu_device *adev, bool enable, uint32_t inst_mask) 1689 { 1690 uint32_t data, def; 1691 int i; 1692 1693 /* leave as default if it is not driver controlled */ 1694 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) 1695 return; 1696 1697 if (enable) { 1698 for_each_inst(i, inst_mask) { 1699 /* 1-not override: enable sdma mem light sleep */ 1700 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL); 1701 data |= SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1702 if (def != data) 1703 WREG32_SDMA(i, regSDMA_POWER_CNTL, data); 1704 } 1705 } else { 1706 for_each_inst(i, inst_mask) { 1707 /* 0-override:disable sdma mem light sleep */ 1708 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL); 1709 data &= ~SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1710 if (def != data) 1711 WREG32_SDMA(i, regSDMA_POWER_CNTL, data); 1712 } 1713 } 1714 } 1715 1716 static void sdma_v4_4_2_inst_update_medium_grain_clock_gating( 1717 struct amdgpu_device *adev, bool enable, uint32_t inst_mask) 1718 { 1719 uint32_t data, def; 1720 int i; 1721 1722 /* leave as default if it is not driver controlled */ 1723 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) 1724 return; 1725 1726 if (enable) { 1727 for_each_inst(i, inst_mask) { 1728 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL); 1729 data &= ~(SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1730 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1731 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1732 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1733 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1734 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1735 if (def != data) 1736 WREG32_SDMA(i, regSDMA_CLK_CTRL, data); 1737 } 1738 } else { 1739 for_each_inst(i, inst_mask) { 1740 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL); 1741 data |= (SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1742 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1743 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1744 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1745 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1746 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1747 if (def != data) 1748 WREG32_SDMA(i, regSDMA_CLK_CTRL, data); 1749 } 1750 } 1751 } 1752 1753 static int sdma_v4_4_2_set_clockgating_state(void *handle, 1754 enum amd_clockgating_state state) 1755 { 1756 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1757 uint32_t inst_mask; 1758 1759 if (amdgpu_sriov_vf(adev)) 1760 return 0; 1761 1762 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1763 1764 sdma_v4_4_2_inst_update_medium_grain_clock_gating( 1765 adev, state == AMD_CG_STATE_GATE, inst_mask); 1766 sdma_v4_4_2_inst_update_medium_grain_light_sleep( 1767 adev, state == AMD_CG_STATE_GATE, inst_mask); 1768 return 0; 1769 } 1770 1771 static int sdma_v4_4_2_set_powergating_state(void *handle, 1772 enum amd_powergating_state state) 1773 { 1774 return 0; 1775 } 1776 1777 static void sdma_v4_4_2_get_clockgating_state(void *handle, u64 *flags) 1778 { 1779 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1780 int data; 1781 1782 if (amdgpu_sriov_vf(adev)) 1783 *flags = 0; 1784 1785 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1786 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL)); 1787 if (!(data & SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK)) 1788 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1789 1790 /* AMD_CG_SUPPORT_SDMA_LS */ 1791 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL)); 1792 if (data & SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1793 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1794 } 1795 1796 const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = { 1797 .name = "sdma_v4_4_2", 1798 .early_init = sdma_v4_4_2_early_init, 1799 .late_init = sdma_v4_4_2_late_init, 1800 .sw_init = sdma_v4_4_2_sw_init, 1801 .sw_fini = sdma_v4_4_2_sw_fini, 1802 .hw_init = sdma_v4_4_2_hw_init, 1803 .hw_fini = sdma_v4_4_2_hw_fini, 1804 .suspend = sdma_v4_4_2_suspend, 1805 .resume = sdma_v4_4_2_resume, 1806 .is_idle = sdma_v4_4_2_is_idle, 1807 .wait_for_idle = sdma_v4_4_2_wait_for_idle, 1808 .soft_reset = sdma_v4_4_2_soft_reset, 1809 .set_clockgating_state = sdma_v4_4_2_set_clockgating_state, 1810 .set_powergating_state = sdma_v4_4_2_set_powergating_state, 1811 .get_clockgating_state = sdma_v4_4_2_get_clockgating_state, 1812 }; 1813 1814 static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = { 1815 .type = AMDGPU_RING_TYPE_SDMA, 1816 .align_mask = 0xff, 1817 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1818 .support_64bit_ptrs = true, 1819 .get_rptr = sdma_v4_4_2_ring_get_rptr, 1820 .get_wptr = sdma_v4_4_2_ring_get_wptr, 1821 .set_wptr = sdma_v4_4_2_ring_set_wptr, 1822 .emit_frame_size = 1823 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */ 1824 3 + /* hdp invalidate */ 1825 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */ 1826 /* sdma_v4_4_2_ring_emit_vm_flush */ 1827 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1828 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1829 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */ 1830 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */ 1831 .emit_ib = sdma_v4_4_2_ring_emit_ib, 1832 .emit_fence = sdma_v4_4_2_ring_emit_fence, 1833 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync, 1834 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush, 1835 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush, 1836 .test_ring = sdma_v4_4_2_ring_test_ring, 1837 .test_ib = sdma_v4_4_2_ring_test_ib, 1838 .insert_nop = sdma_v4_4_2_ring_insert_nop, 1839 .pad_ib = sdma_v4_4_2_ring_pad_ib, 1840 .emit_wreg = sdma_v4_4_2_ring_emit_wreg, 1841 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, 1842 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1843 }; 1844 1845 static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = { 1846 .type = AMDGPU_RING_TYPE_SDMA, 1847 .align_mask = 0xff, 1848 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1849 .support_64bit_ptrs = true, 1850 .get_rptr = sdma_v4_4_2_ring_get_rptr, 1851 .get_wptr = sdma_v4_4_2_page_ring_get_wptr, 1852 .set_wptr = sdma_v4_4_2_page_ring_set_wptr, 1853 .emit_frame_size = 1854 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */ 1855 3 + /* hdp invalidate */ 1856 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */ 1857 /* sdma_v4_4_2_ring_emit_vm_flush */ 1858 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1859 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1860 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */ 1861 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */ 1862 .emit_ib = sdma_v4_4_2_ring_emit_ib, 1863 .emit_fence = sdma_v4_4_2_ring_emit_fence, 1864 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync, 1865 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush, 1866 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush, 1867 .test_ring = sdma_v4_4_2_ring_test_ring, 1868 .test_ib = sdma_v4_4_2_ring_test_ib, 1869 .insert_nop = sdma_v4_4_2_ring_insert_nop, 1870 .pad_ib = sdma_v4_4_2_ring_pad_ib, 1871 .emit_wreg = sdma_v4_4_2_ring_emit_wreg, 1872 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, 1873 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1874 }; 1875 1876 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev) 1877 { 1878 int i, dev_inst; 1879 1880 for (i = 0; i < adev->sdma.num_instances; i++) { 1881 adev->sdma.instance[i].ring.funcs = &sdma_v4_4_2_ring_funcs; 1882 adev->sdma.instance[i].ring.me = i; 1883 if (adev->sdma.has_page_queue) { 1884 adev->sdma.instance[i].page.funcs = 1885 &sdma_v4_4_2_page_ring_funcs; 1886 adev->sdma.instance[i].page.me = i; 1887 } 1888 1889 dev_inst = GET_INST(SDMA0, i); 1890 /* AID to which SDMA belongs depends on physical instance */ 1891 adev->sdma.instance[i].aid_id = 1892 dev_inst / adev->sdma.num_inst_per_aid; 1893 } 1894 } 1895 1896 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_trap_irq_funcs = { 1897 .set = sdma_v4_4_2_set_trap_irq_state, 1898 .process = sdma_v4_4_2_process_trap_irq, 1899 }; 1900 1901 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_illegal_inst_irq_funcs = { 1902 .process = sdma_v4_4_2_process_illegal_inst_irq, 1903 }; 1904 1905 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ecc_irq_funcs = { 1906 .set = sdma_v4_4_2_set_ecc_irq_state, 1907 .process = amdgpu_sdma_process_ecc_irq, 1908 }; 1909 1910 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_vm_hole_irq_funcs = { 1911 .process = sdma_v4_4_2_process_vm_hole_irq, 1912 }; 1913 1914 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_doorbell_invalid_irq_funcs = { 1915 .process = sdma_v4_4_2_process_doorbell_invalid_irq, 1916 }; 1917 1918 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_pool_timeout_irq_funcs = { 1919 .process = sdma_v4_4_2_process_pool_timeout_irq, 1920 }; 1921 1922 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_srbm_write_irq_funcs = { 1923 .process = sdma_v4_4_2_process_srbm_write_irq, 1924 }; 1925 1926 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev) 1927 { 1928 adev->sdma.trap_irq.num_types = adev->sdma.num_instances; 1929 adev->sdma.ecc_irq.num_types = adev->sdma.num_instances; 1930 adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances; 1931 adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances; 1932 adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances; 1933 adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances; 1934 1935 adev->sdma.trap_irq.funcs = &sdma_v4_4_2_trap_irq_funcs; 1936 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_4_2_illegal_inst_irq_funcs; 1937 adev->sdma.ecc_irq.funcs = &sdma_v4_4_2_ecc_irq_funcs; 1938 adev->sdma.vm_hole_irq.funcs = &sdma_v4_4_2_vm_hole_irq_funcs; 1939 adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_4_2_doorbell_invalid_irq_funcs; 1940 adev->sdma.pool_timeout_irq.funcs = &sdma_v4_4_2_pool_timeout_irq_funcs; 1941 adev->sdma.srbm_write_irq.funcs = &sdma_v4_4_2_srbm_write_irq_funcs; 1942 } 1943 1944 /** 1945 * sdma_v4_4_2_emit_copy_buffer - copy buffer using the sDMA engine 1946 * 1947 * @ib: indirect buffer to copy to 1948 * @src_offset: src GPU address 1949 * @dst_offset: dst GPU address 1950 * @byte_count: number of bytes to xfer 1951 * @copy_flags: copy flags for the buffers 1952 * 1953 * Copy GPU buffers using the DMA engine. 1954 * Used by the amdgpu ttm implementation to move pages if 1955 * registered as the asic copy callback. 1956 */ 1957 static void sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib *ib, 1958 uint64_t src_offset, 1959 uint64_t dst_offset, 1960 uint32_t byte_count, 1961 uint32_t copy_flags) 1962 { 1963 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1964 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1965 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0); 1966 ib->ptr[ib->length_dw++] = byte_count - 1; 1967 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1968 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1969 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1970 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1971 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1972 } 1973 1974 /** 1975 * sdma_v4_4_2_emit_fill_buffer - fill buffer using the sDMA engine 1976 * 1977 * @ib: indirect buffer to copy to 1978 * @src_data: value to write to buffer 1979 * @dst_offset: dst GPU address 1980 * @byte_count: number of bytes to xfer 1981 * 1982 * Fill GPU buffers using the DMA engine. 1983 */ 1984 static void sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib *ib, 1985 uint32_t src_data, 1986 uint64_t dst_offset, 1987 uint32_t byte_count) 1988 { 1989 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1990 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1991 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1992 ib->ptr[ib->length_dw++] = src_data; 1993 ib->ptr[ib->length_dw++] = byte_count - 1; 1994 } 1995 1996 static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = { 1997 .copy_max_bytes = 0x400000, 1998 .copy_num_dw = 7, 1999 .emit_copy_buffer = sdma_v4_4_2_emit_copy_buffer, 2000 2001 .fill_max_bytes = 0x400000, 2002 .fill_num_dw = 5, 2003 .emit_fill_buffer = sdma_v4_4_2_emit_fill_buffer, 2004 }; 2005 2006 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev) 2007 { 2008 adev->mman.buffer_funcs = &sdma_v4_4_2_buffer_funcs; 2009 if (adev->sdma.has_page_queue) 2010 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; 2011 else 2012 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2013 } 2014 2015 static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = { 2016 .copy_pte_num_dw = 7, 2017 .copy_pte = sdma_v4_4_2_vm_copy_pte, 2018 2019 .write_pte = sdma_v4_4_2_vm_write_pte, 2020 .set_pte_pde = sdma_v4_4_2_vm_set_pte_pde, 2021 }; 2022 2023 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev) 2024 { 2025 struct drm_gpu_scheduler *sched; 2026 unsigned i; 2027 2028 adev->vm_manager.vm_pte_funcs = &sdma_v4_4_2_vm_pte_funcs; 2029 for (i = 0; i < adev->sdma.num_instances; i++) { 2030 if (adev->sdma.has_page_queue) 2031 sched = &adev->sdma.instance[i].page.sched; 2032 else 2033 sched = &adev->sdma.instance[i].ring.sched; 2034 adev->vm_manager.vm_pte_scheds[i] = sched; 2035 } 2036 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 2037 } 2038 2039 const struct amdgpu_ip_block_version sdma_v4_4_2_ip_block = { 2040 .type = AMD_IP_BLOCK_TYPE_SDMA, 2041 .major = 4, 2042 .minor = 4, 2043 .rev = 2, 2044 .funcs = &sdma_v4_4_2_ip_funcs, 2045 }; 2046 2047 static int sdma_v4_4_2_xcp_resume(void *handle, uint32_t inst_mask) 2048 { 2049 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2050 int r; 2051 2052 if (!amdgpu_sriov_vf(adev)) 2053 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask); 2054 2055 r = sdma_v4_4_2_inst_start(adev, inst_mask); 2056 2057 return r; 2058 } 2059 2060 static int sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask) 2061 { 2062 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2063 uint32_t tmp_mask = inst_mask; 2064 int i; 2065 2066 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2067 for_each_inst(i, tmp_mask) { 2068 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 2069 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 2070 } 2071 } 2072 2073 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 2074 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 2075 2076 return 0; 2077 } 2078 2079 struct amdgpu_xcp_ip_funcs sdma_v4_4_2_xcp_funcs = { 2080 .suspend = &sdma_v4_4_2_xcp_suspend, 2081 .resume = &sdma_v4_4_2_xcp_resume 2082 }; 2083 2084 static const struct amdgpu_ras_err_status_reg_entry sdma_v4_2_2_ue_reg_list[] = { 2085 {AMDGPU_RAS_REG_ENTRY(SDMA0, 0, regSDMA_UE_ERR_STATUS_LO, regSDMA_UE_ERR_STATUS_HI), 2086 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SDMA"}, 2087 }; 2088 2089 static const struct amdgpu_ras_memory_id_entry sdma_v4_4_2_ras_memory_list[] = { 2090 {AMDGPU_SDMA_MBANK_DATA_BUF0, "SDMA_MBANK_DATA_BUF0"}, 2091 {AMDGPU_SDMA_MBANK_DATA_BUF1, "SDMA_MBANK_DATA_BUF1"}, 2092 {AMDGPU_SDMA_MBANK_DATA_BUF2, "SDMA_MBANK_DATA_BUF2"}, 2093 {AMDGPU_SDMA_MBANK_DATA_BUF3, "SDMA_MBANK_DATA_BUF3"}, 2094 {AMDGPU_SDMA_MBANK_DATA_BUF4, "SDMA_MBANK_DATA_BUF4"}, 2095 {AMDGPU_SDMA_MBANK_DATA_BUF5, "SDMA_MBANK_DATA_BUF5"}, 2096 {AMDGPU_SDMA_MBANK_DATA_BUF6, "SDMA_MBANK_DATA_BUF6"}, 2097 {AMDGPU_SDMA_MBANK_DATA_BUF7, "SDMA_MBANK_DATA_BUF7"}, 2098 {AMDGPU_SDMA_MBANK_DATA_BUF8, "SDMA_MBANK_DATA_BUF8"}, 2099 {AMDGPU_SDMA_MBANK_DATA_BUF9, "SDMA_MBANK_DATA_BUF9"}, 2100 {AMDGPU_SDMA_MBANK_DATA_BUF10, "SDMA_MBANK_DATA_BUF10"}, 2101 {AMDGPU_SDMA_MBANK_DATA_BUF11, "SDMA_MBANK_DATA_BUF11"}, 2102 {AMDGPU_SDMA_MBANK_DATA_BUF12, "SDMA_MBANK_DATA_BUF12"}, 2103 {AMDGPU_SDMA_MBANK_DATA_BUF13, "SDMA_MBANK_DATA_BUF13"}, 2104 {AMDGPU_SDMA_MBANK_DATA_BUF14, "SDMA_MBANK_DATA_BUF14"}, 2105 {AMDGPU_SDMA_MBANK_DATA_BUF15, "SDMA_MBANK_DATA_BUF15"}, 2106 {AMDGPU_SDMA_UCODE_BUF, "SDMA_UCODE_BUF"}, 2107 {AMDGPU_SDMA_RB_CMD_BUF, "SDMA_RB_CMD_BUF"}, 2108 {AMDGPU_SDMA_IB_CMD_BUF, "SDMA_IB_CMD_BUF"}, 2109 {AMDGPU_SDMA_UTCL1_RD_FIFO, "SDMA_UTCL1_RD_FIFO"}, 2110 {AMDGPU_SDMA_UTCL1_RDBST_FIFO, "SDMA_UTCL1_RDBST_FIFO"}, 2111 {AMDGPU_SDMA_UTCL1_WR_FIFO, "SDMA_UTCL1_WR_FIFO"}, 2112 {AMDGPU_SDMA_DATA_LUT_FIFO, "SDMA_DATA_LUT_FIFO"}, 2113 {AMDGPU_SDMA_SPLIT_DAT_BUF, "SDMA_SPLIT_DAT_BUF"}, 2114 }; 2115 2116 static void sdma_v4_4_2_inst_query_ras_error_count(struct amdgpu_device *adev, 2117 uint32_t sdma_inst, 2118 void *ras_err_status) 2119 { 2120 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 2121 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); 2122 unsigned long ue_count = 0; 2123 struct amdgpu_smuio_mcm_config_info mcm_info = { 2124 .socket_id = adev->smuio.funcs->get_socket_id(adev), 2125 .die_id = adev->sdma.instance[sdma_inst].aid_id, 2126 }; 2127 2128 /* sdma v4_4_2 doesn't support query ce counts */ 2129 amdgpu_ras_inst_query_ras_error_count(adev, 2130 sdma_v4_2_2_ue_reg_list, 2131 ARRAY_SIZE(sdma_v4_2_2_ue_reg_list), 2132 sdma_v4_4_2_ras_memory_list, 2133 ARRAY_SIZE(sdma_v4_4_2_ras_memory_list), 2134 sdma_dev_inst, 2135 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 2136 &ue_count); 2137 2138 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, NULL, ue_count); 2139 } 2140 2141 static void sdma_v4_4_2_query_ras_error_count(struct amdgpu_device *adev, 2142 void *ras_err_status) 2143 { 2144 uint32_t inst_mask; 2145 int i = 0; 2146 2147 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 2148 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2149 for_each_inst(i, inst_mask) 2150 sdma_v4_4_2_inst_query_ras_error_count(adev, i, ras_err_status); 2151 } else { 2152 dev_warn(adev->dev, "SDMA RAS is not supported\n"); 2153 } 2154 } 2155 2156 static void sdma_v4_4_2_inst_reset_ras_error_count(struct amdgpu_device *adev, 2157 uint32_t sdma_inst) 2158 { 2159 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); 2160 2161 amdgpu_ras_inst_reset_ras_error_count(adev, 2162 sdma_v4_2_2_ue_reg_list, 2163 ARRAY_SIZE(sdma_v4_2_2_ue_reg_list), 2164 sdma_dev_inst); 2165 } 2166 2167 static void sdma_v4_4_2_reset_ras_error_count(struct amdgpu_device *adev) 2168 { 2169 uint32_t inst_mask; 2170 int i = 0; 2171 2172 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 2173 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2174 for_each_inst(i, inst_mask) 2175 sdma_v4_4_2_inst_reset_ras_error_count(adev, i); 2176 } else { 2177 dev_warn(adev->dev, "SDMA RAS is not supported\n"); 2178 } 2179 } 2180 2181 static const struct amdgpu_ras_block_hw_ops sdma_v4_4_2_ras_hw_ops = { 2182 .query_ras_error_count = sdma_v4_4_2_query_ras_error_count, 2183 .reset_ras_error_count = sdma_v4_4_2_reset_ras_error_count, 2184 }; 2185 2186 static int sdma_v4_4_2_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, 2187 enum aca_smu_type type, void *data) 2188 { 2189 struct aca_bank_info info; 2190 u64 misc0; 2191 int ret; 2192 2193 ret = aca_bank_info_decode(bank, &info); 2194 if (ret) 2195 return ret; 2196 2197 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 2198 switch (type) { 2199 case ACA_SMU_TYPE_UE: 2200 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE, 2201 1ULL); 2202 break; 2203 case ACA_SMU_TYPE_CE: 2204 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_CE, 2205 ACA_REG__MISC0__ERRCNT(misc0)); 2206 break; 2207 default: 2208 return -EINVAL; 2209 } 2210 2211 return ret; 2212 } 2213 2214 /* CODE_SDMA0 - CODE_SDMA4, reference to smu driver if header file */ 2215 static int sdma_v4_4_2_err_codes[] = { 33, 34, 35, 36 }; 2216 2217 static bool sdma_v4_4_2_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 2218 enum aca_smu_type type, void *data) 2219 { 2220 u32 instlo; 2221 2222 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 2223 instlo &= GENMASK(31, 1); 2224 2225 if (instlo != mmSMNAID_AID0_MCA_SMU) 2226 return false; 2227 2228 if (aca_bank_check_error_codes(handle->adev, bank, 2229 sdma_v4_4_2_err_codes, 2230 ARRAY_SIZE(sdma_v4_4_2_err_codes))) 2231 return false; 2232 2233 return true; 2234 } 2235 2236 static const struct aca_bank_ops sdma_v4_4_2_aca_bank_ops = { 2237 .aca_bank_parser = sdma_v4_4_2_aca_bank_parser, 2238 .aca_bank_is_valid = sdma_v4_4_2_aca_bank_is_valid, 2239 }; 2240 2241 static const struct aca_info sdma_v4_4_2_aca_info = { 2242 .hwip = ACA_HWIP_TYPE_SMU, 2243 .mask = ACA_ERROR_UE_MASK, 2244 .bank_ops = &sdma_v4_4_2_aca_bank_ops, 2245 }; 2246 2247 static int sdma_v4_4_2_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 2248 { 2249 int r; 2250 2251 r = amdgpu_sdma_ras_late_init(adev, ras_block); 2252 if (r) 2253 return r; 2254 2255 return amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__SDMA, 2256 &sdma_v4_4_2_aca_info, NULL); 2257 } 2258 2259 static struct amdgpu_sdma_ras sdma_v4_4_2_ras = { 2260 .ras_block = { 2261 .hw_ops = &sdma_v4_4_2_ras_hw_ops, 2262 .ras_late_init = sdma_v4_4_2_ras_late_init, 2263 }, 2264 }; 2265 2266 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev) 2267 { 2268 adev->sdma.ras = &sdma_v4_4_2_ras; 2269 } 2270