1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_xcp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_trace.h" 33 #include "amdgpu_reset.h" 34 35 #include "sdma/sdma_4_4_2_offset.h" 36 #include "sdma/sdma_4_4_2_sh_mask.h" 37 38 #include "soc15_common.h" 39 #include "soc15.h" 40 #include "vega10_sdma_pkt_open.h" 41 42 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 43 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 44 45 #include "amdgpu_ras.h" 46 47 MODULE_FIRMWARE("amdgpu/sdma_4_4_2.bin"); 48 MODULE_FIRMWARE("amdgpu/sdma_4_4_4.bin"); 49 MODULE_FIRMWARE("amdgpu/sdma_4_4_5.bin"); 50 51 static const struct amdgpu_hwip_reg_entry sdma_reg_list_4_4_2[] = { 52 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS_REG), 53 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS1_REG), 54 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS2_REG), 55 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS3_REG), 56 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UCODE_CHECKSUM), 57 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH_HI), 58 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH), 59 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_STATUS), 60 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_STATUS), 61 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK0), 62 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK1), 63 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK0), 64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK1), 65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_CNTL), 66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR), 67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR_HI), 68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR), 69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR_HI), 70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_OFFSET), 71 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_LO), 72 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_HI), 73 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_CNTL), 74 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_RPTR), 75 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_SUB_REMAIN), 76 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_DUMMY_REG), 77 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_CNTL), 78 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR), 79 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR_HI), 80 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR), 81 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR_HI), 82 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_OFFSET), 83 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_LO), 84 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_HI), 85 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_DUMMY_REG), 86 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_CNTL), 87 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR), 88 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR_HI), 89 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR), 90 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR_HI), 91 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_OFFSET), 92 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_LO), 93 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_HI), 94 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_DUMMY_REG), 95 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_VM_CNTL) 96 }; 97 98 #define WREG32_SDMA(instance, offset, value) \ 99 WREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)), value) 100 #define RREG32_SDMA(instance, offset) \ 101 RREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset))) 102 103 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev); 104 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev); 105 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev); 106 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev); 107 static void sdma_v4_4_2_update_reset_mask(struct amdgpu_device *adev); 108 static int sdma_v4_4_2_stop_queue(struct amdgpu_ring *ring); 109 static int sdma_v4_4_2_restore_queue(struct amdgpu_ring *ring); 110 static int sdma_v4_4_2_soft_reset_engine(struct amdgpu_device *adev, 111 u32 instance_id); 112 113 static u32 sdma_v4_4_2_get_reg_offset(struct amdgpu_device *adev, 114 u32 instance, u32 offset) 115 { 116 u32 dev_inst = GET_INST(SDMA0, instance); 117 118 return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset); 119 } 120 121 static unsigned sdma_v4_4_2_seq_to_irq_id(int seq_num) 122 { 123 switch (seq_num) { 124 case 0: 125 return SOC15_IH_CLIENTID_SDMA0; 126 case 1: 127 return SOC15_IH_CLIENTID_SDMA1; 128 case 2: 129 return SOC15_IH_CLIENTID_SDMA2; 130 case 3: 131 return SOC15_IH_CLIENTID_SDMA3; 132 default: 133 return -EINVAL; 134 } 135 } 136 137 static int sdma_v4_4_2_irq_id_to_seq(struct amdgpu_device *adev, unsigned client_id) 138 { 139 switch (client_id) { 140 case SOC15_IH_CLIENTID_SDMA0: 141 return 0; 142 case SOC15_IH_CLIENTID_SDMA1: 143 return 1; 144 case SOC15_IH_CLIENTID_SDMA2: 145 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) 146 return 0; 147 else 148 return 2; 149 case SOC15_IH_CLIENTID_SDMA3: 150 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) 151 return 1; 152 else 153 return 3; 154 default: 155 return -EINVAL; 156 } 157 } 158 159 static void sdma_v4_4_2_inst_init_golden_registers(struct amdgpu_device *adev, 160 uint32_t inst_mask) 161 { 162 u32 val; 163 int i; 164 165 for (i = 0; i < adev->sdma.num_instances; i++) { 166 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG); 167 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4); 168 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, 169 PIPE_INTERLEAVE_SIZE, 0); 170 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG, val); 171 172 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ); 173 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS, 174 4); 175 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, 176 PIPE_INTERLEAVE_SIZE, 0); 177 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ, val); 178 } 179 } 180 181 /** 182 * sdma_v4_4_2_init_microcode - load ucode images from disk 183 * 184 * @adev: amdgpu_device pointer 185 * 186 * Use the firmware interface to load the ucode images into 187 * the driver (not loaded into hw). 188 * Returns 0 on success, error on failure. 189 */ 190 static int sdma_v4_4_2_init_microcode(struct amdgpu_device *adev) 191 { 192 int ret, i; 193 194 for (i = 0; i < adev->sdma.num_instances; i++) { 195 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) || 196 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 4) || 197 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) { 198 ret = amdgpu_sdma_init_microcode(adev, 0, true); 199 break; 200 } else { 201 ret = amdgpu_sdma_init_microcode(adev, i, false); 202 if (ret) 203 return ret; 204 } 205 } 206 207 return ret; 208 } 209 210 /** 211 * sdma_v4_4_2_ring_get_rptr - get the current read pointer 212 * 213 * @ring: amdgpu ring pointer 214 * 215 * Get the current rptr from the hardware. 216 */ 217 static uint64_t sdma_v4_4_2_ring_get_rptr(struct amdgpu_ring *ring) 218 { 219 u64 rptr; 220 221 /* XXX check if swapping is necessary on BE */ 222 rptr = READ_ONCE(*((u64 *)&ring->adev->wb.wb[ring->rptr_offs])); 223 224 DRM_DEBUG("rptr before shift == 0x%016llx\n", rptr); 225 return rptr >> 2; 226 } 227 228 /** 229 * sdma_v4_4_2_ring_get_wptr - get the current write pointer 230 * 231 * @ring: amdgpu ring pointer 232 * 233 * Get the current wptr from the hardware. 234 */ 235 static uint64_t sdma_v4_4_2_ring_get_wptr(struct amdgpu_ring *ring) 236 { 237 struct amdgpu_device *adev = ring->adev; 238 u64 wptr; 239 240 if (ring->use_doorbell) { 241 /* XXX check if swapping is necessary on BE */ 242 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 243 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 244 } else { 245 wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI); 246 wptr = wptr << 32; 247 wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR); 248 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 249 ring->me, wptr); 250 } 251 252 return wptr >> 2; 253 } 254 255 /** 256 * sdma_v4_4_2_ring_set_wptr - commit the write pointer 257 * 258 * @ring: amdgpu ring pointer 259 * 260 * Write the wptr back to the hardware. 261 */ 262 static void sdma_v4_4_2_ring_set_wptr(struct amdgpu_ring *ring) 263 { 264 struct amdgpu_device *adev = ring->adev; 265 266 DRM_DEBUG("Setting write pointer\n"); 267 if (ring->use_doorbell) { 268 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 269 270 DRM_DEBUG("Using doorbell -- " 271 "wptr_offs == 0x%08x " 272 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 273 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 274 ring->wptr_offs, 275 lower_32_bits(ring->wptr << 2), 276 upper_32_bits(ring->wptr << 2)); 277 /* XXX check if swapping is necessary on BE */ 278 WRITE_ONCE(*wb, (ring->wptr << 2)); 279 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 280 ring->doorbell_index, ring->wptr << 2); 281 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 282 } else { 283 DRM_DEBUG("Not using doorbell -- " 284 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 285 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 286 ring->me, 287 lower_32_bits(ring->wptr << 2), 288 ring->me, 289 upper_32_bits(ring->wptr << 2)); 290 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR, 291 lower_32_bits(ring->wptr << 2)); 292 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI, 293 upper_32_bits(ring->wptr << 2)); 294 } 295 } 296 297 /** 298 * sdma_v4_4_2_page_ring_get_wptr - get the current write pointer 299 * 300 * @ring: amdgpu ring pointer 301 * 302 * Get the current wptr from the hardware. 303 */ 304 static uint64_t sdma_v4_4_2_page_ring_get_wptr(struct amdgpu_ring *ring) 305 { 306 struct amdgpu_device *adev = ring->adev; 307 u64 wptr; 308 309 if (ring->use_doorbell) { 310 /* XXX check if swapping is necessary on BE */ 311 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 312 } else { 313 wptr = RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI); 314 wptr = wptr << 32; 315 wptr |= RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR); 316 } 317 318 return wptr >> 2; 319 } 320 321 /** 322 * sdma_v4_4_2_page_ring_set_wptr - commit the write pointer 323 * 324 * @ring: amdgpu ring pointer 325 * 326 * Write the wptr back to the hardware. 327 */ 328 static void sdma_v4_4_2_page_ring_set_wptr(struct amdgpu_ring *ring) 329 { 330 struct amdgpu_device *adev = ring->adev; 331 332 if (ring->use_doorbell) { 333 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 334 335 /* XXX check if swapping is necessary on BE */ 336 WRITE_ONCE(*wb, (ring->wptr << 2)); 337 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 338 } else { 339 uint64_t wptr = ring->wptr << 2; 340 341 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR, 342 lower_32_bits(wptr)); 343 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI, 344 upper_32_bits(wptr)); 345 } 346 } 347 348 static void sdma_v4_4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 349 { 350 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 351 int i; 352 353 for (i = 0; i < count; i++) 354 if (sdma && sdma->burst_nop && (i == 0)) 355 amdgpu_ring_write(ring, ring->funcs->nop | 356 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 357 else 358 amdgpu_ring_write(ring, ring->funcs->nop); 359 } 360 361 /** 362 * sdma_v4_4_2_ring_emit_ib - Schedule an IB on the DMA engine 363 * 364 * @ring: amdgpu ring pointer 365 * @job: job to retrieve vmid from 366 * @ib: IB object to schedule 367 * @flags: unused 368 * 369 * Schedule an IB in the DMA ring. 370 */ 371 static void sdma_v4_4_2_ring_emit_ib(struct amdgpu_ring *ring, 372 struct amdgpu_job *job, 373 struct amdgpu_ib *ib, 374 uint32_t flags) 375 { 376 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 377 378 /* IB packet must end on a 8 DW boundary */ 379 sdma_v4_4_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 380 381 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 382 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 383 /* base must be 32 byte aligned */ 384 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 385 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 386 amdgpu_ring_write(ring, ib->length_dw); 387 amdgpu_ring_write(ring, 0); 388 amdgpu_ring_write(ring, 0); 389 390 } 391 392 static void sdma_v4_4_2_wait_reg_mem(struct amdgpu_ring *ring, 393 int mem_space, int hdp, 394 uint32_t addr0, uint32_t addr1, 395 uint32_t ref, uint32_t mask, 396 uint32_t inv) 397 { 398 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 399 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 400 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 401 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 402 if (mem_space) { 403 /* memory */ 404 amdgpu_ring_write(ring, addr0); 405 amdgpu_ring_write(ring, addr1); 406 } else { 407 /* registers */ 408 amdgpu_ring_write(ring, addr0 << 2); 409 amdgpu_ring_write(ring, addr1 << 2); 410 } 411 amdgpu_ring_write(ring, ref); /* reference */ 412 amdgpu_ring_write(ring, mask); /* mask */ 413 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 414 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 415 } 416 417 /** 418 * sdma_v4_4_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 419 * 420 * @ring: amdgpu ring pointer 421 * 422 * Emit an hdp flush packet on the requested DMA ring. 423 */ 424 static void sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 425 { 426 struct amdgpu_device *adev = ring->adev; 427 u32 ref_and_mask = 0; 428 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 429 430 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 431 << (ring->me % adev->sdma.num_inst_per_aid); 432 433 sdma_v4_4_2_wait_reg_mem(ring, 0, 1, 434 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 435 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 436 ref_and_mask, ref_and_mask, 10); 437 } 438 439 /** 440 * sdma_v4_4_2_ring_emit_fence - emit a fence on the DMA ring 441 * 442 * @ring: amdgpu ring pointer 443 * @addr: address 444 * @seq: sequence number 445 * @flags: fence related flags 446 * 447 * Add a DMA fence packet to the ring to write 448 * the fence seq number and DMA trap packet to generate 449 * an interrupt if needed. 450 */ 451 static void sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 452 unsigned flags) 453 { 454 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 455 /* write the fence */ 456 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 457 /* zero in first two bits */ 458 WARN_ON(addr & 0x3); 459 amdgpu_ring_write(ring, lower_32_bits(addr)); 460 amdgpu_ring_write(ring, upper_32_bits(addr)); 461 amdgpu_ring_write(ring, lower_32_bits(seq)); 462 463 /* optionally write high bits as well */ 464 if (write64bit) { 465 addr += 4; 466 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 467 /* zero in first two bits */ 468 WARN_ON(addr & 0x3); 469 amdgpu_ring_write(ring, lower_32_bits(addr)); 470 amdgpu_ring_write(ring, upper_32_bits(addr)); 471 amdgpu_ring_write(ring, upper_32_bits(seq)); 472 } 473 474 /* generate an interrupt */ 475 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 476 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 477 } 478 479 480 /** 481 * sdma_v4_4_2_inst_gfx_stop - stop the gfx async dma engines 482 * 483 * @adev: amdgpu_device pointer 484 * @inst_mask: mask of dma engine instances to be disabled 485 * 486 * Stop the gfx async dma ring buffers. 487 */ 488 static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev, 489 uint32_t inst_mask) 490 { 491 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 492 u32 doorbell_offset, doorbell; 493 u32 rb_cntl, ib_cntl, sdma_cntl; 494 int i; 495 496 for_each_inst(i, inst_mask) { 497 sdma[i] = &adev->sdma.instance[i].ring; 498 499 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); 500 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0); 501 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 502 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 503 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0); 504 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 505 sdma_cntl = RREG32_SDMA(i, regSDMA_CNTL); 506 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, UTC_L1_ENABLE, 0); 507 WREG32_SDMA(i, regSDMA_CNTL, sdma_cntl); 508 509 if (sdma[i]->use_doorbell) { 510 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL); 511 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET); 512 513 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 0); 514 doorbell_offset = REG_SET_FIELD(doorbell_offset, 515 SDMA_GFX_DOORBELL_OFFSET, 516 OFFSET, 0); 517 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell); 518 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset); 519 } 520 } 521 } 522 523 /** 524 * sdma_v4_4_2_inst_rlc_stop - stop the compute async dma engines 525 * 526 * @adev: amdgpu_device pointer 527 * @inst_mask: mask of dma engine instances to be disabled 528 * 529 * Stop the compute async dma queues. 530 */ 531 static void sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device *adev, 532 uint32_t inst_mask) 533 { 534 /* XXX todo */ 535 } 536 537 /** 538 * sdma_v4_4_2_inst_page_stop - stop the page async dma engines 539 * 540 * @adev: amdgpu_device pointer 541 * @inst_mask: mask of dma engine instances to be disabled 542 * 543 * Stop the page async dma ring buffers. 544 */ 545 static void sdma_v4_4_2_inst_page_stop(struct amdgpu_device *adev, 546 uint32_t inst_mask) 547 { 548 u32 rb_cntl, ib_cntl; 549 int i; 550 551 for_each_inst(i, inst_mask) { 552 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); 553 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, 554 RB_ENABLE, 0); 555 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 556 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); 557 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, 558 IB_ENABLE, 0); 559 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); 560 } 561 } 562 563 /** 564 * sdma_v4_4_2_inst_ctx_switch_enable - stop the async dma engines context switch 565 * 566 * @adev: amdgpu_device pointer 567 * @enable: enable/disable the DMA MEs context switch. 568 * @inst_mask: mask of dma engine instances to be enabled 569 * 570 * Halt or unhalt the async dma engines context switch. 571 */ 572 static void sdma_v4_4_2_inst_ctx_switch_enable(struct amdgpu_device *adev, 573 bool enable, uint32_t inst_mask) 574 { 575 u32 f32_cntl, phase_quantum = 0; 576 int i; 577 578 if (amdgpu_sdma_phase_quantum) { 579 unsigned value = amdgpu_sdma_phase_quantum; 580 unsigned unit = 0; 581 582 while (value > (SDMA_PHASE0_QUANTUM__VALUE_MASK >> 583 SDMA_PHASE0_QUANTUM__VALUE__SHIFT)) { 584 value = (value + 1) >> 1; 585 unit++; 586 } 587 if (unit > (SDMA_PHASE0_QUANTUM__UNIT_MASK >> 588 SDMA_PHASE0_QUANTUM__UNIT__SHIFT)) { 589 value = (SDMA_PHASE0_QUANTUM__VALUE_MASK >> 590 SDMA_PHASE0_QUANTUM__VALUE__SHIFT); 591 unit = (SDMA_PHASE0_QUANTUM__UNIT_MASK >> 592 SDMA_PHASE0_QUANTUM__UNIT__SHIFT); 593 WARN_ONCE(1, 594 "clamping sdma_phase_quantum to %uK clock cycles\n", 595 value << unit); 596 } 597 phase_quantum = 598 value << SDMA_PHASE0_QUANTUM__VALUE__SHIFT | 599 unit << SDMA_PHASE0_QUANTUM__UNIT__SHIFT; 600 } 601 602 for_each_inst(i, inst_mask) { 603 f32_cntl = RREG32_SDMA(i, regSDMA_CNTL); 604 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_CNTL, 605 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 606 if (enable && amdgpu_sdma_phase_quantum) { 607 WREG32_SDMA(i, regSDMA_PHASE0_QUANTUM, phase_quantum); 608 WREG32_SDMA(i, regSDMA_PHASE1_QUANTUM, phase_quantum); 609 WREG32_SDMA(i, regSDMA_PHASE2_QUANTUM, phase_quantum); 610 } 611 WREG32_SDMA(i, regSDMA_CNTL, f32_cntl); 612 613 /* Extend page fault timeout to avoid interrupt storm */ 614 WREG32_SDMA(i, regSDMA_UTCL1_TIMEOUT, 0x00800080); 615 } 616 } 617 618 /** 619 * sdma_v4_4_2_inst_enable - stop the async dma engines 620 * 621 * @adev: amdgpu_device pointer 622 * @enable: enable/disable the DMA MEs. 623 * @inst_mask: mask of dma engine instances to be enabled 624 * 625 * Halt or unhalt the async dma engines. 626 */ 627 static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable, 628 uint32_t inst_mask) 629 { 630 u32 f32_cntl; 631 int i; 632 633 if (!enable) { 634 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask); 635 sdma_v4_4_2_inst_rlc_stop(adev, inst_mask); 636 if (adev->sdma.has_page_queue) 637 sdma_v4_4_2_inst_page_stop(adev, inst_mask); 638 639 /* SDMA FW needs to respond to FREEZE requests during reset. 640 * Keep it running during reset */ 641 if (!amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 642 return; 643 } 644 645 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 646 return; 647 648 for_each_inst(i, inst_mask) { 649 f32_cntl = RREG32_SDMA(i, regSDMA_F32_CNTL); 650 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1); 651 WREG32_SDMA(i, regSDMA_F32_CNTL, f32_cntl); 652 } 653 } 654 655 /* 656 * sdma_v4_4_2_rb_cntl - get parameters for rb_cntl 657 */ 658 static uint32_t sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 659 { 660 /* Set ring buffer size in dwords */ 661 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 662 663 barrier(); /* work around https://llvm.org/pr42576 */ 664 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 665 #ifdef __BIG_ENDIAN 666 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 667 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, 668 RPTR_WRITEBACK_SWAP_ENABLE, 1); 669 #endif 670 return rb_cntl; 671 } 672 673 /** 674 * sdma_v4_4_2_gfx_resume - setup and start the async dma engines 675 * 676 * @adev: amdgpu_device pointer 677 * @i: instance to resume 678 * @restore: used to restore wptr when restart 679 * 680 * Set up the gfx DMA ring buffers and enable them. 681 * Returns 0 for success, error for failure. 682 */ 683 static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i, bool restore) 684 { 685 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 686 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 687 u32 wb_offset; 688 u32 doorbell; 689 u32 doorbell_offset; 690 u64 wptr_gpu_addr; 691 u64 rwptr; 692 693 wb_offset = (ring->rptr_offs * 4); 694 695 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); 696 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 697 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 698 699 /* set the wb address whether it's enabled or not */ 700 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_HI, 701 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 702 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_LO, 703 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 704 705 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, 706 RPTR_WRITEBACK_ENABLE, 1); 707 708 WREG32_SDMA(i, regSDMA_GFX_RB_BASE, ring->gpu_addr >> 8); 709 WREG32_SDMA(i, regSDMA_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 710 711 if (!restore) 712 ring->wptr = 0; 713 714 /* before programing wptr to a less value, need set minor_ptr_update first */ 715 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 1); 716 717 /* For the guilty queue, set RPTR to the current wptr to skip bad commands, 718 * It is not a guilty queue, restore cache_rptr and continue execution. 719 */ 720 if (adev->sdma.instance[i].gfx_guilty) 721 rwptr = ring->wptr; 722 else 723 rwptr = ring->cached_rptr; 724 725 /* Initialize the ring buffer's read and write pointers */ 726 if (restore) { 727 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, lower_32_bits(rwptr << 2)); 728 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, upper_32_bits(rwptr << 2)); 729 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, lower_32_bits(rwptr << 2)); 730 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, upper_32_bits(rwptr << 2)); 731 } else { 732 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0); 733 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0); 734 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0); 735 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0); 736 } 737 738 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL); 739 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET); 740 741 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 742 ring->use_doorbell); 743 doorbell_offset = REG_SET_FIELD(doorbell_offset, 744 SDMA_GFX_DOORBELL_OFFSET, 745 OFFSET, ring->doorbell_index); 746 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell); 747 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset); 748 749 sdma_v4_4_2_ring_set_wptr(ring); 750 751 /* set minor_ptr_update to 0 after wptr programed */ 752 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 0); 753 754 /* setup the wptr shadow polling */ 755 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 756 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_LO, 757 lower_32_bits(wptr_gpu_addr)); 758 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_HI, 759 upper_32_bits(wptr_gpu_addr)); 760 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL); 761 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 762 SDMA_GFX_RB_WPTR_POLL_CNTL, 763 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 764 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 765 766 /* enable DMA RB */ 767 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 1); 768 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 769 770 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 771 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 1); 772 #ifdef __BIG_ENDIAN 773 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 774 #endif 775 /* enable DMA IBs */ 776 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 777 } 778 779 /** 780 * sdma_v4_4_2_page_resume - setup and start the async dma engines 781 * 782 * @adev: amdgpu_device pointer 783 * @i: instance to resume 784 * @restore: boolean to say restore needed or not 785 * 786 * Set up the page DMA ring buffers and enable them. 787 * Returns 0 for success, error for failure. 788 */ 789 static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i, bool restore) 790 { 791 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 792 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 793 u32 wb_offset; 794 u32 doorbell; 795 u32 doorbell_offset; 796 u64 wptr_gpu_addr; 797 u64 rwptr; 798 799 wb_offset = (ring->rptr_offs * 4); 800 801 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); 802 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 803 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 804 805 /* For the guilty queue, set RPTR to the current wptr to skip bad commands, 806 * It is not a guilty queue, restore cache_rptr and continue execution. 807 */ 808 if (adev->sdma.instance[i].page_guilty) 809 rwptr = ring->wptr; 810 else 811 rwptr = ring->cached_rptr; 812 813 /* Initialize the ring buffer's read and write pointers */ 814 if (restore) { 815 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, lower_32_bits(rwptr << 2)); 816 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, upper_32_bits(rwptr << 2)); 817 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, lower_32_bits(rwptr << 2)); 818 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, upper_32_bits(rwptr << 2)); 819 } else { 820 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, 0); 821 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, 0); 822 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, 0); 823 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, 0); 824 } 825 826 /* set the wb address whether it's enabled or not */ 827 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_HI, 828 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 829 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_LO, 830 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 831 832 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, 833 RPTR_WRITEBACK_ENABLE, 1); 834 835 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE, ring->gpu_addr >> 8); 836 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 837 838 if (!restore) 839 ring->wptr = 0; 840 841 /* before programing wptr to a less value, need set minor_ptr_update first */ 842 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 1); 843 844 doorbell = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL); 845 doorbell_offset = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET); 846 847 doorbell = REG_SET_FIELD(doorbell, SDMA_PAGE_DOORBELL, ENABLE, 848 ring->use_doorbell); 849 doorbell_offset = REG_SET_FIELD(doorbell_offset, 850 SDMA_PAGE_DOORBELL_OFFSET, 851 OFFSET, ring->doorbell_index); 852 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL, doorbell); 853 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET, doorbell_offset); 854 855 /* paging queue doorbell range is setup at sdma_v4_4_2_gfx_resume */ 856 sdma_v4_4_2_page_ring_set_wptr(ring); 857 858 /* set minor_ptr_update to 0 after wptr programed */ 859 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 0); 860 861 /* setup the wptr shadow polling */ 862 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 863 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_LO, 864 lower_32_bits(wptr_gpu_addr)); 865 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_HI, 866 upper_32_bits(wptr_gpu_addr)); 867 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL); 868 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 869 SDMA_PAGE_RB_WPTR_POLL_CNTL, 870 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 871 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 872 873 /* enable DMA RB */ 874 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, RB_ENABLE, 1); 875 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 876 877 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); 878 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_ENABLE, 1); 879 #ifdef __BIG_ENDIAN 880 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 881 #endif 882 /* enable DMA IBs */ 883 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); 884 } 885 886 static void sdma_v4_4_2_init_pg(struct amdgpu_device *adev) 887 { 888 889 } 890 891 /** 892 * sdma_v4_4_2_inst_rlc_resume - setup and start the async dma engines 893 * 894 * @adev: amdgpu_device pointer 895 * @inst_mask: mask of dma engine instances to be enabled 896 * 897 * Set up the compute DMA queues and enable them. 898 * Returns 0 for success, error for failure. 899 */ 900 static int sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device *adev, 901 uint32_t inst_mask) 902 { 903 sdma_v4_4_2_init_pg(adev); 904 905 return 0; 906 } 907 908 /** 909 * sdma_v4_4_2_inst_load_microcode - load the sDMA ME ucode 910 * 911 * @adev: amdgpu_device pointer 912 * @inst_mask: mask of dma engine instances to be enabled 913 * 914 * Loads the sDMA0/1 ucode. 915 * Returns 0 for success, -EINVAL if the ucode is not available. 916 */ 917 static int sdma_v4_4_2_inst_load_microcode(struct amdgpu_device *adev, 918 uint32_t inst_mask) 919 { 920 const struct sdma_firmware_header_v1_0 *hdr; 921 const __le32 *fw_data; 922 u32 fw_size; 923 int i, j; 924 925 /* halt the MEs */ 926 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 927 928 for_each_inst(i, inst_mask) { 929 if (!adev->sdma.instance[i].fw) 930 return -EINVAL; 931 932 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 933 amdgpu_ucode_print_sdma_hdr(&hdr->header); 934 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 935 936 fw_data = (const __le32 *) 937 (adev->sdma.instance[i].fw->data + 938 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 939 940 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 0); 941 942 for (j = 0; j < fw_size; j++) 943 WREG32_SDMA(i, regSDMA_UCODE_DATA, 944 le32_to_cpup(fw_data++)); 945 946 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 947 adev->sdma.instance[i].fw_version); 948 } 949 950 return 0; 951 } 952 953 /** 954 * sdma_v4_4_2_inst_start - setup and start the async dma engines 955 * 956 * @adev: amdgpu_device pointer 957 * @inst_mask: mask of dma engine instances to be enabled 958 * @restore: boolean to say restore needed or not 959 * 960 * Set up the DMA engines and enable them. 961 * Returns 0 for success, error for failure. 962 */ 963 static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev, 964 uint32_t inst_mask, bool restore) 965 { 966 struct amdgpu_ring *ring; 967 uint32_t tmp_mask; 968 int i, r = 0; 969 970 if (amdgpu_sriov_vf(adev)) { 971 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 972 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 973 } else { 974 /* bypass sdma microcode loading on Gopher */ 975 if (!restore && adev->firmware.load_type != AMDGPU_FW_LOAD_PSP && 976 adev->sdma.instance[0].fw) { 977 r = sdma_v4_4_2_inst_load_microcode(adev, inst_mask); 978 if (r) 979 return r; 980 } 981 982 /* unhalt the MEs */ 983 sdma_v4_4_2_inst_enable(adev, true, inst_mask); 984 /* enable sdma ring preemption */ 985 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask); 986 } 987 988 /* start the gfx rings and rlc compute queues */ 989 tmp_mask = inst_mask; 990 for_each_inst(i, tmp_mask) { 991 uint32_t temp; 992 993 WREG32_SDMA(i, regSDMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); 994 sdma_v4_4_2_gfx_resume(adev, i, restore); 995 if (adev->sdma.has_page_queue) 996 sdma_v4_4_2_page_resume(adev, i, restore); 997 998 /* set utc l1 enable flag always to 1 */ 999 temp = RREG32_SDMA(i, regSDMA_CNTL); 1000 temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1); 1001 WREG32_SDMA(i, regSDMA_CNTL, temp); 1002 1003 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) < IP_VERSION(4, 4, 5)) { 1004 /* enable context empty interrupt during initialization */ 1005 temp = REG_SET_FIELD(temp, SDMA_CNTL, CTXEMPTY_INT_ENABLE, 1); 1006 WREG32_SDMA(i, regSDMA_CNTL, temp); 1007 } 1008 if (!amdgpu_sriov_vf(adev)) { 1009 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1010 /* unhalt engine */ 1011 temp = RREG32_SDMA(i, regSDMA_F32_CNTL); 1012 temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0); 1013 WREG32_SDMA(i, regSDMA_F32_CNTL, temp); 1014 } 1015 } 1016 } 1017 1018 if (amdgpu_sriov_vf(adev)) { 1019 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask); 1020 sdma_v4_4_2_inst_enable(adev, true, inst_mask); 1021 } else { 1022 r = sdma_v4_4_2_inst_rlc_resume(adev, inst_mask); 1023 if (r) 1024 return r; 1025 } 1026 1027 tmp_mask = inst_mask; 1028 for_each_inst(i, tmp_mask) { 1029 ring = &adev->sdma.instance[i].ring; 1030 1031 r = amdgpu_ring_test_helper(ring); 1032 if (r) 1033 return r; 1034 1035 if (adev->sdma.has_page_queue) { 1036 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 1037 1038 r = amdgpu_ring_test_helper(page); 1039 if (r) 1040 return r; 1041 } 1042 } 1043 1044 return r; 1045 } 1046 1047 /** 1048 * sdma_v4_4_2_ring_test_ring - simple async dma engine test 1049 * 1050 * @ring: amdgpu_ring structure holding ring information 1051 * 1052 * Test the DMA engine by writing using it to write an 1053 * value to memory. 1054 * Returns 0 for success, error for failure. 1055 */ 1056 static int sdma_v4_4_2_ring_test_ring(struct amdgpu_ring *ring) 1057 { 1058 struct amdgpu_device *adev = ring->adev; 1059 unsigned i; 1060 unsigned index; 1061 int r; 1062 u32 tmp; 1063 u64 gpu_addr; 1064 1065 r = amdgpu_wb_get(adev, &index); 1066 if (r) 1067 return r; 1068 1069 gpu_addr = adev->wb.gpu_addr + (index * 4); 1070 tmp = 0xCAFEDEAD; 1071 adev->wb.wb[index] = cpu_to_le32(tmp); 1072 1073 r = amdgpu_ring_alloc(ring, 5); 1074 if (r) 1075 goto error_free_wb; 1076 1077 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1078 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1079 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1080 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1081 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1082 amdgpu_ring_write(ring, 0xDEADBEEF); 1083 amdgpu_ring_commit(ring); 1084 1085 for (i = 0; i < adev->usec_timeout; i++) { 1086 tmp = le32_to_cpu(adev->wb.wb[index]); 1087 if (tmp == 0xDEADBEEF) 1088 break; 1089 udelay(1); 1090 } 1091 1092 if (i >= adev->usec_timeout) 1093 r = -ETIMEDOUT; 1094 1095 error_free_wb: 1096 amdgpu_wb_free(adev, index); 1097 return r; 1098 } 1099 1100 /** 1101 * sdma_v4_4_2_ring_test_ib - test an IB on the DMA engine 1102 * 1103 * @ring: amdgpu_ring structure holding ring information 1104 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1105 * 1106 * Test a simple IB in the DMA ring. 1107 * Returns 0 on success, error on failure. 1108 */ 1109 static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1110 { 1111 struct amdgpu_device *adev = ring->adev; 1112 struct amdgpu_ib ib; 1113 struct dma_fence *f = NULL; 1114 unsigned index; 1115 long r; 1116 u32 tmp = 0; 1117 u64 gpu_addr; 1118 1119 r = amdgpu_wb_get(adev, &index); 1120 if (r) 1121 return r; 1122 1123 gpu_addr = adev->wb.gpu_addr + (index * 4); 1124 tmp = 0xCAFEDEAD; 1125 adev->wb.wb[index] = cpu_to_le32(tmp); 1126 memset(&ib, 0, sizeof(ib)); 1127 r = amdgpu_ib_get(adev, NULL, 256, 1128 AMDGPU_IB_POOL_DIRECT, &ib); 1129 if (r) 1130 goto err0; 1131 1132 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1133 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1134 ib.ptr[1] = lower_32_bits(gpu_addr); 1135 ib.ptr[2] = upper_32_bits(gpu_addr); 1136 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1137 ib.ptr[4] = 0xDEADBEEF; 1138 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1139 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1140 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1141 ib.length_dw = 8; 1142 1143 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1144 if (r) 1145 goto err1; 1146 1147 r = dma_fence_wait_timeout(f, false, timeout); 1148 if (r == 0) { 1149 r = -ETIMEDOUT; 1150 goto err1; 1151 } else if (r < 0) { 1152 goto err1; 1153 } 1154 tmp = le32_to_cpu(adev->wb.wb[index]); 1155 if (tmp == 0xDEADBEEF) 1156 r = 0; 1157 else 1158 r = -EINVAL; 1159 1160 err1: 1161 amdgpu_ib_free(&ib, NULL); 1162 dma_fence_put(f); 1163 err0: 1164 amdgpu_wb_free(adev, index); 1165 return r; 1166 } 1167 1168 1169 /** 1170 * sdma_v4_4_2_vm_copy_pte - update PTEs by copying them from the GART 1171 * 1172 * @ib: indirect buffer to fill with commands 1173 * @pe: addr of the page entry 1174 * @src: src addr to copy from 1175 * @count: number of page entries to update 1176 * 1177 * Update PTEs by copying them from the GART using sDMA. 1178 */ 1179 static void sdma_v4_4_2_vm_copy_pte(struct amdgpu_ib *ib, 1180 uint64_t pe, uint64_t src, 1181 unsigned count) 1182 { 1183 unsigned bytes = count * 8; 1184 1185 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1186 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1187 ib->ptr[ib->length_dw++] = bytes - 1; 1188 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1189 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1190 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1191 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1192 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1193 1194 } 1195 1196 /** 1197 * sdma_v4_4_2_vm_write_pte - update PTEs by writing them manually 1198 * 1199 * @ib: indirect buffer to fill with commands 1200 * @pe: addr of the page entry 1201 * @value: dst addr to write into pe 1202 * @count: number of page entries to update 1203 * @incr: increase next addr by incr bytes 1204 * 1205 * Update PTEs by writing them manually using sDMA. 1206 */ 1207 static void sdma_v4_4_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1208 uint64_t value, unsigned count, 1209 uint32_t incr) 1210 { 1211 unsigned ndw = count * 2; 1212 1213 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1214 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1215 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1216 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1217 ib->ptr[ib->length_dw++] = ndw - 1; 1218 for (; ndw > 0; ndw -= 2) { 1219 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1220 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1221 value += incr; 1222 } 1223 } 1224 1225 /** 1226 * sdma_v4_4_2_vm_set_pte_pde - update the page tables using sDMA 1227 * 1228 * @ib: indirect buffer to fill with commands 1229 * @pe: addr of the page entry 1230 * @addr: dst addr to write into pe 1231 * @count: number of page entries to update 1232 * @incr: increase next addr by incr bytes 1233 * @flags: access flags 1234 * 1235 * Update the page tables using sDMA. 1236 */ 1237 static void sdma_v4_4_2_vm_set_pte_pde(struct amdgpu_ib *ib, 1238 uint64_t pe, 1239 uint64_t addr, unsigned count, 1240 uint32_t incr, uint64_t flags) 1241 { 1242 /* for physically contiguous pages (vram) */ 1243 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1244 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1245 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1246 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1247 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1248 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1249 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1250 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1251 ib->ptr[ib->length_dw++] = 0; 1252 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1253 } 1254 1255 /** 1256 * sdma_v4_4_2_ring_pad_ib - pad the IB to the required number of dw 1257 * 1258 * @ring: amdgpu_ring structure holding ring information 1259 * @ib: indirect buffer to fill with padding 1260 */ 1261 static void sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1262 { 1263 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1264 u32 pad_count; 1265 int i; 1266 1267 pad_count = (-ib->length_dw) & 7; 1268 for (i = 0; i < pad_count; i++) 1269 if (sdma && sdma->burst_nop && (i == 0)) 1270 ib->ptr[ib->length_dw++] = 1271 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1272 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1273 else 1274 ib->ptr[ib->length_dw++] = 1275 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1276 } 1277 1278 1279 /** 1280 * sdma_v4_4_2_ring_emit_pipeline_sync - sync the pipeline 1281 * 1282 * @ring: amdgpu_ring pointer 1283 * 1284 * Make sure all previous operations are completed (CIK). 1285 */ 1286 static void sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1287 { 1288 uint32_t seq = ring->fence_drv.sync_seq; 1289 uint64_t addr = ring->fence_drv.gpu_addr; 1290 1291 /* wait for idle */ 1292 sdma_v4_4_2_wait_reg_mem(ring, 1, 0, 1293 addr & 0xfffffffc, 1294 upper_32_bits(addr) & 0xffffffff, 1295 seq, 0xffffffff, 4); 1296 } 1297 1298 1299 /** 1300 * sdma_v4_4_2_ring_emit_vm_flush - vm flush using sDMA 1301 * 1302 * @ring: amdgpu_ring pointer 1303 * @vmid: vmid number to use 1304 * @pd_addr: address 1305 * 1306 * Update the page table base and flush the VM TLB 1307 * using sDMA. 1308 */ 1309 static void sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring *ring, 1310 unsigned vmid, uint64_t pd_addr) 1311 { 1312 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1313 } 1314 1315 static void sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring *ring, 1316 uint32_t reg, uint32_t val) 1317 { 1318 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1319 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1320 amdgpu_ring_write(ring, reg); 1321 amdgpu_ring_write(ring, val); 1322 } 1323 1324 static void sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1325 uint32_t val, uint32_t mask) 1326 { 1327 sdma_v4_4_2_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1328 } 1329 1330 static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev) 1331 { 1332 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1333 case IP_VERSION(4, 4, 2): 1334 case IP_VERSION(4, 4, 5): 1335 return false; 1336 default: 1337 return false; 1338 } 1339 } 1340 1341 static const struct amdgpu_sdma_funcs sdma_v4_4_2_sdma_funcs = { 1342 .stop_kernel_queue = &sdma_v4_4_2_stop_queue, 1343 .start_kernel_queue = &sdma_v4_4_2_restore_queue, 1344 .soft_reset_kernel_queue = &sdma_v4_4_2_soft_reset_engine, 1345 }; 1346 1347 static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = { 1348 .copy_pte_num_dw = 7, 1349 .copy_pte = sdma_v4_4_2_vm_copy_pte, 1350 1351 .write_pte = sdma_v4_4_2_vm_write_pte, 1352 .set_pte_pde = sdma_v4_4_2_vm_set_pte_pde, 1353 }; 1354 1355 static int sdma_v4_4_2_early_init(struct amdgpu_ip_block *ip_block) 1356 { 1357 struct amdgpu_device *adev = ip_block->adev; 1358 int r; 1359 1360 switch (amdgpu_user_queue) { 1361 case -1: 1362 case 0: 1363 default: 1364 adev->sdma.no_user_submission = false; 1365 adev->sdma.disable_uq = true; 1366 break; 1367 case 2: 1368 adev->sdma.no_user_submission = true; 1369 adev->sdma.disable_uq = true; 1370 break; 1371 } 1372 1373 r = sdma_v4_4_2_init_microcode(adev); 1374 if (r) 1375 return r; 1376 1377 /* TODO: Page queue breaks driver reload under SRIOV */ 1378 if (sdma_v4_4_2_fw_support_paging_queue(adev)) 1379 adev->sdma.has_page_queue = true; 1380 1381 sdma_v4_4_2_set_ring_funcs(adev); 1382 amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v4_4_2_vm_pte_funcs); 1383 sdma_v4_4_2_set_irq_funcs(adev); 1384 sdma_v4_4_2_set_ras_funcs(adev); 1385 return 0; 1386 } 1387 1388 #if 0 1389 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, 1390 void *err_data, 1391 struct amdgpu_iv_entry *entry); 1392 #endif 1393 1394 static int sdma_v4_4_2_late_init(struct amdgpu_ip_block *ip_block) 1395 { 1396 struct amdgpu_device *adev = ip_block->adev; 1397 #if 0 1398 struct ras_ih_if ih_info = { 1399 .cb = sdma_v4_4_2_process_ras_data_cb, 1400 }; 1401 #endif 1402 if (!amdgpu_persistent_edc_harvesting_supported(adev)) 1403 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__SDMA); 1404 1405 /* The initialization is done in the late_init stage to ensure that the SMU 1406 * initialization and capability setup are completed before we check the SDMA 1407 * reset capability 1408 */ 1409 sdma_v4_4_2_update_reset_mask(adev); 1410 1411 return 0; 1412 } 1413 1414 static int sdma_v4_4_2_sw_init(struct amdgpu_ip_block *ip_block) 1415 { 1416 struct amdgpu_ring *ring; 1417 int r, i; 1418 struct amdgpu_device *adev = ip_block->adev; 1419 u32 aid_id; 1420 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); 1421 uint32_t *ptr; 1422 1423 /* SDMA trap event */ 1424 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1425 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1426 SDMA0_4_0__SRCID__SDMA_TRAP, 1427 &adev->sdma.trap_irq); 1428 if (r) 1429 return r; 1430 } 1431 1432 /* SDMA SRAM ECC event */ 1433 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1434 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1435 SDMA0_4_0__SRCID__SDMA_SRAM_ECC, 1436 &adev->sdma.ecc_irq); 1437 if (r) 1438 return r; 1439 } 1440 1441 /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/ 1442 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1443 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1444 SDMA0_4_0__SRCID__SDMA_VM_HOLE, 1445 &adev->sdma.vm_hole_irq); 1446 if (r) 1447 return r; 1448 1449 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1450 SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID, 1451 &adev->sdma.doorbell_invalid_irq); 1452 if (r) 1453 return r; 1454 1455 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1456 SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT, 1457 &adev->sdma.pool_timeout_irq); 1458 if (r) 1459 return r; 1460 1461 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1462 SDMA0_4_0__SRCID__SDMA_SRBMWRITE, 1463 &adev->sdma.srbm_write_irq); 1464 if (r) 1465 return r; 1466 1467 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1468 SDMA0_4_0__SRCID__SDMA_CTXEMPTY, 1469 &adev->sdma.ctxt_empty_irq); 1470 if (r) 1471 return r; 1472 } 1473 1474 for (i = 0; i < adev->sdma.num_instances; i++) { 1475 mutex_init(&adev->sdma.instance[i].engine_reset_mutex); 1476 /* Initialize guilty flags for GFX and PAGE queues */ 1477 adev->sdma.instance[i].gfx_guilty = false; 1478 adev->sdma.instance[i].page_guilty = false; 1479 adev->sdma.instance[i].funcs = &sdma_v4_4_2_sdma_funcs; 1480 1481 ring = &adev->sdma.instance[i].ring; 1482 ring->ring_obj = NULL; 1483 ring->use_doorbell = true; 1484 aid_id = adev->sdma.instance[i].aid_id; 1485 1486 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1487 ring->use_doorbell?"true":"false"); 1488 1489 /* doorbell size is 2 dwords, get DWORD offset */ 1490 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1491 ring->vm_hub = AMDGPU_MMHUB0(aid_id); 1492 ring->no_user_submission = adev->sdma.no_user_submission; 1493 1494 sprintf(ring->name, "sdma%d.%d", aid_id, 1495 i % adev->sdma.num_inst_per_aid); 1496 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1497 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1498 AMDGPU_RING_PRIO_DEFAULT, NULL); 1499 if (r) 1500 return r; 1501 1502 if (adev->sdma.has_page_queue) { 1503 ring = &adev->sdma.instance[i].page; 1504 ring->ring_obj = NULL; 1505 ring->use_doorbell = true; 1506 1507 /* doorbell index of page queue is assigned right after 1508 * gfx queue on the same instance 1509 */ 1510 ring->doorbell_index = 1511 (adev->doorbell_index.sdma_engine[i] + 1) << 1; 1512 ring->vm_hub = AMDGPU_MMHUB0(aid_id); 1513 1514 sprintf(ring->name, "page%d.%d", aid_id, 1515 i % adev->sdma.num_inst_per_aid); 1516 r = amdgpu_ring_init(adev, ring, 1024, 1517 &adev->sdma.trap_irq, 1518 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1519 AMDGPU_RING_PRIO_DEFAULT, NULL); 1520 if (r) 1521 return r; 1522 } 1523 } 1524 1525 adev->sdma.supported_reset = 1526 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); 1527 1528 if (amdgpu_sdma_ras_sw_init(adev)) { 1529 dev_err(adev->dev, "fail to initialize sdma ras block\n"); 1530 return -EINVAL; 1531 } 1532 1533 /* Allocate memory for SDMA IP Dump buffer */ 1534 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); 1535 if (ptr) 1536 adev->sdma.ip_dump = ptr; 1537 else 1538 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n"); 1539 1540 r = amdgpu_sdma_sysfs_reset_mask_init(adev); 1541 if (r) 1542 return r; 1543 1544 return r; 1545 } 1546 1547 static int sdma_v4_4_2_sw_fini(struct amdgpu_ip_block *ip_block) 1548 { 1549 struct amdgpu_device *adev = ip_block->adev; 1550 int i; 1551 1552 for (i = 0; i < adev->sdma.num_instances; i++) { 1553 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1554 if (adev->sdma.has_page_queue) 1555 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1556 } 1557 1558 amdgpu_sdma_sysfs_reset_mask_fini(adev); 1559 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) || 1560 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 4) || 1561 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) 1562 amdgpu_sdma_destroy_inst_ctx(adev, true); 1563 else 1564 amdgpu_sdma_destroy_inst_ctx(adev, false); 1565 1566 kfree(adev->sdma.ip_dump); 1567 1568 return 0; 1569 } 1570 1571 static int sdma_v4_4_2_hw_init(struct amdgpu_ip_block *ip_block) 1572 { 1573 int r; 1574 struct amdgpu_device *adev = ip_block->adev; 1575 uint32_t inst_mask; 1576 1577 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1578 if (!amdgpu_sriov_vf(adev)) 1579 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask); 1580 1581 r = sdma_v4_4_2_inst_start(adev, inst_mask, false); 1582 if (r) 1583 return r; 1584 sdma_v4_4_2_set_buffer_funcs(adev); 1585 1586 return 0; 1587 } 1588 1589 static int sdma_v4_4_2_hw_fini(struct amdgpu_ip_block *ip_block) 1590 { 1591 struct amdgpu_device *adev = ip_block->adev; 1592 uint32_t inst_mask; 1593 int i; 1594 1595 if (amdgpu_sriov_vf(adev)) 1596 return 0; 1597 1598 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1599 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 1600 for (i = 0; i < adev->sdma.num_instances; i++) { 1601 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 1602 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1603 } 1604 } 1605 1606 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 1607 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 1608 1609 return 0; 1610 } 1611 1612 static int sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1613 enum amd_clockgating_state state); 1614 1615 static int sdma_v4_4_2_suspend(struct amdgpu_ip_block *ip_block) 1616 { 1617 struct amdgpu_device *adev = ip_block->adev; 1618 1619 if (amdgpu_in_reset(adev)) 1620 sdma_v4_4_2_set_clockgating_state(ip_block, AMD_CG_STATE_UNGATE); 1621 1622 return sdma_v4_4_2_hw_fini(ip_block); 1623 } 1624 1625 static int sdma_v4_4_2_resume(struct amdgpu_ip_block *ip_block) 1626 { 1627 return sdma_v4_4_2_hw_init(ip_block); 1628 } 1629 1630 static bool sdma_v4_4_2_is_idle(struct amdgpu_ip_block *ip_block) 1631 { 1632 struct amdgpu_device *adev = ip_block->adev; 1633 u32 i; 1634 1635 for (i = 0; i < adev->sdma.num_instances; i++) { 1636 u32 tmp = RREG32_SDMA(i, regSDMA_STATUS_REG); 1637 1638 if (!(tmp & SDMA_STATUS_REG__IDLE_MASK)) 1639 return false; 1640 } 1641 1642 return true; 1643 } 1644 1645 static int sdma_v4_4_2_wait_for_idle(struct amdgpu_ip_block *ip_block) 1646 { 1647 unsigned i, j; 1648 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; 1649 struct amdgpu_device *adev = ip_block->adev; 1650 1651 for (i = 0; i < adev->usec_timeout; i++) { 1652 for (j = 0; j < adev->sdma.num_instances; j++) { 1653 sdma[j] = RREG32_SDMA(j, regSDMA_STATUS_REG); 1654 if (!(sdma[j] & SDMA_STATUS_REG__IDLE_MASK)) 1655 break; 1656 } 1657 if (j == adev->sdma.num_instances) 1658 return 0; 1659 udelay(1); 1660 } 1661 return -ETIMEDOUT; 1662 } 1663 1664 static int sdma_v4_4_2_soft_reset(struct amdgpu_ip_block *ip_block) 1665 { 1666 /* todo */ 1667 1668 return 0; 1669 } 1670 1671 static bool sdma_v4_4_2_is_queue_selected(struct amdgpu_device *adev, uint32_t instance_id, bool is_page_queue) 1672 { 1673 uint32_t reg_offset = is_page_queue ? regSDMA_PAGE_CONTEXT_STATUS : regSDMA_GFX_CONTEXT_STATUS; 1674 uint32_t context_status = RREG32(sdma_v4_4_2_get_reg_offset(adev, instance_id, reg_offset)); 1675 1676 /* Check if the SELECTED bit is set */ 1677 return (context_status & SDMA_GFX_CONTEXT_STATUS__SELECTED_MASK) != 0; 1678 } 1679 1680 static int sdma_v4_4_2_reset_queue(struct amdgpu_ring *ring, 1681 unsigned int vmid, 1682 struct amdgpu_fence *timedout_fence) 1683 { 1684 struct amdgpu_device *adev = ring->adev; 1685 u32 id = ring->me; 1686 int r; 1687 1688 amdgpu_amdkfd_suspend(adev, true); 1689 r = amdgpu_sdma_reset_engine(adev, id, false); 1690 amdgpu_amdkfd_resume(adev, true); 1691 return r; 1692 } 1693 1694 static int sdma_v4_4_2_stop_queue(struct amdgpu_ring *ring) 1695 { 1696 struct amdgpu_device *adev = ring->adev; 1697 u32 instance_id = ring->me; 1698 u32 inst_mask; 1699 uint64_t rptr; 1700 1701 if (amdgpu_sriov_vf(adev)) 1702 return -EINVAL; 1703 1704 /* Check if this queue is the guilty one */ 1705 adev->sdma.instance[instance_id].gfx_guilty = 1706 sdma_v4_4_2_is_queue_selected(adev, instance_id, false); 1707 if (adev->sdma.has_page_queue) 1708 adev->sdma.instance[instance_id].page_guilty = 1709 sdma_v4_4_2_is_queue_selected(adev, instance_id, true); 1710 1711 /* Cache the rptr before reset, after the reset, 1712 * all of the registers will be reset to 0 1713 */ 1714 rptr = amdgpu_ring_get_rptr(ring); 1715 ring->cached_rptr = rptr; 1716 /* Cache the rptr for the page queue if it exists */ 1717 if (adev->sdma.has_page_queue) { 1718 struct amdgpu_ring *page_ring = &adev->sdma.instance[instance_id].page; 1719 rptr = amdgpu_ring_get_rptr(page_ring); 1720 page_ring->cached_rptr = rptr; 1721 } 1722 1723 /* stop queue */ 1724 inst_mask = 1 << ring->me; 1725 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask); 1726 if (adev->sdma.has_page_queue) 1727 sdma_v4_4_2_inst_page_stop(adev, inst_mask); 1728 1729 return 0; 1730 } 1731 1732 static int sdma_v4_4_2_restore_queue(struct amdgpu_ring *ring) 1733 { 1734 struct amdgpu_device *adev = ring->adev; 1735 u32 inst_mask; 1736 int i, r; 1737 1738 inst_mask = 1 << ring->me; 1739 udelay(50); 1740 1741 for (i = 0; i < adev->usec_timeout; i++) { 1742 if (!REG_GET_FIELD(RREG32_SDMA(ring->me, regSDMA_F32_CNTL), SDMA_F32_CNTL, HALT)) 1743 break; 1744 udelay(1); 1745 } 1746 1747 if (i == adev->usec_timeout) { 1748 dev_err(adev->dev, "timed out waiting for SDMA%d unhalt after reset\n", 1749 ring->me); 1750 return -ETIMEDOUT; 1751 } 1752 1753 r = sdma_v4_4_2_inst_start(adev, inst_mask, true); 1754 1755 return r; 1756 } 1757 1758 static int sdma_v4_4_2_soft_reset_engine(struct amdgpu_device *adev, 1759 u32 instance_id) 1760 { 1761 /* For SDMA 4.x, use the existing DPM interface for backward compatibility 1762 * we need to convert the logical instance ID to physical instance ID before reset. 1763 */ 1764 return amdgpu_dpm_reset_sdma(adev, 1 << GET_INST(SDMA0, instance_id)); 1765 } 1766 1767 static int sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device *adev, 1768 struct amdgpu_irq_src *source, 1769 unsigned type, 1770 enum amdgpu_interrupt_state state) 1771 { 1772 u32 sdma_cntl; 1773 1774 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); 1775 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE, 1776 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1777 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); 1778 1779 return 0; 1780 } 1781 1782 static int sdma_v4_4_2_process_trap_irq(struct amdgpu_device *adev, 1783 struct amdgpu_irq_src *source, 1784 struct amdgpu_iv_entry *entry) 1785 { 1786 uint32_t instance, i; 1787 1788 DRM_DEBUG("IH: SDMA trap\n"); 1789 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1790 1791 /* Client id gives the SDMA instance in AID. To know the exact SDMA 1792 * instance, interrupt entry gives the node id which corresponds to the AID instance. 1793 * Match node id with the AID id associated with the SDMA instance. */ 1794 for (i = instance; i < adev->sdma.num_instances; 1795 i += adev->sdma.num_inst_per_aid) { 1796 if (adev->sdma.instance[i].aid_id == 1797 node_id_to_phys_map[entry->node_id]) 1798 break; 1799 } 1800 1801 if (i >= adev->sdma.num_instances) { 1802 dev_WARN_ONCE( 1803 adev->dev, 1, 1804 "Couldn't find the right sdma instance in trap handler"); 1805 return 0; 1806 } 1807 1808 switch (entry->ring_id) { 1809 case 0: 1810 amdgpu_fence_process(&adev->sdma.instance[i].ring); 1811 break; 1812 case 1: 1813 amdgpu_fence_process(&adev->sdma.instance[i].page); 1814 break; 1815 default: 1816 break; 1817 } 1818 return 0; 1819 } 1820 1821 #if 0 1822 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, 1823 void *err_data, 1824 struct amdgpu_iv_entry *entry) 1825 { 1826 int instance; 1827 1828 /* When “Full RAS” is enabled, the per-IP interrupt sources should 1829 * be disabled and the driver should only look for the aggregated 1830 * interrupt via sync flood 1831 */ 1832 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) 1833 goto out; 1834 1835 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1836 if (instance < 0) 1837 goto out; 1838 1839 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry); 1840 1841 out: 1842 return AMDGPU_RAS_SUCCESS; 1843 } 1844 #endif 1845 1846 static int sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device *adev, 1847 struct amdgpu_irq_src *source, 1848 struct amdgpu_iv_entry *entry) 1849 { 1850 int instance; 1851 1852 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1853 1854 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1855 if (instance < 0) 1856 return 0; 1857 1858 switch (entry->ring_id) { 1859 case 0: 1860 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 1861 break; 1862 } 1863 return 0; 1864 } 1865 1866 static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev, 1867 struct amdgpu_irq_src *source, 1868 unsigned type, 1869 enum amdgpu_interrupt_state state) 1870 { 1871 u32 sdma_cntl; 1872 1873 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); 1874 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, DRAM_ECC_INT_ENABLE, 1875 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1876 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); 1877 1878 return 0; 1879 } 1880 1881 static int sdma_v4_4_2_print_iv_entry(struct amdgpu_device *adev, 1882 struct amdgpu_iv_entry *entry) 1883 { 1884 int instance; 1885 struct amdgpu_task_info *task_info; 1886 u64 addr; 1887 1888 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1889 if (instance < 0 || instance >= adev->sdma.num_instances) { 1890 dev_err(adev->dev, "sdma instance invalid %d\n", instance); 1891 return -EINVAL; 1892 } 1893 1894 addr = (u64)entry->src_data[0] << 12; 1895 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 1896 1897 dev_dbg_ratelimited(adev->dev, 1898 "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u pasid:%u\n", 1899 instance, addr, entry->src_id, entry->ring_id, entry->vmid, 1900 entry->pasid); 1901 1902 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 1903 if (task_info) { 1904 dev_dbg_ratelimited(adev->dev, " for process %s pid %d thread %s pid %d\n", 1905 task_info->process_name, task_info->tgid, 1906 task_info->task.comm, task_info->task.pid); 1907 amdgpu_vm_put_task_info(task_info); 1908 } 1909 1910 return 0; 1911 } 1912 1913 static int sdma_v4_4_2_process_vm_hole_irq(struct amdgpu_device *adev, 1914 struct amdgpu_irq_src *source, 1915 struct amdgpu_iv_entry *entry) 1916 { 1917 dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n"); 1918 sdma_v4_4_2_print_iv_entry(adev, entry); 1919 return 0; 1920 } 1921 1922 static int sdma_v4_4_2_process_doorbell_invalid_irq(struct amdgpu_device *adev, 1923 struct amdgpu_irq_src *source, 1924 struct amdgpu_iv_entry *entry) 1925 { 1926 1927 dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n"); 1928 sdma_v4_4_2_print_iv_entry(adev, entry); 1929 return 0; 1930 } 1931 1932 static int sdma_v4_4_2_process_pool_timeout_irq(struct amdgpu_device *adev, 1933 struct amdgpu_irq_src *source, 1934 struct amdgpu_iv_entry *entry) 1935 { 1936 dev_dbg_ratelimited(adev->dev, 1937 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n"); 1938 sdma_v4_4_2_print_iv_entry(adev, entry); 1939 return 0; 1940 } 1941 1942 static int sdma_v4_4_2_process_srbm_write_irq(struct amdgpu_device *adev, 1943 struct amdgpu_irq_src *source, 1944 struct amdgpu_iv_entry *entry) 1945 { 1946 dev_dbg_ratelimited(adev->dev, 1947 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n"); 1948 sdma_v4_4_2_print_iv_entry(adev, entry); 1949 return 0; 1950 } 1951 1952 static int sdma_v4_4_2_process_ctxt_empty_irq(struct amdgpu_device *adev, 1953 struct amdgpu_irq_src *source, 1954 struct amdgpu_iv_entry *entry) 1955 { 1956 /* There is nothing useful to be done here, only kept for debug */ 1957 dev_dbg_ratelimited(adev->dev, "SDMA context empty interrupt"); 1958 sdma_v4_4_2_print_iv_entry(adev, entry); 1959 return 0; 1960 } 1961 1962 static void sdma_v4_4_2_inst_update_medium_grain_light_sleep( 1963 struct amdgpu_device *adev, bool enable, uint32_t inst_mask) 1964 { 1965 uint32_t data, def; 1966 int i; 1967 1968 /* leave as default if it is not driver controlled */ 1969 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) 1970 return; 1971 1972 if (enable) { 1973 for_each_inst(i, inst_mask) { 1974 /* 1-not override: enable sdma mem light sleep */ 1975 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL); 1976 data |= SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1977 if (def != data) 1978 WREG32_SDMA(i, regSDMA_POWER_CNTL, data); 1979 } 1980 } else { 1981 for_each_inst(i, inst_mask) { 1982 /* 0-override:disable sdma mem light sleep */ 1983 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL); 1984 data &= ~SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1985 if (def != data) 1986 WREG32_SDMA(i, regSDMA_POWER_CNTL, data); 1987 } 1988 } 1989 } 1990 1991 static void sdma_v4_4_2_inst_update_medium_grain_clock_gating( 1992 struct amdgpu_device *adev, bool enable, uint32_t inst_mask) 1993 { 1994 uint32_t data, def; 1995 int i; 1996 1997 /* leave as default if it is not driver controlled */ 1998 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) 1999 return; 2000 2001 if (enable) { 2002 for_each_inst(i, inst_mask) { 2003 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL); 2004 data &= ~(SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2005 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2006 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2007 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2008 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2009 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2010 if (def != data) 2011 WREG32_SDMA(i, regSDMA_CLK_CTRL, data); 2012 } 2013 } else { 2014 for_each_inst(i, inst_mask) { 2015 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL); 2016 data |= (SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2017 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2018 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2019 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2020 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2021 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2022 if (def != data) 2023 WREG32_SDMA(i, regSDMA_CLK_CTRL, data); 2024 } 2025 } 2026 } 2027 2028 static int sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2029 enum amd_clockgating_state state) 2030 { 2031 struct amdgpu_device *adev = ip_block->adev; 2032 uint32_t inst_mask; 2033 2034 if (amdgpu_sriov_vf(adev)) 2035 return 0; 2036 2037 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 2038 2039 sdma_v4_4_2_inst_update_medium_grain_clock_gating( 2040 adev, state == AMD_CG_STATE_GATE, inst_mask); 2041 sdma_v4_4_2_inst_update_medium_grain_light_sleep( 2042 adev, state == AMD_CG_STATE_GATE, inst_mask); 2043 return 0; 2044 } 2045 2046 static int sdma_v4_4_2_set_powergating_state(struct amdgpu_ip_block *ip_block, 2047 enum amd_powergating_state state) 2048 { 2049 return 0; 2050 } 2051 2052 static void sdma_v4_4_2_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 2053 { 2054 struct amdgpu_device *adev = ip_block->adev; 2055 int data; 2056 2057 if (amdgpu_sriov_vf(adev)) 2058 *flags = 0; 2059 2060 /* AMD_CG_SUPPORT_SDMA_MGCG */ 2061 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL)); 2062 if (!(data & SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK)) 2063 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 2064 2065 /* AMD_CG_SUPPORT_SDMA_LS */ 2066 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL)); 2067 if (data & SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 2068 *flags |= AMD_CG_SUPPORT_SDMA_LS; 2069 } 2070 2071 static void sdma_v4_4_2_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 2072 { 2073 struct amdgpu_device *adev = ip_block->adev; 2074 int i, j; 2075 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); 2076 uint32_t instance_offset; 2077 2078 if (!adev->sdma.ip_dump) 2079 return; 2080 2081 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances); 2082 for (i = 0; i < adev->sdma.num_instances; i++) { 2083 instance_offset = i * reg_count; 2084 drm_printf(p, "\nInstance:%d\n", i); 2085 2086 for (j = 0; j < reg_count; j++) 2087 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_4_4_2[j].reg_name, 2088 adev->sdma.ip_dump[instance_offset + j]); 2089 } 2090 } 2091 2092 static void sdma_v4_4_2_dump_ip_state(struct amdgpu_ip_block *ip_block) 2093 { 2094 struct amdgpu_device *adev = ip_block->adev; 2095 int i, j; 2096 uint32_t instance_offset; 2097 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); 2098 2099 if (!adev->sdma.ip_dump) 2100 return; 2101 2102 for (i = 0; i < adev->sdma.num_instances; i++) { 2103 instance_offset = i * reg_count; 2104 for (j = 0; j < reg_count; j++) 2105 adev->sdma.ip_dump[instance_offset + j] = 2106 RREG32(sdma_v4_4_2_get_reg_offset(adev, i, 2107 sdma_reg_list_4_4_2[j].reg_offset)); 2108 } 2109 } 2110 2111 const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = { 2112 .name = "sdma_v4_4_2", 2113 .early_init = sdma_v4_4_2_early_init, 2114 .late_init = sdma_v4_4_2_late_init, 2115 .sw_init = sdma_v4_4_2_sw_init, 2116 .sw_fini = sdma_v4_4_2_sw_fini, 2117 .hw_init = sdma_v4_4_2_hw_init, 2118 .hw_fini = sdma_v4_4_2_hw_fini, 2119 .suspend = sdma_v4_4_2_suspend, 2120 .resume = sdma_v4_4_2_resume, 2121 .is_idle = sdma_v4_4_2_is_idle, 2122 .wait_for_idle = sdma_v4_4_2_wait_for_idle, 2123 .soft_reset = sdma_v4_4_2_soft_reset, 2124 .set_clockgating_state = sdma_v4_4_2_set_clockgating_state, 2125 .set_powergating_state = sdma_v4_4_2_set_powergating_state, 2126 .get_clockgating_state = sdma_v4_4_2_get_clockgating_state, 2127 .dump_ip_state = sdma_v4_4_2_dump_ip_state, 2128 .print_ip_state = sdma_v4_4_2_print_ip_state, 2129 }; 2130 2131 static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = { 2132 .type = AMDGPU_RING_TYPE_SDMA, 2133 .align_mask = 0xff, 2134 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2135 .support_64bit_ptrs = true, 2136 .get_rptr = sdma_v4_4_2_ring_get_rptr, 2137 .get_wptr = sdma_v4_4_2_ring_get_wptr, 2138 .set_wptr = sdma_v4_4_2_ring_set_wptr, 2139 .emit_frame_size = 2140 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */ 2141 3 + /* hdp invalidate */ 2142 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */ 2143 /* sdma_v4_4_2_ring_emit_vm_flush */ 2144 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2145 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2146 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */ 2147 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */ 2148 .emit_ib = sdma_v4_4_2_ring_emit_ib, 2149 .emit_fence = sdma_v4_4_2_ring_emit_fence, 2150 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync, 2151 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush, 2152 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush, 2153 .test_ring = sdma_v4_4_2_ring_test_ring, 2154 .test_ib = sdma_v4_4_2_ring_test_ib, 2155 .insert_nop = sdma_v4_4_2_ring_insert_nop, 2156 .pad_ib = sdma_v4_4_2_ring_pad_ib, 2157 .emit_wreg = sdma_v4_4_2_ring_emit_wreg, 2158 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, 2159 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2160 .reset = sdma_v4_4_2_reset_queue, 2161 }; 2162 2163 static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = { 2164 .type = AMDGPU_RING_TYPE_SDMA, 2165 .align_mask = 0xff, 2166 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2167 .support_64bit_ptrs = true, 2168 .get_rptr = sdma_v4_4_2_ring_get_rptr, 2169 .get_wptr = sdma_v4_4_2_page_ring_get_wptr, 2170 .set_wptr = sdma_v4_4_2_page_ring_set_wptr, 2171 .emit_frame_size = 2172 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */ 2173 3 + /* hdp invalidate */ 2174 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */ 2175 /* sdma_v4_4_2_ring_emit_vm_flush */ 2176 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2177 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2178 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */ 2179 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */ 2180 .emit_ib = sdma_v4_4_2_ring_emit_ib, 2181 .emit_fence = sdma_v4_4_2_ring_emit_fence, 2182 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync, 2183 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush, 2184 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush, 2185 .test_ring = sdma_v4_4_2_ring_test_ring, 2186 .test_ib = sdma_v4_4_2_ring_test_ib, 2187 .insert_nop = sdma_v4_4_2_ring_insert_nop, 2188 .pad_ib = sdma_v4_4_2_ring_pad_ib, 2189 .emit_wreg = sdma_v4_4_2_ring_emit_wreg, 2190 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, 2191 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2192 .reset = sdma_v4_4_2_reset_queue, 2193 }; 2194 2195 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev) 2196 { 2197 int i, dev_inst; 2198 2199 for (i = 0; i < adev->sdma.num_instances; i++) { 2200 adev->sdma.instance[i].ring.funcs = &sdma_v4_4_2_ring_funcs; 2201 adev->sdma.instance[i].ring.me = i; 2202 if (adev->sdma.has_page_queue) { 2203 adev->sdma.instance[i].page.funcs = 2204 &sdma_v4_4_2_page_ring_funcs; 2205 adev->sdma.instance[i].page.me = i; 2206 } 2207 2208 dev_inst = GET_INST(SDMA0, i); 2209 /* AID to which SDMA belongs depends on physical instance */ 2210 adev->sdma.instance[i].aid_id = 2211 dev_inst / adev->sdma.num_inst_per_aid; 2212 } 2213 } 2214 2215 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_trap_irq_funcs = { 2216 .set = sdma_v4_4_2_set_trap_irq_state, 2217 .process = sdma_v4_4_2_process_trap_irq, 2218 }; 2219 2220 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_illegal_inst_irq_funcs = { 2221 .process = sdma_v4_4_2_process_illegal_inst_irq, 2222 }; 2223 2224 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ecc_irq_funcs = { 2225 .set = sdma_v4_4_2_set_ecc_irq_state, 2226 .process = amdgpu_sdma_process_ecc_irq, 2227 }; 2228 2229 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_vm_hole_irq_funcs = { 2230 .process = sdma_v4_4_2_process_vm_hole_irq, 2231 }; 2232 2233 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_doorbell_invalid_irq_funcs = { 2234 .process = sdma_v4_4_2_process_doorbell_invalid_irq, 2235 }; 2236 2237 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_pool_timeout_irq_funcs = { 2238 .process = sdma_v4_4_2_process_pool_timeout_irq, 2239 }; 2240 2241 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_srbm_write_irq_funcs = { 2242 .process = sdma_v4_4_2_process_srbm_write_irq, 2243 }; 2244 2245 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ctxt_empty_irq_funcs = { 2246 .process = sdma_v4_4_2_process_ctxt_empty_irq, 2247 }; 2248 2249 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev) 2250 { 2251 adev->sdma.trap_irq.num_types = adev->sdma.num_instances; 2252 adev->sdma.ecc_irq.num_types = adev->sdma.num_instances; 2253 adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances; 2254 adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances; 2255 adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances; 2256 adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances; 2257 adev->sdma.ctxt_empty_irq.num_types = adev->sdma.num_instances; 2258 2259 adev->sdma.trap_irq.funcs = &sdma_v4_4_2_trap_irq_funcs; 2260 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_4_2_illegal_inst_irq_funcs; 2261 adev->sdma.ecc_irq.funcs = &sdma_v4_4_2_ecc_irq_funcs; 2262 adev->sdma.vm_hole_irq.funcs = &sdma_v4_4_2_vm_hole_irq_funcs; 2263 adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_4_2_doorbell_invalid_irq_funcs; 2264 adev->sdma.pool_timeout_irq.funcs = &sdma_v4_4_2_pool_timeout_irq_funcs; 2265 adev->sdma.srbm_write_irq.funcs = &sdma_v4_4_2_srbm_write_irq_funcs; 2266 adev->sdma.ctxt_empty_irq.funcs = &sdma_v4_4_2_ctxt_empty_irq_funcs; 2267 } 2268 2269 /** 2270 * sdma_v4_4_2_emit_copy_buffer - copy buffer using the sDMA engine 2271 * 2272 * @ib: indirect buffer to copy to 2273 * @src_offset: src GPU address 2274 * @dst_offset: dst GPU address 2275 * @byte_count: number of bytes to xfer 2276 * @copy_flags: copy flags for the buffers 2277 * 2278 * Copy GPU buffers using the DMA engine. 2279 * Used by the amdgpu ttm implementation to move pages if 2280 * registered as the asic copy callback. 2281 */ 2282 static void sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib *ib, 2283 uint64_t src_offset, 2284 uint64_t dst_offset, 2285 uint32_t byte_count, 2286 uint32_t copy_flags) 2287 { 2288 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 2289 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 2290 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0); 2291 ib->ptr[ib->length_dw++] = byte_count - 1; 2292 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 2293 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 2294 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 2295 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2296 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2297 } 2298 2299 /** 2300 * sdma_v4_4_2_emit_fill_buffer - fill buffer using the sDMA engine 2301 * 2302 * @ib: indirect buffer to copy to 2303 * @src_data: value to write to buffer 2304 * @dst_offset: dst GPU address 2305 * @byte_count: number of bytes to xfer 2306 * 2307 * Fill GPU buffers using the DMA engine. 2308 */ 2309 static void sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib *ib, 2310 uint32_t src_data, 2311 uint64_t dst_offset, 2312 uint32_t byte_count) 2313 { 2314 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2315 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2316 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2317 ib->ptr[ib->length_dw++] = src_data; 2318 ib->ptr[ib->length_dw++] = byte_count - 1; 2319 } 2320 2321 static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = { 2322 .copy_max_bytes = 1 << 30, 2323 .copy_num_dw = 7, 2324 .emit_copy_buffer = sdma_v4_4_2_emit_copy_buffer, 2325 2326 .fill_max_bytes = 1 << 30, 2327 .fill_num_dw = 5, 2328 .emit_fill_buffer = sdma_v4_4_2_emit_fill_buffer, 2329 }; 2330 2331 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev) 2332 { 2333 amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v4_4_2_buffer_funcs); 2334 } 2335 2336 /** 2337 * sdma_v4_4_2_update_reset_mask - update reset mask for SDMA 2338 * @adev: Pointer to the AMDGPU device structure 2339 * 2340 * This function update reset mask for SDMA and sets the supported 2341 * reset types based on the IP version and firmware versions. 2342 * 2343 */ 2344 static void sdma_v4_4_2_update_reset_mask(struct amdgpu_device *adev) 2345 { 2346 /* per queue reset not supported for SRIOV */ 2347 if (amdgpu_sriov_vf(adev)) 2348 return; 2349 2350 /* 2351 * the user queue relies on MEC fw and pmfw when the sdma queue do reset. 2352 * it needs to check both of them at here to skip old mec and pmfw. 2353 */ 2354 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2355 case IP_VERSION(9, 4, 3): 2356 case IP_VERSION(9, 4, 4): 2357 if ((adev->gfx.mec_fw_version >= 0xb0) && 2358 amdgpu_dpm_reset_sdma_is_supported(adev) && 2359 !adev->debug_disable_gpu_ring_reset) 2360 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 2361 break; 2362 case IP_VERSION(9, 5, 0): 2363 if ((adev->gfx.mec_fw_version >= 0xf) && 2364 amdgpu_dpm_reset_sdma_is_supported(adev) && 2365 !adev->debug_disable_gpu_ring_reset) 2366 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 2367 break; 2368 default: 2369 break; 2370 } 2371 2372 } 2373 2374 const struct amdgpu_ip_block_version sdma_v4_4_2_ip_block = { 2375 .type = AMD_IP_BLOCK_TYPE_SDMA, 2376 .major = 4, 2377 .minor = 4, 2378 .rev = 2, 2379 .funcs = &sdma_v4_4_2_ip_funcs, 2380 }; 2381 2382 static int sdma_v4_4_2_xcp_resume(void *handle, uint32_t inst_mask) 2383 { 2384 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2385 int r; 2386 2387 if (!amdgpu_sriov_vf(adev)) 2388 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask); 2389 2390 r = sdma_v4_4_2_inst_start(adev, inst_mask, false); 2391 2392 return r; 2393 } 2394 2395 static int sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask) 2396 { 2397 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2398 uint32_t tmp_mask = inst_mask; 2399 int i; 2400 2401 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2402 for_each_inst(i, tmp_mask) { 2403 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 2404 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 2405 } 2406 } 2407 2408 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 2409 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 2410 2411 return 0; 2412 } 2413 2414 struct amdgpu_xcp_ip_funcs sdma_v4_4_2_xcp_funcs = { 2415 .suspend = &sdma_v4_4_2_xcp_suspend, 2416 .resume = &sdma_v4_4_2_xcp_resume 2417 }; 2418 2419 static struct amdgpu_sdma_ras sdma_v4_4_2_ras = { 2420 .ras_block = { 2421 .hw_ops = NULL, 2422 }, 2423 }; 2424 2425 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev) 2426 { 2427 adev->sdma.ras = &sdma_v4_4_2_ras; 2428 } 2429