1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_xcp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_trace.h" 33 #include "amdgpu_reset.h" 34 35 #include "sdma/sdma_4_4_2_offset.h" 36 #include "sdma/sdma_4_4_2_sh_mask.h" 37 38 #include "soc15_common.h" 39 #include "soc15.h" 40 #include "vega10_sdma_pkt_open.h" 41 42 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 43 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 44 45 #include "amdgpu_ras.h" 46 47 MODULE_FIRMWARE("amdgpu/sdma_4_4_2.bin"); 48 MODULE_FIRMWARE("amdgpu/sdma_4_4_5.bin"); 49 50 static const struct amdgpu_hwip_reg_entry sdma_reg_list_4_4_2[] = { 51 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS_REG), 52 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS1_REG), 53 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS2_REG), 54 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS3_REG), 55 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UCODE_CHECKSUM), 56 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH_HI), 57 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH), 58 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_STATUS), 59 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_STATUS), 60 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK0), 61 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK1), 62 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK0), 63 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK1), 64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_CNTL), 65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR), 66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR_HI), 67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR), 68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR_HI), 69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_OFFSET), 70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_LO), 71 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_HI), 72 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_CNTL), 73 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_RPTR), 74 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_SUB_REMAIN), 75 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_DUMMY_REG), 76 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_CNTL), 77 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR), 78 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR_HI), 79 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR), 80 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR_HI), 81 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_OFFSET), 82 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_LO), 83 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_HI), 84 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_DUMMY_REG), 85 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_CNTL), 86 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR), 87 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR_HI), 88 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR), 89 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR_HI), 90 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_OFFSET), 91 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_LO), 92 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_HI), 93 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_DUMMY_REG), 94 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_VM_CNTL) 95 }; 96 97 #define mmSMNAID_AID0_MCA_SMU 0x03b30400 98 99 #define WREG32_SDMA(instance, offset, value) \ 100 WREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)), value) 101 #define RREG32_SDMA(instance, offset) \ 102 RREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset))) 103 104 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev); 105 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev); 106 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev); 107 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev); 108 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev); 109 static void sdma_v4_4_2_set_engine_reset_funcs(struct amdgpu_device *adev); 110 static void sdma_v4_4_2_update_reset_mask(struct amdgpu_device *adev); 111 112 static u32 sdma_v4_4_2_get_reg_offset(struct amdgpu_device *adev, 113 u32 instance, u32 offset) 114 { 115 u32 dev_inst = GET_INST(SDMA0, instance); 116 117 return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset); 118 } 119 120 static unsigned sdma_v4_4_2_seq_to_irq_id(int seq_num) 121 { 122 switch (seq_num) { 123 case 0: 124 return SOC15_IH_CLIENTID_SDMA0; 125 case 1: 126 return SOC15_IH_CLIENTID_SDMA1; 127 case 2: 128 return SOC15_IH_CLIENTID_SDMA2; 129 case 3: 130 return SOC15_IH_CLIENTID_SDMA3; 131 default: 132 return -EINVAL; 133 } 134 } 135 136 static int sdma_v4_4_2_irq_id_to_seq(struct amdgpu_device *adev, unsigned client_id) 137 { 138 switch (client_id) { 139 case SOC15_IH_CLIENTID_SDMA0: 140 return 0; 141 case SOC15_IH_CLIENTID_SDMA1: 142 return 1; 143 case SOC15_IH_CLIENTID_SDMA2: 144 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) 145 return 0; 146 else 147 return 2; 148 case SOC15_IH_CLIENTID_SDMA3: 149 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) 150 return 1; 151 else 152 return 3; 153 default: 154 return -EINVAL; 155 } 156 } 157 158 static void sdma_v4_4_2_inst_init_golden_registers(struct amdgpu_device *adev, 159 uint32_t inst_mask) 160 { 161 u32 val; 162 int i; 163 164 for (i = 0; i < adev->sdma.num_instances; i++) { 165 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG); 166 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4); 167 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, 168 PIPE_INTERLEAVE_SIZE, 0); 169 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG, val); 170 171 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ); 172 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS, 173 4); 174 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, 175 PIPE_INTERLEAVE_SIZE, 0); 176 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ, val); 177 } 178 } 179 180 /** 181 * sdma_v4_4_2_init_microcode - load ucode images from disk 182 * 183 * @adev: amdgpu_device pointer 184 * 185 * Use the firmware interface to load the ucode images into 186 * the driver (not loaded into hw). 187 * Returns 0 on success, error on failure. 188 */ 189 static int sdma_v4_4_2_init_microcode(struct amdgpu_device *adev) 190 { 191 int ret, i; 192 193 for (i = 0; i < adev->sdma.num_instances; i++) { 194 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) || 195 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 4) || 196 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) { 197 ret = amdgpu_sdma_init_microcode(adev, 0, true); 198 break; 199 } else { 200 ret = amdgpu_sdma_init_microcode(adev, i, false); 201 if (ret) 202 return ret; 203 } 204 } 205 206 return ret; 207 } 208 209 /** 210 * sdma_v4_4_2_ring_get_rptr - get the current read pointer 211 * 212 * @ring: amdgpu ring pointer 213 * 214 * Get the current rptr from the hardware. 215 */ 216 static uint64_t sdma_v4_4_2_ring_get_rptr(struct amdgpu_ring *ring) 217 { 218 u64 rptr; 219 220 /* XXX check if swapping is necessary on BE */ 221 rptr = READ_ONCE(*((u64 *)&ring->adev->wb.wb[ring->rptr_offs])); 222 223 DRM_DEBUG("rptr before shift == 0x%016llx\n", rptr); 224 return rptr >> 2; 225 } 226 227 /** 228 * sdma_v4_4_2_ring_get_wptr - get the current write pointer 229 * 230 * @ring: amdgpu ring pointer 231 * 232 * Get the current wptr from the hardware. 233 */ 234 static uint64_t sdma_v4_4_2_ring_get_wptr(struct amdgpu_ring *ring) 235 { 236 struct amdgpu_device *adev = ring->adev; 237 u64 wptr; 238 239 if (ring->use_doorbell) { 240 /* XXX check if swapping is necessary on BE */ 241 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 242 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 243 } else { 244 wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI); 245 wptr = wptr << 32; 246 wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR); 247 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 248 ring->me, wptr); 249 } 250 251 return wptr >> 2; 252 } 253 254 /** 255 * sdma_v4_4_2_ring_set_wptr - commit the write pointer 256 * 257 * @ring: amdgpu ring pointer 258 * 259 * Write the wptr back to the hardware. 260 */ 261 static void sdma_v4_4_2_ring_set_wptr(struct amdgpu_ring *ring) 262 { 263 struct amdgpu_device *adev = ring->adev; 264 265 DRM_DEBUG("Setting write pointer\n"); 266 if (ring->use_doorbell) { 267 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 268 269 DRM_DEBUG("Using doorbell -- " 270 "wptr_offs == 0x%08x " 271 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 272 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 273 ring->wptr_offs, 274 lower_32_bits(ring->wptr << 2), 275 upper_32_bits(ring->wptr << 2)); 276 /* XXX check if swapping is necessary on BE */ 277 WRITE_ONCE(*wb, (ring->wptr << 2)); 278 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 279 ring->doorbell_index, ring->wptr << 2); 280 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 281 } else { 282 DRM_DEBUG("Not using doorbell -- " 283 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 284 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 285 ring->me, 286 lower_32_bits(ring->wptr << 2), 287 ring->me, 288 upper_32_bits(ring->wptr << 2)); 289 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR, 290 lower_32_bits(ring->wptr << 2)); 291 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI, 292 upper_32_bits(ring->wptr << 2)); 293 } 294 } 295 296 /** 297 * sdma_v4_4_2_page_ring_get_wptr - get the current write pointer 298 * 299 * @ring: amdgpu ring pointer 300 * 301 * Get the current wptr from the hardware. 302 */ 303 static uint64_t sdma_v4_4_2_page_ring_get_wptr(struct amdgpu_ring *ring) 304 { 305 struct amdgpu_device *adev = ring->adev; 306 u64 wptr; 307 308 if (ring->use_doorbell) { 309 /* XXX check if swapping is necessary on BE */ 310 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 311 } else { 312 wptr = RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI); 313 wptr = wptr << 32; 314 wptr |= RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR); 315 } 316 317 return wptr >> 2; 318 } 319 320 /** 321 * sdma_v4_4_2_page_ring_set_wptr - commit the write pointer 322 * 323 * @ring: amdgpu ring pointer 324 * 325 * Write the wptr back to the hardware. 326 */ 327 static void sdma_v4_4_2_page_ring_set_wptr(struct amdgpu_ring *ring) 328 { 329 struct amdgpu_device *adev = ring->adev; 330 331 if (ring->use_doorbell) { 332 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 333 334 /* XXX check if swapping is necessary on BE */ 335 WRITE_ONCE(*wb, (ring->wptr << 2)); 336 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 337 } else { 338 uint64_t wptr = ring->wptr << 2; 339 340 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR, 341 lower_32_bits(wptr)); 342 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI, 343 upper_32_bits(wptr)); 344 } 345 } 346 347 static void sdma_v4_4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 348 { 349 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 350 int i; 351 352 for (i = 0; i < count; i++) 353 if (sdma && sdma->burst_nop && (i == 0)) 354 amdgpu_ring_write(ring, ring->funcs->nop | 355 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 356 else 357 amdgpu_ring_write(ring, ring->funcs->nop); 358 } 359 360 /** 361 * sdma_v4_4_2_ring_emit_ib - Schedule an IB on the DMA engine 362 * 363 * @ring: amdgpu ring pointer 364 * @job: job to retrieve vmid from 365 * @ib: IB object to schedule 366 * @flags: unused 367 * 368 * Schedule an IB in the DMA ring. 369 */ 370 static void sdma_v4_4_2_ring_emit_ib(struct amdgpu_ring *ring, 371 struct amdgpu_job *job, 372 struct amdgpu_ib *ib, 373 uint32_t flags) 374 { 375 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 376 377 /* IB packet must end on a 8 DW boundary */ 378 sdma_v4_4_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 379 380 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 381 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 382 /* base must be 32 byte aligned */ 383 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 384 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 385 amdgpu_ring_write(ring, ib->length_dw); 386 amdgpu_ring_write(ring, 0); 387 amdgpu_ring_write(ring, 0); 388 389 } 390 391 static void sdma_v4_4_2_wait_reg_mem(struct amdgpu_ring *ring, 392 int mem_space, int hdp, 393 uint32_t addr0, uint32_t addr1, 394 uint32_t ref, uint32_t mask, 395 uint32_t inv) 396 { 397 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 398 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 399 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 400 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 401 if (mem_space) { 402 /* memory */ 403 amdgpu_ring_write(ring, addr0); 404 amdgpu_ring_write(ring, addr1); 405 } else { 406 /* registers */ 407 amdgpu_ring_write(ring, addr0 << 2); 408 amdgpu_ring_write(ring, addr1 << 2); 409 } 410 amdgpu_ring_write(ring, ref); /* reference */ 411 amdgpu_ring_write(ring, mask); /* mask */ 412 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 413 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 414 } 415 416 /** 417 * sdma_v4_4_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 418 * 419 * @ring: amdgpu ring pointer 420 * 421 * Emit an hdp flush packet on the requested DMA ring. 422 */ 423 static void sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 424 { 425 struct amdgpu_device *adev = ring->adev; 426 u32 ref_and_mask = 0; 427 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 428 429 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 430 << (ring->me % adev->sdma.num_inst_per_aid); 431 432 sdma_v4_4_2_wait_reg_mem(ring, 0, 1, 433 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 434 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 435 ref_and_mask, ref_and_mask, 10); 436 } 437 438 /** 439 * sdma_v4_4_2_ring_emit_fence - emit a fence on the DMA ring 440 * 441 * @ring: amdgpu ring pointer 442 * @addr: address 443 * @seq: sequence number 444 * @flags: fence related flags 445 * 446 * Add a DMA fence packet to the ring to write 447 * the fence seq number and DMA trap packet to generate 448 * an interrupt if needed. 449 */ 450 static void sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 451 unsigned flags) 452 { 453 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 454 /* write the fence */ 455 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 456 /* zero in first two bits */ 457 BUG_ON(addr & 0x3); 458 amdgpu_ring_write(ring, lower_32_bits(addr)); 459 amdgpu_ring_write(ring, upper_32_bits(addr)); 460 amdgpu_ring_write(ring, lower_32_bits(seq)); 461 462 /* optionally write high bits as well */ 463 if (write64bit) { 464 addr += 4; 465 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 466 /* zero in first two bits */ 467 BUG_ON(addr & 0x3); 468 amdgpu_ring_write(ring, lower_32_bits(addr)); 469 amdgpu_ring_write(ring, upper_32_bits(addr)); 470 amdgpu_ring_write(ring, upper_32_bits(seq)); 471 } 472 473 /* generate an interrupt */ 474 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 475 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 476 } 477 478 479 /** 480 * sdma_v4_4_2_inst_gfx_stop - stop the gfx async dma engines 481 * 482 * @adev: amdgpu_device pointer 483 * @inst_mask: mask of dma engine instances to be disabled 484 * 485 * Stop the gfx async dma ring buffers. 486 */ 487 static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev, 488 uint32_t inst_mask) 489 { 490 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 491 u32 doorbell_offset, doorbell; 492 u32 rb_cntl, ib_cntl; 493 int i; 494 495 for_each_inst(i, inst_mask) { 496 sdma[i] = &adev->sdma.instance[i].ring; 497 498 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); 499 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0); 500 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 501 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 502 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0); 503 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 504 505 if (sdma[i]->use_doorbell) { 506 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL); 507 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET); 508 509 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 0); 510 doorbell_offset = REG_SET_FIELD(doorbell_offset, 511 SDMA_GFX_DOORBELL_OFFSET, 512 OFFSET, 0); 513 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell); 514 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset); 515 } 516 } 517 } 518 519 /** 520 * sdma_v4_4_2_inst_rlc_stop - stop the compute async dma engines 521 * 522 * @adev: amdgpu_device pointer 523 * @inst_mask: mask of dma engine instances to be disabled 524 * 525 * Stop the compute async dma queues. 526 */ 527 static void sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device *adev, 528 uint32_t inst_mask) 529 { 530 /* XXX todo */ 531 } 532 533 /** 534 * sdma_v4_4_2_inst_page_stop - stop the page async dma engines 535 * 536 * @adev: amdgpu_device pointer 537 * @inst_mask: mask of dma engine instances to be disabled 538 * 539 * Stop the page async dma ring buffers. 540 */ 541 static void sdma_v4_4_2_inst_page_stop(struct amdgpu_device *adev, 542 uint32_t inst_mask) 543 { 544 u32 rb_cntl, ib_cntl; 545 int i; 546 547 for_each_inst(i, inst_mask) { 548 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); 549 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, 550 RB_ENABLE, 0); 551 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 552 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); 553 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, 554 IB_ENABLE, 0); 555 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); 556 } 557 } 558 559 /** 560 * sdma_v4_4_2_inst_ctx_switch_enable - stop the async dma engines context switch 561 * 562 * @adev: amdgpu_device pointer 563 * @enable: enable/disable the DMA MEs context switch. 564 * @inst_mask: mask of dma engine instances to be enabled 565 * 566 * Halt or unhalt the async dma engines context switch. 567 */ 568 static void sdma_v4_4_2_inst_ctx_switch_enable(struct amdgpu_device *adev, 569 bool enable, uint32_t inst_mask) 570 { 571 u32 f32_cntl, phase_quantum = 0; 572 int i; 573 574 if (amdgpu_sdma_phase_quantum) { 575 unsigned value = amdgpu_sdma_phase_quantum; 576 unsigned unit = 0; 577 578 while (value > (SDMA_PHASE0_QUANTUM__VALUE_MASK >> 579 SDMA_PHASE0_QUANTUM__VALUE__SHIFT)) { 580 value = (value + 1) >> 1; 581 unit++; 582 } 583 if (unit > (SDMA_PHASE0_QUANTUM__UNIT_MASK >> 584 SDMA_PHASE0_QUANTUM__UNIT__SHIFT)) { 585 value = (SDMA_PHASE0_QUANTUM__VALUE_MASK >> 586 SDMA_PHASE0_QUANTUM__VALUE__SHIFT); 587 unit = (SDMA_PHASE0_QUANTUM__UNIT_MASK >> 588 SDMA_PHASE0_QUANTUM__UNIT__SHIFT); 589 WARN_ONCE(1, 590 "clamping sdma_phase_quantum to %uK clock cycles\n", 591 value << unit); 592 } 593 phase_quantum = 594 value << SDMA_PHASE0_QUANTUM__VALUE__SHIFT | 595 unit << SDMA_PHASE0_QUANTUM__UNIT__SHIFT; 596 } 597 598 for_each_inst(i, inst_mask) { 599 f32_cntl = RREG32_SDMA(i, regSDMA_CNTL); 600 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_CNTL, 601 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 602 if (enable && amdgpu_sdma_phase_quantum) { 603 WREG32_SDMA(i, regSDMA_PHASE0_QUANTUM, phase_quantum); 604 WREG32_SDMA(i, regSDMA_PHASE1_QUANTUM, phase_quantum); 605 WREG32_SDMA(i, regSDMA_PHASE2_QUANTUM, phase_quantum); 606 } 607 WREG32_SDMA(i, regSDMA_CNTL, f32_cntl); 608 609 /* Extend page fault timeout to avoid interrupt storm */ 610 WREG32_SDMA(i, regSDMA_UTCL1_TIMEOUT, 0x00800080); 611 } 612 } 613 614 /** 615 * sdma_v4_4_2_inst_enable - stop the async dma engines 616 * 617 * @adev: amdgpu_device pointer 618 * @enable: enable/disable the DMA MEs. 619 * @inst_mask: mask of dma engine instances to be enabled 620 * 621 * Halt or unhalt the async dma engines. 622 */ 623 static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable, 624 uint32_t inst_mask) 625 { 626 u32 f32_cntl; 627 int i; 628 629 if (!enable) { 630 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask); 631 sdma_v4_4_2_inst_rlc_stop(adev, inst_mask); 632 if (adev->sdma.has_page_queue) 633 sdma_v4_4_2_inst_page_stop(adev, inst_mask); 634 635 /* SDMA FW needs to respond to FREEZE requests during reset. 636 * Keep it running during reset */ 637 if (!amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 638 return; 639 } 640 641 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 642 return; 643 644 for_each_inst(i, inst_mask) { 645 f32_cntl = RREG32_SDMA(i, regSDMA_F32_CNTL); 646 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1); 647 WREG32_SDMA(i, regSDMA_F32_CNTL, f32_cntl); 648 } 649 } 650 651 /* 652 * sdma_v4_4_2_rb_cntl - get parameters for rb_cntl 653 */ 654 static uint32_t sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 655 { 656 /* Set ring buffer size in dwords */ 657 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 658 659 barrier(); /* work around https://llvm.org/pr42576 */ 660 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 661 #ifdef __BIG_ENDIAN 662 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 663 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, 664 RPTR_WRITEBACK_SWAP_ENABLE, 1); 665 #endif 666 return rb_cntl; 667 } 668 669 /** 670 * sdma_v4_4_2_gfx_resume - setup and start the async dma engines 671 * 672 * @adev: amdgpu_device pointer 673 * @i: instance to resume 674 * @restore: used to restore wptr when restart 675 * @guilty: boolean indicating whether this queue is the guilty one (caused the timeout/error) 676 * 677 * Set up the gfx DMA ring buffers and enable them. 678 * Returns 0 for success, error for failure. 679 */ 680 static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i, bool restore, bool guilty) 681 { 682 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 683 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 684 u32 wb_offset; 685 u32 doorbell; 686 u32 doorbell_offset; 687 u64 wptr_gpu_addr; 688 u64 rwptr; 689 690 wb_offset = (ring->rptr_offs * 4); 691 692 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); 693 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 694 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 695 696 /* set the wb address whether it's enabled or not */ 697 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_HI, 698 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 699 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_LO, 700 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 701 702 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, 703 RPTR_WRITEBACK_ENABLE, 1); 704 705 WREG32_SDMA(i, regSDMA_GFX_RB_BASE, ring->gpu_addr >> 8); 706 WREG32_SDMA(i, regSDMA_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 707 708 if (!restore) 709 ring->wptr = 0; 710 711 /* before programing wptr to a less value, need set minor_ptr_update first */ 712 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 1); 713 714 /* For the guilty queue, set RPTR to the current wptr to skip bad commands, 715 * It is not a guilty queue, restore cache_rptr and continue execution. 716 */ 717 if (guilty) 718 rwptr = ring->wptr; 719 else 720 rwptr = ring->cached_rptr; 721 722 /* Initialize the ring buffer's read and write pointers */ 723 if (restore) { 724 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, lower_32_bits(rwptr << 2)); 725 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, upper_32_bits(rwptr << 2)); 726 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, lower_32_bits(rwptr << 2)); 727 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, upper_32_bits(rwptr << 2)); 728 } else { 729 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0); 730 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0); 731 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0); 732 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0); 733 } 734 735 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL); 736 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET); 737 738 doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 739 ring->use_doorbell); 740 doorbell_offset = REG_SET_FIELD(doorbell_offset, 741 SDMA_GFX_DOORBELL_OFFSET, 742 OFFSET, ring->doorbell_index); 743 WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell); 744 WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset); 745 746 sdma_v4_4_2_ring_set_wptr(ring); 747 748 /* set minor_ptr_update to 0 after wptr programed */ 749 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 0); 750 751 /* setup the wptr shadow polling */ 752 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 753 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_LO, 754 lower_32_bits(wptr_gpu_addr)); 755 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_HI, 756 upper_32_bits(wptr_gpu_addr)); 757 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL); 758 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 759 SDMA_GFX_RB_WPTR_POLL_CNTL, 760 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 761 WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 762 763 /* enable DMA RB */ 764 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 1); 765 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 766 767 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 768 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 1); 769 #ifdef __BIG_ENDIAN 770 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 771 #endif 772 /* enable DMA IBs */ 773 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 774 } 775 776 /** 777 * sdma_v4_4_2_page_resume - setup and start the async dma engines 778 * 779 * @adev: amdgpu_device pointer 780 * @i: instance to resume 781 * @restore: boolean to say restore needed or not 782 * @guilty: boolean indicating whether this queue is the guilty one (caused the timeout/error) 783 * 784 * Set up the page DMA ring buffers and enable them. 785 * Returns 0 for success, error for failure. 786 */ 787 static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i, bool restore, bool guilty) 788 { 789 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 790 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 791 u32 wb_offset; 792 u32 doorbell; 793 u32 doorbell_offset; 794 u64 wptr_gpu_addr; 795 u64 rwptr; 796 797 wb_offset = (ring->rptr_offs * 4); 798 799 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); 800 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 801 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 802 803 /* For the guilty queue, set RPTR to the current wptr to skip bad commands, 804 * It is not a guilty queue, restore cache_rptr and continue execution. 805 */ 806 if (guilty) 807 rwptr = ring->wptr; 808 else 809 rwptr = ring->cached_rptr; 810 811 /* Initialize the ring buffer's read and write pointers */ 812 if (restore) { 813 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, lower_32_bits(rwptr << 2)); 814 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, upper_32_bits(rwptr << 2)); 815 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, lower_32_bits(rwptr << 2)); 816 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, upper_32_bits(rwptr << 2)); 817 } else { 818 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, 0); 819 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, 0); 820 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, 0); 821 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, 0); 822 } 823 824 /* set the wb address whether it's enabled or not */ 825 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_HI, 826 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 827 WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_LO, 828 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 829 830 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, 831 RPTR_WRITEBACK_ENABLE, 1); 832 833 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE, ring->gpu_addr >> 8); 834 WREG32_SDMA(i, regSDMA_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 835 836 if (!restore) 837 ring->wptr = 0; 838 839 /* before programing wptr to a less value, need set minor_ptr_update first */ 840 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 1); 841 842 doorbell = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL); 843 doorbell_offset = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET); 844 845 doorbell = REG_SET_FIELD(doorbell, SDMA_PAGE_DOORBELL, ENABLE, 846 ring->use_doorbell); 847 doorbell_offset = REG_SET_FIELD(doorbell_offset, 848 SDMA_PAGE_DOORBELL_OFFSET, 849 OFFSET, ring->doorbell_index); 850 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL, doorbell); 851 WREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET, doorbell_offset); 852 853 /* paging queue doorbell range is setup at sdma_v4_4_2_gfx_resume */ 854 sdma_v4_4_2_page_ring_set_wptr(ring); 855 856 /* set minor_ptr_update to 0 after wptr programed */ 857 WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 0); 858 859 /* setup the wptr shadow polling */ 860 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 861 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_LO, 862 lower_32_bits(wptr_gpu_addr)); 863 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_HI, 864 upper_32_bits(wptr_gpu_addr)); 865 wptr_poll_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL); 866 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 867 SDMA_PAGE_RB_WPTR_POLL_CNTL, 868 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 869 WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 870 871 /* enable DMA RB */ 872 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, RB_ENABLE, 1); 873 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); 874 875 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL); 876 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_ENABLE, 1); 877 #ifdef __BIG_ENDIAN 878 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 879 #endif 880 /* enable DMA IBs */ 881 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl); 882 } 883 884 static void sdma_v4_4_2_init_pg(struct amdgpu_device *adev) 885 { 886 887 } 888 889 /** 890 * sdma_v4_4_2_inst_rlc_resume - setup and start the async dma engines 891 * 892 * @adev: amdgpu_device pointer 893 * @inst_mask: mask of dma engine instances to be enabled 894 * 895 * Set up the compute DMA queues and enable them. 896 * Returns 0 for success, error for failure. 897 */ 898 static int sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device *adev, 899 uint32_t inst_mask) 900 { 901 sdma_v4_4_2_init_pg(adev); 902 903 return 0; 904 } 905 906 /** 907 * sdma_v4_4_2_inst_load_microcode - load the sDMA ME ucode 908 * 909 * @adev: amdgpu_device pointer 910 * @inst_mask: mask of dma engine instances to be enabled 911 * 912 * Loads the sDMA0/1 ucode. 913 * Returns 0 for success, -EINVAL if the ucode is not available. 914 */ 915 static int sdma_v4_4_2_inst_load_microcode(struct amdgpu_device *adev, 916 uint32_t inst_mask) 917 { 918 const struct sdma_firmware_header_v1_0 *hdr; 919 const __le32 *fw_data; 920 u32 fw_size; 921 int i, j; 922 923 /* halt the MEs */ 924 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 925 926 for_each_inst(i, inst_mask) { 927 if (!adev->sdma.instance[i].fw) 928 return -EINVAL; 929 930 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 931 amdgpu_ucode_print_sdma_hdr(&hdr->header); 932 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 933 934 fw_data = (const __le32 *) 935 (adev->sdma.instance[i].fw->data + 936 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 937 938 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 0); 939 940 for (j = 0; j < fw_size; j++) 941 WREG32_SDMA(i, regSDMA_UCODE_DATA, 942 le32_to_cpup(fw_data++)); 943 944 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 945 adev->sdma.instance[i].fw_version); 946 } 947 948 return 0; 949 } 950 951 /** 952 * sdma_v4_4_2_inst_start - setup and start the async dma engines 953 * 954 * @adev: amdgpu_device pointer 955 * @inst_mask: mask of dma engine instances to be enabled 956 * @restore: boolean to say restore needed or not 957 * 958 * Set up the DMA engines and enable them. 959 * Returns 0 for success, error for failure. 960 */ 961 static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev, 962 uint32_t inst_mask, bool restore) 963 { 964 struct amdgpu_ring *ring; 965 uint32_t tmp_mask; 966 int i, r = 0; 967 968 if (amdgpu_sriov_vf(adev)) { 969 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 970 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 971 } else { 972 /* bypass sdma microcode loading on Gopher */ 973 if (!restore && adev->firmware.load_type != AMDGPU_FW_LOAD_PSP && 974 adev->sdma.instance[0].fw) { 975 r = sdma_v4_4_2_inst_load_microcode(adev, inst_mask); 976 if (r) 977 return r; 978 } 979 980 /* unhalt the MEs */ 981 sdma_v4_4_2_inst_enable(adev, true, inst_mask); 982 /* enable sdma ring preemption */ 983 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask); 984 } 985 986 /* start the gfx rings and rlc compute queues */ 987 tmp_mask = inst_mask; 988 for_each_inst(i, tmp_mask) { 989 uint32_t temp; 990 991 WREG32_SDMA(i, regSDMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); 992 sdma_v4_4_2_gfx_resume(adev, i, restore, adev->sdma.gfx_guilty); 993 if (adev->sdma.has_page_queue) 994 sdma_v4_4_2_page_resume(adev, i, restore, adev->sdma.page_guilty); 995 996 /* set utc l1 enable flag always to 1 */ 997 temp = RREG32_SDMA(i, regSDMA_CNTL); 998 temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1); 999 1000 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) < IP_VERSION(4, 4, 5)) { 1001 /* enable context empty interrupt during initialization */ 1002 temp = REG_SET_FIELD(temp, SDMA_CNTL, CTXEMPTY_INT_ENABLE, 1); 1003 WREG32_SDMA(i, regSDMA_CNTL, temp); 1004 } 1005 if (!amdgpu_sriov_vf(adev)) { 1006 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1007 /* unhalt engine */ 1008 temp = RREG32_SDMA(i, regSDMA_F32_CNTL); 1009 temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0); 1010 WREG32_SDMA(i, regSDMA_F32_CNTL, temp); 1011 } 1012 } 1013 } 1014 1015 if (amdgpu_sriov_vf(adev)) { 1016 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask); 1017 sdma_v4_4_2_inst_enable(adev, true, inst_mask); 1018 } else { 1019 r = sdma_v4_4_2_inst_rlc_resume(adev, inst_mask); 1020 if (r) 1021 return r; 1022 } 1023 1024 tmp_mask = inst_mask; 1025 for_each_inst(i, tmp_mask) { 1026 ring = &adev->sdma.instance[i].ring; 1027 1028 r = amdgpu_ring_test_helper(ring); 1029 if (r) 1030 return r; 1031 1032 if (adev->sdma.has_page_queue) { 1033 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 1034 1035 r = amdgpu_ring_test_helper(page); 1036 if (r) 1037 return r; 1038 } 1039 } 1040 1041 return r; 1042 } 1043 1044 /** 1045 * sdma_v4_4_2_ring_test_ring - simple async dma engine test 1046 * 1047 * @ring: amdgpu_ring structure holding ring information 1048 * 1049 * Test the DMA engine by writing using it to write an 1050 * value to memory. 1051 * Returns 0 for success, error for failure. 1052 */ 1053 static int sdma_v4_4_2_ring_test_ring(struct amdgpu_ring *ring) 1054 { 1055 struct amdgpu_device *adev = ring->adev; 1056 unsigned i; 1057 unsigned index; 1058 int r; 1059 u32 tmp; 1060 u64 gpu_addr; 1061 1062 r = amdgpu_device_wb_get(adev, &index); 1063 if (r) 1064 return r; 1065 1066 gpu_addr = adev->wb.gpu_addr + (index * 4); 1067 tmp = 0xCAFEDEAD; 1068 adev->wb.wb[index] = cpu_to_le32(tmp); 1069 1070 r = amdgpu_ring_alloc(ring, 5); 1071 if (r) 1072 goto error_free_wb; 1073 1074 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1075 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1076 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1077 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1078 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1079 amdgpu_ring_write(ring, 0xDEADBEEF); 1080 amdgpu_ring_commit(ring); 1081 1082 for (i = 0; i < adev->usec_timeout; i++) { 1083 tmp = le32_to_cpu(adev->wb.wb[index]); 1084 if (tmp == 0xDEADBEEF) 1085 break; 1086 udelay(1); 1087 } 1088 1089 if (i >= adev->usec_timeout) 1090 r = -ETIMEDOUT; 1091 1092 error_free_wb: 1093 amdgpu_device_wb_free(adev, index); 1094 return r; 1095 } 1096 1097 /** 1098 * sdma_v4_4_2_ring_test_ib - test an IB on the DMA engine 1099 * 1100 * @ring: amdgpu_ring structure holding ring information 1101 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1102 * 1103 * Test a simple IB in the DMA ring. 1104 * Returns 0 on success, error on failure. 1105 */ 1106 static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1107 { 1108 struct amdgpu_device *adev = ring->adev; 1109 struct amdgpu_ib ib; 1110 struct dma_fence *f = NULL; 1111 unsigned index; 1112 long r; 1113 u32 tmp = 0; 1114 u64 gpu_addr; 1115 1116 r = amdgpu_device_wb_get(adev, &index); 1117 if (r) 1118 return r; 1119 1120 gpu_addr = adev->wb.gpu_addr + (index * 4); 1121 tmp = 0xCAFEDEAD; 1122 adev->wb.wb[index] = cpu_to_le32(tmp); 1123 memset(&ib, 0, sizeof(ib)); 1124 r = amdgpu_ib_get(adev, NULL, 256, 1125 AMDGPU_IB_POOL_DIRECT, &ib); 1126 if (r) 1127 goto err0; 1128 1129 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1130 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1131 ib.ptr[1] = lower_32_bits(gpu_addr); 1132 ib.ptr[2] = upper_32_bits(gpu_addr); 1133 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1134 ib.ptr[4] = 0xDEADBEEF; 1135 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1136 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1137 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1138 ib.length_dw = 8; 1139 1140 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1141 if (r) 1142 goto err1; 1143 1144 r = dma_fence_wait_timeout(f, false, timeout); 1145 if (r == 0) { 1146 r = -ETIMEDOUT; 1147 goto err1; 1148 } else if (r < 0) { 1149 goto err1; 1150 } 1151 tmp = le32_to_cpu(adev->wb.wb[index]); 1152 if (tmp == 0xDEADBEEF) 1153 r = 0; 1154 else 1155 r = -EINVAL; 1156 1157 err1: 1158 amdgpu_ib_free(&ib, NULL); 1159 dma_fence_put(f); 1160 err0: 1161 amdgpu_device_wb_free(adev, index); 1162 return r; 1163 } 1164 1165 1166 /** 1167 * sdma_v4_4_2_vm_copy_pte - update PTEs by copying them from the GART 1168 * 1169 * @ib: indirect buffer to fill with commands 1170 * @pe: addr of the page entry 1171 * @src: src addr to copy from 1172 * @count: number of page entries to update 1173 * 1174 * Update PTEs by copying them from the GART using sDMA. 1175 */ 1176 static void sdma_v4_4_2_vm_copy_pte(struct amdgpu_ib *ib, 1177 uint64_t pe, uint64_t src, 1178 unsigned count) 1179 { 1180 unsigned bytes = count * 8; 1181 1182 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1183 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1184 ib->ptr[ib->length_dw++] = bytes - 1; 1185 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1186 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1187 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1188 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1189 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1190 1191 } 1192 1193 /** 1194 * sdma_v4_4_2_vm_write_pte - update PTEs by writing them manually 1195 * 1196 * @ib: indirect buffer to fill with commands 1197 * @pe: addr of the page entry 1198 * @value: dst addr to write into pe 1199 * @count: number of page entries to update 1200 * @incr: increase next addr by incr bytes 1201 * 1202 * Update PTEs by writing them manually using sDMA. 1203 */ 1204 static void sdma_v4_4_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1205 uint64_t value, unsigned count, 1206 uint32_t incr) 1207 { 1208 unsigned ndw = count * 2; 1209 1210 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1211 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1212 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1213 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1214 ib->ptr[ib->length_dw++] = ndw - 1; 1215 for (; ndw > 0; ndw -= 2) { 1216 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1217 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1218 value += incr; 1219 } 1220 } 1221 1222 /** 1223 * sdma_v4_4_2_vm_set_pte_pde - update the page tables using sDMA 1224 * 1225 * @ib: indirect buffer to fill with commands 1226 * @pe: addr of the page entry 1227 * @addr: dst addr to write into pe 1228 * @count: number of page entries to update 1229 * @incr: increase next addr by incr bytes 1230 * @flags: access flags 1231 * 1232 * Update the page tables using sDMA. 1233 */ 1234 static void sdma_v4_4_2_vm_set_pte_pde(struct amdgpu_ib *ib, 1235 uint64_t pe, 1236 uint64_t addr, unsigned count, 1237 uint32_t incr, uint64_t flags) 1238 { 1239 /* for physically contiguous pages (vram) */ 1240 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1241 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1242 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1243 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1244 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1245 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1246 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1247 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1248 ib->ptr[ib->length_dw++] = 0; 1249 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1250 } 1251 1252 /** 1253 * sdma_v4_4_2_ring_pad_ib - pad the IB to the required number of dw 1254 * 1255 * @ring: amdgpu_ring structure holding ring information 1256 * @ib: indirect buffer to fill with padding 1257 */ 1258 static void sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1259 { 1260 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1261 u32 pad_count; 1262 int i; 1263 1264 pad_count = (-ib->length_dw) & 7; 1265 for (i = 0; i < pad_count; i++) 1266 if (sdma && sdma->burst_nop && (i == 0)) 1267 ib->ptr[ib->length_dw++] = 1268 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1269 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1270 else 1271 ib->ptr[ib->length_dw++] = 1272 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1273 } 1274 1275 1276 /** 1277 * sdma_v4_4_2_ring_emit_pipeline_sync - sync the pipeline 1278 * 1279 * @ring: amdgpu_ring pointer 1280 * 1281 * Make sure all previous operations are completed (CIK). 1282 */ 1283 static void sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1284 { 1285 uint32_t seq = ring->fence_drv.sync_seq; 1286 uint64_t addr = ring->fence_drv.gpu_addr; 1287 1288 /* wait for idle */ 1289 sdma_v4_4_2_wait_reg_mem(ring, 1, 0, 1290 addr & 0xfffffffc, 1291 upper_32_bits(addr) & 0xffffffff, 1292 seq, 0xffffffff, 4); 1293 } 1294 1295 1296 /** 1297 * sdma_v4_4_2_ring_emit_vm_flush - vm flush using sDMA 1298 * 1299 * @ring: amdgpu_ring pointer 1300 * @vmid: vmid number to use 1301 * @pd_addr: address 1302 * 1303 * Update the page table base and flush the VM TLB 1304 * using sDMA. 1305 */ 1306 static void sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring *ring, 1307 unsigned vmid, uint64_t pd_addr) 1308 { 1309 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1310 } 1311 1312 static void sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring *ring, 1313 uint32_t reg, uint32_t val) 1314 { 1315 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1316 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1317 amdgpu_ring_write(ring, reg); 1318 amdgpu_ring_write(ring, val); 1319 } 1320 1321 static void sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1322 uint32_t val, uint32_t mask) 1323 { 1324 sdma_v4_4_2_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1325 } 1326 1327 static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev) 1328 { 1329 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1330 case IP_VERSION(4, 4, 2): 1331 case IP_VERSION(4, 4, 5): 1332 return false; 1333 default: 1334 return false; 1335 } 1336 } 1337 1338 static int sdma_v4_4_2_early_init(struct amdgpu_ip_block *ip_block) 1339 { 1340 struct amdgpu_device *adev = ip_block->adev; 1341 int r; 1342 1343 r = sdma_v4_4_2_init_microcode(adev); 1344 if (r) 1345 return r; 1346 1347 /* TODO: Page queue breaks driver reload under SRIOV */ 1348 if (sdma_v4_4_2_fw_support_paging_queue(adev)) 1349 adev->sdma.has_page_queue = true; 1350 1351 sdma_v4_4_2_set_ring_funcs(adev); 1352 sdma_v4_4_2_set_buffer_funcs(adev); 1353 sdma_v4_4_2_set_vm_pte_funcs(adev); 1354 sdma_v4_4_2_set_irq_funcs(adev); 1355 sdma_v4_4_2_set_ras_funcs(adev); 1356 sdma_v4_4_2_set_engine_reset_funcs(adev); 1357 1358 return 0; 1359 } 1360 1361 #if 0 1362 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, 1363 void *err_data, 1364 struct amdgpu_iv_entry *entry); 1365 #endif 1366 1367 static int sdma_v4_4_2_late_init(struct amdgpu_ip_block *ip_block) 1368 { 1369 struct amdgpu_device *adev = ip_block->adev; 1370 #if 0 1371 struct ras_ih_if ih_info = { 1372 .cb = sdma_v4_4_2_process_ras_data_cb, 1373 }; 1374 #endif 1375 if (!amdgpu_persistent_edc_harvesting_supported(adev)) 1376 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__SDMA); 1377 1378 /* The initialization is done in the late_init stage to ensure that the SMU 1379 * initialization and capability setup are completed before we check the SDMA 1380 * reset capability 1381 */ 1382 sdma_v4_4_2_update_reset_mask(adev); 1383 1384 return 0; 1385 } 1386 1387 static int sdma_v4_4_2_sw_init(struct amdgpu_ip_block *ip_block) 1388 { 1389 struct amdgpu_ring *ring; 1390 int r, i; 1391 struct amdgpu_device *adev = ip_block->adev; 1392 u32 aid_id; 1393 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); 1394 uint32_t *ptr; 1395 1396 /* SDMA trap event */ 1397 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1398 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1399 SDMA0_4_0__SRCID__SDMA_TRAP, 1400 &adev->sdma.trap_irq); 1401 if (r) 1402 return r; 1403 } 1404 1405 /* SDMA SRAM ECC event */ 1406 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1407 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1408 SDMA0_4_0__SRCID__SDMA_SRAM_ECC, 1409 &adev->sdma.ecc_irq); 1410 if (r) 1411 return r; 1412 } 1413 1414 /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/ 1415 for (i = 0; i < adev->sdma.num_inst_per_aid; i++) { 1416 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1417 SDMA0_4_0__SRCID__SDMA_VM_HOLE, 1418 &adev->sdma.vm_hole_irq); 1419 if (r) 1420 return r; 1421 1422 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1423 SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID, 1424 &adev->sdma.doorbell_invalid_irq); 1425 if (r) 1426 return r; 1427 1428 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1429 SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT, 1430 &adev->sdma.pool_timeout_irq); 1431 if (r) 1432 return r; 1433 1434 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1435 SDMA0_4_0__SRCID__SDMA_SRBMWRITE, 1436 &adev->sdma.srbm_write_irq); 1437 if (r) 1438 return r; 1439 1440 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i), 1441 SDMA0_4_0__SRCID__SDMA_CTXEMPTY, 1442 &adev->sdma.ctxt_empty_irq); 1443 if (r) 1444 return r; 1445 } 1446 1447 for (i = 0; i < adev->sdma.num_instances; i++) { 1448 ring = &adev->sdma.instance[i].ring; 1449 ring->ring_obj = NULL; 1450 ring->use_doorbell = true; 1451 aid_id = adev->sdma.instance[i].aid_id; 1452 1453 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1454 ring->use_doorbell?"true":"false"); 1455 1456 /* doorbell size is 2 dwords, get DWORD offset */ 1457 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1458 ring->vm_hub = AMDGPU_MMHUB0(aid_id); 1459 1460 sprintf(ring->name, "sdma%d.%d", aid_id, 1461 i % adev->sdma.num_inst_per_aid); 1462 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1463 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1464 AMDGPU_RING_PRIO_DEFAULT, NULL); 1465 if (r) 1466 return r; 1467 1468 if (adev->sdma.has_page_queue) { 1469 ring = &adev->sdma.instance[i].page; 1470 ring->ring_obj = NULL; 1471 ring->use_doorbell = true; 1472 1473 /* doorbell index of page queue is assigned right after 1474 * gfx queue on the same instance 1475 */ 1476 ring->doorbell_index = 1477 (adev->doorbell_index.sdma_engine[i] + 1) << 1; 1478 ring->vm_hub = AMDGPU_MMHUB0(aid_id); 1479 1480 sprintf(ring->name, "page%d.%d", aid_id, 1481 i % adev->sdma.num_inst_per_aid); 1482 r = amdgpu_ring_init(adev, ring, 1024, 1483 &adev->sdma.trap_irq, 1484 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1485 AMDGPU_RING_PRIO_DEFAULT, NULL); 1486 if (r) 1487 return r; 1488 } 1489 } 1490 1491 adev->sdma.supported_reset = 1492 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); 1493 1494 if (amdgpu_sdma_ras_sw_init(adev)) { 1495 dev_err(adev->dev, "fail to initialize sdma ras block\n"); 1496 return -EINVAL; 1497 } 1498 1499 /* Allocate memory for SDMA IP Dump buffer */ 1500 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); 1501 if (ptr) 1502 adev->sdma.ip_dump = ptr; 1503 else 1504 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n"); 1505 1506 r = amdgpu_sdma_sysfs_reset_mask_init(adev); 1507 if (r) 1508 return r; 1509 /* Initialize guilty flags for GFX and PAGE queues */ 1510 adev->sdma.gfx_guilty = false; 1511 adev->sdma.page_guilty = false; 1512 1513 return r; 1514 } 1515 1516 static int sdma_v4_4_2_sw_fini(struct amdgpu_ip_block *ip_block) 1517 { 1518 struct amdgpu_device *adev = ip_block->adev; 1519 int i; 1520 1521 for (i = 0; i < adev->sdma.num_instances; i++) { 1522 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1523 if (adev->sdma.has_page_queue) 1524 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1525 } 1526 1527 amdgpu_sdma_sysfs_reset_mask_fini(adev); 1528 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) || 1529 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 4) || 1530 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) 1531 amdgpu_sdma_destroy_inst_ctx(adev, true); 1532 else 1533 amdgpu_sdma_destroy_inst_ctx(adev, false); 1534 1535 kfree(adev->sdma.ip_dump); 1536 1537 return 0; 1538 } 1539 1540 static int sdma_v4_4_2_hw_init(struct amdgpu_ip_block *ip_block) 1541 { 1542 int r; 1543 struct amdgpu_device *adev = ip_block->adev; 1544 uint32_t inst_mask; 1545 1546 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1547 if (!amdgpu_sriov_vf(adev)) 1548 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask); 1549 1550 r = sdma_v4_4_2_inst_start(adev, inst_mask, false); 1551 1552 return r; 1553 } 1554 1555 static int sdma_v4_4_2_hw_fini(struct amdgpu_ip_block *ip_block) 1556 { 1557 struct amdgpu_device *adev = ip_block->adev; 1558 uint32_t inst_mask; 1559 int i; 1560 1561 if (amdgpu_sriov_vf(adev)) 1562 return 0; 1563 1564 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 1565 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 1566 for (i = 0; i < adev->sdma.num_instances; i++) { 1567 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 1568 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1569 } 1570 } 1571 1572 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 1573 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 1574 1575 return 0; 1576 } 1577 1578 static int sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1579 enum amd_clockgating_state state); 1580 1581 static int sdma_v4_4_2_suspend(struct amdgpu_ip_block *ip_block) 1582 { 1583 struct amdgpu_device *adev = ip_block->adev; 1584 1585 if (amdgpu_in_reset(adev)) 1586 sdma_v4_4_2_set_clockgating_state(ip_block, AMD_CG_STATE_UNGATE); 1587 1588 return sdma_v4_4_2_hw_fini(ip_block); 1589 } 1590 1591 static int sdma_v4_4_2_resume(struct amdgpu_ip_block *ip_block) 1592 { 1593 return sdma_v4_4_2_hw_init(ip_block); 1594 } 1595 1596 static bool sdma_v4_4_2_is_idle(struct amdgpu_ip_block *ip_block) 1597 { 1598 struct amdgpu_device *adev = ip_block->adev; 1599 u32 i; 1600 1601 for (i = 0; i < adev->sdma.num_instances; i++) { 1602 u32 tmp = RREG32_SDMA(i, regSDMA_STATUS_REG); 1603 1604 if (!(tmp & SDMA_STATUS_REG__IDLE_MASK)) 1605 return false; 1606 } 1607 1608 return true; 1609 } 1610 1611 static int sdma_v4_4_2_wait_for_idle(struct amdgpu_ip_block *ip_block) 1612 { 1613 unsigned i, j; 1614 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; 1615 struct amdgpu_device *adev = ip_block->adev; 1616 1617 for (i = 0; i < adev->usec_timeout; i++) { 1618 for (j = 0; j < adev->sdma.num_instances; j++) { 1619 sdma[j] = RREG32_SDMA(j, regSDMA_STATUS_REG); 1620 if (!(sdma[j] & SDMA_STATUS_REG__IDLE_MASK)) 1621 break; 1622 } 1623 if (j == adev->sdma.num_instances) 1624 return 0; 1625 udelay(1); 1626 } 1627 return -ETIMEDOUT; 1628 } 1629 1630 static int sdma_v4_4_2_soft_reset(struct amdgpu_ip_block *ip_block) 1631 { 1632 /* todo */ 1633 1634 return 0; 1635 } 1636 1637 static bool sdma_v4_4_2_is_queue_selected(struct amdgpu_device *adev, uint32_t instance_id, bool is_page_queue) 1638 { 1639 uint32_t reg_offset = is_page_queue ? regSDMA_PAGE_CONTEXT_STATUS : regSDMA_GFX_CONTEXT_STATUS; 1640 uint32_t context_status = RREG32(sdma_v4_4_2_get_reg_offset(adev, instance_id, reg_offset)); 1641 1642 /* Check if the SELECTED bit is set */ 1643 return (context_status & SDMA_GFX_CONTEXT_STATUS__SELECTED_MASK) != 0; 1644 } 1645 1646 static bool sdma_v4_4_2_ring_is_guilty(struct amdgpu_ring *ring) 1647 { 1648 struct amdgpu_device *adev = ring->adev; 1649 uint32_t instance_id = ring->me; 1650 1651 return sdma_v4_4_2_is_queue_selected(adev, instance_id, false); 1652 } 1653 1654 static bool sdma_v4_4_2_page_ring_is_guilty(struct amdgpu_ring *ring) 1655 { 1656 struct amdgpu_device *adev = ring->adev; 1657 uint32_t instance_id = ring->me; 1658 1659 if (!adev->sdma.has_page_queue) 1660 return false; 1661 1662 return sdma_v4_4_2_is_queue_selected(adev, instance_id, true); 1663 } 1664 1665 static int sdma_v4_4_2_reset_queue(struct amdgpu_ring *ring, unsigned int vmid) 1666 { 1667 struct amdgpu_device *adev = ring->adev; 1668 u32 id = GET_INST(SDMA0, ring->me); 1669 return amdgpu_sdma_reset_engine(adev, id, true); 1670 } 1671 1672 static int sdma_v4_4_2_stop_queue(struct amdgpu_device *adev, uint32_t instance_id) 1673 { 1674 u32 inst_mask; 1675 uint64_t rptr; 1676 struct amdgpu_ring *ring = &adev->sdma.instance[instance_id].ring; 1677 1678 if (amdgpu_sriov_vf(adev)) 1679 return -EINVAL; 1680 1681 /* Check if this queue is the guilty one */ 1682 adev->sdma.gfx_guilty = sdma_v4_4_2_is_queue_selected(adev, instance_id, false); 1683 if (adev->sdma.has_page_queue) 1684 adev->sdma.page_guilty = sdma_v4_4_2_is_queue_selected(adev, instance_id, true); 1685 1686 /* Cache the rptr before reset, after the reset, 1687 * all of the registers will be reset to 0 1688 */ 1689 rptr = amdgpu_ring_get_rptr(ring); 1690 ring->cached_rptr = rptr; 1691 /* Cache the rptr for the page queue if it exists */ 1692 if (adev->sdma.has_page_queue) { 1693 struct amdgpu_ring *page_ring = &adev->sdma.instance[instance_id].page; 1694 rptr = amdgpu_ring_get_rptr(page_ring); 1695 page_ring->cached_rptr = rptr; 1696 } 1697 1698 /* stop queue */ 1699 inst_mask = 1 << ring->me; 1700 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask); 1701 if (adev->sdma.has_page_queue) 1702 sdma_v4_4_2_inst_page_stop(adev, inst_mask); 1703 1704 return 0; 1705 } 1706 1707 static int sdma_v4_4_2_restore_queue(struct amdgpu_device *adev, uint32_t instance_id) 1708 { 1709 int i; 1710 u32 inst_mask; 1711 struct amdgpu_ring *ring = &adev->sdma.instance[instance_id].ring; 1712 1713 inst_mask = 1 << ring->me; 1714 udelay(50); 1715 1716 for (i = 0; i < adev->usec_timeout; i++) { 1717 if (!REG_GET_FIELD(RREG32_SDMA(ring->me, regSDMA_F32_CNTL), SDMA_F32_CNTL, HALT)) 1718 break; 1719 udelay(1); 1720 } 1721 1722 if (i == adev->usec_timeout) { 1723 dev_err(adev->dev, "timed out waiting for SDMA%d unhalt after reset\n", 1724 ring->me); 1725 return -ETIMEDOUT; 1726 } 1727 1728 return sdma_v4_4_2_inst_start(adev, inst_mask, true); 1729 } 1730 1731 static struct sdma_on_reset_funcs sdma_v4_4_2_engine_reset_funcs = { 1732 .pre_reset = sdma_v4_4_2_stop_queue, 1733 .post_reset = sdma_v4_4_2_restore_queue, 1734 }; 1735 1736 static void sdma_v4_4_2_set_engine_reset_funcs(struct amdgpu_device *adev) 1737 { 1738 amdgpu_sdma_register_on_reset_callbacks(adev, &sdma_v4_4_2_engine_reset_funcs); 1739 } 1740 1741 static int sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device *adev, 1742 struct amdgpu_irq_src *source, 1743 unsigned type, 1744 enum amdgpu_interrupt_state state) 1745 { 1746 u32 sdma_cntl; 1747 1748 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); 1749 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE, 1750 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1751 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); 1752 1753 return 0; 1754 } 1755 1756 static int sdma_v4_4_2_process_trap_irq(struct amdgpu_device *adev, 1757 struct amdgpu_irq_src *source, 1758 struct amdgpu_iv_entry *entry) 1759 { 1760 uint32_t instance, i; 1761 1762 DRM_DEBUG("IH: SDMA trap\n"); 1763 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1764 1765 /* Client id gives the SDMA instance in AID. To know the exact SDMA 1766 * instance, interrupt entry gives the node id which corresponds to the AID instance. 1767 * Match node id with the AID id associated with the SDMA instance. */ 1768 for (i = instance; i < adev->sdma.num_instances; 1769 i += adev->sdma.num_inst_per_aid) { 1770 if (adev->sdma.instance[i].aid_id == 1771 node_id_to_phys_map[entry->node_id]) 1772 break; 1773 } 1774 1775 if (i >= adev->sdma.num_instances) { 1776 dev_WARN_ONCE( 1777 adev->dev, 1, 1778 "Couldn't find the right sdma instance in trap handler"); 1779 return 0; 1780 } 1781 1782 switch (entry->ring_id) { 1783 case 0: 1784 amdgpu_fence_process(&adev->sdma.instance[i].ring); 1785 break; 1786 case 1: 1787 amdgpu_fence_process(&adev->sdma.instance[i].page); 1788 break; 1789 default: 1790 break; 1791 } 1792 return 0; 1793 } 1794 1795 #if 0 1796 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, 1797 void *err_data, 1798 struct amdgpu_iv_entry *entry) 1799 { 1800 int instance; 1801 1802 /* When “Full RAS” is enabled, the per-IP interrupt sources should 1803 * be disabled and the driver should only look for the aggregated 1804 * interrupt via sync flood 1805 */ 1806 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) 1807 goto out; 1808 1809 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1810 if (instance < 0) 1811 goto out; 1812 1813 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry); 1814 1815 out: 1816 return AMDGPU_RAS_SUCCESS; 1817 } 1818 #endif 1819 1820 static int sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device *adev, 1821 struct amdgpu_irq_src *source, 1822 struct amdgpu_iv_entry *entry) 1823 { 1824 int instance; 1825 1826 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1827 1828 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1829 if (instance < 0) 1830 return 0; 1831 1832 switch (entry->ring_id) { 1833 case 0: 1834 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 1835 break; 1836 } 1837 return 0; 1838 } 1839 1840 static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev, 1841 struct amdgpu_irq_src *source, 1842 unsigned type, 1843 enum amdgpu_interrupt_state state) 1844 { 1845 u32 sdma_cntl; 1846 1847 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); 1848 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, DRAM_ECC_INT_ENABLE, 1849 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1850 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); 1851 1852 return 0; 1853 } 1854 1855 static int sdma_v4_4_2_print_iv_entry(struct amdgpu_device *adev, 1856 struct amdgpu_iv_entry *entry) 1857 { 1858 int instance; 1859 struct amdgpu_task_info *task_info; 1860 u64 addr; 1861 1862 instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id); 1863 if (instance < 0 || instance >= adev->sdma.num_instances) { 1864 dev_err(adev->dev, "sdma instance invalid %d\n", instance); 1865 return -EINVAL; 1866 } 1867 1868 addr = (u64)entry->src_data[0] << 12; 1869 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 1870 1871 dev_dbg_ratelimited(adev->dev, 1872 "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u pasid:%u\n", 1873 instance, addr, entry->src_id, entry->ring_id, entry->vmid, 1874 entry->pasid); 1875 1876 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 1877 if (task_info) { 1878 dev_dbg_ratelimited(adev->dev, " for process %s pid %d thread %s pid %d\n", 1879 task_info->process_name, task_info->tgid, 1880 task_info->task_name, task_info->pid); 1881 amdgpu_vm_put_task_info(task_info); 1882 } 1883 1884 return 0; 1885 } 1886 1887 static int sdma_v4_4_2_process_vm_hole_irq(struct amdgpu_device *adev, 1888 struct amdgpu_irq_src *source, 1889 struct amdgpu_iv_entry *entry) 1890 { 1891 dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n"); 1892 sdma_v4_4_2_print_iv_entry(adev, entry); 1893 return 0; 1894 } 1895 1896 static int sdma_v4_4_2_process_doorbell_invalid_irq(struct amdgpu_device *adev, 1897 struct amdgpu_irq_src *source, 1898 struct amdgpu_iv_entry *entry) 1899 { 1900 1901 dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n"); 1902 sdma_v4_4_2_print_iv_entry(adev, entry); 1903 return 0; 1904 } 1905 1906 static int sdma_v4_4_2_process_pool_timeout_irq(struct amdgpu_device *adev, 1907 struct amdgpu_irq_src *source, 1908 struct amdgpu_iv_entry *entry) 1909 { 1910 dev_dbg_ratelimited(adev->dev, 1911 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n"); 1912 sdma_v4_4_2_print_iv_entry(adev, entry); 1913 return 0; 1914 } 1915 1916 static int sdma_v4_4_2_process_srbm_write_irq(struct amdgpu_device *adev, 1917 struct amdgpu_irq_src *source, 1918 struct amdgpu_iv_entry *entry) 1919 { 1920 dev_dbg_ratelimited(adev->dev, 1921 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n"); 1922 sdma_v4_4_2_print_iv_entry(adev, entry); 1923 return 0; 1924 } 1925 1926 static int sdma_v4_4_2_process_ctxt_empty_irq(struct amdgpu_device *adev, 1927 struct amdgpu_irq_src *source, 1928 struct amdgpu_iv_entry *entry) 1929 { 1930 /* There is nothing useful to be done here, only kept for debug */ 1931 dev_dbg_ratelimited(adev->dev, "SDMA context empty interrupt"); 1932 sdma_v4_4_2_print_iv_entry(adev, entry); 1933 return 0; 1934 } 1935 1936 static void sdma_v4_4_2_inst_update_medium_grain_light_sleep( 1937 struct amdgpu_device *adev, bool enable, uint32_t inst_mask) 1938 { 1939 uint32_t data, def; 1940 int i; 1941 1942 /* leave as default if it is not driver controlled */ 1943 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) 1944 return; 1945 1946 if (enable) { 1947 for_each_inst(i, inst_mask) { 1948 /* 1-not override: enable sdma mem light sleep */ 1949 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL); 1950 data |= SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1951 if (def != data) 1952 WREG32_SDMA(i, regSDMA_POWER_CNTL, data); 1953 } 1954 } else { 1955 for_each_inst(i, inst_mask) { 1956 /* 0-override:disable sdma mem light sleep */ 1957 def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL); 1958 data &= ~SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1959 if (def != data) 1960 WREG32_SDMA(i, regSDMA_POWER_CNTL, data); 1961 } 1962 } 1963 } 1964 1965 static void sdma_v4_4_2_inst_update_medium_grain_clock_gating( 1966 struct amdgpu_device *adev, bool enable, uint32_t inst_mask) 1967 { 1968 uint32_t data, def; 1969 int i; 1970 1971 /* leave as default if it is not driver controlled */ 1972 if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) 1973 return; 1974 1975 if (enable) { 1976 for_each_inst(i, inst_mask) { 1977 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL); 1978 data &= ~(SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1979 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1980 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1981 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1982 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1983 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1984 if (def != data) 1985 WREG32_SDMA(i, regSDMA_CLK_CTRL, data); 1986 } 1987 } else { 1988 for_each_inst(i, inst_mask) { 1989 def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL); 1990 data |= (SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1991 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1992 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1993 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1994 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1995 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1996 if (def != data) 1997 WREG32_SDMA(i, regSDMA_CLK_CTRL, data); 1998 } 1999 } 2000 } 2001 2002 static int sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2003 enum amd_clockgating_state state) 2004 { 2005 struct amdgpu_device *adev = ip_block->adev; 2006 uint32_t inst_mask; 2007 2008 if (amdgpu_sriov_vf(adev)) 2009 return 0; 2010 2011 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 2012 2013 sdma_v4_4_2_inst_update_medium_grain_clock_gating( 2014 adev, state == AMD_CG_STATE_GATE, inst_mask); 2015 sdma_v4_4_2_inst_update_medium_grain_light_sleep( 2016 adev, state == AMD_CG_STATE_GATE, inst_mask); 2017 return 0; 2018 } 2019 2020 static int sdma_v4_4_2_set_powergating_state(struct amdgpu_ip_block *ip_block, 2021 enum amd_powergating_state state) 2022 { 2023 return 0; 2024 } 2025 2026 static void sdma_v4_4_2_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 2027 { 2028 struct amdgpu_device *adev = ip_block->adev; 2029 int data; 2030 2031 if (amdgpu_sriov_vf(adev)) 2032 *flags = 0; 2033 2034 /* AMD_CG_SUPPORT_SDMA_MGCG */ 2035 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL)); 2036 if (!(data & SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK)) 2037 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 2038 2039 /* AMD_CG_SUPPORT_SDMA_LS */ 2040 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL)); 2041 if (data & SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 2042 *flags |= AMD_CG_SUPPORT_SDMA_LS; 2043 } 2044 2045 static void sdma_v4_4_2_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 2046 { 2047 struct amdgpu_device *adev = ip_block->adev; 2048 int i, j; 2049 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); 2050 uint32_t instance_offset; 2051 2052 if (!adev->sdma.ip_dump) 2053 return; 2054 2055 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances); 2056 for (i = 0; i < adev->sdma.num_instances; i++) { 2057 instance_offset = i * reg_count; 2058 drm_printf(p, "\nInstance:%d\n", i); 2059 2060 for (j = 0; j < reg_count; j++) 2061 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_4_4_2[j].reg_name, 2062 adev->sdma.ip_dump[instance_offset + j]); 2063 } 2064 } 2065 2066 static void sdma_v4_4_2_dump_ip_state(struct amdgpu_ip_block *ip_block) 2067 { 2068 struct amdgpu_device *adev = ip_block->adev; 2069 int i, j; 2070 uint32_t instance_offset; 2071 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); 2072 2073 if (!adev->sdma.ip_dump) 2074 return; 2075 2076 for (i = 0; i < adev->sdma.num_instances; i++) { 2077 instance_offset = i * reg_count; 2078 for (j = 0; j < reg_count; j++) 2079 adev->sdma.ip_dump[instance_offset + j] = 2080 RREG32(sdma_v4_4_2_get_reg_offset(adev, i, 2081 sdma_reg_list_4_4_2[j].reg_offset)); 2082 } 2083 } 2084 2085 const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = { 2086 .name = "sdma_v4_4_2", 2087 .early_init = sdma_v4_4_2_early_init, 2088 .late_init = sdma_v4_4_2_late_init, 2089 .sw_init = sdma_v4_4_2_sw_init, 2090 .sw_fini = sdma_v4_4_2_sw_fini, 2091 .hw_init = sdma_v4_4_2_hw_init, 2092 .hw_fini = sdma_v4_4_2_hw_fini, 2093 .suspend = sdma_v4_4_2_suspend, 2094 .resume = sdma_v4_4_2_resume, 2095 .is_idle = sdma_v4_4_2_is_idle, 2096 .wait_for_idle = sdma_v4_4_2_wait_for_idle, 2097 .soft_reset = sdma_v4_4_2_soft_reset, 2098 .set_clockgating_state = sdma_v4_4_2_set_clockgating_state, 2099 .set_powergating_state = sdma_v4_4_2_set_powergating_state, 2100 .get_clockgating_state = sdma_v4_4_2_get_clockgating_state, 2101 .dump_ip_state = sdma_v4_4_2_dump_ip_state, 2102 .print_ip_state = sdma_v4_4_2_print_ip_state, 2103 }; 2104 2105 static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = { 2106 .type = AMDGPU_RING_TYPE_SDMA, 2107 .align_mask = 0xff, 2108 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2109 .support_64bit_ptrs = true, 2110 .get_rptr = sdma_v4_4_2_ring_get_rptr, 2111 .get_wptr = sdma_v4_4_2_ring_get_wptr, 2112 .set_wptr = sdma_v4_4_2_ring_set_wptr, 2113 .emit_frame_size = 2114 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */ 2115 3 + /* hdp invalidate */ 2116 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */ 2117 /* sdma_v4_4_2_ring_emit_vm_flush */ 2118 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2119 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2120 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */ 2121 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */ 2122 .emit_ib = sdma_v4_4_2_ring_emit_ib, 2123 .emit_fence = sdma_v4_4_2_ring_emit_fence, 2124 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync, 2125 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush, 2126 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush, 2127 .test_ring = sdma_v4_4_2_ring_test_ring, 2128 .test_ib = sdma_v4_4_2_ring_test_ib, 2129 .insert_nop = sdma_v4_4_2_ring_insert_nop, 2130 .pad_ib = sdma_v4_4_2_ring_pad_ib, 2131 .emit_wreg = sdma_v4_4_2_ring_emit_wreg, 2132 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, 2133 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2134 .reset = sdma_v4_4_2_reset_queue, 2135 .is_guilty = sdma_v4_4_2_ring_is_guilty, 2136 }; 2137 2138 static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = { 2139 .type = AMDGPU_RING_TYPE_SDMA, 2140 .align_mask = 0xff, 2141 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2142 .support_64bit_ptrs = true, 2143 .get_rptr = sdma_v4_4_2_ring_get_rptr, 2144 .get_wptr = sdma_v4_4_2_page_ring_get_wptr, 2145 .set_wptr = sdma_v4_4_2_page_ring_set_wptr, 2146 .emit_frame_size = 2147 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */ 2148 3 + /* hdp invalidate */ 2149 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */ 2150 /* sdma_v4_4_2_ring_emit_vm_flush */ 2151 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2152 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2153 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */ 2154 .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */ 2155 .emit_ib = sdma_v4_4_2_ring_emit_ib, 2156 .emit_fence = sdma_v4_4_2_ring_emit_fence, 2157 .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync, 2158 .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush, 2159 .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush, 2160 .test_ring = sdma_v4_4_2_ring_test_ring, 2161 .test_ib = sdma_v4_4_2_ring_test_ib, 2162 .insert_nop = sdma_v4_4_2_ring_insert_nop, 2163 .pad_ib = sdma_v4_4_2_ring_pad_ib, 2164 .emit_wreg = sdma_v4_4_2_ring_emit_wreg, 2165 .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, 2166 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2167 .reset = sdma_v4_4_2_reset_queue, 2168 .is_guilty = sdma_v4_4_2_page_ring_is_guilty, 2169 }; 2170 2171 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev) 2172 { 2173 int i, dev_inst; 2174 2175 for (i = 0; i < adev->sdma.num_instances; i++) { 2176 adev->sdma.instance[i].ring.funcs = &sdma_v4_4_2_ring_funcs; 2177 adev->sdma.instance[i].ring.me = i; 2178 if (adev->sdma.has_page_queue) { 2179 adev->sdma.instance[i].page.funcs = 2180 &sdma_v4_4_2_page_ring_funcs; 2181 adev->sdma.instance[i].page.me = i; 2182 } 2183 2184 dev_inst = GET_INST(SDMA0, i); 2185 /* AID to which SDMA belongs depends on physical instance */ 2186 adev->sdma.instance[i].aid_id = 2187 dev_inst / adev->sdma.num_inst_per_aid; 2188 } 2189 } 2190 2191 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_trap_irq_funcs = { 2192 .set = sdma_v4_4_2_set_trap_irq_state, 2193 .process = sdma_v4_4_2_process_trap_irq, 2194 }; 2195 2196 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_illegal_inst_irq_funcs = { 2197 .process = sdma_v4_4_2_process_illegal_inst_irq, 2198 }; 2199 2200 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ecc_irq_funcs = { 2201 .set = sdma_v4_4_2_set_ecc_irq_state, 2202 .process = amdgpu_sdma_process_ecc_irq, 2203 }; 2204 2205 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_vm_hole_irq_funcs = { 2206 .process = sdma_v4_4_2_process_vm_hole_irq, 2207 }; 2208 2209 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_doorbell_invalid_irq_funcs = { 2210 .process = sdma_v4_4_2_process_doorbell_invalid_irq, 2211 }; 2212 2213 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_pool_timeout_irq_funcs = { 2214 .process = sdma_v4_4_2_process_pool_timeout_irq, 2215 }; 2216 2217 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_srbm_write_irq_funcs = { 2218 .process = sdma_v4_4_2_process_srbm_write_irq, 2219 }; 2220 2221 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ctxt_empty_irq_funcs = { 2222 .process = sdma_v4_4_2_process_ctxt_empty_irq, 2223 }; 2224 2225 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev) 2226 { 2227 adev->sdma.trap_irq.num_types = adev->sdma.num_instances; 2228 adev->sdma.ecc_irq.num_types = adev->sdma.num_instances; 2229 adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances; 2230 adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances; 2231 adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances; 2232 adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances; 2233 adev->sdma.ctxt_empty_irq.num_types = adev->sdma.num_instances; 2234 2235 adev->sdma.trap_irq.funcs = &sdma_v4_4_2_trap_irq_funcs; 2236 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_4_2_illegal_inst_irq_funcs; 2237 adev->sdma.ecc_irq.funcs = &sdma_v4_4_2_ecc_irq_funcs; 2238 adev->sdma.vm_hole_irq.funcs = &sdma_v4_4_2_vm_hole_irq_funcs; 2239 adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_4_2_doorbell_invalid_irq_funcs; 2240 adev->sdma.pool_timeout_irq.funcs = &sdma_v4_4_2_pool_timeout_irq_funcs; 2241 adev->sdma.srbm_write_irq.funcs = &sdma_v4_4_2_srbm_write_irq_funcs; 2242 adev->sdma.ctxt_empty_irq.funcs = &sdma_v4_4_2_ctxt_empty_irq_funcs; 2243 } 2244 2245 /** 2246 * sdma_v4_4_2_emit_copy_buffer - copy buffer using the sDMA engine 2247 * 2248 * @ib: indirect buffer to copy to 2249 * @src_offset: src GPU address 2250 * @dst_offset: dst GPU address 2251 * @byte_count: number of bytes to xfer 2252 * @copy_flags: copy flags for the buffers 2253 * 2254 * Copy GPU buffers using the DMA engine. 2255 * Used by the amdgpu ttm implementation to move pages if 2256 * registered as the asic copy callback. 2257 */ 2258 static void sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib *ib, 2259 uint64_t src_offset, 2260 uint64_t dst_offset, 2261 uint32_t byte_count, 2262 uint32_t copy_flags) 2263 { 2264 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 2265 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 2266 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0); 2267 ib->ptr[ib->length_dw++] = byte_count - 1; 2268 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 2269 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 2270 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 2271 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2272 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2273 } 2274 2275 /** 2276 * sdma_v4_4_2_emit_fill_buffer - fill buffer using the sDMA engine 2277 * 2278 * @ib: indirect buffer to copy to 2279 * @src_data: value to write to buffer 2280 * @dst_offset: dst GPU address 2281 * @byte_count: number of bytes to xfer 2282 * 2283 * Fill GPU buffers using the DMA engine. 2284 */ 2285 static void sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib *ib, 2286 uint32_t src_data, 2287 uint64_t dst_offset, 2288 uint32_t byte_count) 2289 { 2290 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2291 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2292 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2293 ib->ptr[ib->length_dw++] = src_data; 2294 ib->ptr[ib->length_dw++] = byte_count - 1; 2295 } 2296 2297 static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = { 2298 .copy_max_bytes = 0x400000, 2299 .copy_num_dw = 7, 2300 .emit_copy_buffer = sdma_v4_4_2_emit_copy_buffer, 2301 2302 .fill_max_bytes = 0x400000, 2303 .fill_num_dw = 5, 2304 .emit_fill_buffer = sdma_v4_4_2_emit_fill_buffer, 2305 }; 2306 2307 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev) 2308 { 2309 adev->mman.buffer_funcs = &sdma_v4_4_2_buffer_funcs; 2310 if (adev->sdma.has_page_queue) 2311 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; 2312 else 2313 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2314 } 2315 2316 static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = { 2317 .copy_pte_num_dw = 7, 2318 .copy_pte = sdma_v4_4_2_vm_copy_pte, 2319 2320 .write_pte = sdma_v4_4_2_vm_write_pte, 2321 .set_pte_pde = sdma_v4_4_2_vm_set_pte_pde, 2322 }; 2323 2324 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev) 2325 { 2326 struct drm_gpu_scheduler *sched; 2327 unsigned i; 2328 2329 adev->vm_manager.vm_pte_funcs = &sdma_v4_4_2_vm_pte_funcs; 2330 for (i = 0; i < adev->sdma.num_instances; i++) { 2331 if (adev->sdma.has_page_queue) 2332 sched = &adev->sdma.instance[i].page.sched; 2333 else 2334 sched = &adev->sdma.instance[i].ring.sched; 2335 adev->vm_manager.vm_pte_scheds[i] = sched; 2336 } 2337 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 2338 } 2339 2340 /** 2341 * sdma_v4_4_2_update_reset_mask - update reset mask for SDMA 2342 * @adev: Pointer to the AMDGPU device structure 2343 * 2344 * This function update reset mask for SDMA and sets the supported 2345 * reset types based on the IP version and firmware versions. 2346 * 2347 */ 2348 static void sdma_v4_4_2_update_reset_mask(struct amdgpu_device *adev) 2349 { 2350 2351 /* 2352 * the user queue relies on MEC fw and pmfw when the sdma queue do reset. 2353 * it needs to check both of them at here to skip old mec and pmfw. 2354 */ 2355 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2356 case IP_VERSION(9, 4, 3): 2357 case IP_VERSION(9, 4, 4): 2358 if ((adev->gfx.mec_fw_version >= 0xb0) && amdgpu_dpm_reset_sdma_is_supported(adev)) 2359 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 2360 break; 2361 case IP_VERSION(9, 5, 0): 2362 /*TODO: enable the queue reset flag until fw supported */ 2363 default: 2364 break; 2365 } 2366 2367 } 2368 2369 const struct amdgpu_ip_block_version sdma_v4_4_2_ip_block = { 2370 .type = AMD_IP_BLOCK_TYPE_SDMA, 2371 .major = 4, 2372 .minor = 4, 2373 .rev = 2, 2374 .funcs = &sdma_v4_4_2_ip_funcs, 2375 }; 2376 2377 static int sdma_v4_4_2_xcp_resume(void *handle, uint32_t inst_mask) 2378 { 2379 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2380 int r; 2381 2382 if (!amdgpu_sriov_vf(adev)) 2383 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask); 2384 2385 r = sdma_v4_4_2_inst_start(adev, inst_mask, false); 2386 2387 return r; 2388 } 2389 2390 static int sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask) 2391 { 2392 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2393 uint32_t tmp_mask = inst_mask; 2394 int i; 2395 2396 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2397 for_each_inst(i, tmp_mask) { 2398 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 2399 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 2400 } 2401 } 2402 2403 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask); 2404 sdma_v4_4_2_inst_enable(adev, false, inst_mask); 2405 2406 return 0; 2407 } 2408 2409 struct amdgpu_xcp_ip_funcs sdma_v4_4_2_xcp_funcs = { 2410 .suspend = &sdma_v4_4_2_xcp_suspend, 2411 .resume = &sdma_v4_4_2_xcp_resume 2412 }; 2413 2414 static const struct amdgpu_ras_err_status_reg_entry sdma_v4_2_2_ue_reg_list[] = { 2415 {AMDGPU_RAS_REG_ENTRY(SDMA0, 0, regSDMA_UE_ERR_STATUS_LO, regSDMA_UE_ERR_STATUS_HI), 2416 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SDMA"}, 2417 }; 2418 2419 static const struct amdgpu_ras_memory_id_entry sdma_v4_4_2_ras_memory_list[] = { 2420 {AMDGPU_SDMA_MBANK_DATA_BUF0, "SDMA_MBANK_DATA_BUF0"}, 2421 {AMDGPU_SDMA_MBANK_DATA_BUF1, "SDMA_MBANK_DATA_BUF1"}, 2422 {AMDGPU_SDMA_MBANK_DATA_BUF2, "SDMA_MBANK_DATA_BUF2"}, 2423 {AMDGPU_SDMA_MBANK_DATA_BUF3, "SDMA_MBANK_DATA_BUF3"}, 2424 {AMDGPU_SDMA_MBANK_DATA_BUF4, "SDMA_MBANK_DATA_BUF4"}, 2425 {AMDGPU_SDMA_MBANK_DATA_BUF5, "SDMA_MBANK_DATA_BUF5"}, 2426 {AMDGPU_SDMA_MBANK_DATA_BUF6, "SDMA_MBANK_DATA_BUF6"}, 2427 {AMDGPU_SDMA_MBANK_DATA_BUF7, "SDMA_MBANK_DATA_BUF7"}, 2428 {AMDGPU_SDMA_MBANK_DATA_BUF8, "SDMA_MBANK_DATA_BUF8"}, 2429 {AMDGPU_SDMA_MBANK_DATA_BUF9, "SDMA_MBANK_DATA_BUF9"}, 2430 {AMDGPU_SDMA_MBANK_DATA_BUF10, "SDMA_MBANK_DATA_BUF10"}, 2431 {AMDGPU_SDMA_MBANK_DATA_BUF11, "SDMA_MBANK_DATA_BUF11"}, 2432 {AMDGPU_SDMA_MBANK_DATA_BUF12, "SDMA_MBANK_DATA_BUF12"}, 2433 {AMDGPU_SDMA_MBANK_DATA_BUF13, "SDMA_MBANK_DATA_BUF13"}, 2434 {AMDGPU_SDMA_MBANK_DATA_BUF14, "SDMA_MBANK_DATA_BUF14"}, 2435 {AMDGPU_SDMA_MBANK_DATA_BUF15, "SDMA_MBANK_DATA_BUF15"}, 2436 {AMDGPU_SDMA_UCODE_BUF, "SDMA_UCODE_BUF"}, 2437 {AMDGPU_SDMA_RB_CMD_BUF, "SDMA_RB_CMD_BUF"}, 2438 {AMDGPU_SDMA_IB_CMD_BUF, "SDMA_IB_CMD_BUF"}, 2439 {AMDGPU_SDMA_UTCL1_RD_FIFO, "SDMA_UTCL1_RD_FIFO"}, 2440 {AMDGPU_SDMA_UTCL1_RDBST_FIFO, "SDMA_UTCL1_RDBST_FIFO"}, 2441 {AMDGPU_SDMA_UTCL1_WR_FIFO, "SDMA_UTCL1_WR_FIFO"}, 2442 {AMDGPU_SDMA_DATA_LUT_FIFO, "SDMA_DATA_LUT_FIFO"}, 2443 {AMDGPU_SDMA_SPLIT_DAT_BUF, "SDMA_SPLIT_DAT_BUF"}, 2444 }; 2445 2446 static void sdma_v4_4_2_inst_query_ras_error_count(struct amdgpu_device *adev, 2447 uint32_t sdma_inst, 2448 void *ras_err_status) 2449 { 2450 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 2451 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); 2452 unsigned long ue_count = 0; 2453 struct amdgpu_smuio_mcm_config_info mcm_info = { 2454 .socket_id = adev->smuio.funcs->get_socket_id(adev), 2455 .die_id = adev->sdma.instance[sdma_inst].aid_id, 2456 }; 2457 2458 /* sdma v4_4_2 doesn't support query ce counts */ 2459 amdgpu_ras_inst_query_ras_error_count(adev, 2460 sdma_v4_2_2_ue_reg_list, 2461 ARRAY_SIZE(sdma_v4_2_2_ue_reg_list), 2462 sdma_v4_4_2_ras_memory_list, 2463 ARRAY_SIZE(sdma_v4_4_2_ras_memory_list), 2464 sdma_dev_inst, 2465 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 2466 &ue_count); 2467 2468 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count); 2469 } 2470 2471 static void sdma_v4_4_2_query_ras_error_count(struct amdgpu_device *adev, 2472 void *ras_err_status) 2473 { 2474 uint32_t inst_mask; 2475 int i = 0; 2476 2477 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 2478 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2479 for_each_inst(i, inst_mask) 2480 sdma_v4_4_2_inst_query_ras_error_count(adev, i, ras_err_status); 2481 } else { 2482 dev_warn(adev->dev, "SDMA RAS is not supported\n"); 2483 } 2484 } 2485 2486 static void sdma_v4_4_2_inst_reset_ras_error_count(struct amdgpu_device *adev, 2487 uint32_t sdma_inst) 2488 { 2489 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); 2490 2491 amdgpu_ras_inst_reset_ras_error_count(adev, 2492 sdma_v4_2_2_ue_reg_list, 2493 ARRAY_SIZE(sdma_v4_2_2_ue_reg_list), 2494 sdma_dev_inst); 2495 } 2496 2497 static void sdma_v4_4_2_reset_ras_error_count(struct amdgpu_device *adev) 2498 { 2499 uint32_t inst_mask; 2500 int i = 0; 2501 2502 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); 2503 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2504 for_each_inst(i, inst_mask) 2505 sdma_v4_4_2_inst_reset_ras_error_count(adev, i); 2506 } else { 2507 dev_warn(adev->dev, "SDMA RAS is not supported\n"); 2508 } 2509 } 2510 2511 static const struct amdgpu_ras_block_hw_ops sdma_v4_4_2_ras_hw_ops = { 2512 .query_ras_error_count = sdma_v4_4_2_query_ras_error_count, 2513 .reset_ras_error_count = sdma_v4_4_2_reset_ras_error_count, 2514 }; 2515 2516 static int sdma_v4_4_2_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, 2517 enum aca_smu_type type, void *data) 2518 { 2519 struct aca_bank_info info; 2520 u64 misc0; 2521 int ret; 2522 2523 ret = aca_bank_info_decode(bank, &info); 2524 if (ret) 2525 return ret; 2526 2527 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 2528 switch (type) { 2529 case ACA_SMU_TYPE_UE: 2530 bank->aca_err_type = ACA_ERROR_TYPE_UE; 2531 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE, 2532 1ULL); 2533 break; 2534 case ACA_SMU_TYPE_CE: 2535 bank->aca_err_type = ACA_BANK_ERR_CE_DE_DECODE(bank); 2536 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 2537 ACA_REG__MISC0__ERRCNT(misc0)); 2538 break; 2539 default: 2540 return -EINVAL; 2541 } 2542 2543 return ret; 2544 } 2545 2546 /* CODE_SDMA0 - CODE_SDMA4, reference to smu driver if header file */ 2547 static int sdma_v4_4_2_err_codes[] = { 33, 34, 35, 36 }; 2548 2549 static bool sdma_v4_4_2_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 2550 enum aca_smu_type type, void *data) 2551 { 2552 u32 instlo; 2553 2554 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 2555 instlo &= GENMASK(31, 1); 2556 2557 if (instlo != mmSMNAID_AID0_MCA_SMU) 2558 return false; 2559 2560 if (aca_bank_check_error_codes(handle->adev, bank, 2561 sdma_v4_4_2_err_codes, 2562 ARRAY_SIZE(sdma_v4_4_2_err_codes))) 2563 return false; 2564 2565 return true; 2566 } 2567 2568 static const struct aca_bank_ops sdma_v4_4_2_aca_bank_ops = { 2569 .aca_bank_parser = sdma_v4_4_2_aca_bank_parser, 2570 .aca_bank_is_valid = sdma_v4_4_2_aca_bank_is_valid, 2571 }; 2572 2573 static const struct aca_info sdma_v4_4_2_aca_info = { 2574 .hwip = ACA_HWIP_TYPE_SMU, 2575 .mask = ACA_ERROR_UE_MASK, 2576 .bank_ops = &sdma_v4_4_2_aca_bank_ops, 2577 }; 2578 2579 static int sdma_v4_4_2_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 2580 { 2581 int r; 2582 2583 r = amdgpu_sdma_ras_late_init(adev, ras_block); 2584 if (r) 2585 return r; 2586 2587 return amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__SDMA, 2588 &sdma_v4_4_2_aca_info, NULL); 2589 } 2590 2591 static struct amdgpu_sdma_ras sdma_v4_4_2_ras = { 2592 .ras_block = { 2593 .hw_ops = &sdma_v4_4_2_ras_hw_ops, 2594 .ras_late_init = sdma_v4_4_2_ras_late_init, 2595 }, 2596 }; 2597 2598 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev) 2599 { 2600 adev->sdma.ras = &sdma_v4_4_2_ras; 2601 } 2602