1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "sdma0/sdma0_4_2_offset.h" 34 #include "sdma0/sdma0_4_2_sh_mask.h" 35 #include "sdma1/sdma1_4_2_offset.h" 36 #include "sdma1/sdma1_4_2_sh_mask.h" 37 #include "sdma2/sdma2_4_2_2_offset.h" 38 #include "sdma2/sdma2_4_2_2_sh_mask.h" 39 #include "sdma3/sdma3_4_2_2_offset.h" 40 #include "sdma3/sdma3_4_2_2_sh_mask.h" 41 #include "sdma4/sdma4_4_2_2_offset.h" 42 #include "sdma4/sdma4_4_2_2_sh_mask.h" 43 #include "sdma5/sdma5_4_2_2_offset.h" 44 #include "sdma5/sdma5_4_2_2_sh_mask.h" 45 #include "sdma6/sdma6_4_2_2_offset.h" 46 #include "sdma6/sdma6_4_2_2_sh_mask.h" 47 #include "sdma7/sdma7_4_2_2_offset.h" 48 #include "sdma7/sdma7_4_2_2_sh_mask.h" 49 #include "sdma0/sdma0_4_1_default.h" 50 51 #include "soc15_common.h" 52 #include "soc15.h" 53 #include "vega10_sdma_pkt_open.h" 54 55 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 56 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 57 58 #include "amdgpu_ras.h" 59 #include "sdma_v4_4.h" 60 61 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); 62 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); 63 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin"); 65 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin"); 66 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin"); 67 MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); 68 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin"); 69 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin"); 70 MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin"); 71 MODULE_FIRMWARE("amdgpu/renoir_sdma.bin"); 72 MODULE_FIRMWARE("amdgpu/green_sardine_sdma.bin"); 73 MODULE_FIRMWARE("amdgpu/aldebaran_sdma.bin"); 74 75 static const struct amdgpu_hwip_reg_entry sdma_reg_list_4_0[] = { 76 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG), 77 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG), 78 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG), 79 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG), 80 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UCODE_CHECKSUM), 81 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH_HI), 82 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH), 83 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_STATUS), 84 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_STATUS), 85 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK0), 86 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK1), 87 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK0), 88 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK1), 89 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_CNTL), 90 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR), 91 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR_HI), 92 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR), 93 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR_HI), 94 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_OFFSET), 95 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_LO), 96 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_HI), 97 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_CNTL), 98 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_RPTR), 99 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_SUB_REMAIN), 100 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_DUMMY_REG), 101 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_CNTL), 102 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR), 103 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR_HI), 104 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR), 105 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR_HI), 106 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_OFFSET), 107 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_LO), 108 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_HI), 109 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_DUMMY_REG), 110 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_CNTL), 111 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR), 112 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR_HI), 113 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR), 114 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR_HI), 115 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_OFFSET), 116 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_LO), 117 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_HI), 118 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_DUMMY_REG), 119 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_VM_CNTL) 120 }; 121 122 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 123 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 124 125 #define WREG32_SDMA(instance, offset, value) \ 126 WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value) 127 #define RREG32_SDMA(instance, offset) \ 128 RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset))) 129 130 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); 131 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); 132 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); 133 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev); 134 135 static const struct soc15_reg_golden golden_settings_sdma_4[] = { 136 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 137 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100), 138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100), 139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 142 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000), 143 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 144 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 146 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 147 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 148 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000), 149 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 150 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100), 151 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 152 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 153 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 154 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000), 155 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 156 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 157 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 158 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 159 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 160 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000) 161 }; 162 163 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { 164 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 165 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 166 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 167 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 168 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 169 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 170 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 171 }; 172 173 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = { 174 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 175 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 176 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 177 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 178 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 179 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 180 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 181 }; 182 183 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = { 184 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 185 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 186 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100), 187 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 188 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051), 189 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100), 190 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 191 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100), 192 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 193 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003e0), 194 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000) 195 }; 196 197 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = { 198 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 199 }; 200 201 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] = 202 { 203 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 204 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 205 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 206 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 207 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 208 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 209 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 210 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 211 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003), 212 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 213 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 214 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 215 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 216 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 217 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 218 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 219 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 220 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 221 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 222 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 223 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 224 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 225 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 226 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 227 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 228 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 229 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 230 }; 231 232 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = { 233 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 234 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 235 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 236 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 237 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 238 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 239 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 240 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 241 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003), 242 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 243 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 244 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 245 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 246 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 247 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 248 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 249 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 250 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 251 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 252 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 253 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 254 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 255 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 256 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 257 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 258 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 259 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 260 }; 261 262 static const struct soc15_reg_golden golden_settings_sdma_rv1[] = 263 { 264 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 265 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002) 266 }; 267 268 static const struct soc15_reg_golden golden_settings_sdma_rv2[] = 269 { 270 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001), 271 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001) 272 }; 273 274 static const struct soc15_reg_golden golden_settings_sdma_arct[] = 275 { 276 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 277 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 278 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 279 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 280 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 281 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 282 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 283 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 284 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 285 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 286 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 287 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 288 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 289 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 290 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 291 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 292 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 293 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 294 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 295 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 296 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 297 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 298 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 299 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 300 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 301 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 302 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 303 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 304 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 305 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 306 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 307 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_UTCL1_TIMEOUT, 0xffffffff, 0x00010001) 308 }; 309 310 static const struct soc15_reg_golden golden_settings_sdma_aldebaran[] = { 311 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 312 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 313 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 314 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 315 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 316 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 317 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 318 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 319 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 320 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 321 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 322 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 323 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 324 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 325 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 326 }; 327 328 static const struct soc15_reg_golden golden_settings_sdma_4_3[] = { 329 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 330 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 331 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 332 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002), 333 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 334 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051), 335 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 336 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 337 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003e0), 338 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x03fbe1fe) 339 }; 340 341 static const struct soc15_ras_field_entry sdma_v4_0_ras_fields[] = { 342 { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 343 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UCODE_BUF_SED), 344 0, 0, 345 }, 346 { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 347 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_RB_CMD_BUF_SED), 348 0, 0, 349 }, 350 { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 351 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_IB_CMD_BUF_SED), 352 0, 0, 353 }, 354 { "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 355 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RD_FIFO_SED), 356 0, 0, 357 }, 358 { "SDMA_UTCL1_RDBST_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 359 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RDBST_FIFO_SED), 360 0, 0, 361 }, 362 { "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 363 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_DATA_LUT_FIFO_SED), 364 0, 0, 365 }, 366 { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 367 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF0_SED), 368 0, 0, 369 }, 370 { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 371 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF1_SED), 372 0, 0, 373 }, 374 { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 375 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF2_SED), 376 0, 0, 377 }, 378 { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 379 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF3_SED), 380 0, 0, 381 }, 382 { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 383 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF4_SED), 384 0, 0, 385 }, 386 { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 387 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF5_SED), 388 0, 0, 389 }, 390 { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 391 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF6_SED), 392 0, 0, 393 }, 394 { "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 395 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF7_SED), 396 0, 0, 397 }, 398 { "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 399 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF8_SED), 400 0, 0, 401 }, 402 { "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 403 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF9_SED), 404 0, 0, 405 }, 406 { "SDMA_MBANK_DATA_BUF10_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 407 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF10_SED), 408 0, 0, 409 }, 410 { "SDMA_MBANK_DATA_BUF11_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 411 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF11_SED), 412 0, 0, 413 }, 414 { "SDMA_MBANK_DATA_BUF12_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 415 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF12_SED), 416 0, 0, 417 }, 418 { "SDMA_MBANK_DATA_BUF13_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 419 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF13_SED), 420 0, 0, 421 }, 422 { "SDMA_MBANK_DATA_BUF14_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 423 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF14_SED), 424 0, 0, 425 }, 426 { "SDMA_MBANK_DATA_BUF15_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 427 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF15_SED), 428 0, 0, 429 }, 430 { "SDMA_SPLIT_DAT_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 431 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_SPLIT_DAT_BUF_SED), 432 0, 0, 433 }, 434 { "SDMA_MC_WR_ADDR_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 435 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MC_WR_ADDR_FIFO_SED), 436 0, 0, 437 }, 438 }; 439 440 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, 441 u32 instance, u32 offset) 442 { 443 switch (instance) { 444 case 0: 445 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset); 446 case 1: 447 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset); 448 case 2: 449 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset); 450 case 3: 451 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset); 452 case 4: 453 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset); 454 case 5: 455 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset); 456 case 6: 457 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset); 458 case 7: 459 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset); 460 default: 461 break; 462 } 463 return 0; 464 } 465 466 static unsigned sdma_v4_0_seq_to_irq_id(int seq_num) 467 { 468 switch (seq_num) { 469 case 0: 470 return SOC15_IH_CLIENTID_SDMA0; 471 case 1: 472 return SOC15_IH_CLIENTID_SDMA1; 473 case 2: 474 return SOC15_IH_CLIENTID_SDMA2; 475 case 3: 476 return SOC15_IH_CLIENTID_SDMA3; 477 case 4: 478 return SOC15_IH_CLIENTID_SDMA4; 479 case 5: 480 return SOC15_IH_CLIENTID_SDMA5; 481 case 6: 482 return SOC15_IH_CLIENTID_SDMA6; 483 case 7: 484 return SOC15_IH_CLIENTID_SDMA7; 485 default: 486 break; 487 } 488 return -EINVAL; 489 } 490 491 static int sdma_v4_0_irq_id_to_seq(unsigned client_id) 492 { 493 switch (client_id) { 494 case SOC15_IH_CLIENTID_SDMA0: 495 return 0; 496 case SOC15_IH_CLIENTID_SDMA1: 497 return 1; 498 case SOC15_IH_CLIENTID_SDMA2: 499 return 2; 500 case SOC15_IH_CLIENTID_SDMA3: 501 return 3; 502 case SOC15_IH_CLIENTID_SDMA4: 503 return 4; 504 case SOC15_IH_CLIENTID_SDMA5: 505 return 5; 506 case SOC15_IH_CLIENTID_SDMA6: 507 return 6; 508 case SOC15_IH_CLIENTID_SDMA7: 509 return 7; 510 default: 511 break; 512 } 513 return -EINVAL; 514 } 515 516 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 517 { 518 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 519 case IP_VERSION(4, 0, 0): 520 soc15_program_register_sequence(adev, 521 golden_settings_sdma_4, 522 ARRAY_SIZE(golden_settings_sdma_4)); 523 soc15_program_register_sequence(adev, 524 golden_settings_sdma_vg10, 525 ARRAY_SIZE(golden_settings_sdma_vg10)); 526 break; 527 case IP_VERSION(4, 0, 1): 528 soc15_program_register_sequence(adev, 529 golden_settings_sdma_4, 530 ARRAY_SIZE(golden_settings_sdma_4)); 531 soc15_program_register_sequence(adev, 532 golden_settings_sdma_vg12, 533 ARRAY_SIZE(golden_settings_sdma_vg12)); 534 break; 535 case IP_VERSION(4, 2, 0): 536 soc15_program_register_sequence(adev, 537 golden_settings_sdma0_4_2_init, 538 ARRAY_SIZE(golden_settings_sdma0_4_2_init)); 539 soc15_program_register_sequence(adev, 540 golden_settings_sdma0_4_2, 541 ARRAY_SIZE(golden_settings_sdma0_4_2)); 542 soc15_program_register_sequence(adev, 543 golden_settings_sdma1_4_2, 544 ARRAY_SIZE(golden_settings_sdma1_4_2)); 545 break; 546 case IP_VERSION(4, 2, 2): 547 soc15_program_register_sequence(adev, 548 golden_settings_sdma_arct, 549 ARRAY_SIZE(golden_settings_sdma_arct)); 550 break; 551 case IP_VERSION(4, 4, 0): 552 soc15_program_register_sequence(adev, 553 golden_settings_sdma_aldebaran, 554 ARRAY_SIZE(golden_settings_sdma_aldebaran)); 555 break; 556 case IP_VERSION(4, 1, 0): 557 case IP_VERSION(4, 1, 1): 558 soc15_program_register_sequence(adev, 559 golden_settings_sdma_4_1, 560 ARRAY_SIZE(golden_settings_sdma_4_1)); 561 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 562 soc15_program_register_sequence(adev, 563 golden_settings_sdma_rv2, 564 ARRAY_SIZE(golden_settings_sdma_rv2)); 565 else 566 soc15_program_register_sequence(adev, 567 golden_settings_sdma_rv1, 568 ARRAY_SIZE(golden_settings_sdma_rv1)); 569 break; 570 case IP_VERSION(4, 1, 2): 571 soc15_program_register_sequence(adev, 572 golden_settings_sdma_4_3, 573 ARRAY_SIZE(golden_settings_sdma_4_3)); 574 break; 575 default: 576 break; 577 } 578 } 579 580 static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev) 581 { 582 int i; 583 584 /* 585 * The only chips with SDMAv4 and ULV are VG10 and VG20. 586 * Server SKUs take a different hysteresis setting from other SKUs. 587 */ 588 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 589 case IP_VERSION(4, 0, 0): 590 if (adev->pdev->device == 0x6860) 591 break; 592 return; 593 case IP_VERSION(4, 2, 0): 594 if (adev->pdev->device == 0x66a1) 595 break; 596 return; 597 default: 598 return; 599 } 600 601 for (i = 0; i < adev->sdma.num_instances; i++) { 602 uint32_t temp; 603 604 temp = RREG32_SDMA(i, mmSDMA0_ULV_CNTL); 605 temp = REG_SET_FIELD(temp, SDMA0_ULV_CNTL, HYSTERESIS, 0x0); 606 WREG32_SDMA(i, mmSDMA0_ULV_CNTL, temp); 607 } 608 } 609 610 /** 611 * sdma_v4_0_init_microcode - load ucode images from disk 612 * 613 * @adev: amdgpu_device pointer 614 * 615 * Use the firmware interface to load the ucode images into 616 * the driver (not loaded into hw). 617 * Returns 0 on success, error on failure. 618 */ 619 620 // emulation only, won't work on real chip 621 // vega10 real chip need to use PSP to load firmware 622 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) 623 { 624 int ret, i; 625 626 for (i = 0; i < adev->sdma.num_instances; i++) { 627 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == 628 IP_VERSION(4, 2, 2) || 629 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == 630 IP_VERSION(4, 4, 0)) { 631 /* Acturus & Aldebaran will leverage the same FW memory 632 for every SDMA instance */ 633 ret = amdgpu_sdma_init_microcode(adev, 0, true); 634 break; 635 } else { 636 ret = amdgpu_sdma_init_microcode(adev, i, false); 637 if (ret) 638 return ret; 639 } 640 } 641 642 return ret; 643 } 644 645 /** 646 * sdma_v4_0_ring_get_rptr - get the current read pointer 647 * 648 * @ring: amdgpu ring pointer 649 * 650 * Get the current rptr from the hardware (VEGA10+). 651 */ 652 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) 653 { 654 u64 *rptr; 655 656 /* XXX check if swapping is necessary on BE */ 657 rptr = ((u64 *)ring->rptr_cpu_addr); 658 659 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 660 return ((*rptr) >> 2); 661 } 662 663 /** 664 * sdma_v4_0_ring_get_wptr - get the current write pointer 665 * 666 * @ring: amdgpu ring pointer 667 * 668 * Get the current wptr from the hardware (VEGA10+). 669 */ 670 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 671 { 672 struct amdgpu_device *adev = ring->adev; 673 u64 wptr; 674 675 if (ring->use_doorbell) { 676 /* XXX check if swapping is necessary on BE */ 677 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 678 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 679 } else { 680 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI); 681 wptr = wptr << 32; 682 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR); 683 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 684 ring->me, wptr); 685 } 686 687 return wptr >> 2; 688 } 689 690 /** 691 * sdma_v4_0_ring_set_wptr - commit the write pointer 692 * 693 * @ring: amdgpu ring pointer 694 * 695 * Write the wptr back to the hardware (VEGA10+). 696 */ 697 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) 698 { 699 struct amdgpu_device *adev = ring->adev; 700 701 DRM_DEBUG("Setting write pointer\n"); 702 if (ring->use_doorbell) { 703 u64 *wb = (u64 *)ring->wptr_cpu_addr; 704 705 DRM_DEBUG("Using doorbell -- " 706 "wptr_offs == 0x%08x " 707 "lower_32_bits(ring->wptr << 2) == 0x%08x " 708 "upper_32_bits(ring->wptr << 2) == 0x%08x\n", 709 ring->wptr_offs, 710 lower_32_bits(ring->wptr << 2), 711 upper_32_bits(ring->wptr << 2)); 712 /* XXX check if swapping is necessary on BE */ 713 WRITE_ONCE(*wb, (ring->wptr << 2)); 714 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 715 ring->doorbell_index, ring->wptr << 2); 716 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 717 } else { 718 DRM_DEBUG("Not using doorbell -- " 719 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 720 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 721 ring->me, 722 lower_32_bits(ring->wptr << 2), 723 ring->me, 724 upper_32_bits(ring->wptr << 2)); 725 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR, 726 lower_32_bits(ring->wptr << 2)); 727 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI, 728 upper_32_bits(ring->wptr << 2)); 729 } 730 } 731 732 /** 733 * sdma_v4_0_page_ring_get_wptr - get the current write pointer 734 * 735 * @ring: amdgpu ring pointer 736 * 737 * Get the current wptr from the hardware (VEGA10+). 738 */ 739 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring) 740 { 741 struct amdgpu_device *adev = ring->adev; 742 u64 wptr; 743 744 if (ring->use_doorbell) { 745 /* XXX check if swapping is necessary on BE */ 746 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 747 } else { 748 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI); 749 wptr = wptr << 32; 750 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR); 751 } 752 753 return wptr >> 2; 754 } 755 756 /** 757 * sdma_v4_0_page_ring_set_wptr - commit the write pointer 758 * 759 * @ring: amdgpu ring pointer 760 * 761 * Write the wptr back to the hardware (VEGA10+). 762 */ 763 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring) 764 { 765 struct amdgpu_device *adev = ring->adev; 766 767 if (ring->use_doorbell) { 768 u64 *wb = (u64 *)ring->wptr_cpu_addr; 769 770 /* XXX check if swapping is necessary on BE */ 771 WRITE_ONCE(*wb, (ring->wptr << 2)); 772 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 773 } else { 774 uint64_t wptr = ring->wptr << 2; 775 776 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR, 777 lower_32_bits(wptr)); 778 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI, 779 upper_32_bits(wptr)); 780 } 781 } 782 783 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 784 { 785 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 786 int i; 787 788 for (i = 0; i < count; i++) 789 if (sdma && sdma->burst_nop && (i == 0)) 790 amdgpu_ring_write(ring, ring->funcs->nop | 791 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 792 else 793 amdgpu_ring_write(ring, ring->funcs->nop); 794 } 795 796 /** 797 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine 798 * 799 * @ring: amdgpu ring pointer 800 * @job: job to retrieve vmid from 801 * @ib: IB object to schedule 802 * @flags: unused 803 * 804 * Schedule an IB in the DMA ring (VEGA10). 805 */ 806 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 807 struct amdgpu_job *job, 808 struct amdgpu_ib *ib, 809 uint32_t flags) 810 { 811 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 812 813 /* IB packet must end on a 8 DW boundary */ 814 sdma_v4_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 815 816 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 817 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 818 /* base must be 32 byte aligned */ 819 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 820 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 821 amdgpu_ring_write(ring, ib->length_dw); 822 amdgpu_ring_write(ring, 0); 823 amdgpu_ring_write(ring, 0); 824 825 } 826 827 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring, 828 int mem_space, int hdp, 829 uint32_t addr0, uint32_t addr1, 830 uint32_t ref, uint32_t mask, 831 uint32_t inv) 832 { 833 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 834 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 835 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 836 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 837 if (mem_space) { 838 /* memory */ 839 amdgpu_ring_write(ring, addr0); 840 amdgpu_ring_write(ring, addr1); 841 } else { 842 /* registers */ 843 amdgpu_ring_write(ring, addr0 << 2); 844 amdgpu_ring_write(ring, addr1 << 2); 845 } 846 amdgpu_ring_write(ring, ref); /* reference */ 847 amdgpu_ring_write(ring, mask); /* mask */ 848 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 849 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 850 } 851 852 /** 853 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 854 * 855 * @ring: amdgpu ring pointer 856 * 857 * Emit an hdp flush packet on the requested DMA ring. 858 */ 859 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 860 { 861 struct amdgpu_device *adev = ring->adev; 862 u32 ref_and_mask = 0; 863 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 864 865 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 866 867 sdma_v4_0_wait_reg_mem(ring, 0, 1, 868 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 869 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 870 ref_and_mask, ref_and_mask, 10); 871 } 872 873 /** 874 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring 875 * 876 * @ring: amdgpu ring pointer 877 * @addr: address 878 * @seq: sequence number 879 * @flags: fence related flags 880 * 881 * Add a DMA fence packet to the ring to write 882 * the fence seq number and DMA trap packet to generate 883 * an interrupt if needed (VEGA10). 884 */ 885 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 886 unsigned flags) 887 { 888 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 889 /* write the fence */ 890 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 891 /* zero in first two bits */ 892 WARN_ON(addr & 0x3); 893 amdgpu_ring_write(ring, lower_32_bits(addr)); 894 amdgpu_ring_write(ring, upper_32_bits(addr)); 895 amdgpu_ring_write(ring, lower_32_bits(seq)); 896 897 /* optionally write high bits as well */ 898 if (write64bit) { 899 addr += 4; 900 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 901 /* zero in first two bits */ 902 WARN_ON(addr & 0x3); 903 amdgpu_ring_write(ring, lower_32_bits(addr)); 904 amdgpu_ring_write(ring, upper_32_bits(addr)); 905 amdgpu_ring_write(ring, upper_32_bits(seq)); 906 } 907 908 /* generate an interrupt */ 909 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 910 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 911 } 912 913 914 /** 915 * sdma_v4_0_gfx_enable - enable the gfx async dma engines 916 * 917 * @adev: amdgpu_device pointer 918 * @enable: enable SDMA RB/IB 919 * control the gfx async dma ring buffers (VEGA10). 920 */ 921 static void sdma_v4_0_gfx_enable(struct amdgpu_device *adev, bool enable) 922 { 923 u32 rb_cntl, ib_cntl; 924 int i; 925 926 for (i = 0; i < adev->sdma.num_instances; i++) { 927 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 928 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, enable ? 1 : 0); 929 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 930 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 931 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, enable ? 1 : 0); 932 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 933 } 934 } 935 936 /** 937 * sdma_v4_0_rlc_stop - stop the compute async dma engines 938 * 939 * @adev: amdgpu_device pointer 940 * 941 * Stop the compute async dma queues (VEGA10). 942 */ 943 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev) 944 { 945 /* XXX todo */ 946 } 947 948 /** 949 * sdma_v4_0_page_stop - stop the page async dma engines 950 * 951 * @adev: amdgpu_device pointer 952 * 953 * Stop the page async dma ring buffers (VEGA10). 954 */ 955 static void sdma_v4_0_page_stop(struct amdgpu_device *adev) 956 { 957 u32 rb_cntl, ib_cntl; 958 int i; 959 960 for (i = 0; i < adev->sdma.num_instances; i++) { 961 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 962 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 963 RB_ENABLE, 0); 964 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 965 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 966 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, 967 IB_ENABLE, 0); 968 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 969 } 970 } 971 972 /** 973 * sdma_v4_0_ctx_switch_enable - stop the async dma engines context switch 974 * 975 * @adev: amdgpu_device pointer 976 * @enable: enable/disable the DMA MEs context switch. 977 * 978 * Halt or unhalt the async dma engines context switch (VEGA10). 979 */ 980 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 981 { 982 u32 f32_cntl, phase_quantum = 0; 983 int i; 984 985 if (amdgpu_sdma_phase_quantum) { 986 unsigned value = amdgpu_sdma_phase_quantum; 987 unsigned unit = 0; 988 989 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 990 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 991 value = (value + 1) >> 1; 992 unit++; 993 } 994 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 995 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 996 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 997 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 998 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 999 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 1000 WARN_ONCE(1, 1001 "clamping sdma_phase_quantum to %uK clock cycles\n", 1002 value << unit); 1003 } 1004 phase_quantum = 1005 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 1006 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 1007 } 1008 1009 for (i = 0; i < adev->sdma.num_instances; i++) { 1010 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL); 1011 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 1012 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 1013 if (enable && amdgpu_sdma_phase_quantum) { 1014 WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum); 1015 WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum); 1016 WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum); 1017 } 1018 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl); 1019 1020 /* 1021 * Enable SDMA utilization. Its only supported on 1022 * Arcturus for the moment and firmware version 14 1023 * and above. 1024 */ 1025 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == 1026 IP_VERSION(4, 2, 2) && 1027 adev->sdma.instance[i].fw_version >= 14) 1028 WREG32_SDMA(i, mmSDMA0_PUB_DUMMY_REG2, enable); 1029 /* Extend page fault timeout to avoid interrupt storm */ 1030 WREG32_SDMA(i, mmSDMA0_UTCL1_TIMEOUT, 0x00800080); 1031 } 1032 1033 } 1034 1035 /** 1036 * sdma_v4_0_enable - stop the async dma engines 1037 * 1038 * @adev: amdgpu_device pointer 1039 * @enable: enable/disable the DMA MEs. 1040 * 1041 * Halt or unhalt the async dma engines (VEGA10). 1042 */ 1043 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) 1044 { 1045 u32 f32_cntl; 1046 int i; 1047 1048 if (!enable) { 1049 sdma_v4_0_gfx_enable(adev, enable); 1050 sdma_v4_0_rlc_stop(adev); 1051 if (adev->sdma.has_page_queue) 1052 sdma_v4_0_page_stop(adev); 1053 } 1054 1055 for (i = 0; i < adev->sdma.num_instances; i++) { 1056 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1057 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 1058 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl); 1059 } 1060 } 1061 1062 /* 1063 * sdma_v4_0_rb_cntl - get parameters for rb_cntl 1064 */ 1065 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 1066 { 1067 /* Set ring buffer size in dwords */ 1068 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 1069 1070 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 1071 #ifdef __BIG_ENDIAN 1072 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 1073 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 1074 RPTR_WRITEBACK_SWAP_ENABLE, 1); 1075 #endif 1076 return rb_cntl; 1077 } 1078 1079 /** 1080 * sdma_v4_0_gfx_resume - setup and start the async dma engines 1081 * 1082 * @adev: amdgpu_device pointer 1083 * @i: instance to resume 1084 * 1085 * Set up the gfx DMA ring buffers and enable them (VEGA10). 1086 * Returns 0 for success, error for failure. 1087 */ 1088 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i) 1089 { 1090 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 1091 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 1092 u32 doorbell; 1093 u32 doorbell_offset; 1094 u64 wptr_gpu_addr; 1095 1096 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 1097 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 1098 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 1099 1100 /* Initialize the ring buffer's read and write pointers */ 1101 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0); 1102 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0); 1103 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0); 1104 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0); 1105 1106 /* set the wb address whether it's enabled or not */ 1107 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI, 1108 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 1109 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 1110 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 1111 1112 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 1113 RPTR_WRITEBACK_ENABLE, 1); 1114 1115 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8); 1116 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 1117 1118 ring->wptr = 0; 1119 1120 /* before programing wptr to a less value, need set minor_ptr_update first */ 1121 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1); 1122 1123 doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL); 1124 doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET); 1125 1126 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1127 ring->use_doorbell); 1128 doorbell_offset = REG_SET_FIELD(doorbell_offset, 1129 SDMA0_GFX_DOORBELL_OFFSET, 1130 OFFSET, ring->doorbell_index); 1131 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell); 1132 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset); 1133 1134 sdma_v4_0_ring_set_wptr(ring); 1135 1136 /* set minor_ptr_update to 0 after wptr programed */ 1137 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0); 1138 1139 /* setup the wptr shadow polling */ 1140 wptr_gpu_addr = ring->wptr_gpu_addr; 1141 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO, 1142 lower_32_bits(wptr_gpu_addr)); 1143 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI, 1144 upper_32_bits(wptr_gpu_addr)); 1145 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL); 1146 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 1147 SDMA0_GFX_RB_WPTR_POLL_CNTL, 1148 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 1149 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 1150 1151 /* enable DMA RB */ 1152 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 1153 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 1154 1155 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 1156 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 1157 #ifdef __BIG_ENDIAN 1158 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 1159 #endif 1160 /* enable DMA IBs */ 1161 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 1162 } 1163 1164 /** 1165 * sdma_v4_0_page_resume - setup and start the async dma engines 1166 * 1167 * @adev: amdgpu_device pointer 1168 * @i: instance to resume 1169 * 1170 * Set up the page DMA ring buffers and enable them (VEGA10). 1171 * Returns 0 for success, error for failure. 1172 */ 1173 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i) 1174 { 1175 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 1176 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 1177 u32 doorbell; 1178 u32 doorbell_offset; 1179 u64 wptr_gpu_addr; 1180 1181 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 1182 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 1183 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1184 1185 /* Initialize the ring buffer's read and write pointers */ 1186 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0); 1187 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0); 1188 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0); 1189 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0); 1190 1191 /* set the wb address whether it's enabled or not */ 1192 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI, 1193 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 1194 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 1195 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 1196 1197 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 1198 RPTR_WRITEBACK_ENABLE, 1); 1199 1200 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8); 1201 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 1202 1203 ring->wptr = 0; 1204 1205 /* before programing wptr to a less value, need set minor_ptr_update first */ 1206 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1); 1207 1208 doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL); 1209 doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET); 1210 1211 doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE, 1212 ring->use_doorbell); 1213 doorbell_offset = REG_SET_FIELD(doorbell_offset, 1214 SDMA0_PAGE_DOORBELL_OFFSET, 1215 OFFSET, ring->doorbell_index); 1216 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell); 1217 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset); 1218 1219 /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */ 1220 sdma_v4_0_page_ring_set_wptr(ring); 1221 1222 /* set minor_ptr_update to 0 after wptr programed */ 1223 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0); 1224 1225 /* setup the wptr shadow polling */ 1226 wptr_gpu_addr = ring->wptr_gpu_addr; 1227 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO, 1228 lower_32_bits(wptr_gpu_addr)); 1229 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI, 1230 upper_32_bits(wptr_gpu_addr)); 1231 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL); 1232 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 1233 SDMA0_PAGE_RB_WPTR_POLL_CNTL, 1234 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 1235 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 1236 1237 /* enable DMA RB */ 1238 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1); 1239 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1240 1241 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 1242 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1); 1243 #ifdef __BIG_ENDIAN 1244 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 1245 #endif 1246 /* enable DMA IBs */ 1247 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 1248 } 1249 1250 static void 1251 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable) 1252 { 1253 uint32_t def, data; 1254 1255 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) { 1256 /* enable idle interrupt */ 1257 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1258 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1259 1260 if (data != def) 1261 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1262 } else { 1263 /* disable idle interrupt */ 1264 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1265 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1266 if (data != def) 1267 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1268 } 1269 } 1270 1271 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev) 1272 { 1273 uint32_t def, data; 1274 1275 /* Enable HW based PG. */ 1276 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1277 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK; 1278 if (data != def) 1279 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1280 1281 /* enable interrupt */ 1282 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1283 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1284 if (data != def) 1285 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1286 1287 /* Configure hold time to filter in-valid power on/off request. Use default right now */ 1288 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1289 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK; 1290 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK); 1291 /* Configure switch time for hysteresis purpose. Use default right now */ 1292 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK; 1293 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK); 1294 if(data != def) 1295 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1296 } 1297 1298 static void sdma_v4_0_init_pg(struct amdgpu_device *adev) 1299 { 1300 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA)) 1301 return; 1302 1303 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1304 case IP_VERSION(4, 1, 0): 1305 case IP_VERSION(4, 1, 1): 1306 case IP_VERSION(4, 1, 2): 1307 sdma_v4_1_init_power_gating(adev); 1308 sdma_v4_1_update_power_gating(adev, true); 1309 break; 1310 default: 1311 break; 1312 } 1313 } 1314 1315 /** 1316 * sdma_v4_0_rlc_resume - setup and start the async dma engines 1317 * 1318 * @adev: amdgpu_device pointer 1319 * 1320 * Set up the compute DMA queues and enable them (VEGA10). 1321 * Returns 0 for success, error for failure. 1322 */ 1323 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) 1324 { 1325 sdma_v4_0_init_pg(adev); 1326 1327 return 0; 1328 } 1329 1330 /** 1331 * sdma_v4_0_load_microcode - load the sDMA ME ucode 1332 * 1333 * @adev: amdgpu_device pointer 1334 * 1335 * Loads the sDMA0/1 ucode. 1336 * Returns 0 for success, -EINVAL if the ucode is not available. 1337 */ 1338 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 1339 { 1340 const struct sdma_firmware_header_v1_0 *hdr; 1341 const __le32 *fw_data; 1342 u32 fw_size; 1343 int i, j; 1344 1345 /* halt the MEs */ 1346 sdma_v4_0_enable(adev, false); 1347 1348 for (i = 0; i < adev->sdma.num_instances; i++) { 1349 if (!adev->sdma.instance[i].fw) 1350 return -EINVAL; 1351 1352 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 1353 amdgpu_ucode_print_sdma_hdr(&hdr->header); 1354 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1355 1356 fw_data = (const __le32 *) 1357 (adev->sdma.instance[i].fw->data + 1358 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1359 1360 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0); 1361 1362 for (j = 0; j < fw_size; j++) 1363 WREG32_SDMA(i, mmSDMA0_UCODE_DATA, 1364 le32_to_cpup(fw_data++)); 1365 1366 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 1367 adev->sdma.instance[i].fw_version); 1368 } 1369 1370 return 0; 1371 } 1372 1373 /** 1374 * sdma_v4_0_start - setup and start the async dma engines 1375 * 1376 * @adev: amdgpu_device pointer 1377 * 1378 * Set up the DMA engines and enable them (VEGA10). 1379 * Returns 0 for success, error for failure. 1380 */ 1381 static int sdma_v4_0_start(struct amdgpu_device *adev) 1382 { 1383 struct amdgpu_ring *ring; 1384 int i, r = 0; 1385 1386 if (amdgpu_sriov_vf(adev)) { 1387 sdma_v4_0_ctx_switch_enable(adev, false); 1388 sdma_v4_0_enable(adev, false); 1389 } else { 1390 1391 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1392 r = sdma_v4_0_load_microcode(adev); 1393 if (r) 1394 return r; 1395 } 1396 1397 /* unhalt the MEs */ 1398 sdma_v4_0_enable(adev, true); 1399 /* enable sdma ring preemption */ 1400 sdma_v4_0_ctx_switch_enable(adev, true); 1401 } 1402 1403 /* start the gfx rings and rlc compute queues */ 1404 for (i = 0; i < adev->sdma.num_instances; i++) { 1405 uint32_t temp; 1406 1407 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0); 1408 sdma_v4_0_gfx_resume(adev, i); 1409 if (adev->sdma.has_page_queue) 1410 sdma_v4_0_page_resume(adev, i); 1411 1412 /* set utc l1 enable flag always to 1 */ 1413 temp = RREG32_SDMA(i, mmSDMA0_CNTL); 1414 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 1415 WREG32_SDMA(i, mmSDMA0_CNTL, temp); 1416 1417 if (!amdgpu_sriov_vf(adev)) { 1418 /* unhalt engine */ 1419 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1420 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 1421 WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp); 1422 } 1423 } 1424 1425 if (amdgpu_sriov_vf(adev)) { 1426 sdma_v4_0_ctx_switch_enable(adev, true); 1427 sdma_v4_0_enable(adev, true); 1428 } else { 1429 r = sdma_v4_0_rlc_resume(adev); 1430 if (r) 1431 return r; 1432 } 1433 1434 for (i = 0; i < adev->sdma.num_instances; i++) { 1435 ring = &adev->sdma.instance[i].ring; 1436 1437 r = amdgpu_ring_test_helper(ring); 1438 if (r) 1439 return r; 1440 1441 if (adev->sdma.has_page_queue) { 1442 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 1443 1444 r = amdgpu_ring_test_helper(page); 1445 if (r) 1446 return r; 1447 } 1448 } 1449 1450 return r; 1451 } 1452 1453 /** 1454 * sdma_v4_0_ring_test_ring - simple async dma engine test 1455 * 1456 * @ring: amdgpu_ring structure holding ring information 1457 * 1458 * Test the DMA engine by writing using it to write an 1459 * value to memory. (VEGA10). 1460 * Returns 0 for success, error for failure. 1461 */ 1462 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) 1463 { 1464 struct amdgpu_device *adev = ring->adev; 1465 unsigned i; 1466 unsigned index; 1467 int r; 1468 u32 tmp; 1469 u64 gpu_addr; 1470 1471 r = amdgpu_device_wb_get(adev, &index); 1472 if (r) 1473 return r; 1474 1475 gpu_addr = adev->wb.gpu_addr + (index * 4); 1476 tmp = 0xCAFEDEAD; 1477 adev->wb.wb[index] = cpu_to_le32(tmp); 1478 1479 r = amdgpu_ring_alloc(ring, 5); 1480 if (r) 1481 goto error_free_wb; 1482 1483 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1484 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1485 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1486 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1487 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1488 amdgpu_ring_write(ring, 0xDEADBEEF); 1489 amdgpu_ring_commit(ring); 1490 1491 for (i = 0; i < adev->usec_timeout; i++) { 1492 tmp = le32_to_cpu(adev->wb.wb[index]); 1493 if (tmp == 0xDEADBEEF) 1494 break; 1495 udelay(1); 1496 } 1497 1498 if (i >= adev->usec_timeout) 1499 r = -ETIMEDOUT; 1500 1501 error_free_wb: 1502 amdgpu_device_wb_free(adev, index); 1503 return r; 1504 } 1505 1506 /** 1507 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine 1508 * 1509 * @ring: amdgpu_ring structure holding ring information 1510 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1511 * 1512 * Test a simple IB in the DMA ring (VEGA10). 1513 * Returns 0 on success, error on failure. 1514 */ 1515 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1516 { 1517 struct amdgpu_device *adev = ring->adev; 1518 struct amdgpu_ib ib; 1519 struct dma_fence *f = NULL; 1520 unsigned index; 1521 long r; 1522 u32 tmp = 0; 1523 u64 gpu_addr; 1524 1525 r = amdgpu_device_wb_get(adev, &index); 1526 if (r) 1527 return r; 1528 1529 gpu_addr = adev->wb.gpu_addr + (index * 4); 1530 tmp = 0xCAFEDEAD; 1531 adev->wb.wb[index] = cpu_to_le32(tmp); 1532 memset(&ib, 0, sizeof(ib)); 1533 r = amdgpu_ib_get(adev, NULL, 256, 1534 AMDGPU_IB_POOL_DIRECT, &ib); 1535 if (r) 1536 goto err0; 1537 1538 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1539 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1540 ib.ptr[1] = lower_32_bits(gpu_addr); 1541 ib.ptr[2] = upper_32_bits(gpu_addr); 1542 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1543 ib.ptr[4] = 0xDEADBEEF; 1544 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1545 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1546 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1547 ib.length_dw = 8; 1548 1549 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1550 if (r) 1551 goto err1; 1552 1553 r = dma_fence_wait_timeout(f, false, timeout); 1554 if (r == 0) { 1555 r = -ETIMEDOUT; 1556 goto err1; 1557 } else if (r < 0) { 1558 goto err1; 1559 } 1560 tmp = le32_to_cpu(adev->wb.wb[index]); 1561 if (tmp == 0xDEADBEEF) 1562 r = 0; 1563 else 1564 r = -EINVAL; 1565 1566 err1: 1567 amdgpu_ib_free(&ib, NULL); 1568 dma_fence_put(f); 1569 err0: 1570 amdgpu_device_wb_free(adev, index); 1571 return r; 1572 } 1573 1574 1575 /** 1576 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART 1577 * 1578 * @ib: indirect buffer to fill with commands 1579 * @pe: addr of the page entry 1580 * @src: src addr to copy from 1581 * @count: number of page entries to update 1582 * 1583 * Update PTEs by copying them from the GART using sDMA (VEGA10). 1584 */ 1585 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib, 1586 uint64_t pe, uint64_t src, 1587 unsigned count) 1588 { 1589 unsigned bytes = count * 8; 1590 1591 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1592 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1593 ib->ptr[ib->length_dw++] = bytes - 1; 1594 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1595 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1596 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1597 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1598 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1599 1600 } 1601 1602 /** 1603 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually 1604 * 1605 * @ib: indirect buffer to fill with commands 1606 * @pe: addr of the page entry 1607 * @value: dst addr to write into pe 1608 * @count: number of page entries to update 1609 * @incr: increase next addr by incr bytes 1610 * 1611 * Update PTEs by writing them manually using sDMA (VEGA10). 1612 */ 1613 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1614 uint64_t value, unsigned count, 1615 uint32_t incr) 1616 { 1617 unsigned ndw = count * 2; 1618 1619 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1620 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1621 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1622 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1623 ib->ptr[ib->length_dw++] = ndw - 1; 1624 for (; ndw > 0; ndw -= 2) { 1625 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1626 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1627 value += incr; 1628 } 1629 } 1630 1631 /** 1632 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA 1633 * 1634 * @ib: indirect buffer to fill with commands 1635 * @pe: addr of the page entry 1636 * @addr: dst addr to write into pe 1637 * @count: number of page entries to update 1638 * @incr: increase next addr by incr bytes 1639 * @flags: access flags 1640 * 1641 * Update the page tables using sDMA (VEGA10). 1642 */ 1643 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1644 uint64_t pe, 1645 uint64_t addr, unsigned count, 1646 uint32_t incr, uint64_t flags) 1647 { 1648 /* for physically contiguous pages (vram) */ 1649 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1650 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1651 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1652 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1653 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1654 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1655 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1656 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1657 ib->ptr[ib->length_dw++] = 0; 1658 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1659 } 1660 1661 /** 1662 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw 1663 * 1664 * @ring: amdgpu_ring structure holding ring information 1665 * @ib: indirect buffer to fill with padding 1666 */ 1667 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1668 { 1669 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1670 u32 pad_count; 1671 int i; 1672 1673 pad_count = (-ib->length_dw) & 7; 1674 for (i = 0; i < pad_count; i++) 1675 if (sdma && sdma->burst_nop && (i == 0)) 1676 ib->ptr[ib->length_dw++] = 1677 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1678 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1679 else 1680 ib->ptr[ib->length_dw++] = 1681 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1682 } 1683 1684 1685 /** 1686 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline 1687 * 1688 * @ring: amdgpu_ring pointer 1689 * 1690 * Make sure all previous operations are completed (CIK). 1691 */ 1692 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1693 { 1694 uint32_t seq = ring->fence_drv.sync_seq; 1695 uint64_t addr = ring->fence_drv.gpu_addr; 1696 1697 /* wait for idle */ 1698 sdma_v4_0_wait_reg_mem(ring, 1, 0, 1699 addr & 0xfffffffc, 1700 upper_32_bits(addr) & 0xffffffff, 1701 seq, 0xffffffff, 4); 1702 } 1703 1704 1705 /** 1706 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA 1707 * 1708 * @ring: amdgpu_ring pointer 1709 * @vmid: vmid number to use 1710 * @pd_addr: address 1711 * 1712 * Update the page table base and flush the VM TLB 1713 * using sDMA (VEGA10). 1714 */ 1715 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1716 unsigned vmid, uint64_t pd_addr) 1717 { 1718 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1719 } 1720 1721 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring, 1722 uint32_t reg, uint32_t val) 1723 { 1724 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1725 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1726 amdgpu_ring_write(ring, reg); 1727 amdgpu_ring_write(ring, val); 1728 } 1729 1730 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1731 uint32_t val, uint32_t mask) 1732 { 1733 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1734 } 1735 1736 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev) 1737 { 1738 uint fw_version = adev->sdma.instance[0].fw_version; 1739 1740 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1741 case IP_VERSION(4, 0, 0): 1742 return fw_version >= 430; 1743 case IP_VERSION(4, 0, 1): 1744 /*return fw_version >= 31;*/ 1745 return false; 1746 case IP_VERSION(4, 2, 0): 1747 return fw_version >= 123; 1748 default: 1749 return false; 1750 } 1751 } 1752 1753 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 1754 .copy_pte_num_dw = 7, 1755 .copy_pte = sdma_v4_0_vm_copy_pte, 1756 1757 .write_pte = sdma_v4_0_vm_write_pte, 1758 .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 1759 }; 1760 1761 static int sdma_v4_0_early_init(struct amdgpu_ip_block *ip_block) 1762 { 1763 struct amdgpu_device *adev = ip_block->adev; 1764 int r; 1765 1766 r = sdma_v4_0_init_microcode(adev); 1767 if (r) 1768 return r; 1769 1770 /* TODO: Page queue breaks driver reload under SRIOV */ 1771 if ((amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 0, 0)) && 1772 amdgpu_sriov_vf((adev))) 1773 adev->sdma.has_page_queue = false; 1774 else if (sdma_v4_0_fw_support_paging_queue(adev)) 1775 adev->sdma.has_page_queue = true; 1776 1777 sdma_v4_0_set_ring_funcs(adev); 1778 amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v4_0_vm_pte_funcs); 1779 sdma_v4_0_set_irq_funcs(adev); 1780 sdma_v4_0_set_ras_funcs(adev); 1781 1782 return 0; 1783 } 1784 1785 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, 1786 void *err_data, 1787 struct amdgpu_iv_entry *entry); 1788 1789 static int sdma_v4_0_late_init(struct amdgpu_ip_block *ip_block) 1790 { 1791 struct amdgpu_device *adev = ip_block->adev; 1792 1793 sdma_v4_0_setup_ulv(adev); 1794 1795 if (!amdgpu_persistent_edc_harvesting_supported(adev)) 1796 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__SDMA); 1797 1798 return 0; 1799 } 1800 1801 static int sdma_v4_0_sw_init(struct amdgpu_ip_block *ip_block) 1802 { 1803 struct amdgpu_ring *ring; 1804 int r, i; 1805 struct amdgpu_device *adev = ip_block->adev; 1806 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_0); 1807 uint32_t *ptr; 1808 1809 /* SDMA trap event */ 1810 for (i = 0; i < adev->sdma.num_instances; i++) { 1811 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1812 SDMA0_4_0__SRCID__SDMA_TRAP, 1813 &adev->sdma.trap_irq); 1814 if (r) 1815 return r; 1816 } 1817 1818 /* SDMA SRAM ECC event */ 1819 for (i = 0; i < adev->sdma.num_instances; i++) { 1820 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1821 SDMA0_4_0__SRCID__SDMA_SRAM_ECC, 1822 &adev->sdma.ecc_irq); 1823 if (r) 1824 return r; 1825 } 1826 1827 /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/ 1828 for (i = 0; i < adev->sdma.num_instances; i++) { 1829 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1830 SDMA0_4_0__SRCID__SDMA_VM_HOLE, 1831 &adev->sdma.vm_hole_irq); 1832 if (r) 1833 return r; 1834 1835 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1836 SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID, 1837 &adev->sdma.doorbell_invalid_irq); 1838 if (r) 1839 return r; 1840 1841 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1842 SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT, 1843 &adev->sdma.pool_timeout_irq); 1844 if (r) 1845 return r; 1846 1847 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1848 SDMA0_4_0__SRCID__SDMA_SRBMWRITE, 1849 &adev->sdma.srbm_write_irq); 1850 if (r) 1851 return r; 1852 } 1853 1854 for (i = 0; i < adev->sdma.num_instances; i++) { 1855 ring = &adev->sdma.instance[i].ring; 1856 ring->ring_obj = NULL; 1857 ring->use_doorbell = true; 1858 1859 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1860 ring->use_doorbell?"true":"false"); 1861 1862 /* doorbell size is 2 dwords, get DWORD offset */ 1863 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1864 1865 /* 1866 * On Arcturus, SDMA instance 5~7 has a different vmhub 1867 * type(AMDGPU_MMHUB1). 1868 */ 1869 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == 1870 IP_VERSION(4, 2, 2) && 1871 i >= 5) 1872 ring->vm_hub = AMDGPU_MMHUB1(0); 1873 else 1874 ring->vm_hub = AMDGPU_MMHUB0(0); 1875 1876 sprintf(ring->name, "sdma%d", i); 1877 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1878 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1879 AMDGPU_RING_PRIO_DEFAULT, NULL); 1880 if (r) 1881 return r; 1882 1883 if (adev->sdma.has_page_queue) { 1884 ring = &adev->sdma.instance[i].page; 1885 ring->ring_obj = NULL; 1886 ring->use_doorbell = true; 1887 1888 /* paging queue use same doorbell index/routing as gfx queue 1889 * with 0x400 (4096 dwords) offset on second doorbell page 1890 */ 1891 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) >= 1892 IP_VERSION(4, 0, 0) && 1893 amdgpu_ip_version(adev, SDMA0_HWIP, 0) < 1894 IP_VERSION(4, 2, 0)) { 1895 ring->doorbell_index = 1896 adev->doorbell_index.sdma_engine[i] << 1; 1897 ring->doorbell_index += 0x400; 1898 } else { 1899 /* From vega20, the sdma_doorbell_range in 1st 1900 * doorbell page is reserved for page queue. 1901 */ 1902 ring->doorbell_index = 1903 (adev->doorbell_index.sdma_engine[i] + 1) << 1; 1904 } 1905 1906 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == 1907 IP_VERSION(4, 2, 2) && 1908 i >= 5) 1909 ring->vm_hub = AMDGPU_MMHUB1(0); 1910 else 1911 ring->vm_hub = AMDGPU_MMHUB0(0); 1912 1913 sprintf(ring->name, "page%d", i); 1914 r = amdgpu_ring_init(adev, ring, 1024, 1915 &adev->sdma.trap_irq, 1916 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1917 AMDGPU_RING_PRIO_DEFAULT, NULL); 1918 if (r) 1919 return r; 1920 } 1921 } 1922 1923 if (amdgpu_sdma_ras_sw_init(adev)) { 1924 dev_err(adev->dev, "Failed to initialize sdma ras block!\n"); 1925 return -EINVAL; 1926 } 1927 1928 /* Allocate memory for SDMA IP Dump buffer */ 1929 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); 1930 if (ptr) 1931 adev->sdma.ip_dump = ptr; 1932 else 1933 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n"); 1934 1935 return r; 1936 } 1937 1938 static int sdma_v4_0_sw_fini(struct amdgpu_ip_block *ip_block) 1939 { 1940 struct amdgpu_device *adev = ip_block->adev; 1941 int i; 1942 1943 for (i = 0; i < adev->sdma.num_instances; i++) { 1944 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1945 if (adev->sdma.has_page_queue) 1946 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1947 } 1948 1949 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 2, 2) || 1950 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 0)) 1951 amdgpu_sdma_destroy_inst_ctx(adev, true); 1952 else 1953 amdgpu_sdma_destroy_inst_ctx(adev, false); 1954 1955 kfree(adev->sdma.ip_dump); 1956 1957 return 0; 1958 } 1959 1960 static int sdma_v4_0_hw_init(struct amdgpu_ip_block *ip_block) 1961 { 1962 struct amdgpu_device *adev = ip_block->adev; 1963 int r; 1964 1965 if (adev->flags & AMD_IS_APU) 1966 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false, 0); 1967 1968 if (!amdgpu_sriov_vf(adev)) 1969 sdma_v4_0_init_golden_registers(adev); 1970 1971 r = sdma_v4_0_start(adev); 1972 if (r) 1973 return r; 1974 sdma_v4_0_set_buffer_funcs(adev); 1975 1976 return 0; 1977 } 1978 1979 static int sdma_v4_0_hw_fini(struct amdgpu_ip_block *ip_block) 1980 { 1981 struct amdgpu_device *adev = ip_block->adev; 1982 int i; 1983 1984 if (amdgpu_sriov_vf(adev)) 1985 return 0; 1986 1987 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 1988 for (i = 0; i < adev->sdma.num_instances; i++) { 1989 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 1990 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1991 } 1992 } 1993 1994 sdma_v4_0_ctx_switch_enable(adev, false); 1995 sdma_v4_0_enable(adev, false); 1996 1997 if (adev->flags & AMD_IS_APU) 1998 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true, 0); 1999 2000 return 0; 2001 } 2002 2003 static int sdma_v4_0_suspend(struct amdgpu_ip_block *ip_block) 2004 { 2005 struct amdgpu_device *adev = ip_block->adev; 2006 2007 /* SMU saves SDMA state for us */ 2008 if (adev->in_s0ix) { 2009 sdma_v4_0_gfx_enable(adev, false); 2010 return 0; 2011 } 2012 2013 return sdma_v4_0_hw_fini(ip_block); 2014 } 2015 2016 static int sdma_v4_0_resume(struct amdgpu_ip_block *ip_block) 2017 { 2018 struct amdgpu_device *adev = ip_block->adev; 2019 2020 /* SMU restores SDMA state for us */ 2021 if (adev->in_s0ix) { 2022 sdma_v4_0_enable(adev, true); 2023 sdma_v4_0_gfx_enable(adev, true); 2024 return 0; 2025 } 2026 2027 return sdma_v4_0_hw_init(ip_block); 2028 } 2029 2030 static bool sdma_v4_0_is_idle(struct amdgpu_ip_block *ip_block) 2031 { 2032 struct amdgpu_device *adev = ip_block->adev; 2033 u32 i; 2034 2035 for (i = 0; i < adev->sdma.num_instances; i++) { 2036 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG); 2037 2038 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 2039 return false; 2040 } 2041 2042 return true; 2043 } 2044 2045 static int sdma_v4_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 2046 { 2047 unsigned i, j; 2048 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; 2049 struct amdgpu_device *adev = ip_block->adev; 2050 2051 for (i = 0; i < adev->usec_timeout; i++) { 2052 for (j = 0; j < adev->sdma.num_instances; j++) { 2053 sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG); 2054 if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK)) 2055 break; 2056 } 2057 if (j == adev->sdma.num_instances) 2058 return 0; 2059 udelay(1); 2060 } 2061 return -ETIMEDOUT; 2062 } 2063 2064 static int sdma_v4_0_soft_reset(struct amdgpu_ip_block *ip_block) 2065 { 2066 /* todo */ 2067 2068 return 0; 2069 } 2070 2071 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, 2072 struct amdgpu_irq_src *source, 2073 unsigned type, 2074 enum amdgpu_interrupt_state state) 2075 { 2076 u32 sdma_cntl; 2077 2078 sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL); 2079 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 2080 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2081 WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl); 2082 2083 return 0; 2084 } 2085 2086 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, 2087 struct amdgpu_irq_src *source, 2088 struct amdgpu_iv_entry *entry) 2089 { 2090 int instance; 2091 2092 DRM_DEBUG("IH: SDMA trap\n"); 2093 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2094 if (instance < 0) 2095 return instance; 2096 2097 switch (entry->ring_id) { 2098 case 0: 2099 amdgpu_fence_process(&adev->sdma.instance[instance].ring); 2100 break; 2101 case 1: 2102 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == 2103 IP_VERSION(4, 2, 0)) 2104 amdgpu_fence_process(&adev->sdma.instance[instance].page); 2105 break; 2106 case 2: 2107 /* XXX compute */ 2108 break; 2109 case 3: 2110 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) != 2111 IP_VERSION(4, 2, 0)) 2112 amdgpu_fence_process(&adev->sdma.instance[instance].page); 2113 break; 2114 } 2115 return 0; 2116 } 2117 2118 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, 2119 void *err_data, 2120 struct amdgpu_iv_entry *entry) 2121 { 2122 int instance; 2123 2124 /* When “Full RAS” is enabled, the per-IP interrupt sources should 2125 * be disabled and the driver should only look for the aggregated 2126 * interrupt via sync flood 2127 */ 2128 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 2129 goto out; 2130 2131 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2132 if (instance < 0) 2133 goto out; 2134 2135 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry); 2136 2137 out: 2138 return AMDGPU_RAS_SUCCESS; 2139 } 2140 2141 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev, 2142 struct amdgpu_irq_src *source, 2143 struct amdgpu_iv_entry *entry) 2144 { 2145 int instance; 2146 2147 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 2148 2149 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2150 if (instance < 0) 2151 return 0; 2152 2153 switch (entry->ring_id) { 2154 case 0: 2155 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 2156 break; 2157 } 2158 return 0; 2159 } 2160 2161 static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev, 2162 struct amdgpu_irq_src *source, 2163 unsigned type, 2164 enum amdgpu_interrupt_state state) 2165 { 2166 u32 sdma_edc_config; 2167 2168 sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG); 2169 sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE, 2170 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2171 WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config); 2172 2173 return 0; 2174 } 2175 2176 static int sdma_v4_0_print_iv_entry(struct amdgpu_device *adev, 2177 struct amdgpu_iv_entry *entry) 2178 { 2179 int instance; 2180 struct amdgpu_task_info *task_info; 2181 u64 addr; 2182 2183 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2184 if (instance < 0 || instance >= adev->sdma.num_instances) { 2185 dev_err(adev->dev, "sdma instance invalid %d\n", instance); 2186 return -EINVAL; 2187 } 2188 2189 addr = (u64)entry->src_data[0] << 12; 2190 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 2191 2192 dev_dbg_ratelimited(adev->dev, 2193 "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u pasid:%u\n", 2194 instance, addr, entry->src_id, entry->ring_id, entry->vmid, 2195 entry->pasid); 2196 2197 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 2198 if (task_info) { 2199 dev_dbg_ratelimited(adev->dev, 2200 " for process %s pid %d thread %s pid %d\n", 2201 task_info->process_name, task_info->tgid, 2202 task_info->task.comm, task_info->task.pid); 2203 amdgpu_vm_put_task_info(task_info); 2204 } 2205 2206 return 0; 2207 } 2208 2209 static int sdma_v4_0_process_vm_hole_irq(struct amdgpu_device *adev, 2210 struct amdgpu_irq_src *source, 2211 struct amdgpu_iv_entry *entry) 2212 { 2213 dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n"); 2214 sdma_v4_0_print_iv_entry(adev, entry); 2215 return 0; 2216 } 2217 2218 static int sdma_v4_0_process_doorbell_invalid_irq(struct amdgpu_device *adev, 2219 struct amdgpu_irq_src *source, 2220 struct amdgpu_iv_entry *entry) 2221 { 2222 dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n"); 2223 sdma_v4_0_print_iv_entry(adev, entry); 2224 return 0; 2225 } 2226 2227 static int sdma_v4_0_process_pool_timeout_irq(struct amdgpu_device *adev, 2228 struct amdgpu_irq_src *source, 2229 struct amdgpu_iv_entry *entry) 2230 { 2231 dev_dbg_ratelimited(adev->dev, 2232 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n"); 2233 sdma_v4_0_print_iv_entry(adev, entry); 2234 return 0; 2235 } 2236 2237 static int sdma_v4_0_process_srbm_write_irq(struct amdgpu_device *adev, 2238 struct amdgpu_irq_src *source, 2239 struct amdgpu_iv_entry *entry) 2240 { 2241 dev_dbg_ratelimited(adev->dev, 2242 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n"); 2243 sdma_v4_0_print_iv_entry(adev, entry); 2244 return 0; 2245 } 2246 2247 static void sdma_v4_0_update_medium_grain_clock_gating( 2248 struct amdgpu_device *adev, 2249 bool enable) 2250 { 2251 uint32_t data, def; 2252 int i; 2253 2254 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 2255 for (i = 0; i < adev->sdma.num_instances; i++) { 2256 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); 2257 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2258 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2259 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2260 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2261 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2262 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2263 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2264 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2265 if (def != data) 2266 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); 2267 } 2268 } else { 2269 for (i = 0; i < adev->sdma.num_instances; i++) { 2270 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); 2271 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2272 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2273 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2274 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2275 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2276 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2277 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2278 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2279 if (def != data) 2280 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); 2281 } 2282 } 2283 } 2284 2285 2286 static void sdma_v4_0_update_medium_grain_light_sleep( 2287 struct amdgpu_device *adev, 2288 bool enable) 2289 { 2290 uint32_t data, def; 2291 int i; 2292 2293 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 2294 for (i = 0; i < adev->sdma.num_instances; i++) { 2295 /* 1-not override: enable sdma mem light sleep */ 2296 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); 2297 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2298 if (def != data) 2299 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); 2300 } 2301 } else { 2302 for (i = 0; i < adev->sdma.num_instances; i++) { 2303 /* 0-override:disable sdma mem light sleep */ 2304 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); 2305 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2306 if (def != data) 2307 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); 2308 } 2309 } 2310 } 2311 2312 static int sdma_v4_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2313 enum amd_clockgating_state state) 2314 { 2315 struct amdgpu_device *adev = ip_block->adev; 2316 2317 if (amdgpu_sriov_vf(adev)) 2318 return 0; 2319 2320 sdma_v4_0_update_medium_grain_clock_gating(adev, 2321 state == AMD_CG_STATE_GATE); 2322 sdma_v4_0_update_medium_grain_light_sleep(adev, 2323 state == AMD_CG_STATE_GATE); 2324 return 0; 2325 } 2326 2327 static int sdma_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 2328 enum amd_powergating_state state) 2329 { 2330 struct amdgpu_device *adev = ip_block->adev; 2331 2332 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 2333 case IP_VERSION(4, 1, 0): 2334 case IP_VERSION(4, 1, 1): 2335 case IP_VERSION(4, 1, 2): 2336 sdma_v4_1_update_power_gating(adev, 2337 state == AMD_PG_STATE_GATE); 2338 break; 2339 default: 2340 break; 2341 } 2342 2343 return 0; 2344 } 2345 2346 static void sdma_v4_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 2347 { 2348 struct amdgpu_device *adev = ip_block->adev; 2349 int data; 2350 2351 if (amdgpu_sriov_vf(adev)) 2352 *flags = 0; 2353 2354 /* AMD_CG_SUPPORT_SDMA_MGCG */ 2355 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 2356 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 2357 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 2358 2359 /* AMD_CG_SUPPORT_SDMA_LS */ 2360 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 2361 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 2362 *flags |= AMD_CG_SUPPORT_SDMA_LS; 2363 } 2364 2365 static void sdma_v4_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 2366 { 2367 struct amdgpu_device *adev = ip_block->adev; 2368 int i, j; 2369 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_0); 2370 uint32_t instance_offset; 2371 2372 if (!adev->sdma.ip_dump) 2373 return; 2374 2375 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances); 2376 for (i = 0; i < adev->sdma.num_instances; i++) { 2377 instance_offset = i * reg_count; 2378 drm_printf(p, "\nInstance:%d\n", i); 2379 2380 for (j = 0; j < reg_count; j++) 2381 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_4_0[j].reg_name, 2382 adev->sdma.ip_dump[instance_offset + j]); 2383 } 2384 } 2385 2386 static void sdma_v4_0_dump_ip_state(struct amdgpu_ip_block *ip_block) 2387 { 2388 struct amdgpu_device *adev = ip_block->adev; 2389 int i, j; 2390 uint32_t instance_offset; 2391 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_0); 2392 2393 if (!adev->sdma.ip_dump) 2394 return; 2395 2396 for (i = 0; i < adev->sdma.num_instances; i++) { 2397 instance_offset = i * reg_count; 2398 for (j = 0; j < reg_count; j++) 2399 adev->sdma.ip_dump[instance_offset + j] = 2400 RREG32(sdma_v4_0_get_reg_offset(adev, i, 2401 sdma_reg_list_4_0[j].reg_offset)); 2402 } 2403 } 2404 2405 const struct amd_ip_funcs sdma_v4_0_ip_funcs = { 2406 .name = "sdma_v4_0", 2407 .early_init = sdma_v4_0_early_init, 2408 .late_init = sdma_v4_0_late_init, 2409 .sw_init = sdma_v4_0_sw_init, 2410 .sw_fini = sdma_v4_0_sw_fini, 2411 .hw_init = sdma_v4_0_hw_init, 2412 .hw_fini = sdma_v4_0_hw_fini, 2413 .suspend = sdma_v4_0_suspend, 2414 .resume = sdma_v4_0_resume, 2415 .is_idle = sdma_v4_0_is_idle, 2416 .wait_for_idle = sdma_v4_0_wait_for_idle, 2417 .soft_reset = sdma_v4_0_soft_reset, 2418 .set_clockgating_state = sdma_v4_0_set_clockgating_state, 2419 .set_powergating_state = sdma_v4_0_set_powergating_state, 2420 .get_clockgating_state = sdma_v4_0_get_clockgating_state, 2421 .dump_ip_state = sdma_v4_0_dump_ip_state, 2422 .print_ip_state = sdma_v4_0_print_ip_state, 2423 }; 2424 2425 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { 2426 .type = AMDGPU_RING_TYPE_SDMA, 2427 .align_mask = 0xff, 2428 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2429 .support_64bit_ptrs = true, 2430 .secure_submission_supported = true, 2431 .get_rptr = sdma_v4_0_ring_get_rptr, 2432 .get_wptr = sdma_v4_0_ring_get_wptr, 2433 .set_wptr = sdma_v4_0_ring_set_wptr, 2434 .emit_frame_size = 2435 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2436 3 + /* hdp invalidate */ 2437 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2438 /* sdma_v4_0_ring_emit_vm_flush */ 2439 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2440 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2441 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2442 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2443 .emit_ib = sdma_v4_0_ring_emit_ib, 2444 .emit_fence = sdma_v4_0_ring_emit_fence, 2445 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2446 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2447 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2448 .test_ring = sdma_v4_0_ring_test_ring, 2449 .test_ib = sdma_v4_0_ring_test_ib, 2450 .insert_nop = sdma_v4_0_ring_insert_nop, 2451 .pad_ib = sdma_v4_0_ring_pad_ib, 2452 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2453 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2454 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2455 }; 2456 2457 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = { 2458 .type = AMDGPU_RING_TYPE_SDMA, 2459 .align_mask = 0xff, 2460 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2461 .support_64bit_ptrs = true, 2462 .secure_submission_supported = true, 2463 .get_rptr = sdma_v4_0_ring_get_rptr, 2464 .get_wptr = sdma_v4_0_page_ring_get_wptr, 2465 .set_wptr = sdma_v4_0_page_ring_set_wptr, 2466 .emit_frame_size = 2467 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2468 3 + /* hdp invalidate */ 2469 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2470 /* sdma_v4_0_ring_emit_vm_flush */ 2471 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2472 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2473 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2474 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2475 .emit_ib = sdma_v4_0_ring_emit_ib, 2476 .emit_fence = sdma_v4_0_ring_emit_fence, 2477 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2478 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2479 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2480 .test_ring = sdma_v4_0_ring_test_ring, 2481 .test_ib = sdma_v4_0_ring_test_ib, 2482 .insert_nop = sdma_v4_0_ring_insert_nop, 2483 .pad_ib = sdma_v4_0_ring_pad_ib, 2484 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2485 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2486 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2487 }; 2488 2489 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev) 2490 { 2491 int i; 2492 2493 for (i = 0; i < adev->sdma.num_instances; i++) { 2494 adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs; 2495 adev->sdma.instance[i].ring.me = i; 2496 if (adev->sdma.has_page_queue) { 2497 adev->sdma.instance[i].page.funcs = 2498 &sdma_v4_0_page_ring_funcs; 2499 adev->sdma.instance[i].page.me = i; 2500 } 2501 } 2502 } 2503 2504 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = { 2505 .set = sdma_v4_0_set_trap_irq_state, 2506 .process = sdma_v4_0_process_trap_irq, 2507 }; 2508 2509 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = { 2510 .process = sdma_v4_0_process_illegal_inst_irq, 2511 }; 2512 2513 static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = { 2514 .set = sdma_v4_0_set_ecc_irq_state, 2515 .process = amdgpu_sdma_process_ecc_irq, 2516 }; 2517 2518 static const struct amdgpu_irq_src_funcs sdma_v4_0_vm_hole_irq_funcs = { 2519 .process = sdma_v4_0_process_vm_hole_irq, 2520 }; 2521 2522 static const struct amdgpu_irq_src_funcs sdma_v4_0_doorbell_invalid_irq_funcs = { 2523 .process = sdma_v4_0_process_doorbell_invalid_irq, 2524 }; 2525 2526 static const struct amdgpu_irq_src_funcs sdma_v4_0_pool_timeout_irq_funcs = { 2527 .process = sdma_v4_0_process_pool_timeout_irq, 2528 }; 2529 2530 static const struct amdgpu_irq_src_funcs sdma_v4_0_srbm_write_irq_funcs = { 2531 .process = sdma_v4_0_process_srbm_write_irq, 2532 }; 2533 2534 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) 2535 { 2536 adev->sdma.trap_irq.num_types = adev->sdma.num_instances; 2537 adev->sdma.ecc_irq.num_types = adev->sdma.num_instances; 2538 /*For Arcturus and Aldebaran, add another 4 irq handler*/ 2539 switch (adev->sdma.num_instances) { 2540 case 5: 2541 case 8: 2542 adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances; 2543 adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances; 2544 adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances; 2545 adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances; 2546 break; 2547 default: 2548 break; 2549 } 2550 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; 2551 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; 2552 adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs; 2553 adev->sdma.vm_hole_irq.funcs = &sdma_v4_0_vm_hole_irq_funcs; 2554 adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_0_doorbell_invalid_irq_funcs; 2555 adev->sdma.pool_timeout_irq.funcs = &sdma_v4_0_pool_timeout_irq_funcs; 2556 adev->sdma.srbm_write_irq.funcs = &sdma_v4_0_srbm_write_irq_funcs; 2557 } 2558 2559 /** 2560 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine 2561 * 2562 * @ib: indirect buffer to copy to 2563 * @src_offset: src GPU address 2564 * @dst_offset: dst GPU address 2565 * @byte_count: number of bytes to xfer 2566 * @copy_flags: copy flags for the buffers 2567 * 2568 * Copy GPU buffers using the DMA engine (VEGA10/12). 2569 * Used by the amdgpu ttm implementation to move pages if 2570 * registered as the asic copy callback. 2571 */ 2572 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, 2573 uint64_t src_offset, 2574 uint64_t dst_offset, 2575 uint32_t byte_count, 2576 uint32_t copy_flags) 2577 { 2578 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 2579 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 2580 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0); 2581 ib->ptr[ib->length_dw++] = byte_count - 1; 2582 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 2583 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 2584 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 2585 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2586 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2587 } 2588 2589 /** 2590 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine 2591 * 2592 * @ib: indirect buffer to copy to 2593 * @src_data: value to write to buffer 2594 * @dst_offset: dst GPU address 2595 * @byte_count: number of bytes to xfer 2596 * 2597 * Fill GPU buffers using the DMA engine (VEGA10/12). 2598 */ 2599 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, 2600 uint32_t src_data, 2601 uint64_t dst_offset, 2602 uint32_t byte_count) 2603 { 2604 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2605 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2606 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2607 ib->ptr[ib->length_dw++] = src_data; 2608 ib->ptr[ib->length_dw++] = byte_count - 1; 2609 } 2610 2611 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { 2612 .copy_max_bytes = 1 << 22, 2613 .copy_num_dw = 7, 2614 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, 2615 2616 .fill_max_bytes = 1 << 22, 2617 .fill_num_dw = 5, 2618 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, 2619 }; 2620 2621 static const struct amdgpu_buffer_funcs sdma_v4_4_buffer_funcs = { 2622 .copy_max_bytes = 1 << 30, 2623 .copy_num_dw = 7, 2624 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, 2625 2626 .fill_max_bytes = 1 << 30, 2627 .fill_num_dw = 5, 2628 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, 2629 }; 2630 2631 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) 2632 { 2633 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) >= IP_VERSION(4, 4, 0)) 2634 amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v4_4_buffer_funcs); 2635 else 2636 amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v4_0_buffer_funcs); 2637 } 2638 2639 static void sdma_v4_0_get_ras_error_count(uint32_t value, 2640 uint32_t instance, 2641 uint32_t *sec_count) 2642 { 2643 uint32_t i; 2644 uint32_t sec_cnt; 2645 2646 /* double bits error (multiple bits) error detection is not supported */ 2647 for (i = 0; i < ARRAY_SIZE(sdma_v4_0_ras_fields); i++) { 2648 /* the SDMA_EDC_COUNTER register in each sdma instance 2649 * shares the same sed shift_mask 2650 * */ 2651 sec_cnt = (value & 2652 sdma_v4_0_ras_fields[i].sec_count_mask) >> 2653 sdma_v4_0_ras_fields[i].sec_count_shift; 2654 if (sec_cnt) { 2655 DRM_INFO("Detected %s in SDMA%d, SED %d\n", 2656 sdma_v4_0_ras_fields[i].name, 2657 instance, sec_cnt); 2658 *sec_count += sec_cnt; 2659 } 2660 } 2661 } 2662 2663 static int sdma_v4_0_query_ras_error_count_by_instance(struct amdgpu_device *adev, 2664 uint32_t instance, void *ras_error_status) 2665 { 2666 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 2667 uint32_t sec_count = 0; 2668 uint32_t reg_value = 0; 2669 2670 reg_value = RREG32_SDMA(instance, mmSDMA0_EDC_COUNTER); 2671 /* double bit error is not supported */ 2672 if (reg_value) 2673 sdma_v4_0_get_ras_error_count(reg_value, 2674 instance, &sec_count); 2675 /* err_data->ce_count should be initialized to 0 2676 * before calling into this function */ 2677 err_data->ce_count += sec_count; 2678 /* double bit error is not supported 2679 * set ue count to 0 */ 2680 err_data->ue_count = 0; 2681 2682 return 0; 2683 }; 2684 2685 static void sdma_v4_0_query_ras_error_count(struct amdgpu_device *adev, void *ras_error_status) 2686 { 2687 int i = 0; 2688 2689 for (i = 0; i < adev->sdma.num_instances; i++) { 2690 if (sdma_v4_0_query_ras_error_count_by_instance(adev, i, ras_error_status)) { 2691 dev_err(adev->dev, "Query ras error count failed in SDMA%d\n", i); 2692 return; 2693 } 2694 } 2695 } 2696 2697 static void sdma_v4_0_reset_ras_error_count(struct amdgpu_device *adev) 2698 { 2699 int i; 2700 2701 /* read back edc counter registers to clear the counters */ 2702 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2703 for (i = 0; i < adev->sdma.num_instances; i++) 2704 RREG32_SDMA(i, mmSDMA0_EDC_COUNTER); 2705 } 2706 } 2707 2708 const struct amdgpu_ras_block_hw_ops sdma_v4_0_ras_hw_ops = { 2709 .query_ras_error_count = sdma_v4_0_query_ras_error_count, 2710 .reset_ras_error_count = sdma_v4_0_reset_ras_error_count, 2711 }; 2712 2713 static struct amdgpu_sdma_ras sdma_v4_0_ras = { 2714 .ras_block = { 2715 .hw_ops = &sdma_v4_0_ras_hw_ops, 2716 .ras_cb = sdma_v4_0_process_ras_data_cb, 2717 }, 2718 }; 2719 2720 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev) 2721 { 2722 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 2723 case IP_VERSION(4, 2, 0): 2724 case IP_VERSION(4, 2, 2): 2725 adev->sdma.ras = &sdma_v4_0_ras; 2726 break; 2727 case IP_VERSION(4, 4, 0): 2728 adev->sdma.ras = &sdma_v4_4_ras; 2729 break; 2730 default: 2731 break; 2732 } 2733 } 2734 2735 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = { 2736 .type = AMD_IP_BLOCK_TYPE_SDMA, 2737 .major = 4, 2738 .minor = 0, 2739 .rev = 0, 2740 .funcs = &sdma_v4_0_ip_funcs, 2741 }; 2742