1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "sdma0/sdma0_4_2_offset.h" 34 #include "sdma0/sdma0_4_2_sh_mask.h" 35 #include "sdma1/sdma1_4_2_offset.h" 36 #include "sdma1/sdma1_4_2_sh_mask.h" 37 #include "sdma2/sdma2_4_2_2_offset.h" 38 #include "sdma2/sdma2_4_2_2_sh_mask.h" 39 #include "sdma3/sdma3_4_2_2_offset.h" 40 #include "sdma3/sdma3_4_2_2_sh_mask.h" 41 #include "sdma4/sdma4_4_2_2_offset.h" 42 #include "sdma4/sdma4_4_2_2_sh_mask.h" 43 #include "sdma5/sdma5_4_2_2_offset.h" 44 #include "sdma5/sdma5_4_2_2_sh_mask.h" 45 #include "sdma6/sdma6_4_2_2_offset.h" 46 #include "sdma6/sdma6_4_2_2_sh_mask.h" 47 #include "sdma7/sdma7_4_2_2_offset.h" 48 #include "sdma7/sdma7_4_2_2_sh_mask.h" 49 #include "hdp/hdp_4_0_offset.h" 50 #include "sdma0/sdma0_4_1_default.h" 51 52 #include "soc15_common.h" 53 #include "soc15.h" 54 #include "vega10_sdma_pkt_open.h" 55 56 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 57 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 58 59 #include "amdgpu_ras.h" 60 61 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); 62 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); 63 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin"); 65 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin"); 66 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin"); 67 MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); 68 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin"); 69 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin"); 70 MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin"); 71 72 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 73 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 74 75 #define WREG32_SDMA(instance, offset, value) \ 76 WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value) 77 #define RREG32_SDMA(instance, offset) \ 78 RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset))) 79 80 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); 81 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); 82 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); 83 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); 84 85 static const struct soc15_reg_golden golden_settings_sdma_4[] = { 86 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 87 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100), 88 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100), 89 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000), 93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 94 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000), 99 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 100 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100), 101 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 102 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 103 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 104 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000), 105 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 106 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 107 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 108 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 109 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 110 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000) 111 }; 112 113 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { 114 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 115 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 116 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 117 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 118 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002) 119 }; 120 121 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = { 122 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 123 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 124 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 125 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 126 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001) 127 }; 128 129 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = { 130 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 131 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 132 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100), 133 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 134 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051), 135 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100), 136 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 137 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100), 138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000) 141 }; 142 143 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = { 144 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 145 }; 146 147 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] = 148 { 149 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 150 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 151 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 152 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 153 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 154 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 155 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 156 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 157 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003), 158 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 159 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 160 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 161 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 162 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 163 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 164 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 165 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 166 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 167 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 168 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 169 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 170 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 171 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 172 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 173 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 174 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 175 }; 176 177 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = { 178 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 179 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 180 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 181 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 182 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 183 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 184 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 185 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 186 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003), 187 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 188 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 189 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 190 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 191 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 192 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 193 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 194 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 195 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 196 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 197 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 198 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 199 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 200 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 201 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 202 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 203 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 204 }; 205 206 static const struct soc15_reg_golden golden_settings_sdma_rv1[] = 207 { 208 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 209 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002) 210 }; 211 212 static const struct soc15_reg_golden golden_settings_sdma_rv2[] = 213 { 214 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001), 215 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001) 216 }; 217 218 static const struct soc15_reg_golden golden_settings_sdma_arct[] = 219 { 220 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 221 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 222 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 223 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 224 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 225 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 226 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 227 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 228 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 229 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 230 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 231 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 232 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 233 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 234 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 235 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 236 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 237 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 238 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 239 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 240 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 241 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 242 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 243 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002) 244 }; 245 246 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, 247 u32 instance, u32 offset) 248 { 249 switch (instance) { 250 case 0: 251 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset); 252 case 1: 253 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset); 254 case 2: 255 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset); 256 case 3: 257 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset); 258 case 4: 259 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset); 260 case 5: 261 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset); 262 case 6: 263 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset); 264 case 7: 265 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset); 266 default: 267 break; 268 } 269 return 0; 270 } 271 272 static unsigned sdma_v4_0_seq_to_irq_id(int seq_num) 273 { 274 switch (seq_num) { 275 case 0: 276 return SOC15_IH_CLIENTID_SDMA0; 277 case 1: 278 return SOC15_IH_CLIENTID_SDMA1; 279 case 2: 280 return SOC15_IH_CLIENTID_SDMA2; 281 case 3: 282 return SOC15_IH_CLIENTID_SDMA3; 283 case 4: 284 return SOC15_IH_CLIENTID_SDMA4; 285 case 5: 286 return SOC15_IH_CLIENTID_SDMA5; 287 case 6: 288 return SOC15_IH_CLIENTID_SDMA6; 289 case 7: 290 return SOC15_IH_CLIENTID_SDMA7; 291 default: 292 break; 293 } 294 return -EINVAL; 295 } 296 297 static int sdma_v4_0_irq_id_to_seq(unsigned client_id) 298 { 299 switch (client_id) { 300 case SOC15_IH_CLIENTID_SDMA0: 301 return 0; 302 case SOC15_IH_CLIENTID_SDMA1: 303 return 1; 304 case SOC15_IH_CLIENTID_SDMA2: 305 return 2; 306 case SOC15_IH_CLIENTID_SDMA3: 307 return 3; 308 case SOC15_IH_CLIENTID_SDMA4: 309 return 4; 310 case SOC15_IH_CLIENTID_SDMA5: 311 return 5; 312 case SOC15_IH_CLIENTID_SDMA6: 313 return 6; 314 case SOC15_IH_CLIENTID_SDMA7: 315 return 7; 316 default: 317 break; 318 } 319 return -EINVAL; 320 } 321 322 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 323 { 324 switch (adev->asic_type) { 325 case CHIP_VEGA10: 326 soc15_program_register_sequence(adev, 327 golden_settings_sdma_4, 328 ARRAY_SIZE(golden_settings_sdma_4)); 329 soc15_program_register_sequence(adev, 330 golden_settings_sdma_vg10, 331 ARRAY_SIZE(golden_settings_sdma_vg10)); 332 break; 333 case CHIP_VEGA12: 334 soc15_program_register_sequence(adev, 335 golden_settings_sdma_4, 336 ARRAY_SIZE(golden_settings_sdma_4)); 337 soc15_program_register_sequence(adev, 338 golden_settings_sdma_vg12, 339 ARRAY_SIZE(golden_settings_sdma_vg12)); 340 break; 341 case CHIP_VEGA20: 342 soc15_program_register_sequence(adev, 343 golden_settings_sdma0_4_2_init, 344 ARRAY_SIZE(golden_settings_sdma0_4_2_init)); 345 soc15_program_register_sequence(adev, 346 golden_settings_sdma0_4_2, 347 ARRAY_SIZE(golden_settings_sdma0_4_2)); 348 soc15_program_register_sequence(adev, 349 golden_settings_sdma1_4_2, 350 ARRAY_SIZE(golden_settings_sdma1_4_2)); 351 break; 352 case CHIP_ARCTURUS: 353 soc15_program_register_sequence(adev, 354 golden_settings_sdma_arct, 355 ARRAY_SIZE(golden_settings_sdma_arct)); 356 break; 357 case CHIP_RAVEN: 358 soc15_program_register_sequence(adev, 359 golden_settings_sdma_4_1, 360 ARRAY_SIZE(golden_settings_sdma_4_1)); 361 if (adev->rev_id >= 8) 362 soc15_program_register_sequence(adev, 363 golden_settings_sdma_rv2, 364 ARRAY_SIZE(golden_settings_sdma_rv2)); 365 else 366 soc15_program_register_sequence(adev, 367 golden_settings_sdma_rv1, 368 ARRAY_SIZE(golden_settings_sdma_rv1)); 369 break; 370 default: 371 break; 372 } 373 } 374 375 static int sdma_v4_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst) 376 { 377 int err = 0; 378 const struct sdma_firmware_header_v1_0 *hdr; 379 380 err = amdgpu_ucode_validate(sdma_inst->fw); 381 if (err) 382 return err; 383 384 hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data; 385 sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version); 386 sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version); 387 388 if (sdma_inst->feature_version >= 20) 389 sdma_inst->burst_nop = true; 390 391 return 0; 392 } 393 394 static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev) 395 { 396 int i; 397 398 for (i = 0; i < adev->sdma.num_instances; i++) { 399 if (adev->sdma.instance[i].fw != NULL) 400 release_firmware(adev->sdma.instance[i].fw); 401 402 /* arcturus shares the same FW memory across 403 all SDMA isntances */ 404 if (adev->asic_type == CHIP_ARCTURUS) 405 break; 406 } 407 408 memset((void*)adev->sdma.instance, 0, 409 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES); 410 } 411 412 /** 413 * sdma_v4_0_init_microcode - load ucode images from disk 414 * 415 * @adev: amdgpu_device pointer 416 * 417 * Use the firmware interface to load the ucode images into 418 * the driver (not loaded into hw). 419 * Returns 0 on success, error on failure. 420 */ 421 422 // emulation only, won't work on real chip 423 // vega10 real chip need to use PSP to load firmware 424 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) 425 { 426 const char *chip_name; 427 char fw_name[30]; 428 int err = 0, i; 429 struct amdgpu_firmware_info *info = NULL; 430 const struct common_firmware_header *header = NULL; 431 432 DRM_DEBUG("\n"); 433 434 switch (adev->asic_type) { 435 case CHIP_VEGA10: 436 chip_name = "vega10"; 437 break; 438 case CHIP_VEGA12: 439 chip_name = "vega12"; 440 break; 441 case CHIP_VEGA20: 442 chip_name = "vega20"; 443 break; 444 case CHIP_RAVEN: 445 if (adev->rev_id >= 8) 446 chip_name = "raven2"; 447 else if (adev->pdev->device == 0x15d8) 448 chip_name = "picasso"; 449 else 450 chip_name = "raven"; 451 break; 452 case CHIP_ARCTURUS: 453 chip_name = "arcturus"; 454 break; 455 default: 456 BUG(); 457 } 458 459 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 460 461 err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev); 462 if (err) 463 goto out; 464 465 err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[0]); 466 if (err) 467 goto out; 468 469 for (i = 1; i < adev->sdma.num_instances; i++) { 470 if (adev->asic_type == CHIP_ARCTURUS) { 471 /* Acturus will leverage the same FW memory 472 for every SDMA instance */ 473 memcpy((void*)&adev->sdma.instance[i], 474 (void*)&adev->sdma.instance[0], 475 sizeof(struct amdgpu_sdma_instance)); 476 } 477 else { 478 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i); 479 480 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 481 if (err) 482 goto out; 483 484 err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[i]); 485 if (err) 486 goto out; 487 } 488 } 489 490 DRM_DEBUG("psp_load == '%s'\n", 491 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 492 493 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 494 for (i = 0; i < adev->sdma.num_instances; i++) { 495 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 496 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 497 info->fw = adev->sdma.instance[i].fw; 498 header = (const struct common_firmware_header *)info->fw->data; 499 adev->firmware.fw_size += 500 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 501 } 502 } 503 504 out: 505 if (err) { 506 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name); 507 sdma_v4_0_destroy_inst_ctx(adev); 508 } 509 return err; 510 } 511 512 /** 513 * sdma_v4_0_ring_get_rptr - get the current read pointer 514 * 515 * @ring: amdgpu ring pointer 516 * 517 * Get the current rptr from the hardware (VEGA10+). 518 */ 519 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) 520 { 521 u64 *rptr; 522 523 /* XXX check if swapping is necessary on BE */ 524 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 525 526 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 527 return ((*rptr) >> 2); 528 } 529 530 /** 531 * sdma_v4_0_ring_get_wptr - get the current write pointer 532 * 533 * @ring: amdgpu ring pointer 534 * 535 * Get the current wptr from the hardware (VEGA10+). 536 */ 537 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 538 { 539 struct amdgpu_device *adev = ring->adev; 540 u64 wptr; 541 542 if (ring->use_doorbell) { 543 /* XXX check if swapping is necessary on BE */ 544 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 545 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 546 } else { 547 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI); 548 wptr = wptr << 32; 549 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR); 550 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 551 ring->me, wptr); 552 } 553 554 return wptr >> 2; 555 } 556 557 /** 558 * sdma_v4_0_ring_set_wptr - commit the write pointer 559 * 560 * @ring: amdgpu ring pointer 561 * 562 * Write the wptr back to the hardware (VEGA10+). 563 */ 564 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) 565 { 566 struct amdgpu_device *adev = ring->adev; 567 568 DRM_DEBUG("Setting write pointer\n"); 569 if (ring->use_doorbell) { 570 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 571 572 DRM_DEBUG("Using doorbell -- " 573 "wptr_offs == 0x%08x " 574 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 575 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 576 ring->wptr_offs, 577 lower_32_bits(ring->wptr << 2), 578 upper_32_bits(ring->wptr << 2)); 579 /* XXX check if swapping is necessary on BE */ 580 WRITE_ONCE(*wb, (ring->wptr << 2)); 581 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 582 ring->doorbell_index, ring->wptr << 2); 583 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 584 } else { 585 DRM_DEBUG("Not using doorbell -- " 586 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 587 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 588 ring->me, 589 lower_32_bits(ring->wptr << 2), 590 ring->me, 591 upper_32_bits(ring->wptr << 2)); 592 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR, 593 lower_32_bits(ring->wptr << 2)); 594 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI, 595 upper_32_bits(ring->wptr << 2)); 596 } 597 } 598 599 /** 600 * sdma_v4_0_page_ring_get_wptr - get the current write pointer 601 * 602 * @ring: amdgpu ring pointer 603 * 604 * Get the current wptr from the hardware (VEGA10+). 605 */ 606 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring) 607 { 608 struct amdgpu_device *adev = ring->adev; 609 u64 wptr; 610 611 if (ring->use_doorbell) { 612 /* XXX check if swapping is necessary on BE */ 613 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 614 } else { 615 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI); 616 wptr = wptr << 32; 617 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR); 618 } 619 620 return wptr >> 2; 621 } 622 623 /** 624 * sdma_v4_0_ring_set_wptr - commit the write pointer 625 * 626 * @ring: amdgpu ring pointer 627 * 628 * Write the wptr back to the hardware (VEGA10+). 629 */ 630 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring) 631 { 632 struct amdgpu_device *adev = ring->adev; 633 634 if (ring->use_doorbell) { 635 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 636 637 /* XXX check if swapping is necessary on BE */ 638 WRITE_ONCE(*wb, (ring->wptr << 2)); 639 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 640 } else { 641 uint64_t wptr = ring->wptr << 2; 642 643 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR, 644 lower_32_bits(wptr)); 645 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI, 646 upper_32_bits(wptr)); 647 } 648 } 649 650 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 651 { 652 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 653 int i; 654 655 for (i = 0; i < count; i++) 656 if (sdma && sdma->burst_nop && (i == 0)) 657 amdgpu_ring_write(ring, ring->funcs->nop | 658 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 659 else 660 amdgpu_ring_write(ring, ring->funcs->nop); 661 } 662 663 /** 664 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine 665 * 666 * @ring: amdgpu ring pointer 667 * @ib: IB object to schedule 668 * 669 * Schedule an IB in the DMA ring (VEGA10). 670 */ 671 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 672 struct amdgpu_job *job, 673 struct amdgpu_ib *ib, 674 uint32_t flags) 675 { 676 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 677 678 /* IB packet must end on a 8 DW boundary */ 679 sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 680 681 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 682 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 683 /* base must be 32 byte aligned */ 684 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 685 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 686 amdgpu_ring_write(ring, ib->length_dw); 687 amdgpu_ring_write(ring, 0); 688 amdgpu_ring_write(ring, 0); 689 690 } 691 692 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring, 693 int mem_space, int hdp, 694 uint32_t addr0, uint32_t addr1, 695 uint32_t ref, uint32_t mask, 696 uint32_t inv) 697 { 698 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 699 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 700 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 701 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 702 if (mem_space) { 703 /* memory */ 704 amdgpu_ring_write(ring, addr0); 705 amdgpu_ring_write(ring, addr1); 706 } else { 707 /* registers */ 708 amdgpu_ring_write(ring, addr0 << 2); 709 amdgpu_ring_write(ring, addr1 << 2); 710 } 711 amdgpu_ring_write(ring, ref); /* reference */ 712 amdgpu_ring_write(ring, mask); /* mask */ 713 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 714 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 715 } 716 717 /** 718 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 719 * 720 * @ring: amdgpu ring pointer 721 * 722 * Emit an hdp flush packet on the requested DMA ring. 723 */ 724 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 725 { 726 struct amdgpu_device *adev = ring->adev; 727 u32 ref_and_mask = 0; 728 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg; 729 730 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 731 732 sdma_v4_0_wait_reg_mem(ring, 0, 1, 733 adev->nbio_funcs->get_hdp_flush_done_offset(adev), 734 adev->nbio_funcs->get_hdp_flush_req_offset(adev), 735 ref_and_mask, ref_and_mask, 10); 736 } 737 738 /** 739 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring 740 * 741 * @ring: amdgpu ring pointer 742 * @fence: amdgpu fence object 743 * 744 * Add a DMA fence packet to the ring to write 745 * the fence seq number and DMA trap packet to generate 746 * an interrupt if needed (VEGA10). 747 */ 748 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 749 unsigned flags) 750 { 751 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 752 /* write the fence */ 753 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 754 /* zero in first two bits */ 755 BUG_ON(addr & 0x3); 756 amdgpu_ring_write(ring, lower_32_bits(addr)); 757 amdgpu_ring_write(ring, upper_32_bits(addr)); 758 amdgpu_ring_write(ring, lower_32_bits(seq)); 759 760 /* optionally write high bits as well */ 761 if (write64bit) { 762 addr += 4; 763 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 764 /* zero in first two bits */ 765 BUG_ON(addr & 0x3); 766 amdgpu_ring_write(ring, lower_32_bits(addr)); 767 amdgpu_ring_write(ring, upper_32_bits(addr)); 768 amdgpu_ring_write(ring, upper_32_bits(seq)); 769 } 770 771 /* generate an interrupt */ 772 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 773 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 774 } 775 776 777 /** 778 * sdma_v4_0_gfx_stop - stop the gfx async dma engines 779 * 780 * @adev: amdgpu_device pointer 781 * 782 * Stop the gfx async dma ring buffers (VEGA10). 783 */ 784 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev) 785 { 786 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 787 u32 rb_cntl, ib_cntl; 788 int i, unset = 0; 789 790 for (i = 0; i < adev->sdma.num_instances; i++) { 791 sdma[i] = &adev->sdma.instance[i].ring; 792 793 if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) { 794 amdgpu_ttm_set_buffer_funcs_status(adev, false); 795 unset = 1; 796 } 797 798 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 799 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 800 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 801 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 802 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 803 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 804 805 sdma[i]->sched.ready = false; 806 } 807 } 808 809 /** 810 * sdma_v4_0_rlc_stop - stop the compute async dma engines 811 * 812 * @adev: amdgpu_device pointer 813 * 814 * Stop the compute async dma queues (VEGA10). 815 */ 816 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev) 817 { 818 /* XXX todo */ 819 } 820 821 /** 822 * sdma_v4_0_page_stop - stop the page async dma engines 823 * 824 * @adev: amdgpu_device pointer 825 * 826 * Stop the page async dma ring buffers (VEGA10). 827 */ 828 static void sdma_v4_0_page_stop(struct amdgpu_device *adev) 829 { 830 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 831 u32 rb_cntl, ib_cntl; 832 int i; 833 bool unset = false; 834 835 for (i = 0; i < adev->sdma.num_instances; i++) { 836 sdma[i] = &adev->sdma.instance[i].page; 837 838 if ((adev->mman.buffer_funcs_ring == sdma[i]) && 839 (unset == false)) { 840 amdgpu_ttm_set_buffer_funcs_status(adev, false); 841 unset = true; 842 } 843 844 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 845 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 846 RB_ENABLE, 0); 847 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 848 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 849 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, 850 IB_ENABLE, 0); 851 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 852 853 sdma[i]->sched.ready = false; 854 } 855 } 856 857 /** 858 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch 859 * 860 * @adev: amdgpu_device pointer 861 * @enable: enable/disable the DMA MEs context switch. 862 * 863 * Halt or unhalt the async dma engines context switch (VEGA10). 864 */ 865 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 866 { 867 u32 f32_cntl, phase_quantum = 0; 868 int i; 869 870 if (amdgpu_sdma_phase_quantum) { 871 unsigned value = amdgpu_sdma_phase_quantum; 872 unsigned unit = 0; 873 874 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 875 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 876 value = (value + 1) >> 1; 877 unit++; 878 } 879 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 880 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 881 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 882 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 883 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 884 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 885 WARN_ONCE(1, 886 "clamping sdma_phase_quantum to %uK clock cycles\n", 887 value << unit); 888 } 889 phase_quantum = 890 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 891 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 892 } 893 894 for (i = 0; i < adev->sdma.num_instances; i++) { 895 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL); 896 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 897 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 898 if (enable && amdgpu_sdma_phase_quantum) { 899 WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum); 900 WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum); 901 WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum); 902 } 903 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl); 904 } 905 906 } 907 908 /** 909 * sdma_v4_0_enable - stop the async dma engines 910 * 911 * @adev: amdgpu_device pointer 912 * @enable: enable/disable the DMA MEs. 913 * 914 * Halt or unhalt the async dma engines (VEGA10). 915 */ 916 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) 917 { 918 u32 f32_cntl; 919 int i; 920 921 if (enable == false) { 922 sdma_v4_0_gfx_stop(adev); 923 sdma_v4_0_rlc_stop(adev); 924 if (adev->sdma.has_page_queue) 925 sdma_v4_0_page_stop(adev); 926 } 927 928 for (i = 0; i < adev->sdma.num_instances; i++) { 929 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 930 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 931 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl); 932 } 933 } 934 935 /** 936 * sdma_v4_0_rb_cntl - get parameters for rb_cntl 937 */ 938 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 939 { 940 /* Set ring buffer size in dwords */ 941 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 942 943 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 944 #ifdef __BIG_ENDIAN 945 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 946 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 947 RPTR_WRITEBACK_SWAP_ENABLE, 1); 948 #endif 949 return rb_cntl; 950 } 951 952 /** 953 * sdma_v4_0_gfx_resume - setup and start the async dma engines 954 * 955 * @adev: amdgpu_device pointer 956 * @i: instance to resume 957 * 958 * Set up the gfx DMA ring buffers and enable them (VEGA10). 959 * Returns 0 for success, error for failure. 960 */ 961 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i) 962 { 963 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 964 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 965 u32 wb_offset; 966 u32 doorbell; 967 u32 doorbell_offset; 968 u64 wptr_gpu_addr; 969 970 wb_offset = (ring->rptr_offs * 4); 971 972 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 973 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 974 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 975 976 /* Initialize the ring buffer's read and write pointers */ 977 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0); 978 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0); 979 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0); 980 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0); 981 982 /* set the wb address whether it's enabled or not */ 983 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI, 984 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 985 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 986 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 987 988 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 989 RPTR_WRITEBACK_ENABLE, 1); 990 991 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8); 992 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 993 994 ring->wptr = 0; 995 996 /* before programing wptr to a less value, need set minor_ptr_update first */ 997 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1); 998 999 doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL); 1000 doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET); 1001 1002 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1003 ring->use_doorbell); 1004 doorbell_offset = REG_SET_FIELD(doorbell_offset, 1005 SDMA0_GFX_DOORBELL_OFFSET, 1006 OFFSET, ring->doorbell_index); 1007 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell); 1008 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset); 1009 1010 sdma_v4_0_ring_set_wptr(ring); 1011 1012 /* set minor_ptr_update to 0 after wptr programed */ 1013 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0); 1014 1015 /* setup the wptr shadow polling */ 1016 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1017 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO, 1018 lower_32_bits(wptr_gpu_addr)); 1019 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI, 1020 upper_32_bits(wptr_gpu_addr)); 1021 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL); 1022 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 1023 SDMA0_GFX_RB_WPTR_POLL_CNTL, 1024 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 1025 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 1026 1027 /* enable DMA RB */ 1028 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 1029 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 1030 1031 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 1032 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 1033 #ifdef __BIG_ENDIAN 1034 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 1035 #endif 1036 /* enable DMA IBs */ 1037 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 1038 1039 ring->sched.ready = true; 1040 } 1041 1042 /** 1043 * sdma_v4_0_page_resume - setup and start the async dma engines 1044 * 1045 * @adev: amdgpu_device pointer 1046 * @i: instance to resume 1047 * 1048 * Set up the page DMA ring buffers and enable them (VEGA10). 1049 * Returns 0 for success, error for failure. 1050 */ 1051 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i) 1052 { 1053 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 1054 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 1055 u32 wb_offset; 1056 u32 doorbell; 1057 u32 doorbell_offset; 1058 u64 wptr_gpu_addr; 1059 1060 wb_offset = (ring->rptr_offs * 4); 1061 1062 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 1063 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 1064 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1065 1066 /* Initialize the ring buffer's read and write pointers */ 1067 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0); 1068 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0); 1069 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0); 1070 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0); 1071 1072 /* set the wb address whether it's enabled or not */ 1073 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI, 1074 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 1075 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 1076 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 1077 1078 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 1079 RPTR_WRITEBACK_ENABLE, 1); 1080 1081 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8); 1082 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 1083 1084 ring->wptr = 0; 1085 1086 /* before programing wptr to a less value, need set minor_ptr_update first */ 1087 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1); 1088 1089 doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL); 1090 doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET); 1091 1092 doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE, 1093 ring->use_doorbell); 1094 doorbell_offset = REG_SET_FIELD(doorbell_offset, 1095 SDMA0_PAGE_DOORBELL_OFFSET, 1096 OFFSET, ring->doorbell_index); 1097 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell); 1098 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset); 1099 1100 /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */ 1101 sdma_v4_0_page_ring_set_wptr(ring); 1102 1103 /* set minor_ptr_update to 0 after wptr programed */ 1104 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0); 1105 1106 /* setup the wptr shadow polling */ 1107 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1108 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO, 1109 lower_32_bits(wptr_gpu_addr)); 1110 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI, 1111 upper_32_bits(wptr_gpu_addr)); 1112 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL); 1113 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 1114 SDMA0_PAGE_RB_WPTR_POLL_CNTL, 1115 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 1116 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 1117 1118 /* enable DMA RB */ 1119 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1); 1120 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1121 1122 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 1123 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1); 1124 #ifdef __BIG_ENDIAN 1125 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 1126 #endif 1127 /* enable DMA IBs */ 1128 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 1129 1130 ring->sched.ready = true; 1131 } 1132 1133 static void 1134 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable) 1135 { 1136 uint32_t def, data; 1137 1138 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) { 1139 /* enable idle interrupt */ 1140 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1141 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1142 1143 if (data != def) 1144 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1145 } else { 1146 /* disable idle interrupt */ 1147 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1148 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1149 if (data != def) 1150 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1151 } 1152 } 1153 1154 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev) 1155 { 1156 uint32_t def, data; 1157 1158 /* Enable HW based PG. */ 1159 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1160 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK; 1161 if (data != def) 1162 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1163 1164 /* enable interrupt */ 1165 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1166 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1167 if (data != def) 1168 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1169 1170 /* Configure hold time to filter in-valid power on/off request. Use default right now */ 1171 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1172 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK; 1173 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK); 1174 /* Configure switch time for hysteresis purpose. Use default right now */ 1175 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK; 1176 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK); 1177 if(data != def) 1178 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1179 } 1180 1181 static void sdma_v4_0_init_pg(struct amdgpu_device *adev) 1182 { 1183 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA)) 1184 return; 1185 1186 switch (adev->asic_type) { 1187 case CHIP_RAVEN: 1188 sdma_v4_1_init_power_gating(adev); 1189 sdma_v4_1_update_power_gating(adev, true); 1190 break; 1191 default: 1192 break; 1193 } 1194 } 1195 1196 /** 1197 * sdma_v4_0_rlc_resume - setup and start the async dma engines 1198 * 1199 * @adev: amdgpu_device pointer 1200 * 1201 * Set up the compute DMA queues and enable them (VEGA10). 1202 * Returns 0 for success, error for failure. 1203 */ 1204 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) 1205 { 1206 sdma_v4_0_init_pg(adev); 1207 1208 return 0; 1209 } 1210 1211 /** 1212 * sdma_v4_0_load_microcode - load the sDMA ME ucode 1213 * 1214 * @adev: amdgpu_device pointer 1215 * 1216 * Loads the sDMA0/1 ucode. 1217 * Returns 0 for success, -EINVAL if the ucode is not available. 1218 */ 1219 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 1220 { 1221 const struct sdma_firmware_header_v1_0 *hdr; 1222 const __le32 *fw_data; 1223 u32 fw_size; 1224 int i, j; 1225 1226 /* halt the MEs */ 1227 sdma_v4_0_enable(adev, false); 1228 1229 for (i = 0; i < adev->sdma.num_instances; i++) { 1230 if (!adev->sdma.instance[i].fw) 1231 return -EINVAL; 1232 1233 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 1234 amdgpu_ucode_print_sdma_hdr(&hdr->header); 1235 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1236 1237 fw_data = (const __le32 *) 1238 (adev->sdma.instance[i].fw->data + 1239 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1240 1241 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0); 1242 1243 for (j = 0; j < fw_size; j++) 1244 WREG32_SDMA(i, mmSDMA0_UCODE_DATA, 1245 le32_to_cpup(fw_data++)); 1246 1247 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 1248 adev->sdma.instance[i].fw_version); 1249 } 1250 1251 return 0; 1252 } 1253 1254 /** 1255 * sdma_v4_0_start - setup and start the async dma engines 1256 * 1257 * @adev: amdgpu_device pointer 1258 * 1259 * Set up the DMA engines and enable them (VEGA10). 1260 * Returns 0 for success, error for failure. 1261 */ 1262 static int sdma_v4_0_start(struct amdgpu_device *adev) 1263 { 1264 struct amdgpu_ring *ring; 1265 int i, r = 0; 1266 1267 if (amdgpu_sriov_vf(adev)) { 1268 sdma_v4_0_ctx_switch_enable(adev, false); 1269 sdma_v4_0_enable(adev, false); 1270 } else { 1271 1272 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1273 r = sdma_v4_0_load_microcode(adev); 1274 if (r) 1275 return r; 1276 } 1277 1278 /* unhalt the MEs */ 1279 sdma_v4_0_enable(adev, true); 1280 /* enable sdma ring preemption */ 1281 sdma_v4_0_ctx_switch_enable(adev, true); 1282 } 1283 1284 /* start the gfx rings and rlc compute queues */ 1285 for (i = 0; i < adev->sdma.num_instances; i++) { 1286 uint32_t temp; 1287 1288 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0); 1289 sdma_v4_0_gfx_resume(adev, i); 1290 if (adev->sdma.has_page_queue) 1291 sdma_v4_0_page_resume(adev, i); 1292 1293 /* set utc l1 enable flag always to 1 */ 1294 temp = RREG32_SDMA(i, mmSDMA0_CNTL); 1295 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 1296 WREG32_SDMA(i, mmSDMA0_CNTL, temp); 1297 1298 if (!amdgpu_sriov_vf(adev)) { 1299 /* unhalt engine */ 1300 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1301 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 1302 WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp); 1303 } 1304 } 1305 1306 if (amdgpu_sriov_vf(adev)) { 1307 sdma_v4_0_ctx_switch_enable(adev, true); 1308 sdma_v4_0_enable(adev, true); 1309 } else { 1310 r = sdma_v4_0_rlc_resume(adev); 1311 if (r) 1312 return r; 1313 } 1314 1315 for (i = 0; i < adev->sdma.num_instances; i++) { 1316 ring = &adev->sdma.instance[i].ring; 1317 1318 r = amdgpu_ring_test_helper(ring); 1319 if (r) 1320 return r; 1321 1322 if (adev->sdma.has_page_queue) { 1323 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 1324 1325 r = amdgpu_ring_test_helper(page); 1326 if (r) 1327 return r; 1328 1329 if (adev->mman.buffer_funcs_ring == page) 1330 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1331 } 1332 1333 if (adev->mman.buffer_funcs_ring == ring) 1334 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1335 } 1336 1337 return r; 1338 } 1339 1340 /** 1341 * sdma_v4_0_ring_test_ring - simple async dma engine test 1342 * 1343 * @ring: amdgpu_ring structure holding ring information 1344 * 1345 * Test the DMA engine by writing using it to write an 1346 * value to memory. (VEGA10). 1347 * Returns 0 for success, error for failure. 1348 */ 1349 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) 1350 { 1351 struct amdgpu_device *adev = ring->adev; 1352 unsigned i; 1353 unsigned index; 1354 int r; 1355 u32 tmp; 1356 u64 gpu_addr; 1357 1358 r = amdgpu_device_wb_get(adev, &index); 1359 if (r) 1360 return r; 1361 1362 gpu_addr = adev->wb.gpu_addr + (index * 4); 1363 tmp = 0xCAFEDEAD; 1364 adev->wb.wb[index] = cpu_to_le32(tmp); 1365 1366 r = amdgpu_ring_alloc(ring, 5); 1367 if (r) 1368 goto error_free_wb; 1369 1370 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1371 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1372 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1373 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1374 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1375 amdgpu_ring_write(ring, 0xDEADBEEF); 1376 amdgpu_ring_commit(ring); 1377 1378 for (i = 0; i < adev->usec_timeout; i++) { 1379 tmp = le32_to_cpu(adev->wb.wb[index]); 1380 if (tmp == 0xDEADBEEF) 1381 break; 1382 udelay(1); 1383 } 1384 1385 if (i >= adev->usec_timeout) 1386 r = -ETIMEDOUT; 1387 1388 error_free_wb: 1389 amdgpu_device_wb_free(adev, index); 1390 return r; 1391 } 1392 1393 /** 1394 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine 1395 * 1396 * @ring: amdgpu_ring structure holding ring information 1397 * 1398 * Test a simple IB in the DMA ring (VEGA10). 1399 * Returns 0 on success, error on failure. 1400 */ 1401 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1402 { 1403 struct amdgpu_device *adev = ring->adev; 1404 struct amdgpu_ib ib; 1405 struct dma_fence *f = NULL; 1406 unsigned index; 1407 long r; 1408 u32 tmp = 0; 1409 u64 gpu_addr; 1410 1411 r = amdgpu_device_wb_get(adev, &index); 1412 if (r) 1413 return r; 1414 1415 gpu_addr = adev->wb.gpu_addr + (index * 4); 1416 tmp = 0xCAFEDEAD; 1417 adev->wb.wb[index] = cpu_to_le32(tmp); 1418 memset(&ib, 0, sizeof(ib)); 1419 r = amdgpu_ib_get(adev, NULL, 256, &ib); 1420 if (r) 1421 goto err0; 1422 1423 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1424 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1425 ib.ptr[1] = lower_32_bits(gpu_addr); 1426 ib.ptr[2] = upper_32_bits(gpu_addr); 1427 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1428 ib.ptr[4] = 0xDEADBEEF; 1429 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1430 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1431 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1432 ib.length_dw = 8; 1433 1434 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1435 if (r) 1436 goto err1; 1437 1438 r = dma_fence_wait_timeout(f, false, timeout); 1439 if (r == 0) { 1440 r = -ETIMEDOUT; 1441 goto err1; 1442 } else if (r < 0) { 1443 goto err1; 1444 } 1445 tmp = le32_to_cpu(adev->wb.wb[index]); 1446 if (tmp == 0xDEADBEEF) 1447 r = 0; 1448 else 1449 r = -EINVAL; 1450 1451 err1: 1452 amdgpu_ib_free(adev, &ib, NULL); 1453 dma_fence_put(f); 1454 err0: 1455 amdgpu_device_wb_free(adev, index); 1456 return r; 1457 } 1458 1459 1460 /** 1461 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART 1462 * 1463 * @ib: indirect buffer to fill with commands 1464 * @pe: addr of the page entry 1465 * @src: src addr to copy from 1466 * @count: number of page entries to update 1467 * 1468 * Update PTEs by copying them from the GART using sDMA (VEGA10). 1469 */ 1470 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib, 1471 uint64_t pe, uint64_t src, 1472 unsigned count) 1473 { 1474 unsigned bytes = count * 8; 1475 1476 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1477 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1478 ib->ptr[ib->length_dw++] = bytes - 1; 1479 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1480 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1481 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1482 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1483 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1484 1485 } 1486 1487 /** 1488 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually 1489 * 1490 * @ib: indirect buffer to fill with commands 1491 * @pe: addr of the page entry 1492 * @addr: dst addr to write into pe 1493 * @count: number of page entries to update 1494 * @incr: increase next addr by incr bytes 1495 * @flags: access flags 1496 * 1497 * Update PTEs by writing them manually using sDMA (VEGA10). 1498 */ 1499 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1500 uint64_t value, unsigned count, 1501 uint32_t incr) 1502 { 1503 unsigned ndw = count * 2; 1504 1505 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1506 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1507 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1508 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1509 ib->ptr[ib->length_dw++] = ndw - 1; 1510 for (; ndw > 0; ndw -= 2) { 1511 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1512 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1513 value += incr; 1514 } 1515 } 1516 1517 /** 1518 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA 1519 * 1520 * @ib: indirect buffer to fill with commands 1521 * @pe: addr of the page entry 1522 * @addr: dst addr to write into pe 1523 * @count: number of page entries to update 1524 * @incr: increase next addr by incr bytes 1525 * @flags: access flags 1526 * 1527 * Update the page tables using sDMA (VEGA10). 1528 */ 1529 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1530 uint64_t pe, 1531 uint64_t addr, unsigned count, 1532 uint32_t incr, uint64_t flags) 1533 { 1534 /* for physically contiguous pages (vram) */ 1535 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1536 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1537 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1538 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1539 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1540 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1541 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1542 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1543 ib->ptr[ib->length_dw++] = 0; 1544 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1545 } 1546 1547 /** 1548 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw 1549 * 1550 * @ib: indirect buffer to fill with padding 1551 * 1552 */ 1553 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1554 { 1555 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1556 u32 pad_count; 1557 int i; 1558 1559 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 1560 for (i = 0; i < pad_count; i++) 1561 if (sdma && sdma->burst_nop && (i == 0)) 1562 ib->ptr[ib->length_dw++] = 1563 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1564 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1565 else 1566 ib->ptr[ib->length_dw++] = 1567 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1568 } 1569 1570 1571 /** 1572 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline 1573 * 1574 * @ring: amdgpu_ring pointer 1575 * 1576 * Make sure all previous operations are completed (CIK). 1577 */ 1578 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1579 { 1580 uint32_t seq = ring->fence_drv.sync_seq; 1581 uint64_t addr = ring->fence_drv.gpu_addr; 1582 1583 /* wait for idle */ 1584 sdma_v4_0_wait_reg_mem(ring, 1, 0, 1585 addr & 0xfffffffc, 1586 upper_32_bits(addr) & 0xffffffff, 1587 seq, 0xffffffff, 4); 1588 } 1589 1590 1591 /** 1592 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA 1593 * 1594 * @ring: amdgpu_ring pointer 1595 * @vm: amdgpu_vm pointer 1596 * 1597 * Update the page table base and flush the VM TLB 1598 * using sDMA (VEGA10). 1599 */ 1600 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1601 unsigned vmid, uint64_t pd_addr) 1602 { 1603 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1604 } 1605 1606 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring, 1607 uint32_t reg, uint32_t val) 1608 { 1609 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1610 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1611 amdgpu_ring_write(ring, reg); 1612 amdgpu_ring_write(ring, val); 1613 } 1614 1615 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1616 uint32_t val, uint32_t mask) 1617 { 1618 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1619 } 1620 1621 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev) 1622 { 1623 uint fw_version = adev->sdma.instance[0].fw_version; 1624 1625 switch (adev->asic_type) { 1626 case CHIP_VEGA10: 1627 return fw_version >= 430; 1628 case CHIP_VEGA12: 1629 /*return fw_version >= 31;*/ 1630 return false; 1631 case CHIP_VEGA20: 1632 return fw_version >= 123; 1633 default: 1634 return false; 1635 } 1636 } 1637 1638 static int sdma_v4_0_early_init(void *handle) 1639 { 1640 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1641 int r; 1642 1643 if (adev->asic_type == CHIP_RAVEN) 1644 adev->sdma.num_instances = 1; 1645 else if (adev->asic_type == CHIP_ARCTURUS) 1646 adev->sdma.num_instances = 8; 1647 else 1648 adev->sdma.num_instances = 2; 1649 1650 r = sdma_v4_0_init_microcode(adev); 1651 if (r) { 1652 DRM_ERROR("Failed to load sdma firmware!\n"); 1653 return r; 1654 } 1655 1656 /* TODO: Page queue breaks driver reload under SRIOV */ 1657 if ((adev->asic_type == CHIP_VEGA10) && amdgpu_sriov_vf((adev))) 1658 adev->sdma.has_page_queue = false; 1659 else if (sdma_v4_0_fw_support_paging_queue(adev)) 1660 adev->sdma.has_page_queue = true; 1661 1662 sdma_v4_0_set_ring_funcs(adev); 1663 sdma_v4_0_set_buffer_funcs(adev); 1664 sdma_v4_0_set_vm_pte_funcs(adev); 1665 sdma_v4_0_set_irq_funcs(adev); 1666 1667 return 0; 1668 } 1669 1670 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, 1671 struct ras_err_data *err_data, 1672 struct amdgpu_iv_entry *entry); 1673 1674 static int sdma_v4_0_late_init(void *handle) 1675 { 1676 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1677 struct ras_common_if **ras_if = &adev->sdma.ras_if; 1678 struct ras_ih_if ih_info = { 1679 .cb = sdma_v4_0_process_ras_data_cb, 1680 }; 1681 struct ras_fs_if fs_info = { 1682 .sysfs_name = "sdma_err_count", 1683 .debugfs_name = "sdma_err_inject", 1684 }; 1685 struct ras_common_if ras_block = { 1686 .block = AMDGPU_RAS_BLOCK__SDMA, 1687 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 1688 .sub_block_index = 0, 1689 .name = "sdma", 1690 }; 1691 int r, i; 1692 1693 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 1694 amdgpu_ras_feature_enable_on_boot(adev, &ras_block, 0); 1695 return 0; 1696 } 1697 1698 /* handle resume path. */ 1699 if (*ras_if) { 1700 /* resend ras TA enable cmd during resume. 1701 * prepare to handle failure. 1702 */ 1703 ih_info.head = **ras_if; 1704 r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1); 1705 if (r) { 1706 if (r == -EAGAIN) { 1707 /* request a gpu reset. will run again. */ 1708 amdgpu_ras_request_reset_on_boot(adev, 1709 AMDGPU_RAS_BLOCK__SDMA); 1710 return 0; 1711 } 1712 /* fail to enable ras, cleanup all. */ 1713 goto irq; 1714 } 1715 /* enable successfully. continue. */ 1716 goto resume; 1717 } 1718 1719 *ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL); 1720 if (!*ras_if) 1721 return -ENOMEM; 1722 1723 **ras_if = ras_block; 1724 1725 r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1); 1726 if (r) { 1727 if (r == -EAGAIN) { 1728 amdgpu_ras_request_reset_on_boot(adev, 1729 AMDGPU_RAS_BLOCK__SDMA); 1730 r = 0; 1731 } 1732 goto feature; 1733 } 1734 1735 ih_info.head = **ras_if; 1736 fs_info.head = **ras_if; 1737 1738 r = amdgpu_ras_interrupt_add_handler(adev, &ih_info); 1739 if (r) 1740 goto interrupt; 1741 1742 amdgpu_ras_debugfs_create(adev, &fs_info); 1743 1744 r = amdgpu_ras_sysfs_create(adev, &fs_info); 1745 if (r) 1746 goto sysfs; 1747 resume: 1748 for (i = 0; i < adev->sdma.num_instances; i++) { 1749 r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq, 1750 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1751 if (r) 1752 goto irq; 1753 } 1754 1755 return 0; 1756 irq: 1757 amdgpu_ras_sysfs_remove(adev, *ras_if); 1758 sysfs: 1759 amdgpu_ras_debugfs_remove(adev, *ras_if); 1760 amdgpu_ras_interrupt_remove_handler(adev, &ih_info); 1761 interrupt: 1762 amdgpu_ras_feature_enable(adev, *ras_if, 0); 1763 feature: 1764 kfree(*ras_if); 1765 *ras_if = NULL; 1766 return r; 1767 } 1768 1769 static int sdma_v4_0_sw_init(void *handle) 1770 { 1771 struct amdgpu_ring *ring; 1772 int r, i; 1773 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1774 1775 /* SDMA trap event */ 1776 for (i = 0; i < adev->sdma.num_instances; i++) { 1777 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1778 SDMA0_4_0__SRCID__SDMA_TRAP, 1779 &adev->sdma.trap_irq); 1780 if (r) 1781 return r; 1782 } 1783 1784 /* SDMA SRAM ECC event */ 1785 for (i = 0; i < adev->sdma.num_instances; i++) { 1786 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1787 SDMA0_4_0__SRCID__SDMA_SRAM_ECC, 1788 &adev->sdma.ecc_irq); 1789 if (r) 1790 return r; 1791 } 1792 1793 for (i = 0; i < adev->sdma.num_instances; i++) { 1794 ring = &adev->sdma.instance[i].ring; 1795 ring->ring_obj = NULL; 1796 ring->use_doorbell = true; 1797 1798 DRM_INFO("use_doorbell being set to: [%s]\n", 1799 ring->use_doorbell?"true":"false"); 1800 1801 /* doorbell size is 2 dwords, get DWORD offset */ 1802 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1803 1804 sprintf(ring->name, "sdma%d", i); 1805 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1806 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1807 if (r) 1808 return r; 1809 1810 if (adev->sdma.has_page_queue) { 1811 ring = &adev->sdma.instance[i].page; 1812 ring->ring_obj = NULL; 1813 ring->use_doorbell = true; 1814 1815 /* paging queue use same doorbell index/routing as gfx queue 1816 * with 0x400 (4096 dwords) offset on second doorbell page 1817 */ 1818 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1819 ring->doorbell_index += 0x400; 1820 1821 sprintf(ring->name, "page%d", i); 1822 r = amdgpu_ring_init(adev, ring, 1024, 1823 &adev->sdma.trap_irq, 1824 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1825 if (r) 1826 return r; 1827 } 1828 } 1829 1830 return r; 1831 } 1832 1833 static int sdma_v4_0_sw_fini(void *handle) 1834 { 1835 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1836 int i; 1837 1838 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA) && 1839 adev->sdma.ras_if) { 1840 struct ras_common_if *ras_if = adev->sdma.ras_if; 1841 struct ras_ih_if ih_info = { 1842 .head = *ras_if, 1843 }; 1844 1845 /*remove fs first*/ 1846 amdgpu_ras_debugfs_remove(adev, ras_if); 1847 amdgpu_ras_sysfs_remove(adev, ras_if); 1848 /*remove the IH*/ 1849 amdgpu_ras_interrupt_remove_handler(adev, &ih_info); 1850 amdgpu_ras_feature_enable(adev, ras_if, 0); 1851 kfree(ras_if); 1852 } 1853 1854 for (i = 0; i < adev->sdma.num_instances; i++) { 1855 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1856 if (adev->sdma.has_page_queue) 1857 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1858 } 1859 1860 sdma_v4_0_destroy_inst_ctx(adev); 1861 1862 return 0; 1863 } 1864 1865 static int sdma_v4_0_hw_init(void *handle) 1866 { 1867 int r; 1868 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1869 1870 if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs && 1871 adev->powerplay.pp_funcs->set_powergating_by_smu) 1872 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false); 1873 1874 if (!amdgpu_sriov_vf(adev)) 1875 sdma_v4_0_init_golden_registers(adev); 1876 1877 r = sdma_v4_0_start(adev); 1878 1879 return r; 1880 } 1881 1882 static int sdma_v4_0_hw_fini(void *handle) 1883 { 1884 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1885 int i; 1886 1887 if (amdgpu_sriov_vf(adev)) 1888 return 0; 1889 1890 for (i = 0; i < adev->sdma.num_instances; i++) { 1891 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 1892 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1893 } 1894 1895 sdma_v4_0_ctx_switch_enable(adev, false); 1896 sdma_v4_0_enable(adev, false); 1897 1898 if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs 1899 && adev->powerplay.pp_funcs->set_powergating_by_smu) 1900 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true); 1901 1902 return 0; 1903 } 1904 1905 static int sdma_v4_0_suspend(void *handle) 1906 { 1907 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1908 1909 return sdma_v4_0_hw_fini(adev); 1910 } 1911 1912 static int sdma_v4_0_resume(void *handle) 1913 { 1914 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1915 1916 return sdma_v4_0_hw_init(adev); 1917 } 1918 1919 static bool sdma_v4_0_is_idle(void *handle) 1920 { 1921 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1922 u32 i; 1923 1924 for (i = 0; i < adev->sdma.num_instances; i++) { 1925 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG); 1926 1927 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1928 return false; 1929 } 1930 1931 return true; 1932 } 1933 1934 static int sdma_v4_0_wait_for_idle(void *handle) 1935 { 1936 unsigned i, j; 1937 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; 1938 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1939 1940 for (i = 0; i < adev->usec_timeout; i++) { 1941 for (j = 0; j < adev->sdma.num_instances; j++) { 1942 sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG); 1943 if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK)) 1944 break; 1945 } 1946 if (j == adev->sdma.num_instances) 1947 return 0; 1948 udelay(1); 1949 } 1950 return -ETIMEDOUT; 1951 } 1952 1953 static int sdma_v4_0_soft_reset(void *handle) 1954 { 1955 /* todo */ 1956 1957 return 0; 1958 } 1959 1960 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, 1961 struct amdgpu_irq_src *source, 1962 unsigned type, 1963 enum amdgpu_interrupt_state state) 1964 { 1965 u32 sdma_cntl; 1966 1967 sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL); 1968 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1969 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1970 WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl); 1971 1972 return 0; 1973 } 1974 1975 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, 1976 struct amdgpu_irq_src *source, 1977 struct amdgpu_iv_entry *entry) 1978 { 1979 uint32_t instance; 1980 1981 DRM_DEBUG("IH: SDMA trap\n"); 1982 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 1983 switch (entry->ring_id) { 1984 case 0: 1985 amdgpu_fence_process(&adev->sdma.instance[instance].ring); 1986 break; 1987 case 1: 1988 if (adev->asic_type == CHIP_VEGA20) 1989 amdgpu_fence_process(&adev->sdma.instance[instance].page); 1990 break; 1991 case 2: 1992 /* XXX compute */ 1993 break; 1994 case 3: 1995 if (adev->asic_type != CHIP_VEGA20) 1996 amdgpu_fence_process(&adev->sdma.instance[instance].page); 1997 break; 1998 } 1999 return 0; 2000 } 2001 2002 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, 2003 struct ras_err_data *err_data, 2004 struct amdgpu_iv_entry *entry) 2005 { 2006 uint32_t err_source; 2007 int instance; 2008 2009 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2010 if (instance < 0) 2011 return 0; 2012 2013 switch (entry->src_id) { 2014 case SDMA0_4_0__SRCID__SDMA_SRAM_ECC: 2015 err_source = 0; 2016 break; 2017 case SDMA0_4_0__SRCID__SDMA_ECC: 2018 err_source = 1; 2019 break; 2020 default: 2021 return 0; 2022 } 2023 2024 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); 2025 2026 amdgpu_ras_reset_gpu(adev, 0); 2027 2028 return AMDGPU_RAS_SUCCESS; 2029 } 2030 2031 static int sdma_v4_0_process_ecc_irq(struct amdgpu_device *adev, 2032 struct amdgpu_irq_src *source, 2033 struct amdgpu_iv_entry *entry) 2034 { 2035 struct ras_common_if *ras_if = adev->sdma.ras_if; 2036 struct ras_dispatch_if ih_data = { 2037 .entry = entry, 2038 }; 2039 2040 if (!ras_if) 2041 return 0; 2042 2043 ih_data.head = *ras_if; 2044 2045 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 2046 return 0; 2047 } 2048 2049 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev, 2050 struct amdgpu_irq_src *source, 2051 struct amdgpu_iv_entry *entry) 2052 { 2053 int instance; 2054 2055 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 2056 2057 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2058 if (instance < 0) 2059 return 0; 2060 2061 switch (entry->ring_id) { 2062 case 0: 2063 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 2064 break; 2065 } 2066 return 0; 2067 } 2068 2069 static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev, 2070 struct amdgpu_irq_src *source, 2071 unsigned type, 2072 enum amdgpu_interrupt_state state) 2073 { 2074 u32 sdma_edc_config; 2075 2076 sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG); 2077 sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE, 2078 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2079 WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config); 2080 2081 return 0; 2082 } 2083 2084 static void sdma_v4_0_update_medium_grain_clock_gating( 2085 struct amdgpu_device *adev, 2086 bool enable) 2087 { 2088 uint32_t data, def; 2089 2090 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 2091 /* enable sdma0 clock gating */ 2092 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 2093 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2094 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2095 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2096 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2097 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2098 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2099 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2100 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2101 if (def != data) 2102 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); 2103 2104 if (adev->sdma.num_instances > 1) { 2105 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); 2106 data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2107 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2108 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2109 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2110 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2111 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2112 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2113 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2114 if (def != data) 2115 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 2116 } 2117 } else { 2118 /* disable sdma0 clock gating */ 2119 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 2120 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2121 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2122 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2123 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2124 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2125 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2126 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2127 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2128 2129 if (def != data) 2130 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); 2131 2132 if (adev->sdma.num_instances > 1) { 2133 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); 2134 data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2135 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2136 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2137 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2138 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2139 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2140 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2141 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2142 if (def != data) 2143 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 2144 } 2145 } 2146 } 2147 2148 2149 static void sdma_v4_0_update_medium_grain_light_sleep( 2150 struct amdgpu_device *adev, 2151 bool enable) 2152 { 2153 uint32_t data, def; 2154 2155 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 2156 /* 1-not override: enable sdma0 mem light sleep */ 2157 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 2158 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2159 if (def != data) 2160 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 2161 2162 /* 1-not override: enable sdma1 mem light sleep */ 2163 if (adev->sdma.num_instances > 1) { 2164 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 2165 data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2166 if (def != data) 2167 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 2168 } 2169 } else { 2170 /* 0-override:disable sdma0 mem light sleep */ 2171 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 2172 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2173 if (def != data) 2174 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 2175 2176 /* 0-override:disable sdma1 mem light sleep */ 2177 if (adev->sdma.num_instances > 1) { 2178 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 2179 data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2180 if (def != data) 2181 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 2182 } 2183 } 2184 } 2185 2186 static int sdma_v4_0_set_clockgating_state(void *handle, 2187 enum amd_clockgating_state state) 2188 { 2189 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2190 2191 if (amdgpu_sriov_vf(adev)) 2192 return 0; 2193 2194 switch (adev->asic_type) { 2195 case CHIP_VEGA10: 2196 case CHIP_VEGA12: 2197 case CHIP_VEGA20: 2198 case CHIP_RAVEN: 2199 sdma_v4_0_update_medium_grain_clock_gating(adev, 2200 state == AMD_CG_STATE_GATE ? true : false); 2201 sdma_v4_0_update_medium_grain_light_sleep(adev, 2202 state == AMD_CG_STATE_GATE ? true : false); 2203 break; 2204 default: 2205 break; 2206 } 2207 return 0; 2208 } 2209 2210 static int sdma_v4_0_set_powergating_state(void *handle, 2211 enum amd_powergating_state state) 2212 { 2213 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2214 2215 switch (adev->asic_type) { 2216 case CHIP_RAVEN: 2217 sdma_v4_1_update_power_gating(adev, 2218 state == AMD_PG_STATE_GATE ? true : false); 2219 break; 2220 default: 2221 break; 2222 } 2223 2224 return 0; 2225 } 2226 2227 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags) 2228 { 2229 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2230 int data; 2231 2232 if (amdgpu_sriov_vf(adev)) 2233 *flags = 0; 2234 2235 /* AMD_CG_SUPPORT_SDMA_MGCG */ 2236 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 2237 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 2238 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 2239 2240 /* AMD_CG_SUPPORT_SDMA_LS */ 2241 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 2242 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 2243 *flags |= AMD_CG_SUPPORT_SDMA_LS; 2244 } 2245 2246 const struct amd_ip_funcs sdma_v4_0_ip_funcs = { 2247 .name = "sdma_v4_0", 2248 .early_init = sdma_v4_0_early_init, 2249 .late_init = sdma_v4_0_late_init, 2250 .sw_init = sdma_v4_0_sw_init, 2251 .sw_fini = sdma_v4_0_sw_fini, 2252 .hw_init = sdma_v4_0_hw_init, 2253 .hw_fini = sdma_v4_0_hw_fini, 2254 .suspend = sdma_v4_0_suspend, 2255 .resume = sdma_v4_0_resume, 2256 .is_idle = sdma_v4_0_is_idle, 2257 .wait_for_idle = sdma_v4_0_wait_for_idle, 2258 .soft_reset = sdma_v4_0_soft_reset, 2259 .set_clockgating_state = sdma_v4_0_set_clockgating_state, 2260 .set_powergating_state = sdma_v4_0_set_powergating_state, 2261 .get_clockgating_state = sdma_v4_0_get_clockgating_state, 2262 }; 2263 2264 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { 2265 .type = AMDGPU_RING_TYPE_SDMA, 2266 .align_mask = 0xf, 2267 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2268 .support_64bit_ptrs = true, 2269 .vmhub = AMDGPU_MMHUB_0, 2270 .get_rptr = sdma_v4_0_ring_get_rptr, 2271 .get_wptr = sdma_v4_0_ring_get_wptr, 2272 .set_wptr = sdma_v4_0_ring_set_wptr, 2273 .emit_frame_size = 2274 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2275 3 + /* hdp invalidate */ 2276 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2277 /* sdma_v4_0_ring_emit_vm_flush */ 2278 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2279 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2280 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2281 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2282 .emit_ib = sdma_v4_0_ring_emit_ib, 2283 .emit_fence = sdma_v4_0_ring_emit_fence, 2284 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2285 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2286 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2287 .test_ring = sdma_v4_0_ring_test_ring, 2288 .test_ib = sdma_v4_0_ring_test_ib, 2289 .insert_nop = sdma_v4_0_ring_insert_nop, 2290 .pad_ib = sdma_v4_0_ring_pad_ib, 2291 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2292 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2293 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2294 }; 2295 2296 /* 2297 * On Arcturus, SDMA instance 5~7 has a different vmhub type(AMDGPU_MMHUB_1). 2298 * So create a individual constant ring_funcs for those instances. 2299 */ 2300 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = { 2301 .type = AMDGPU_RING_TYPE_SDMA, 2302 .align_mask = 0xf, 2303 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2304 .support_64bit_ptrs = true, 2305 .vmhub = AMDGPU_MMHUB_1, 2306 .get_rptr = sdma_v4_0_ring_get_rptr, 2307 .get_wptr = sdma_v4_0_ring_get_wptr, 2308 .set_wptr = sdma_v4_0_ring_set_wptr, 2309 .emit_frame_size = 2310 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2311 3 + /* hdp invalidate */ 2312 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2313 /* sdma_v4_0_ring_emit_vm_flush */ 2314 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2315 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2316 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2317 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2318 .emit_ib = sdma_v4_0_ring_emit_ib, 2319 .emit_fence = sdma_v4_0_ring_emit_fence, 2320 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2321 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2322 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2323 .test_ring = sdma_v4_0_ring_test_ring, 2324 .test_ib = sdma_v4_0_ring_test_ib, 2325 .insert_nop = sdma_v4_0_ring_insert_nop, 2326 .pad_ib = sdma_v4_0_ring_pad_ib, 2327 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2328 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2329 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2330 }; 2331 2332 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = { 2333 .type = AMDGPU_RING_TYPE_SDMA, 2334 .align_mask = 0xf, 2335 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2336 .support_64bit_ptrs = true, 2337 .vmhub = AMDGPU_MMHUB_0, 2338 .get_rptr = sdma_v4_0_ring_get_rptr, 2339 .get_wptr = sdma_v4_0_page_ring_get_wptr, 2340 .set_wptr = sdma_v4_0_page_ring_set_wptr, 2341 .emit_frame_size = 2342 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2343 3 + /* hdp invalidate */ 2344 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2345 /* sdma_v4_0_ring_emit_vm_flush */ 2346 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2347 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2348 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2349 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2350 .emit_ib = sdma_v4_0_ring_emit_ib, 2351 .emit_fence = sdma_v4_0_ring_emit_fence, 2352 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2353 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2354 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2355 .test_ring = sdma_v4_0_ring_test_ring, 2356 .test_ib = sdma_v4_0_ring_test_ib, 2357 .insert_nop = sdma_v4_0_ring_insert_nop, 2358 .pad_ib = sdma_v4_0_ring_pad_ib, 2359 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2360 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2361 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2362 }; 2363 2364 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs_2nd_mmhub = { 2365 .type = AMDGPU_RING_TYPE_SDMA, 2366 .align_mask = 0xf, 2367 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2368 .support_64bit_ptrs = true, 2369 .vmhub = AMDGPU_MMHUB_1, 2370 .get_rptr = sdma_v4_0_ring_get_rptr, 2371 .get_wptr = sdma_v4_0_page_ring_get_wptr, 2372 .set_wptr = sdma_v4_0_page_ring_set_wptr, 2373 .emit_frame_size = 2374 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2375 3 + /* hdp invalidate */ 2376 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2377 /* sdma_v4_0_ring_emit_vm_flush */ 2378 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2379 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2380 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2381 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2382 .emit_ib = sdma_v4_0_ring_emit_ib, 2383 .emit_fence = sdma_v4_0_ring_emit_fence, 2384 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2385 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2386 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2387 .test_ring = sdma_v4_0_ring_test_ring, 2388 .test_ib = sdma_v4_0_ring_test_ib, 2389 .insert_nop = sdma_v4_0_ring_insert_nop, 2390 .pad_ib = sdma_v4_0_ring_pad_ib, 2391 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2392 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2393 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2394 }; 2395 2396 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev) 2397 { 2398 int i; 2399 2400 for (i = 0; i < adev->sdma.num_instances; i++) { 2401 if (adev->asic_type == CHIP_ARCTURUS && i >= 5) 2402 adev->sdma.instance[i].ring.funcs = 2403 &sdma_v4_0_ring_funcs_2nd_mmhub; 2404 else 2405 adev->sdma.instance[i].ring.funcs = 2406 &sdma_v4_0_ring_funcs; 2407 adev->sdma.instance[i].ring.me = i; 2408 if (adev->sdma.has_page_queue) { 2409 if (adev->asic_type == CHIP_ARCTURUS && i >= 5) 2410 adev->sdma.instance[i].page.funcs = 2411 &sdma_v4_0_page_ring_funcs_2nd_mmhub; 2412 else 2413 adev->sdma.instance[i].page.funcs = 2414 &sdma_v4_0_page_ring_funcs; 2415 adev->sdma.instance[i].page.me = i; 2416 } 2417 } 2418 } 2419 2420 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = { 2421 .set = sdma_v4_0_set_trap_irq_state, 2422 .process = sdma_v4_0_process_trap_irq, 2423 }; 2424 2425 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = { 2426 .process = sdma_v4_0_process_illegal_inst_irq, 2427 }; 2428 2429 static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = { 2430 .set = sdma_v4_0_set_ecc_irq_state, 2431 .process = sdma_v4_0_process_ecc_irq, 2432 }; 2433 2434 2435 2436 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) 2437 { 2438 switch (adev->sdma.num_instances) { 2439 case 1: 2440 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1; 2441 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1; 2442 break; 2443 case 8: 2444 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 2445 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 2446 break; 2447 case 2: 2448 default: 2449 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2; 2450 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2; 2451 break; 2452 } 2453 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; 2454 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; 2455 adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs; 2456 } 2457 2458 /** 2459 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine 2460 * 2461 * @ring: amdgpu_ring structure holding ring information 2462 * @src_offset: src GPU address 2463 * @dst_offset: dst GPU address 2464 * @byte_count: number of bytes to xfer 2465 * 2466 * Copy GPU buffers using the DMA engine (VEGA10/12). 2467 * Used by the amdgpu ttm implementation to move pages if 2468 * registered as the asic copy callback. 2469 */ 2470 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, 2471 uint64_t src_offset, 2472 uint64_t dst_offset, 2473 uint32_t byte_count) 2474 { 2475 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 2476 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 2477 ib->ptr[ib->length_dw++] = byte_count - 1; 2478 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 2479 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 2480 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 2481 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2482 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2483 } 2484 2485 /** 2486 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine 2487 * 2488 * @ring: amdgpu_ring structure holding ring information 2489 * @src_data: value to write to buffer 2490 * @dst_offset: dst GPU address 2491 * @byte_count: number of bytes to xfer 2492 * 2493 * Fill GPU buffers using the DMA engine (VEGA10/12). 2494 */ 2495 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, 2496 uint32_t src_data, 2497 uint64_t dst_offset, 2498 uint32_t byte_count) 2499 { 2500 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2501 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2502 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2503 ib->ptr[ib->length_dw++] = src_data; 2504 ib->ptr[ib->length_dw++] = byte_count - 1; 2505 } 2506 2507 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { 2508 .copy_max_bytes = 0x400000, 2509 .copy_num_dw = 7, 2510 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, 2511 2512 .fill_max_bytes = 0x400000, 2513 .fill_num_dw = 5, 2514 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, 2515 }; 2516 2517 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) 2518 { 2519 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; 2520 if (adev->sdma.has_page_queue && adev->sdma.num_instances > 1) 2521 adev->mman.buffer_funcs_ring = &adev->sdma.instance[1].page; 2522 else 2523 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2524 } 2525 2526 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 2527 .copy_pte_num_dw = 7, 2528 .copy_pte = sdma_v4_0_vm_copy_pte, 2529 2530 .write_pte = sdma_v4_0_vm_write_pte, 2531 .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 2532 }; 2533 2534 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) 2535 { 2536 struct drm_gpu_scheduler *sched; 2537 unsigned i; 2538 2539 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; 2540 if (adev->sdma.has_page_queue && adev->sdma.num_instances > 1) { 2541 for (i = 1; i < adev->sdma.num_instances; i++) { 2542 sched = &adev->sdma.instance[i].page.sched; 2543 adev->vm_manager.vm_pte_rqs[i - 1] = 2544 &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL]; 2545 } 2546 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances - 1; 2547 adev->vm_manager.page_fault = &adev->sdma.instance[0].page; 2548 } else { 2549 for (i = 0; i < adev->sdma.num_instances; i++) { 2550 sched = &adev->sdma.instance[i].ring.sched; 2551 adev->vm_manager.vm_pte_rqs[i] = 2552 &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL]; 2553 } 2554 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances; 2555 } 2556 } 2557 2558 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = { 2559 .type = AMD_IP_BLOCK_TYPE_SDMA, 2560 .major = 4, 2561 .minor = 0, 2562 .rev = 0, 2563 .funcs = &sdma_v4_0_ip_funcs, 2564 }; 2565