1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "sdma0/sdma0_4_2_offset.h" 34 #include "sdma0/sdma0_4_2_sh_mask.h" 35 #include "sdma1/sdma1_4_2_offset.h" 36 #include "sdma1/sdma1_4_2_sh_mask.h" 37 #include "sdma2/sdma2_4_2_2_offset.h" 38 #include "sdma2/sdma2_4_2_2_sh_mask.h" 39 #include "sdma3/sdma3_4_2_2_offset.h" 40 #include "sdma3/sdma3_4_2_2_sh_mask.h" 41 #include "sdma4/sdma4_4_2_2_offset.h" 42 #include "sdma4/sdma4_4_2_2_sh_mask.h" 43 #include "sdma5/sdma5_4_2_2_offset.h" 44 #include "sdma5/sdma5_4_2_2_sh_mask.h" 45 #include "sdma6/sdma6_4_2_2_offset.h" 46 #include "sdma6/sdma6_4_2_2_sh_mask.h" 47 #include "sdma7/sdma7_4_2_2_offset.h" 48 #include "sdma7/sdma7_4_2_2_sh_mask.h" 49 #include "sdma0/sdma0_4_1_default.h" 50 51 #include "soc15_common.h" 52 #include "soc15.h" 53 #include "vega10_sdma_pkt_open.h" 54 55 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 56 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 57 58 #include "amdgpu_ras.h" 59 #include "sdma_v4_4.h" 60 61 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); 62 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); 63 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin"); 65 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin"); 66 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin"); 67 MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); 68 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin"); 69 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin"); 70 MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin"); 71 MODULE_FIRMWARE("amdgpu/renoir_sdma.bin"); 72 MODULE_FIRMWARE("amdgpu/green_sardine_sdma.bin"); 73 MODULE_FIRMWARE("amdgpu/aldebaran_sdma.bin"); 74 75 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 76 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 77 78 #define WREG32_SDMA(instance, offset, value) \ 79 WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value) 80 #define RREG32_SDMA(instance, offset) \ 81 RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset))) 82 83 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); 84 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); 85 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); 86 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); 87 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev); 88 89 static const struct soc15_reg_golden golden_settings_sdma_4[] = { 90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100), 92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100), 93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 94 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000), 97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 99 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 100 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 101 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 102 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000), 103 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 104 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100), 105 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 106 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 107 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 108 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000), 109 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 110 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 111 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 112 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 113 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 114 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000) 115 }; 116 117 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { 118 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 119 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 120 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 121 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 122 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 123 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 124 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 125 }; 126 127 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = { 128 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 129 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 130 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 131 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 132 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 133 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 134 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 135 }; 136 137 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = { 138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100), 141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 142 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051), 143 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100), 144 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100), 146 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 147 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003e0), 148 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000) 149 }; 150 151 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = { 152 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 153 }; 154 155 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] = 156 { 157 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 158 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 159 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 160 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 161 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 162 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 163 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 164 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 165 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003), 166 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 167 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 168 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 169 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 170 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 171 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 172 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 173 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 174 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 175 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 176 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 177 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 178 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 179 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 180 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 181 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 182 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 183 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 184 }; 185 186 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = { 187 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 188 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 189 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 190 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 191 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 192 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 193 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 194 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 195 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003), 196 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 197 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 198 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 199 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 200 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 201 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 202 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 203 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 204 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 205 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 206 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 207 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 208 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 209 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 210 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 211 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 212 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 213 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 214 }; 215 216 static const struct soc15_reg_golden golden_settings_sdma_rv1[] = 217 { 218 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 219 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002) 220 }; 221 222 static const struct soc15_reg_golden golden_settings_sdma_rv2[] = 223 { 224 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001), 225 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001) 226 }; 227 228 static const struct soc15_reg_golden golden_settings_sdma_arct[] = 229 { 230 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 231 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 232 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 233 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 234 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 235 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 236 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 237 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 238 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 239 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 240 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 241 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 242 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 243 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 244 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 245 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 246 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 247 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 248 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 249 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 250 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 251 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 252 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 253 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 254 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 255 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 256 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 257 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 258 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 259 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 260 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 261 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_UTCL1_TIMEOUT, 0xffffffff, 0x00010001) 262 }; 263 264 static const struct soc15_reg_golden golden_settings_sdma_aldebaran[] = { 265 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 266 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 267 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 268 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 269 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 270 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 271 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 272 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 273 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 274 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 275 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 276 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 277 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 278 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 279 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001), 280 }; 281 282 static const struct soc15_reg_golden golden_settings_sdma_4_3[] = { 283 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 284 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 285 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 286 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002), 287 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 288 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051), 289 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 290 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 291 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003e0), 292 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x03fbe1fe) 293 }; 294 295 static const struct soc15_ras_field_entry sdma_v4_0_ras_fields[] = { 296 { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 297 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UCODE_BUF_SED), 298 0, 0, 299 }, 300 { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 301 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_RB_CMD_BUF_SED), 302 0, 0, 303 }, 304 { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 305 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_IB_CMD_BUF_SED), 306 0, 0, 307 }, 308 { "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 309 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RD_FIFO_SED), 310 0, 0, 311 }, 312 { "SDMA_UTCL1_RDBST_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 313 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RDBST_FIFO_SED), 314 0, 0, 315 }, 316 { "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 317 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_DATA_LUT_FIFO_SED), 318 0, 0, 319 }, 320 { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 321 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF0_SED), 322 0, 0, 323 }, 324 { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 325 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF1_SED), 326 0, 0, 327 }, 328 { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 329 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF2_SED), 330 0, 0, 331 }, 332 { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 333 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF3_SED), 334 0, 0, 335 }, 336 { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 337 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF4_SED), 338 0, 0, 339 }, 340 { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 341 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF5_SED), 342 0, 0, 343 }, 344 { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 345 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF6_SED), 346 0, 0, 347 }, 348 { "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 349 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF7_SED), 350 0, 0, 351 }, 352 { "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 353 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF8_SED), 354 0, 0, 355 }, 356 { "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 357 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF9_SED), 358 0, 0, 359 }, 360 { "SDMA_MBANK_DATA_BUF10_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 361 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF10_SED), 362 0, 0, 363 }, 364 { "SDMA_MBANK_DATA_BUF11_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 365 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF11_SED), 366 0, 0, 367 }, 368 { "SDMA_MBANK_DATA_BUF12_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 369 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF12_SED), 370 0, 0, 371 }, 372 { "SDMA_MBANK_DATA_BUF13_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 373 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF13_SED), 374 0, 0, 375 }, 376 { "SDMA_MBANK_DATA_BUF14_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 377 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF14_SED), 378 0, 0, 379 }, 380 { "SDMA_MBANK_DATA_BUF15_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 381 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF15_SED), 382 0, 0, 383 }, 384 { "SDMA_SPLIT_DAT_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 385 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_SPLIT_DAT_BUF_SED), 386 0, 0, 387 }, 388 { "SDMA_MC_WR_ADDR_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 389 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MC_WR_ADDR_FIFO_SED), 390 0, 0, 391 }, 392 }; 393 394 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, 395 u32 instance, u32 offset) 396 { 397 switch (instance) { 398 case 0: 399 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset); 400 case 1: 401 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset); 402 case 2: 403 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset); 404 case 3: 405 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset); 406 case 4: 407 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset); 408 case 5: 409 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset); 410 case 6: 411 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset); 412 case 7: 413 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset); 414 default: 415 break; 416 } 417 return 0; 418 } 419 420 static unsigned sdma_v4_0_seq_to_irq_id(int seq_num) 421 { 422 switch (seq_num) { 423 case 0: 424 return SOC15_IH_CLIENTID_SDMA0; 425 case 1: 426 return SOC15_IH_CLIENTID_SDMA1; 427 case 2: 428 return SOC15_IH_CLIENTID_SDMA2; 429 case 3: 430 return SOC15_IH_CLIENTID_SDMA3; 431 case 4: 432 return SOC15_IH_CLIENTID_SDMA4; 433 case 5: 434 return SOC15_IH_CLIENTID_SDMA5; 435 case 6: 436 return SOC15_IH_CLIENTID_SDMA6; 437 case 7: 438 return SOC15_IH_CLIENTID_SDMA7; 439 default: 440 break; 441 } 442 return -EINVAL; 443 } 444 445 static int sdma_v4_0_irq_id_to_seq(unsigned client_id) 446 { 447 switch (client_id) { 448 case SOC15_IH_CLIENTID_SDMA0: 449 return 0; 450 case SOC15_IH_CLIENTID_SDMA1: 451 return 1; 452 case SOC15_IH_CLIENTID_SDMA2: 453 return 2; 454 case SOC15_IH_CLIENTID_SDMA3: 455 return 3; 456 case SOC15_IH_CLIENTID_SDMA4: 457 return 4; 458 case SOC15_IH_CLIENTID_SDMA5: 459 return 5; 460 case SOC15_IH_CLIENTID_SDMA6: 461 return 6; 462 case SOC15_IH_CLIENTID_SDMA7: 463 return 7; 464 default: 465 break; 466 } 467 return -EINVAL; 468 } 469 470 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 471 { 472 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 473 case IP_VERSION(4, 0, 0): 474 soc15_program_register_sequence(adev, 475 golden_settings_sdma_4, 476 ARRAY_SIZE(golden_settings_sdma_4)); 477 soc15_program_register_sequence(adev, 478 golden_settings_sdma_vg10, 479 ARRAY_SIZE(golden_settings_sdma_vg10)); 480 break; 481 case IP_VERSION(4, 0, 1): 482 soc15_program_register_sequence(adev, 483 golden_settings_sdma_4, 484 ARRAY_SIZE(golden_settings_sdma_4)); 485 soc15_program_register_sequence(adev, 486 golden_settings_sdma_vg12, 487 ARRAY_SIZE(golden_settings_sdma_vg12)); 488 break; 489 case IP_VERSION(4, 2, 0): 490 soc15_program_register_sequence(adev, 491 golden_settings_sdma0_4_2_init, 492 ARRAY_SIZE(golden_settings_sdma0_4_2_init)); 493 soc15_program_register_sequence(adev, 494 golden_settings_sdma0_4_2, 495 ARRAY_SIZE(golden_settings_sdma0_4_2)); 496 soc15_program_register_sequence(adev, 497 golden_settings_sdma1_4_2, 498 ARRAY_SIZE(golden_settings_sdma1_4_2)); 499 break; 500 case IP_VERSION(4, 2, 2): 501 soc15_program_register_sequence(adev, 502 golden_settings_sdma_arct, 503 ARRAY_SIZE(golden_settings_sdma_arct)); 504 break; 505 case IP_VERSION(4, 4, 0): 506 soc15_program_register_sequence(adev, 507 golden_settings_sdma_aldebaran, 508 ARRAY_SIZE(golden_settings_sdma_aldebaran)); 509 break; 510 case IP_VERSION(4, 1, 0): 511 case IP_VERSION(4, 1, 1): 512 soc15_program_register_sequence(adev, 513 golden_settings_sdma_4_1, 514 ARRAY_SIZE(golden_settings_sdma_4_1)); 515 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 516 soc15_program_register_sequence(adev, 517 golden_settings_sdma_rv2, 518 ARRAY_SIZE(golden_settings_sdma_rv2)); 519 else 520 soc15_program_register_sequence(adev, 521 golden_settings_sdma_rv1, 522 ARRAY_SIZE(golden_settings_sdma_rv1)); 523 break; 524 case IP_VERSION(4, 1, 2): 525 soc15_program_register_sequence(adev, 526 golden_settings_sdma_4_3, 527 ARRAY_SIZE(golden_settings_sdma_4_3)); 528 break; 529 default: 530 break; 531 } 532 } 533 534 static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev) 535 { 536 int i; 537 538 /* 539 * The only chips with SDMAv4 and ULV are VG10 and VG20. 540 * Server SKUs take a different hysteresis setting from other SKUs. 541 */ 542 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 543 case IP_VERSION(4, 0, 0): 544 if (adev->pdev->device == 0x6860) 545 break; 546 return; 547 case IP_VERSION(4, 2, 0): 548 if (adev->pdev->device == 0x66a1) 549 break; 550 return; 551 default: 552 return; 553 } 554 555 for (i = 0; i < adev->sdma.num_instances; i++) { 556 uint32_t temp; 557 558 temp = RREG32_SDMA(i, mmSDMA0_ULV_CNTL); 559 temp = REG_SET_FIELD(temp, SDMA0_ULV_CNTL, HYSTERESIS, 0x0); 560 WREG32_SDMA(i, mmSDMA0_ULV_CNTL, temp); 561 } 562 } 563 564 /** 565 * sdma_v4_0_init_microcode - load ucode images from disk 566 * 567 * @adev: amdgpu_device pointer 568 * 569 * Use the firmware interface to load the ucode images into 570 * the driver (not loaded into hw). 571 * Returns 0 on success, error on failure. 572 */ 573 574 // emulation only, won't work on real chip 575 // vega10 real chip need to use PSP to load firmware 576 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) 577 { 578 int ret, i; 579 580 for (i = 0; i < adev->sdma.num_instances; i++) { 581 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == 582 IP_VERSION(4, 2, 2) || 583 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == 584 IP_VERSION(4, 4, 0)) { 585 /* Acturus & Aldebaran will leverage the same FW memory 586 for every SDMA instance */ 587 ret = amdgpu_sdma_init_microcode(adev, 0, true); 588 break; 589 } else { 590 ret = amdgpu_sdma_init_microcode(adev, i, false); 591 if (ret) 592 return ret; 593 } 594 } 595 596 return ret; 597 } 598 599 /** 600 * sdma_v4_0_ring_get_rptr - get the current read pointer 601 * 602 * @ring: amdgpu ring pointer 603 * 604 * Get the current rptr from the hardware (VEGA10+). 605 */ 606 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) 607 { 608 u64 *rptr; 609 610 /* XXX check if swapping is necessary on BE */ 611 rptr = ((u64 *)ring->rptr_cpu_addr); 612 613 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 614 return ((*rptr) >> 2); 615 } 616 617 /** 618 * sdma_v4_0_ring_get_wptr - get the current write pointer 619 * 620 * @ring: amdgpu ring pointer 621 * 622 * Get the current wptr from the hardware (VEGA10+). 623 */ 624 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 625 { 626 struct amdgpu_device *adev = ring->adev; 627 u64 wptr; 628 629 if (ring->use_doorbell) { 630 /* XXX check if swapping is necessary on BE */ 631 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 632 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 633 } else { 634 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI); 635 wptr = wptr << 32; 636 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR); 637 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", 638 ring->me, wptr); 639 } 640 641 return wptr >> 2; 642 } 643 644 /** 645 * sdma_v4_0_ring_set_wptr - commit the write pointer 646 * 647 * @ring: amdgpu ring pointer 648 * 649 * Write the wptr back to the hardware (VEGA10+). 650 */ 651 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) 652 { 653 struct amdgpu_device *adev = ring->adev; 654 655 DRM_DEBUG("Setting write pointer\n"); 656 if (ring->use_doorbell) { 657 u64 *wb = (u64 *)ring->wptr_cpu_addr; 658 659 DRM_DEBUG("Using doorbell -- " 660 "wptr_offs == 0x%08x " 661 "lower_32_bits(ring->wptr << 2) == 0x%08x " 662 "upper_32_bits(ring->wptr << 2) == 0x%08x\n", 663 ring->wptr_offs, 664 lower_32_bits(ring->wptr << 2), 665 upper_32_bits(ring->wptr << 2)); 666 /* XXX check if swapping is necessary on BE */ 667 WRITE_ONCE(*wb, (ring->wptr << 2)); 668 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 669 ring->doorbell_index, ring->wptr << 2); 670 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 671 } else { 672 DRM_DEBUG("Not using doorbell -- " 673 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 674 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 675 ring->me, 676 lower_32_bits(ring->wptr << 2), 677 ring->me, 678 upper_32_bits(ring->wptr << 2)); 679 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR, 680 lower_32_bits(ring->wptr << 2)); 681 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI, 682 upper_32_bits(ring->wptr << 2)); 683 } 684 } 685 686 /** 687 * sdma_v4_0_page_ring_get_wptr - get the current write pointer 688 * 689 * @ring: amdgpu ring pointer 690 * 691 * Get the current wptr from the hardware (VEGA10+). 692 */ 693 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring) 694 { 695 struct amdgpu_device *adev = ring->adev; 696 u64 wptr; 697 698 if (ring->use_doorbell) { 699 /* XXX check if swapping is necessary on BE */ 700 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 701 } else { 702 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI); 703 wptr = wptr << 32; 704 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR); 705 } 706 707 return wptr >> 2; 708 } 709 710 /** 711 * sdma_v4_0_page_ring_set_wptr - commit the write pointer 712 * 713 * @ring: amdgpu ring pointer 714 * 715 * Write the wptr back to the hardware (VEGA10+). 716 */ 717 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring) 718 { 719 struct amdgpu_device *adev = ring->adev; 720 721 if (ring->use_doorbell) { 722 u64 *wb = (u64 *)ring->wptr_cpu_addr; 723 724 /* XXX check if swapping is necessary on BE */ 725 WRITE_ONCE(*wb, (ring->wptr << 2)); 726 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 727 } else { 728 uint64_t wptr = ring->wptr << 2; 729 730 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR, 731 lower_32_bits(wptr)); 732 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI, 733 upper_32_bits(wptr)); 734 } 735 } 736 737 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 738 { 739 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 740 int i; 741 742 for (i = 0; i < count; i++) 743 if (sdma && sdma->burst_nop && (i == 0)) 744 amdgpu_ring_write(ring, ring->funcs->nop | 745 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 746 else 747 amdgpu_ring_write(ring, ring->funcs->nop); 748 } 749 750 /** 751 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine 752 * 753 * @ring: amdgpu ring pointer 754 * @job: job to retrieve vmid from 755 * @ib: IB object to schedule 756 * @flags: unused 757 * 758 * Schedule an IB in the DMA ring (VEGA10). 759 */ 760 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 761 struct amdgpu_job *job, 762 struct amdgpu_ib *ib, 763 uint32_t flags) 764 { 765 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 766 767 /* IB packet must end on a 8 DW boundary */ 768 sdma_v4_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 769 770 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 771 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 772 /* base must be 32 byte aligned */ 773 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 774 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 775 amdgpu_ring_write(ring, ib->length_dw); 776 amdgpu_ring_write(ring, 0); 777 amdgpu_ring_write(ring, 0); 778 779 } 780 781 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring, 782 int mem_space, int hdp, 783 uint32_t addr0, uint32_t addr1, 784 uint32_t ref, uint32_t mask, 785 uint32_t inv) 786 { 787 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 788 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 789 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 790 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 791 if (mem_space) { 792 /* memory */ 793 amdgpu_ring_write(ring, addr0); 794 amdgpu_ring_write(ring, addr1); 795 } else { 796 /* registers */ 797 amdgpu_ring_write(ring, addr0 << 2); 798 amdgpu_ring_write(ring, addr1 << 2); 799 } 800 amdgpu_ring_write(ring, ref); /* reference */ 801 amdgpu_ring_write(ring, mask); /* mask */ 802 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 803 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 804 } 805 806 /** 807 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 808 * 809 * @ring: amdgpu ring pointer 810 * 811 * Emit an hdp flush packet on the requested DMA ring. 812 */ 813 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 814 { 815 struct amdgpu_device *adev = ring->adev; 816 u32 ref_and_mask = 0; 817 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 818 819 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 820 821 sdma_v4_0_wait_reg_mem(ring, 0, 1, 822 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 823 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 824 ref_and_mask, ref_and_mask, 10); 825 } 826 827 /** 828 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring 829 * 830 * @ring: amdgpu ring pointer 831 * @addr: address 832 * @seq: sequence number 833 * @flags: fence related flags 834 * 835 * Add a DMA fence packet to the ring to write 836 * the fence seq number and DMA trap packet to generate 837 * an interrupt if needed (VEGA10). 838 */ 839 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 840 unsigned flags) 841 { 842 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 843 /* write the fence */ 844 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 845 /* zero in first two bits */ 846 BUG_ON(addr & 0x3); 847 amdgpu_ring_write(ring, lower_32_bits(addr)); 848 amdgpu_ring_write(ring, upper_32_bits(addr)); 849 amdgpu_ring_write(ring, lower_32_bits(seq)); 850 851 /* optionally write high bits as well */ 852 if (write64bit) { 853 addr += 4; 854 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 855 /* zero in first two bits */ 856 BUG_ON(addr & 0x3); 857 amdgpu_ring_write(ring, lower_32_bits(addr)); 858 amdgpu_ring_write(ring, upper_32_bits(addr)); 859 amdgpu_ring_write(ring, upper_32_bits(seq)); 860 } 861 862 /* generate an interrupt */ 863 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 864 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 865 } 866 867 868 /** 869 * sdma_v4_0_gfx_enable - enable the gfx async dma engines 870 * 871 * @adev: amdgpu_device pointer 872 * @enable: enable SDMA RB/IB 873 * control the gfx async dma ring buffers (VEGA10). 874 */ 875 static void sdma_v4_0_gfx_enable(struct amdgpu_device *adev, bool enable) 876 { 877 u32 rb_cntl, ib_cntl; 878 int i; 879 880 amdgpu_sdma_unset_buffer_funcs_helper(adev); 881 882 for (i = 0; i < adev->sdma.num_instances; i++) { 883 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 884 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, enable ? 1 : 0); 885 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 886 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 887 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, enable ? 1 : 0); 888 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 889 } 890 } 891 892 /** 893 * sdma_v4_0_rlc_stop - stop the compute async dma engines 894 * 895 * @adev: amdgpu_device pointer 896 * 897 * Stop the compute async dma queues (VEGA10). 898 */ 899 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev) 900 { 901 /* XXX todo */ 902 } 903 904 /** 905 * sdma_v4_0_page_stop - stop the page async dma engines 906 * 907 * @adev: amdgpu_device pointer 908 * 909 * Stop the page async dma ring buffers (VEGA10). 910 */ 911 static void sdma_v4_0_page_stop(struct amdgpu_device *adev) 912 { 913 u32 rb_cntl, ib_cntl; 914 int i; 915 916 amdgpu_sdma_unset_buffer_funcs_helper(adev); 917 918 for (i = 0; i < adev->sdma.num_instances; i++) { 919 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 920 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 921 RB_ENABLE, 0); 922 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 923 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 924 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, 925 IB_ENABLE, 0); 926 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 927 } 928 } 929 930 /** 931 * sdma_v4_0_ctx_switch_enable - stop the async dma engines context switch 932 * 933 * @adev: amdgpu_device pointer 934 * @enable: enable/disable the DMA MEs context switch. 935 * 936 * Halt or unhalt the async dma engines context switch (VEGA10). 937 */ 938 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 939 { 940 u32 f32_cntl, phase_quantum = 0; 941 int i; 942 943 if (amdgpu_sdma_phase_quantum) { 944 unsigned value = amdgpu_sdma_phase_quantum; 945 unsigned unit = 0; 946 947 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 948 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 949 value = (value + 1) >> 1; 950 unit++; 951 } 952 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 953 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 954 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 955 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 956 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 957 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 958 WARN_ONCE(1, 959 "clamping sdma_phase_quantum to %uK clock cycles\n", 960 value << unit); 961 } 962 phase_quantum = 963 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 964 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 965 } 966 967 for (i = 0; i < adev->sdma.num_instances; i++) { 968 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL); 969 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 970 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 971 if (enable && amdgpu_sdma_phase_quantum) { 972 WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum); 973 WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum); 974 WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum); 975 } 976 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl); 977 978 /* 979 * Enable SDMA utilization. Its only supported on 980 * Arcturus for the moment and firmware version 14 981 * and above. 982 */ 983 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == 984 IP_VERSION(4, 2, 2) && 985 adev->sdma.instance[i].fw_version >= 14) 986 WREG32_SDMA(i, mmSDMA0_PUB_DUMMY_REG2, enable); 987 /* Extend page fault timeout to avoid interrupt storm */ 988 WREG32_SDMA(i, mmSDMA0_UTCL1_TIMEOUT, 0x00800080); 989 } 990 991 } 992 993 /** 994 * sdma_v4_0_enable - stop the async dma engines 995 * 996 * @adev: amdgpu_device pointer 997 * @enable: enable/disable the DMA MEs. 998 * 999 * Halt or unhalt the async dma engines (VEGA10). 1000 */ 1001 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) 1002 { 1003 u32 f32_cntl; 1004 int i; 1005 1006 if (!enable) { 1007 sdma_v4_0_gfx_enable(adev, enable); 1008 sdma_v4_0_rlc_stop(adev); 1009 if (adev->sdma.has_page_queue) 1010 sdma_v4_0_page_stop(adev); 1011 } 1012 1013 for (i = 0; i < adev->sdma.num_instances; i++) { 1014 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1015 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 1016 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl); 1017 } 1018 } 1019 1020 /* 1021 * sdma_v4_0_rb_cntl - get parameters for rb_cntl 1022 */ 1023 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) 1024 { 1025 /* Set ring buffer size in dwords */ 1026 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); 1027 1028 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 1029 #ifdef __BIG_ENDIAN 1030 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 1031 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 1032 RPTR_WRITEBACK_SWAP_ENABLE, 1); 1033 #endif 1034 return rb_cntl; 1035 } 1036 1037 /** 1038 * sdma_v4_0_gfx_resume - setup and start the async dma engines 1039 * 1040 * @adev: amdgpu_device pointer 1041 * @i: instance to resume 1042 * 1043 * Set up the gfx DMA ring buffers and enable them (VEGA10). 1044 * Returns 0 for success, error for failure. 1045 */ 1046 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i) 1047 { 1048 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring; 1049 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 1050 u32 doorbell; 1051 u32 doorbell_offset; 1052 u64 wptr_gpu_addr; 1053 1054 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); 1055 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 1056 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 1057 1058 /* Initialize the ring buffer's read and write pointers */ 1059 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0); 1060 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0); 1061 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0); 1062 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0); 1063 1064 /* set the wb address whether it's enabled or not */ 1065 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI, 1066 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 1067 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 1068 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 1069 1070 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 1071 RPTR_WRITEBACK_ENABLE, 1); 1072 1073 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8); 1074 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40); 1075 1076 ring->wptr = 0; 1077 1078 /* before programing wptr to a less value, need set minor_ptr_update first */ 1079 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1); 1080 1081 doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL); 1082 doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET); 1083 1084 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1085 ring->use_doorbell); 1086 doorbell_offset = REG_SET_FIELD(doorbell_offset, 1087 SDMA0_GFX_DOORBELL_OFFSET, 1088 OFFSET, ring->doorbell_index); 1089 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell); 1090 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset); 1091 1092 sdma_v4_0_ring_set_wptr(ring); 1093 1094 /* set minor_ptr_update to 0 after wptr programed */ 1095 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0); 1096 1097 /* setup the wptr shadow polling */ 1098 wptr_gpu_addr = ring->wptr_gpu_addr; 1099 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO, 1100 lower_32_bits(wptr_gpu_addr)); 1101 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI, 1102 upper_32_bits(wptr_gpu_addr)); 1103 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL); 1104 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 1105 SDMA0_GFX_RB_WPTR_POLL_CNTL, 1106 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 1107 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 1108 1109 /* enable DMA RB */ 1110 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 1111 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); 1112 1113 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); 1114 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 1115 #ifdef __BIG_ENDIAN 1116 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 1117 #endif 1118 /* enable DMA IBs */ 1119 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); 1120 } 1121 1122 /** 1123 * sdma_v4_0_page_resume - setup and start the async dma engines 1124 * 1125 * @adev: amdgpu_device pointer 1126 * @i: instance to resume 1127 * 1128 * Set up the page DMA ring buffers and enable them (VEGA10). 1129 * Returns 0 for success, error for failure. 1130 */ 1131 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i) 1132 { 1133 struct amdgpu_ring *ring = &adev->sdma.instance[i].page; 1134 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 1135 u32 doorbell; 1136 u32 doorbell_offset; 1137 u64 wptr_gpu_addr; 1138 1139 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); 1140 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); 1141 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1142 1143 /* Initialize the ring buffer's read and write pointers */ 1144 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0); 1145 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0); 1146 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0); 1147 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0); 1148 1149 /* set the wb address whether it's enabled or not */ 1150 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI, 1151 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 1152 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 1153 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 1154 1155 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, 1156 RPTR_WRITEBACK_ENABLE, 1); 1157 1158 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8); 1159 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40); 1160 1161 ring->wptr = 0; 1162 1163 /* before programing wptr to a less value, need set minor_ptr_update first */ 1164 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1); 1165 1166 doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL); 1167 doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET); 1168 1169 doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE, 1170 ring->use_doorbell); 1171 doorbell_offset = REG_SET_FIELD(doorbell_offset, 1172 SDMA0_PAGE_DOORBELL_OFFSET, 1173 OFFSET, ring->doorbell_index); 1174 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell); 1175 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset); 1176 1177 /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */ 1178 sdma_v4_0_page_ring_set_wptr(ring); 1179 1180 /* set minor_ptr_update to 0 after wptr programed */ 1181 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0); 1182 1183 /* setup the wptr shadow polling */ 1184 wptr_gpu_addr = ring->wptr_gpu_addr; 1185 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO, 1186 lower_32_bits(wptr_gpu_addr)); 1187 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI, 1188 upper_32_bits(wptr_gpu_addr)); 1189 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL); 1190 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 1191 SDMA0_PAGE_RB_WPTR_POLL_CNTL, 1192 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0); 1193 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl); 1194 1195 /* enable DMA RB */ 1196 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1); 1197 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); 1198 1199 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL); 1200 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1); 1201 #ifdef __BIG_ENDIAN 1202 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1); 1203 #endif 1204 /* enable DMA IBs */ 1205 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl); 1206 } 1207 1208 static void 1209 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable) 1210 { 1211 uint32_t def, data; 1212 1213 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) { 1214 /* enable idle interrupt */ 1215 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1216 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1217 1218 if (data != def) 1219 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1220 } else { 1221 /* disable idle interrupt */ 1222 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1223 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1224 if (data != def) 1225 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1226 } 1227 } 1228 1229 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev) 1230 { 1231 uint32_t def, data; 1232 1233 /* Enable HW based PG. */ 1234 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1235 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK; 1236 if (data != def) 1237 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1238 1239 /* enable interrupt */ 1240 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 1241 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 1242 if (data != def) 1243 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 1244 1245 /* Configure hold time to filter in-valid power on/off request. Use default right now */ 1246 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1247 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK; 1248 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK); 1249 /* Configure switch time for hysteresis purpose. Use default right now */ 1250 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK; 1251 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK); 1252 if(data != def) 1253 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1254 } 1255 1256 static void sdma_v4_0_init_pg(struct amdgpu_device *adev) 1257 { 1258 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA)) 1259 return; 1260 1261 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1262 case IP_VERSION(4, 1, 0): 1263 case IP_VERSION(4, 1, 1): 1264 case IP_VERSION(4, 1, 2): 1265 sdma_v4_1_init_power_gating(adev); 1266 sdma_v4_1_update_power_gating(adev, true); 1267 break; 1268 default: 1269 break; 1270 } 1271 } 1272 1273 /** 1274 * sdma_v4_0_rlc_resume - setup and start the async dma engines 1275 * 1276 * @adev: amdgpu_device pointer 1277 * 1278 * Set up the compute DMA queues and enable them (VEGA10). 1279 * Returns 0 for success, error for failure. 1280 */ 1281 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) 1282 { 1283 sdma_v4_0_init_pg(adev); 1284 1285 return 0; 1286 } 1287 1288 /** 1289 * sdma_v4_0_load_microcode - load the sDMA ME ucode 1290 * 1291 * @adev: amdgpu_device pointer 1292 * 1293 * Loads the sDMA0/1 ucode. 1294 * Returns 0 for success, -EINVAL if the ucode is not available. 1295 */ 1296 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 1297 { 1298 const struct sdma_firmware_header_v1_0 *hdr; 1299 const __le32 *fw_data; 1300 u32 fw_size; 1301 int i, j; 1302 1303 /* halt the MEs */ 1304 sdma_v4_0_enable(adev, false); 1305 1306 for (i = 0; i < adev->sdma.num_instances; i++) { 1307 if (!adev->sdma.instance[i].fw) 1308 return -EINVAL; 1309 1310 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 1311 amdgpu_ucode_print_sdma_hdr(&hdr->header); 1312 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1313 1314 fw_data = (const __le32 *) 1315 (adev->sdma.instance[i].fw->data + 1316 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1317 1318 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0); 1319 1320 for (j = 0; j < fw_size; j++) 1321 WREG32_SDMA(i, mmSDMA0_UCODE_DATA, 1322 le32_to_cpup(fw_data++)); 1323 1324 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 1325 adev->sdma.instance[i].fw_version); 1326 } 1327 1328 return 0; 1329 } 1330 1331 /** 1332 * sdma_v4_0_start - setup and start the async dma engines 1333 * 1334 * @adev: amdgpu_device pointer 1335 * 1336 * Set up the DMA engines and enable them (VEGA10). 1337 * Returns 0 for success, error for failure. 1338 */ 1339 static int sdma_v4_0_start(struct amdgpu_device *adev) 1340 { 1341 struct amdgpu_ring *ring; 1342 int i, r = 0; 1343 1344 if (amdgpu_sriov_vf(adev)) { 1345 sdma_v4_0_ctx_switch_enable(adev, false); 1346 sdma_v4_0_enable(adev, false); 1347 } else { 1348 1349 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1350 r = sdma_v4_0_load_microcode(adev); 1351 if (r) 1352 return r; 1353 } 1354 1355 /* unhalt the MEs */ 1356 sdma_v4_0_enable(adev, true); 1357 /* enable sdma ring preemption */ 1358 sdma_v4_0_ctx_switch_enable(adev, true); 1359 } 1360 1361 /* start the gfx rings and rlc compute queues */ 1362 for (i = 0; i < adev->sdma.num_instances; i++) { 1363 uint32_t temp; 1364 1365 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0); 1366 sdma_v4_0_gfx_resume(adev, i); 1367 if (adev->sdma.has_page_queue) 1368 sdma_v4_0_page_resume(adev, i); 1369 1370 /* set utc l1 enable flag always to 1 */ 1371 temp = RREG32_SDMA(i, mmSDMA0_CNTL); 1372 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 1373 WREG32_SDMA(i, mmSDMA0_CNTL, temp); 1374 1375 if (!amdgpu_sriov_vf(adev)) { 1376 /* unhalt engine */ 1377 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1378 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 1379 WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp); 1380 } 1381 } 1382 1383 if (amdgpu_sriov_vf(adev)) { 1384 sdma_v4_0_ctx_switch_enable(adev, true); 1385 sdma_v4_0_enable(adev, true); 1386 } else { 1387 r = sdma_v4_0_rlc_resume(adev); 1388 if (r) 1389 return r; 1390 } 1391 1392 for (i = 0; i < adev->sdma.num_instances; i++) { 1393 ring = &adev->sdma.instance[i].ring; 1394 1395 r = amdgpu_ring_test_helper(ring); 1396 if (r) 1397 return r; 1398 1399 if (adev->sdma.has_page_queue) { 1400 struct amdgpu_ring *page = &adev->sdma.instance[i].page; 1401 1402 r = amdgpu_ring_test_helper(page); 1403 if (r) 1404 return r; 1405 1406 if (adev->mman.buffer_funcs_ring == page) 1407 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1408 } 1409 1410 if (adev->mman.buffer_funcs_ring == ring) 1411 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1412 } 1413 1414 return r; 1415 } 1416 1417 /** 1418 * sdma_v4_0_ring_test_ring - simple async dma engine test 1419 * 1420 * @ring: amdgpu_ring structure holding ring information 1421 * 1422 * Test the DMA engine by writing using it to write an 1423 * value to memory. (VEGA10). 1424 * Returns 0 for success, error for failure. 1425 */ 1426 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) 1427 { 1428 struct amdgpu_device *adev = ring->adev; 1429 unsigned i; 1430 unsigned index; 1431 int r; 1432 u32 tmp; 1433 u64 gpu_addr; 1434 1435 r = amdgpu_device_wb_get(adev, &index); 1436 if (r) 1437 return r; 1438 1439 gpu_addr = adev->wb.gpu_addr + (index * 4); 1440 tmp = 0xCAFEDEAD; 1441 adev->wb.wb[index] = cpu_to_le32(tmp); 1442 1443 r = amdgpu_ring_alloc(ring, 5); 1444 if (r) 1445 goto error_free_wb; 1446 1447 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1448 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1449 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1450 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1451 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1452 amdgpu_ring_write(ring, 0xDEADBEEF); 1453 amdgpu_ring_commit(ring); 1454 1455 for (i = 0; i < adev->usec_timeout; i++) { 1456 tmp = le32_to_cpu(adev->wb.wb[index]); 1457 if (tmp == 0xDEADBEEF) 1458 break; 1459 udelay(1); 1460 } 1461 1462 if (i >= adev->usec_timeout) 1463 r = -ETIMEDOUT; 1464 1465 error_free_wb: 1466 amdgpu_device_wb_free(adev, index); 1467 return r; 1468 } 1469 1470 /** 1471 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine 1472 * 1473 * @ring: amdgpu_ring structure holding ring information 1474 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1475 * 1476 * Test a simple IB in the DMA ring (VEGA10). 1477 * Returns 0 on success, error on failure. 1478 */ 1479 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1480 { 1481 struct amdgpu_device *adev = ring->adev; 1482 struct amdgpu_ib ib; 1483 struct dma_fence *f = NULL; 1484 unsigned index; 1485 long r; 1486 u32 tmp = 0; 1487 u64 gpu_addr; 1488 1489 r = amdgpu_device_wb_get(adev, &index); 1490 if (r) 1491 return r; 1492 1493 gpu_addr = adev->wb.gpu_addr + (index * 4); 1494 tmp = 0xCAFEDEAD; 1495 adev->wb.wb[index] = cpu_to_le32(tmp); 1496 memset(&ib, 0, sizeof(ib)); 1497 r = amdgpu_ib_get(adev, NULL, 256, 1498 AMDGPU_IB_POOL_DIRECT, &ib); 1499 if (r) 1500 goto err0; 1501 1502 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1503 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1504 ib.ptr[1] = lower_32_bits(gpu_addr); 1505 ib.ptr[2] = upper_32_bits(gpu_addr); 1506 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1507 ib.ptr[4] = 0xDEADBEEF; 1508 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1509 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1510 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1511 ib.length_dw = 8; 1512 1513 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1514 if (r) 1515 goto err1; 1516 1517 r = dma_fence_wait_timeout(f, false, timeout); 1518 if (r == 0) { 1519 r = -ETIMEDOUT; 1520 goto err1; 1521 } else if (r < 0) { 1522 goto err1; 1523 } 1524 tmp = le32_to_cpu(adev->wb.wb[index]); 1525 if (tmp == 0xDEADBEEF) 1526 r = 0; 1527 else 1528 r = -EINVAL; 1529 1530 err1: 1531 amdgpu_ib_free(adev, &ib, NULL); 1532 dma_fence_put(f); 1533 err0: 1534 amdgpu_device_wb_free(adev, index); 1535 return r; 1536 } 1537 1538 1539 /** 1540 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART 1541 * 1542 * @ib: indirect buffer to fill with commands 1543 * @pe: addr of the page entry 1544 * @src: src addr to copy from 1545 * @count: number of page entries to update 1546 * 1547 * Update PTEs by copying them from the GART using sDMA (VEGA10). 1548 */ 1549 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib, 1550 uint64_t pe, uint64_t src, 1551 unsigned count) 1552 { 1553 unsigned bytes = count * 8; 1554 1555 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1556 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1557 ib->ptr[ib->length_dw++] = bytes - 1; 1558 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1559 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1560 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1561 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1562 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1563 1564 } 1565 1566 /** 1567 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually 1568 * 1569 * @ib: indirect buffer to fill with commands 1570 * @pe: addr of the page entry 1571 * @value: dst addr to write into pe 1572 * @count: number of page entries to update 1573 * @incr: increase next addr by incr bytes 1574 * 1575 * Update PTEs by writing them manually using sDMA (VEGA10). 1576 */ 1577 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1578 uint64_t value, unsigned count, 1579 uint32_t incr) 1580 { 1581 unsigned ndw = count * 2; 1582 1583 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1584 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1585 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1586 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1587 ib->ptr[ib->length_dw++] = ndw - 1; 1588 for (; ndw > 0; ndw -= 2) { 1589 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1590 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1591 value += incr; 1592 } 1593 } 1594 1595 /** 1596 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA 1597 * 1598 * @ib: indirect buffer to fill with commands 1599 * @pe: addr of the page entry 1600 * @addr: dst addr to write into pe 1601 * @count: number of page entries to update 1602 * @incr: increase next addr by incr bytes 1603 * @flags: access flags 1604 * 1605 * Update the page tables using sDMA (VEGA10). 1606 */ 1607 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1608 uint64_t pe, 1609 uint64_t addr, unsigned count, 1610 uint32_t incr, uint64_t flags) 1611 { 1612 /* for physically contiguous pages (vram) */ 1613 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1614 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1615 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1616 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1617 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1618 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1619 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1620 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1621 ib->ptr[ib->length_dw++] = 0; 1622 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1623 } 1624 1625 /** 1626 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw 1627 * 1628 * @ring: amdgpu_ring structure holding ring information 1629 * @ib: indirect buffer to fill with padding 1630 */ 1631 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1632 { 1633 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1634 u32 pad_count; 1635 int i; 1636 1637 pad_count = (-ib->length_dw) & 7; 1638 for (i = 0; i < pad_count; i++) 1639 if (sdma && sdma->burst_nop && (i == 0)) 1640 ib->ptr[ib->length_dw++] = 1641 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1642 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1643 else 1644 ib->ptr[ib->length_dw++] = 1645 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1646 } 1647 1648 1649 /** 1650 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline 1651 * 1652 * @ring: amdgpu_ring pointer 1653 * 1654 * Make sure all previous operations are completed (CIK). 1655 */ 1656 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1657 { 1658 uint32_t seq = ring->fence_drv.sync_seq; 1659 uint64_t addr = ring->fence_drv.gpu_addr; 1660 1661 /* wait for idle */ 1662 sdma_v4_0_wait_reg_mem(ring, 1, 0, 1663 addr & 0xfffffffc, 1664 upper_32_bits(addr) & 0xffffffff, 1665 seq, 0xffffffff, 4); 1666 } 1667 1668 1669 /** 1670 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA 1671 * 1672 * @ring: amdgpu_ring pointer 1673 * @vmid: vmid number to use 1674 * @pd_addr: address 1675 * 1676 * Update the page table base and flush the VM TLB 1677 * using sDMA (VEGA10). 1678 */ 1679 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1680 unsigned vmid, uint64_t pd_addr) 1681 { 1682 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1683 } 1684 1685 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring, 1686 uint32_t reg, uint32_t val) 1687 { 1688 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1689 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1690 amdgpu_ring_write(ring, reg); 1691 amdgpu_ring_write(ring, val); 1692 } 1693 1694 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1695 uint32_t val, uint32_t mask) 1696 { 1697 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1698 } 1699 1700 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev) 1701 { 1702 uint fw_version = adev->sdma.instance[0].fw_version; 1703 1704 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1705 case IP_VERSION(4, 0, 0): 1706 return fw_version >= 430; 1707 case IP_VERSION(4, 0, 1): 1708 /*return fw_version >= 31;*/ 1709 return false; 1710 case IP_VERSION(4, 2, 0): 1711 return fw_version >= 123; 1712 default: 1713 return false; 1714 } 1715 } 1716 1717 static int sdma_v4_0_early_init(void *handle) 1718 { 1719 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1720 int r; 1721 1722 r = sdma_v4_0_init_microcode(adev); 1723 if (r) { 1724 DRM_ERROR("Failed to load sdma firmware!\n"); 1725 return r; 1726 } 1727 1728 /* TODO: Page queue breaks driver reload under SRIOV */ 1729 if ((amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 0, 0)) && 1730 amdgpu_sriov_vf((adev))) 1731 adev->sdma.has_page_queue = false; 1732 else if (sdma_v4_0_fw_support_paging_queue(adev)) 1733 adev->sdma.has_page_queue = true; 1734 1735 sdma_v4_0_set_ring_funcs(adev); 1736 sdma_v4_0_set_buffer_funcs(adev); 1737 sdma_v4_0_set_vm_pte_funcs(adev); 1738 sdma_v4_0_set_irq_funcs(adev); 1739 sdma_v4_0_set_ras_funcs(adev); 1740 1741 return 0; 1742 } 1743 1744 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, 1745 void *err_data, 1746 struct amdgpu_iv_entry *entry); 1747 1748 static int sdma_v4_0_late_init(void *handle) 1749 { 1750 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1751 1752 sdma_v4_0_setup_ulv(adev); 1753 1754 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1755 if (adev->sdma.ras && adev->sdma.ras->ras_block.hw_ops && 1756 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count) 1757 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count(adev); 1758 } 1759 1760 return 0; 1761 } 1762 1763 static int sdma_v4_0_sw_init(void *handle) 1764 { 1765 struct amdgpu_ring *ring; 1766 int r, i; 1767 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1768 1769 /* SDMA trap event */ 1770 for (i = 0; i < adev->sdma.num_instances; i++) { 1771 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1772 SDMA0_4_0__SRCID__SDMA_TRAP, 1773 &adev->sdma.trap_irq); 1774 if (r) 1775 return r; 1776 } 1777 1778 /* SDMA SRAM ECC event */ 1779 for (i = 0; i < adev->sdma.num_instances; i++) { 1780 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1781 SDMA0_4_0__SRCID__SDMA_SRAM_ECC, 1782 &adev->sdma.ecc_irq); 1783 if (r) 1784 return r; 1785 } 1786 1787 /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/ 1788 for (i = 0; i < adev->sdma.num_instances; i++) { 1789 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1790 SDMA0_4_0__SRCID__SDMA_VM_HOLE, 1791 &adev->sdma.vm_hole_irq); 1792 if (r) 1793 return r; 1794 1795 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1796 SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID, 1797 &adev->sdma.doorbell_invalid_irq); 1798 if (r) 1799 return r; 1800 1801 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1802 SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT, 1803 &adev->sdma.pool_timeout_irq); 1804 if (r) 1805 return r; 1806 1807 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i), 1808 SDMA0_4_0__SRCID__SDMA_SRBMWRITE, 1809 &adev->sdma.srbm_write_irq); 1810 if (r) 1811 return r; 1812 } 1813 1814 for (i = 0; i < adev->sdma.num_instances; i++) { 1815 ring = &adev->sdma.instance[i].ring; 1816 ring->ring_obj = NULL; 1817 ring->use_doorbell = true; 1818 1819 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1820 ring->use_doorbell?"true":"false"); 1821 1822 /* doorbell size is 2 dwords, get DWORD offset */ 1823 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1; 1824 1825 /* 1826 * On Arcturus, SDMA instance 5~7 has a different vmhub 1827 * type(AMDGPU_MMHUB1). 1828 */ 1829 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == 1830 IP_VERSION(4, 2, 2) && 1831 i >= 5) 1832 ring->vm_hub = AMDGPU_MMHUB1(0); 1833 else 1834 ring->vm_hub = AMDGPU_MMHUB0(0); 1835 1836 sprintf(ring->name, "sdma%d", i); 1837 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1838 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1839 AMDGPU_RING_PRIO_DEFAULT, NULL); 1840 if (r) 1841 return r; 1842 1843 if (adev->sdma.has_page_queue) { 1844 ring = &adev->sdma.instance[i].page; 1845 ring->ring_obj = NULL; 1846 ring->use_doorbell = true; 1847 1848 /* paging queue use same doorbell index/routing as gfx queue 1849 * with 0x400 (4096 dwords) offset on second doorbell page 1850 */ 1851 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) >= 1852 IP_VERSION(4, 0, 0) && 1853 amdgpu_ip_version(adev, SDMA0_HWIP, 0) < 1854 IP_VERSION(4, 2, 0)) { 1855 ring->doorbell_index = 1856 adev->doorbell_index.sdma_engine[i] << 1; 1857 ring->doorbell_index += 0x400; 1858 } else { 1859 /* From vega20, the sdma_doorbell_range in 1st 1860 * doorbell page is reserved for page queue. 1861 */ 1862 ring->doorbell_index = 1863 (adev->doorbell_index.sdma_engine[i] + 1) << 1; 1864 } 1865 1866 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == 1867 IP_VERSION(4, 2, 2) && 1868 i >= 5) 1869 ring->vm_hub = AMDGPU_MMHUB1(0); 1870 else 1871 ring->vm_hub = AMDGPU_MMHUB0(0); 1872 1873 sprintf(ring->name, "page%d", i); 1874 r = amdgpu_ring_init(adev, ring, 1024, 1875 &adev->sdma.trap_irq, 1876 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1877 AMDGPU_RING_PRIO_DEFAULT, NULL); 1878 if (r) 1879 return r; 1880 } 1881 } 1882 1883 if (amdgpu_sdma_ras_sw_init(adev)) { 1884 dev_err(adev->dev, "Failed to initialize sdma ras block!\n"); 1885 return -EINVAL; 1886 } 1887 1888 return r; 1889 } 1890 1891 static int sdma_v4_0_sw_fini(void *handle) 1892 { 1893 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1894 int i; 1895 1896 for (i = 0; i < adev->sdma.num_instances; i++) { 1897 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1898 if (adev->sdma.has_page_queue) 1899 amdgpu_ring_fini(&adev->sdma.instance[i].page); 1900 } 1901 1902 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 2, 2) || 1903 amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 0)) 1904 amdgpu_sdma_destroy_inst_ctx(adev, true); 1905 else 1906 amdgpu_sdma_destroy_inst_ctx(adev, false); 1907 1908 return 0; 1909 } 1910 1911 static int sdma_v4_0_hw_init(void *handle) 1912 { 1913 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1914 1915 if (adev->flags & AMD_IS_APU) 1916 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false); 1917 1918 if (!amdgpu_sriov_vf(adev)) 1919 sdma_v4_0_init_golden_registers(adev); 1920 1921 return sdma_v4_0_start(adev); 1922 } 1923 1924 static int sdma_v4_0_hw_fini(void *handle) 1925 { 1926 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1927 int i; 1928 1929 if (amdgpu_sriov_vf(adev)) { 1930 /* disable the scheduler for SDMA */ 1931 amdgpu_sdma_unset_buffer_funcs_helper(adev); 1932 return 0; 1933 } 1934 1935 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 1936 for (i = 0; i < adev->sdma.num_instances; i++) { 1937 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 1938 AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1939 } 1940 } 1941 1942 sdma_v4_0_ctx_switch_enable(adev, false); 1943 sdma_v4_0_enable(adev, false); 1944 1945 if (adev->flags & AMD_IS_APU) 1946 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true); 1947 1948 return 0; 1949 } 1950 1951 static int sdma_v4_0_suspend(void *handle) 1952 { 1953 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1954 1955 /* SMU saves SDMA state for us */ 1956 if (adev->in_s0ix) { 1957 sdma_v4_0_gfx_enable(adev, false); 1958 return 0; 1959 } 1960 1961 return sdma_v4_0_hw_fini(adev); 1962 } 1963 1964 static int sdma_v4_0_resume(void *handle) 1965 { 1966 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1967 1968 /* SMU restores SDMA state for us */ 1969 if (adev->in_s0ix) { 1970 sdma_v4_0_enable(adev, true); 1971 sdma_v4_0_gfx_enable(adev, true); 1972 amdgpu_ttm_set_buffer_funcs_status(adev, true); 1973 return 0; 1974 } 1975 1976 return sdma_v4_0_hw_init(adev); 1977 } 1978 1979 static bool sdma_v4_0_is_idle(void *handle) 1980 { 1981 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1982 u32 i; 1983 1984 for (i = 0; i < adev->sdma.num_instances; i++) { 1985 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG); 1986 1987 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1988 return false; 1989 } 1990 1991 return true; 1992 } 1993 1994 static int sdma_v4_0_wait_for_idle(void *handle) 1995 { 1996 unsigned i, j; 1997 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; 1998 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1999 2000 for (i = 0; i < adev->usec_timeout; i++) { 2001 for (j = 0; j < adev->sdma.num_instances; j++) { 2002 sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG); 2003 if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK)) 2004 break; 2005 } 2006 if (j == adev->sdma.num_instances) 2007 return 0; 2008 udelay(1); 2009 } 2010 return -ETIMEDOUT; 2011 } 2012 2013 static int sdma_v4_0_soft_reset(void *handle) 2014 { 2015 /* todo */ 2016 2017 return 0; 2018 } 2019 2020 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, 2021 struct amdgpu_irq_src *source, 2022 unsigned type, 2023 enum amdgpu_interrupt_state state) 2024 { 2025 u32 sdma_cntl; 2026 2027 sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL); 2028 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 2029 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2030 WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl); 2031 2032 return 0; 2033 } 2034 2035 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, 2036 struct amdgpu_irq_src *source, 2037 struct amdgpu_iv_entry *entry) 2038 { 2039 uint32_t instance; 2040 2041 DRM_DEBUG("IH: SDMA trap\n"); 2042 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2043 switch (entry->ring_id) { 2044 case 0: 2045 amdgpu_fence_process(&adev->sdma.instance[instance].ring); 2046 break; 2047 case 1: 2048 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == 2049 IP_VERSION(4, 2, 0)) 2050 amdgpu_fence_process(&adev->sdma.instance[instance].page); 2051 break; 2052 case 2: 2053 /* XXX compute */ 2054 break; 2055 case 3: 2056 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) != 2057 IP_VERSION(4, 2, 0)) 2058 amdgpu_fence_process(&adev->sdma.instance[instance].page); 2059 break; 2060 } 2061 return 0; 2062 } 2063 2064 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, 2065 void *err_data, 2066 struct amdgpu_iv_entry *entry) 2067 { 2068 int instance; 2069 2070 /* When “Full RAS” is enabled, the per-IP interrupt sources should 2071 * be disabled and the driver should only look for the aggregated 2072 * interrupt via sync flood 2073 */ 2074 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 2075 goto out; 2076 2077 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2078 if (instance < 0) 2079 goto out; 2080 2081 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry); 2082 2083 out: 2084 return AMDGPU_RAS_SUCCESS; 2085 } 2086 2087 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev, 2088 struct amdgpu_irq_src *source, 2089 struct amdgpu_iv_entry *entry) 2090 { 2091 int instance; 2092 2093 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 2094 2095 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2096 if (instance < 0) 2097 return 0; 2098 2099 switch (entry->ring_id) { 2100 case 0: 2101 drm_sched_fault(&adev->sdma.instance[instance].ring.sched); 2102 break; 2103 } 2104 return 0; 2105 } 2106 2107 static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev, 2108 struct amdgpu_irq_src *source, 2109 unsigned type, 2110 enum amdgpu_interrupt_state state) 2111 { 2112 u32 sdma_edc_config; 2113 2114 sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG); 2115 sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE, 2116 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2117 WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config); 2118 2119 return 0; 2120 } 2121 2122 static int sdma_v4_0_print_iv_entry(struct amdgpu_device *adev, 2123 struct amdgpu_iv_entry *entry) 2124 { 2125 int instance; 2126 struct amdgpu_task_info task_info; 2127 u64 addr; 2128 2129 instance = sdma_v4_0_irq_id_to_seq(entry->client_id); 2130 if (instance < 0 || instance >= adev->sdma.num_instances) { 2131 dev_err(adev->dev, "sdma instance invalid %d\n", instance); 2132 return -EINVAL; 2133 } 2134 2135 addr = (u64)entry->src_data[0] << 12; 2136 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 2137 2138 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 2139 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 2140 2141 dev_dbg_ratelimited(adev->dev, 2142 "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u " 2143 "pasid:%u, for process %s pid %d thread %s pid %d\n", 2144 instance, addr, entry->src_id, entry->ring_id, entry->vmid, 2145 entry->pasid, task_info.process_name, task_info.tgid, 2146 task_info.task_name, task_info.pid); 2147 return 0; 2148 } 2149 2150 static int sdma_v4_0_process_vm_hole_irq(struct amdgpu_device *adev, 2151 struct amdgpu_irq_src *source, 2152 struct amdgpu_iv_entry *entry) 2153 { 2154 dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n"); 2155 sdma_v4_0_print_iv_entry(adev, entry); 2156 return 0; 2157 } 2158 2159 static int sdma_v4_0_process_doorbell_invalid_irq(struct amdgpu_device *adev, 2160 struct amdgpu_irq_src *source, 2161 struct amdgpu_iv_entry *entry) 2162 { 2163 dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n"); 2164 sdma_v4_0_print_iv_entry(adev, entry); 2165 return 0; 2166 } 2167 2168 static int sdma_v4_0_process_pool_timeout_irq(struct amdgpu_device *adev, 2169 struct amdgpu_irq_src *source, 2170 struct amdgpu_iv_entry *entry) 2171 { 2172 dev_dbg_ratelimited(adev->dev, 2173 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n"); 2174 sdma_v4_0_print_iv_entry(adev, entry); 2175 return 0; 2176 } 2177 2178 static int sdma_v4_0_process_srbm_write_irq(struct amdgpu_device *adev, 2179 struct amdgpu_irq_src *source, 2180 struct amdgpu_iv_entry *entry) 2181 { 2182 dev_dbg_ratelimited(adev->dev, 2183 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n"); 2184 sdma_v4_0_print_iv_entry(adev, entry); 2185 return 0; 2186 } 2187 2188 static void sdma_v4_0_update_medium_grain_clock_gating( 2189 struct amdgpu_device *adev, 2190 bool enable) 2191 { 2192 uint32_t data, def; 2193 int i; 2194 2195 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 2196 for (i = 0; i < adev->sdma.num_instances; i++) { 2197 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); 2198 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2199 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2200 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2201 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2202 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2203 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2204 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2205 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2206 if (def != data) 2207 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); 2208 } 2209 } else { 2210 for (i = 0; i < adev->sdma.num_instances; i++) { 2211 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); 2212 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 2213 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 2214 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 2215 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 2216 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 2217 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 2218 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 2219 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 2220 if (def != data) 2221 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); 2222 } 2223 } 2224 } 2225 2226 2227 static void sdma_v4_0_update_medium_grain_light_sleep( 2228 struct amdgpu_device *adev, 2229 bool enable) 2230 { 2231 uint32_t data, def; 2232 int i; 2233 2234 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 2235 for (i = 0; i < adev->sdma.num_instances; i++) { 2236 /* 1-not override: enable sdma mem light sleep */ 2237 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); 2238 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2239 if (def != data) 2240 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); 2241 } 2242 } else { 2243 for (i = 0; i < adev->sdma.num_instances; i++) { 2244 /* 0-override:disable sdma mem light sleep */ 2245 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); 2246 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 2247 if (def != data) 2248 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); 2249 } 2250 } 2251 } 2252 2253 static int sdma_v4_0_set_clockgating_state(void *handle, 2254 enum amd_clockgating_state state) 2255 { 2256 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2257 2258 if (amdgpu_sriov_vf(adev)) 2259 return 0; 2260 2261 sdma_v4_0_update_medium_grain_clock_gating(adev, 2262 state == AMD_CG_STATE_GATE); 2263 sdma_v4_0_update_medium_grain_light_sleep(adev, 2264 state == AMD_CG_STATE_GATE); 2265 return 0; 2266 } 2267 2268 static int sdma_v4_0_set_powergating_state(void *handle, 2269 enum amd_powergating_state state) 2270 { 2271 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2272 2273 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 2274 case IP_VERSION(4, 1, 0): 2275 case IP_VERSION(4, 1, 1): 2276 case IP_VERSION(4, 1, 2): 2277 sdma_v4_1_update_power_gating(adev, 2278 state == AMD_PG_STATE_GATE); 2279 break; 2280 default: 2281 break; 2282 } 2283 2284 return 0; 2285 } 2286 2287 static void sdma_v4_0_get_clockgating_state(void *handle, u64 *flags) 2288 { 2289 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2290 int data; 2291 2292 if (amdgpu_sriov_vf(adev)) 2293 *flags = 0; 2294 2295 /* AMD_CG_SUPPORT_SDMA_MGCG */ 2296 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 2297 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 2298 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 2299 2300 /* AMD_CG_SUPPORT_SDMA_LS */ 2301 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 2302 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 2303 *flags |= AMD_CG_SUPPORT_SDMA_LS; 2304 } 2305 2306 const struct amd_ip_funcs sdma_v4_0_ip_funcs = { 2307 .name = "sdma_v4_0", 2308 .early_init = sdma_v4_0_early_init, 2309 .late_init = sdma_v4_0_late_init, 2310 .sw_init = sdma_v4_0_sw_init, 2311 .sw_fini = sdma_v4_0_sw_fini, 2312 .hw_init = sdma_v4_0_hw_init, 2313 .hw_fini = sdma_v4_0_hw_fini, 2314 .suspend = sdma_v4_0_suspend, 2315 .resume = sdma_v4_0_resume, 2316 .is_idle = sdma_v4_0_is_idle, 2317 .wait_for_idle = sdma_v4_0_wait_for_idle, 2318 .soft_reset = sdma_v4_0_soft_reset, 2319 .set_clockgating_state = sdma_v4_0_set_clockgating_state, 2320 .set_powergating_state = sdma_v4_0_set_powergating_state, 2321 .get_clockgating_state = sdma_v4_0_get_clockgating_state, 2322 }; 2323 2324 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { 2325 .type = AMDGPU_RING_TYPE_SDMA, 2326 .align_mask = 0xff, 2327 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2328 .support_64bit_ptrs = true, 2329 .secure_submission_supported = true, 2330 .get_rptr = sdma_v4_0_ring_get_rptr, 2331 .get_wptr = sdma_v4_0_ring_get_wptr, 2332 .set_wptr = sdma_v4_0_ring_set_wptr, 2333 .emit_frame_size = 2334 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2335 3 + /* hdp invalidate */ 2336 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2337 /* sdma_v4_0_ring_emit_vm_flush */ 2338 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2339 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2340 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2341 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2342 .emit_ib = sdma_v4_0_ring_emit_ib, 2343 .emit_fence = sdma_v4_0_ring_emit_fence, 2344 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2345 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2346 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2347 .test_ring = sdma_v4_0_ring_test_ring, 2348 .test_ib = sdma_v4_0_ring_test_ib, 2349 .insert_nop = sdma_v4_0_ring_insert_nop, 2350 .pad_ib = sdma_v4_0_ring_pad_ib, 2351 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2352 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2353 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2354 }; 2355 2356 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = { 2357 .type = AMDGPU_RING_TYPE_SDMA, 2358 .align_mask = 0xff, 2359 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 2360 .support_64bit_ptrs = true, 2361 .secure_submission_supported = true, 2362 .get_rptr = sdma_v4_0_ring_get_rptr, 2363 .get_wptr = sdma_v4_0_page_ring_get_wptr, 2364 .set_wptr = sdma_v4_0_page_ring_set_wptr, 2365 .emit_frame_size = 2366 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 2367 3 + /* hdp invalidate */ 2368 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 2369 /* sdma_v4_0_ring_emit_vm_flush */ 2370 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2371 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 2372 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 2373 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 2374 .emit_ib = sdma_v4_0_ring_emit_ib, 2375 .emit_fence = sdma_v4_0_ring_emit_fence, 2376 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 2377 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 2378 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 2379 .test_ring = sdma_v4_0_ring_test_ring, 2380 .test_ib = sdma_v4_0_ring_test_ib, 2381 .insert_nop = sdma_v4_0_ring_insert_nop, 2382 .pad_ib = sdma_v4_0_ring_pad_ib, 2383 .emit_wreg = sdma_v4_0_ring_emit_wreg, 2384 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 2385 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2386 }; 2387 2388 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev) 2389 { 2390 int i; 2391 2392 for (i = 0; i < adev->sdma.num_instances; i++) { 2393 adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs; 2394 adev->sdma.instance[i].ring.me = i; 2395 if (adev->sdma.has_page_queue) { 2396 adev->sdma.instance[i].page.funcs = 2397 &sdma_v4_0_page_ring_funcs; 2398 adev->sdma.instance[i].page.me = i; 2399 } 2400 } 2401 } 2402 2403 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = { 2404 .set = sdma_v4_0_set_trap_irq_state, 2405 .process = sdma_v4_0_process_trap_irq, 2406 }; 2407 2408 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = { 2409 .process = sdma_v4_0_process_illegal_inst_irq, 2410 }; 2411 2412 static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = { 2413 .set = sdma_v4_0_set_ecc_irq_state, 2414 .process = amdgpu_sdma_process_ecc_irq, 2415 }; 2416 2417 static const struct amdgpu_irq_src_funcs sdma_v4_0_vm_hole_irq_funcs = { 2418 .process = sdma_v4_0_process_vm_hole_irq, 2419 }; 2420 2421 static const struct amdgpu_irq_src_funcs sdma_v4_0_doorbell_invalid_irq_funcs = { 2422 .process = sdma_v4_0_process_doorbell_invalid_irq, 2423 }; 2424 2425 static const struct amdgpu_irq_src_funcs sdma_v4_0_pool_timeout_irq_funcs = { 2426 .process = sdma_v4_0_process_pool_timeout_irq, 2427 }; 2428 2429 static const struct amdgpu_irq_src_funcs sdma_v4_0_srbm_write_irq_funcs = { 2430 .process = sdma_v4_0_process_srbm_write_irq, 2431 }; 2432 2433 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) 2434 { 2435 adev->sdma.trap_irq.num_types = adev->sdma.num_instances; 2436 adev->sdma.ecc_irq.num_types = adev->sdma.num_instances; 2437 /*For Arcturus and Aldebaran, add another 4 irq handler*/ 2438 switch (adev->sdma.num_instances) { 2439 case 5: 2440 case 8: 2441 adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances; 2442 adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances; 2443 adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances; 2444 adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances; 2445 break; 2446 default: 2447 break; 2448 } 2449 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; 2450 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; 2451 adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs; 2452 adev->sdma.vm_hole_irq.funcs = &sdma_v4_0_vm_hole_irq_funcs; 2453 adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_0_doorbell_invalid_irq_funcs; 2454 adev->sdma.pool_timeout_irq.funcs = &sdma_v4_0_pool_timeout_irq_funcs; 2455 adev->sdma.srbm_write_irq.funcs = &sdma_v4_0_srbm_write_irq_funcs; 2456 } 2457 2458 /** 2459 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine 2460 * 2461 * @ib: indirect buffer to copy to 2462 * @src_offset: src GPU address 2463 * @dst_offset: dst GPU address 2464 * @byte_count: number of bytes to xfer 2465 * @tmz: if a secure copy should be used 2466 * 2467 * Copy GPU buffers using the DMA engine (VEGA10/12). 2468 * Used by the amdgpu ttm implementation to move pages if 2469 * registered as the asic copy callback. 2470 */ 2471 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, 2472 uint64_t src_offset, 2473 uint64_t dst_offset, 2474 uint32_t byte_count, 2475 bool tmz) 2476 { 2477 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 2478 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 2479 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 2480 ib->ptr[ib->length_dw++] = byte_count - 1; 2481 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 2482 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 2483 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 2484 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2485 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2486 } 2487 2488 /** 2489 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine 2490 * 2491 * @ib: indirect buffer to copy to 2492 * @src_data: value to write to buffer 2493 * @dst_offset: dst GPU address 2494 * @byte_count: number of bytes to xfer 2495 * 2496 * Fill GPU buffers using the DMA engine (VEGA10/12). 2497 */ 2498 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, 2499 uint32_t src_data, 2500 uint64_t dst_offset, 2501 uint32_t byte_count) 2502 { 2503 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 2504 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 2505 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 2506 ib->ptr[ib->length_dw++] = src_data; 2507 ib->ptr[ib->length_dw++] = byte_count - 1; 2508 } 2509 2510 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { 2511 .copy_max_bytes = 0x400000, 2512 .copy_num_dw = 7, 2513 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, 2514 2515 .fill_max_bytes = 0x400000, 2516 .fill_num_dw = 5, 2517 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, 2518 }; 2519 2520 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) 2521 { 2522 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; 2523 if (adev->sdma.has_page_queue) 2524 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; 2525 else 2526 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2527 } 2528 2529 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 2530 .copy_pte_num_dw = 7, 2531 .copy_pte = sdma_v4_0_vm_copy_pte, 2532 2533 .write_pte = sdma_v4_0_vm_write_pte, 2534 .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 2535 }; 2536 2537 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) 2538 { 2539 struct drm_gpu_scheduler *sched; 2540 unsigned i; 2541 2542 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; 2543 for (i = 0; i < adev->sdma.num_instances; i++) { 2544 if (adev->sdma.has_page_queue) 2545 sched = &adev->sdma.instance[i].page.sched; 2546 else 2547 sched = &adev->sdma.instance[i].ring.sched; 2548 adev->vm_manager.vm_pte_scheds[i] = sched; 2549 } 2550 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 2551 } 2552 2553 static void sdma_v4_0_get_ras_error_count(uint32_t value, 2554 uint32_t instance, 2555 uint32_t *sec_count) 2556 { 2557 uint32_t i; 2558 uint32_t sec_cnt; 2559 2560 /* double bits error (multiple bits) error detection is not supported */ 2561 for (i = 0; i < ARRAY_SIZE(sdma_v4_0_ras_fields); i++) { 2562 /* the SDMA_EDC_COUNTER register in each sdma instance 2563 * shares the same sed shift_mask 2564 * */ 2565 sec_cnt = (value & 2566 sdma_v4_0_ras_fields[i].sec_count_mask) >> 2567 sdma_v4_0_ras_fields[i].sec_count_shift; 2568 if (sec_cnt) { 2569 DRM_INFO("Detected %s in SDMA%d, SED %d\n", 2570 sdma_v4_0_ras_fields[i].name, 2571 instance, sec_cnt); 2572 *sec_count += sec_cnt; 2573 } 2574 } 2575 } 2576 2577 static int sdma_v4_0_query_ras_error_count_by_instance(struct amdgpu_device *adev, 2578 uint32_t instance, void *ras_error_status) 2579 { 2580 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 2581 uint32_t sec_count = 0; 2582 uint32_t reg_value = 0; 2583 2584 reg_value = RREG32_SDMA(instance, mmSDMA0_EDC_COUNTER); 2585 /* double bit error is not supported */ 2586 if (reg_value) 2587 sdma_v4_0_get_ras_error_count(reg_value, 2588 instance, &sec_count); 2589 /* err_data->ce_count should be initialized to 0 2590 * before calling into this function */ 2591 err_data->ce_count += sec_count; 2592 /* double bit error is not supported 2593 * set ue count to 0 */ 2594 err_data->ue_count = 0; 2595 2596 return 0; 2597 }; 2598 2599 static void sdma_v4_0_query_ras_error_count(struct amdgpu_device *adev, void *ras_error_status) 2600 { 2601 int i = 0; 2602 2603 for (i = 0; i < adev->sdma.num_instances; i++) { 2604 if (sdma_v4_0_query_ras_error_count_by_instance(adev, i, ras_error_status)) { 2605 dev_err(adev->dev, "Query ras error count failed in SDMA%d\n", i); 2606 return; 2607 } 2608 } 2609 } 2610 2611 static void sdma_v4_0_reset_ras_error_count(struct amdgpu_device *adev) 2612 { 2613 int i; 2614 2615 /* read back edc counter registers to clear the counters */ 2616 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 2617 for (i = 0; i < adev->sdma.num_instances; i++) 2618 RREG32_SDMA(i, mmSDMA0_EDC_COUNTER); 2619 } 2620 } 2621 2622 const struct amdgpu_ras_block_hw_ops sdma_v4_0_ras_hw_ops = { 2623 .query_ras_error_count = sdma_v4_0_query_ras_error_count, 2624 .reset_ras_error_count = sdma_v4_0_reset_ras_error_count, 2625 }; 2626 2627 static struct amdgpu_sdma_ras sdma_v4_0_ras = { 2628 .ras_block = { 2629 .hw_ops = &sdma_v4_0_ras_hw_ops, 2630 .ras_cb = sdma_v4_0_process_ras_data_cb, 2631 }, 2632 }; 2633 2634 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev) 2635 { 2636 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 2637 case IP_VERSION(4, 2, 0): 2638 case IP_VERSION(4, 2, 2): 2639 adev->sdma.ras = &sdma_v4_0_ras; 2640 break; 2641 case IP_VERSION(4, 4, 0): 2642 adev->sdma.ras = &sdma_v4_4_ras; 2643 break; 2644 default: 2645 break; 2646 } 2647 } 2648 2649 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = { 2650 .type = AMD_IP_BLOCK_TYPE_SDMA, 2651 .major = 4, 2652 .minor = 0, 2653 .rev = 0, 2654 .funcs = &sdma_v4_0_ip_funcs, 2655 }; 2656