1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 25 #include <linux/delay.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 #include "vi.h" 33 #include "vid.h" 34 35 #include "oss/oss_3_0_d.h" 36 #include "oss/oss_3_0_sh_mask.h" 37 38 #include "gmc/gmc_8_1_d.h" 39 #include "gmc/gmc_8_1_sh_mask.h" 40 41 #include "gca/gfx_8_0_d.h" 42 #include "gca/gfx_8_0_enum.h" 43 #include "gca/gfx_8_0_sh_mask.h" 44 45 #include "bif/bif_5_0_d.h" 46 #include "bif/bif_5_0_sh_mask.h" 47 48 #include "tonga_sdma_pkt_open.h" 49 50 #include "ivsrcid/ivsrcid_vislands30.h" 51 52 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev); 53 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); 54 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev); 55 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); 56 57 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); 58 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin"); 59 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin"); 60 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); 61 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); 62 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); 63 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin"); 65 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin"); 66 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin"); 67 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin"); 68 MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin"); 69 MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin"); 70 MODULE_FIRMWARE("amdgpu/vegam_sdma.bin"); 71 MODULE_FIRMWARE("amdgpu/vegam_sdma1.bin"); 72 73 74 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 75 { 76 SDMA0_REGISTER_OFFSET, 77 SDMA1_REGISTER_OFFSET 78 }; 79 80 static const u32 golden_settings_tonga_a11[] = 81 { 82 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 83 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 84 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 85 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 86 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 87 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 88 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 89 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 90 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 91 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 92 }; 93 94 static const u32 tonga_mgcg_cgcg_init[] = 95 { 96 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 97 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 98 }; 99 100 static const u32 golden_settings_fiji_a10[] = 101 { 102 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 103 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 104 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 105 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 106 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 107 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 108 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 109 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 110 }; 111 112 static const u32 fiji_mgcg_cgcg_init[] = 113 { 114 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 115 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 116 }; 117 118 static const u32 golden_settings_polaris11_a11[] = 119 { 120 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 121 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 122 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 123 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 124 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 125 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 126 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 127 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 128 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 129 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 130 }; 131 132 static const u32 golden_settings_polaris10_a11[] = 133 { 134 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 135 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 136 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 137 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 138 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 139 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 140 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 141 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 142 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 143 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 144 }; 145 146 static const u32 cz_golden_settings_a11[] = 147 { 148 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 149 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 150 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 151 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 152 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 153 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 154 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 155 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 156 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100, 157 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800, 158 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100, 159 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100, 160 }; 161 162 static const u32 cz_mgcg_cgcg_init[] = 163 { 164 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 165 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 166 }; 167 168 static const u32 stoney_golden_settings_a11[] = 169 { 170 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 171 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 172 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 173 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 174 }; 175 176 static const u32 stoney_mgcg_cgcg_init[] = 177 { 178 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100, 179 }; 180 181 /* 182 * sDMA - System DMA 183 * Starting with CIK, the GPU has new asynchronous 184 * DMA engines. These engines are used for compute 185 * and gfx. There are two DMA engines (SDMA0, SDMA1) 186 * and each one supports 1 ring buffer used for gfx 187 * and 2 queues used for compute. 188 * 189 * The programming model is very similar to the CP 190 * (ring buffer, IBs, etc.), but sDMA has it's own 191 * packet format that is different from the PM4 format 192 * used by the CP. sDMA supports copying data, writing 193 * embedded data, solid fills, and a number of other 194 * things. It also has support for tiling/detiling of 195 * buffers. 196 */ 197 198 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) 199 { 200 switch (adev->asic_type) { 201 case CHIP_FIJI: 202 amdgpu_device_program_register_sequence(adev, 203 fiji_mgcg_cgcg_init, 204 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 205 amdgpu_device_program_register_sequence(adev, 206 golden_settings_fiji_a10, 207 ARRAY_SIZE(golden_settings_fiji_a10)); 208 break; 209 case CHIP_TONGA: 210 amdgpu_device_program_register_sequence(adev, 211 tonga_mgcg_cgcg_init, 212 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 213 amdgpu_device_program_register_sequence(adev, 214 golden_settings_tonga_a11, 215 ARRAY_SIZE(golden_settings_tonga_a11)); 216 break; 217 case CHIP_POLARIS11: 218 case CHIP_POLARIS12: 219 case CHIP_VEGAM: 220 amdgpu_device_program_register_sequence(adev, 221 golden_settings_polaris11_a11, 222 ARRAY_SIZE(golden_settings_polaris11_a11)); 223 break; 224 case CHIP_POLARIS10: 225 amdgpu_device_program_register_sequence(adev, 226 golden_settings_polaris10_a11, 227 ARRAY_SIZE(golden_settings_polaris10_a11)); 228 break; 229 case CHIP_CARRIZO: 230 amdgpu_device_program_register_sequence(adev, 231 cz_mgcg_cgcg_init, 232 ARRAY_SIZE(cz_mgcg_cgcg_init)); 233 amdgpu_device_program_register_sequence(adev, 234 cz_golden_settings_a11, 235 ARRAY_SIZE(cz_golden_settings_a11)); 236 break; 237 case CHIP_STONEY: 238 amdgpu_device_program_register_sequence(adev, 239 stoney_mgcg_cgcg_init, 240 ARRAY_SIZE(stoney_mgcg_cgcg_init)); 241 amdgpu_device_program_register_sequence(adev, 242 stoney_golden_settings_a11, 243 ARRAY_SIZE(stoney_golden_settings_a11)); 244 break; 245 default: 246 break; 247 } 248 } 249 250 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev) 251 { 252 int i; 253 254 for (i = 0; i < adev->sdma.num_instances; i++) 255 amdgpu_ucode_release(&adev->sdma.instance[i].fw); 256 } 257 258 /** 259 * sdma_v3_0_init_microcode - load ucode images from disk 260 * 261 * @adev: amdgpu_device pointer 262 * 263 * Use the firmware interface to load the ucode images into 264 * the driver (not loaded into hw). 265 * Returns 0 on success, error on failure. 266 */ 267 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) 268 { 269 const char *chip_name; 270 int err = 0, i; 271 struct amdgpu_firmware_info *info = NULL; 272 const struct common_firmware_header *header = NULL; 273 const struct sdma_firmware_header_v1_0 *hdr; 274 275 DRM_DEBUG("\n"); 276 277 switch (adev->asic_type) { 278 case CHIP_TONGA: 279 chip_name = "tonga"; 280 break; 281 case CHIP_FIJI: 282 chip_name = "fiji"; 283 break; 284 case CHIP_POLARIS10: 285 chip_name = "polaris10"; 286 break; 287 case CHIP_POLARIS11: 288 chip_name = "polaris11"; 289 break; 290 case CHIP_POLARIS12: 291 chip_name = "polaris12"; 292 break; 293 case CHIP_VEGAM: 294 chip_name = "vegam"; 295 break; 296 case CHIP_CARRIZO: 297 chip_name = "carrizo"; 298 break; 299 case CHIP_STONEY: 300 chip_name = "stoney"; 301 break; 302 default: BUG(); 303 } 304 305 for (i = 0; i < adev->sdma.num_instances; i++) { 306 if (i == 0) 307 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw, 308 AMDGPU_UCODE_REQUIRED, 309 "amdgpu/%s_sdma.bin", chip_name); 310 else 311 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw, 312 AMDGPU_UCODE_REQUIRED, 313 "amdgpu/%s_sdma1.bin", chip_name); 314 if (err) 315 goto out; 316 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 317 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 318 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 319 if (adev->sdma.instance[i].feature_version >= 20) 320 adev->sdma.instance[i].burst_nop = true; 321 322 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 323 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 324 info->fw = adev->sdma.instance[i].fw; 325 header = (const struct common_firmware_header *)info->fw->data; 326 adev->firmware.fw_size += 327 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 328 329 } 330 out: 331 if (err) { 332 pr_err("sdma_v3_0: Failed to load firmware \"%s_sdma%s.bin\"\n", 333 chip_name, i == 0 ? "" : "1"); 334 for (i = 0; i < adev->sdma.num_instances; i++) 335 amdgpu_ucode_release(&adev->sdma.instance[i].fw); 336 } 337 return err; 338 } 339 340 /** 341 * sdma_v3_0_ring_get_rptr - get the current read pointer 342 * 343 * @ring: amdgpu ring pointer 344 * 345 * Get the current rptr from the hardware (VI+). 346 */ 347 static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring) 348 { 349 /* XXX check if swapping is necessary on BE */ 350 return *ring->rptr_cpu_addr >> 2; 351 } 352 353 /** 354 * sdma_v3_0_ring_get_wptr - get the current write pointer 355 * 356 * @ring: amdgpu ring pointer 357 * 358 * Get the current wptr from the hardware (VI+). 359 */ 360 static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring) 361 { 362 struct amdgpu_device *adev = ring->adev; 363 u32 wptr; 364 365 if (ring->use_doorbell || ring->use_pollmem) { 366 /* XXX check if swapping is necessary on BE */ 367 wptr = *ring->wptr_cpu_addr >> 2; 368 } else { 369 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; 370 } 371 372 return wptr; 373 } 374 375 /** 376 * sdma_v3_0_ring_set_wptr - commit the write pointer 377 * 378 * @ring: amdgpu ring pointer 379 * 380 * Write the wptr back to the hardware (VI+). 381 */ 382 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) 383 { 384 struct amdgpu_device *adev = ring->adev; 385 386 if (ring->use_doorbell) { 387 u32 *wb = (u32 *)ring->wptr_cpu_addr; 388 /* XXX check if swapping is necessary on BE */ 389 WRITE_ONCE(*wb, ring->wptr << 2); 390 WDOORBELL32(ring->doorbell_index, ring->wptr << 2); 391 } else if (ring->use_pollmem) { 392 u32 *wb = (u32 *)ring->wptr_cpu_addr; 393 394 WRITE_ONCE(*wb, ring->wptr << 2); 395 } else { 396 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2); 397 } 398 } 399 400 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 401 { 402 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 403 int i; 404 405 for (i = 0; i < count; i++) 406 if (sdma && sdma->burst_nop && (i == 0)) 407 amdgpu_ring_write(ring, ring->funcs->nop | 408 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 409 else 410 amdgpu_ring_write(ring, ring->funcs->nop); 411 } 412 413 /** 414 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine 415 * 416 * @ring: amdgpu ring pointer 417 * @job: job to retrieve vmid from 418 * @ib: IB object to schedule 419 * @flags: unused 420 * 421 * Schedule an IB in the DMA ring (VI). 422 */ 423 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, 424 struct amdgpu_job *job, 425 struct amdgpu_ib *ib, 426 uint32_t flags) 427 { 428 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 429 430 /* IB packet must end on a 8 DW boundary */ 431 sdma_v3_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 432 433 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 434 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 435 /* base must be 32 byte aligned */ 436 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 437 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 438 amdgpu_ring_write(ring, ib->length_dw); 439 amdgpu_ring_write(ring, 0); 440 amdgpu_ring_write(ring, 0); 441 442 } 443 444 /** 445 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 446 * 447 * @ring: amdgpu ring pointer 448 * 449 * Emit an hdp flush packet on the requested DMA ring. 450 */ 451 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 452 { 453 u32 ref_and_mask = 0; 454 455 if (ring->me == 0) 456 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); 457 else 458 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); 459 460 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 461 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 462 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 463 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 464 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 465 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 466 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 467 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 468 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 469 } 470 471 /** 472 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring 473 * 474 * @ring: amdgpu ring pointer 475 * @addr: address 476 * @seq: sequence number 477 * @flags: fence related flags 478 * 479 * Add a DMA fence packet to the ring to write 480 * the fence seq number and DMA trap packet to generate 481 * an interrupt if needed (VI). 482 */ 483 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 484 unsigned flags) 485 { 486 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 487 /* write the fence */ 488 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 489 amdgpu_ring_write(ring, lower_32_bits(addr)); 490 amdgpu_ring_write(ring, upper_32_bits(addr)); 491 amdgpu_ring_write(ring, lower_32_bits(seq)); 492 493 /* optionally write high bits as well */ 494 if (write64bit) { 495 addr += 4; 496 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 497 amdgpu_ring_write(ring, lower_32_bits(addr)); 498 amdgpu_ring_write(ring, upper_32_bits(addr)); 499 amdgpu_ring_write(ring, upper_32_bits(seq)); 500 } 501 502 /* generate an interrupt */ 503 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 504 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 505 } 506 507 /** 508 * sdma_v3_0_gfx_stop - stop the gfx async dma engines 509 * 510 * @adev: amdgpu_device pointer 511 * 512 * Stop the gfx async dma ring buffers (VI). 513 */ 514 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev) 515 { 516 u32 rb_cntl, ib_cntl; 517 int i; 518 519 for (i = 0; i < adev->sdma.num_instances; i++) { 520 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 521 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 522 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 523 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 524 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 525 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 526 } 527 } 528 529 /** 530 * sdma_v3_0_rlc_stop - stop the compute async dma engines 531 * 532 * @adev: amdgpu_device pointer 533 * 534 * Stop the compute async dma queues (VI). 535 */ 536 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev) 537 { 538 /* XXX todo */ 539 } 540 541 /** 542 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch 543 * 544 * @adev: amdgpu_device pointer 545 * @enable: enable/disable the DMA MEs context switch. 546 * 547 * Halt or unhalt the async dma engines context switch (VI). 548 */ 549 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 550 { 551 u32 f32_cntl, phase_quantum = 0; 552 int i; 553 554 if (amdgpu_sdma_phase_quantum) { 555 unsigned value = amdgpu_sdma_phase_quantum; 556 unsigned unit = 0; 557 558 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 559 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 560 value = (value + 1) >> 1; 561 unit++; 562 } 563 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 564 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 565 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 566 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 567 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 568 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 569 WARN_ONCE(1, 570 "clamping sdma_phase_quantum to %uK clock cycles\n", 571 value << unit); 572 } 573 phase_quantum = 574 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 575 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 576 } 577 578 for (i = 0; i < adev->sdma.num_instances; i++) { 579 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); 580 if (enable) { 581 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 582 AUTO_CTXSW_ENABLE, 1); 583 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 584 ATC_L1_ENABLE, 1); 585 if (amdgpu_sdma_phase_quantum) { 586 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], 587 phase_quantum); 588 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], 589 phase_quantum); 590 } 591 } else { 592 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 593 AUTO_CTXSW_ENABLE, 0); 594 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 595 ATC_L1_ENABLE, 1); 596 } 597 598 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); 599 } 600 } 601 602 /** 603 * sdma_v3_0_enable - stop the async dma engines 604 * 605 * @adev: amdgpu_device pointer 606 * @enable: enable/disable the DMA MEs. 607 * 608 * Halt or unhalt the async dma engines (VI). 609 */ 610 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable) 611 { 612 u32 f32_cntl; 613 int i; 614 615 if (!enable) { 616 sdma_v3_0_gfx_stop(adev); 617 sdma_v3_0_rlc_stop(adev); 618 } 619 620 for (i = 0; i < adev->sdma.num_instances; i++) { 621 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 622 if (enable) 623 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); 624 else 625 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 626 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); 627 } 628 } 629 630 /** 631 * sdma_v3_0_gfx_resume - setup and start the async dma engines 632 * 633 * @adev: amdgpu_device pointer 634 * 635 * Set up the gfx DMA ring buffers and enable them (VI). 636 * Returns 0 for success, error for failure. 637 */ 638 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) 639 { 640 struct amdgpu_ring *ring; 641 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 642 u32 rb_bufsz; 643 u32 doorbell; 644 u64 wptr_gpu_addr; 645 int i, j, r; 646 647 for (i = 0; i < adev->sdma.num_instances; i++) { 648 ring = &adev->sdma.instance[i].ring; 649 amdgpu_ring_clear_ring(ring); 650 651 mutex_lock(&adev->srbm_mutex); 652 for (j = 0; j < 16; j++) { 653 vi_srbm_select(adev, 0, 0, 0, j); 654 /* SDMA GFX */ 655 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 656 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 657 } 658 vi_srbm_select(adev, 0, 0, 0, 0); 659 mutex_unlock(&adev->srbm_mutex); 660 661 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], 662 adev->gfx.config.gb_addr_config & 0x70); 663 664 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 665 666 /* Set ring buffer size in dwords */ 667 rb_bufsz = order_base_2(ring->ring_size / 4); 668 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 669 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 670 #ifdef __BIG_ENDIAN 671 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 672 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 673 RPTR_WRITEBACK_SWAP_ENABLE, 1); 674 #endif 675 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 676 677 /* Initialize the ring buffer's read and write pointers */ 678 ring->wptr = 0; 679 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 680 sdma_v3_0_ring_set_wptr(ring); 681 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); 682 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); 683 684 /* set the wb address whether it's enabled or not */ 685 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 686 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 687 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 688 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 689 690 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 691 692 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 693 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 694 695 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); 696 697 if (ring->use_doorbell) { 698 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, 699 OFFSET, ring->doorbell_index); 700 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 701 } else { 702 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 703 } 704 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell); 705 706 /* setup the wptr shadow polling */ 707 wptr_gpu_addr = ring->wptr_gpu_addr; 708 709 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i], 710 lower_32_bits(wptr_gpu_addr)); 711 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i], 712 upper_32_bits(wptr_gpu_addr)); 713 wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]); 714 if (ring->use_pollmem) { 715 /*wptr polling is not enough fast, directly clean the wptr register */ 716 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 717 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 718 SDMA0_GFX_RB_WPTR_POLL_CNTL, 719 ENABLE, 1); 720 } else { 721 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 722 SDMA0_GFX_RB_WPTR_POLL_CNTL, 723 ENABLE, 0); 724 } 725 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl); 726 727 /* enable DMA RB */ 728 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 729 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 730 731 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 732 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 733 #ifdef __BIG_ENDIAN 734 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 735 #endif 736 /* enable DMA IBs */ 737 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 738 } 739 740 /* unhalt the MEs */ 741 sdma_v3_0_enable(adev, true); 742 /* enable sdma ring preemption */ 743 sdma_v3_0_ctx_switch_enable(adev, true); 744 745 for (i = 0; i < adev->sdma.num_instances; i++) { 746 ring = &adev->sdma.instance[i].ring; 747 r = amdgpu_ring_test_helper(ring); 748 if (r) 749 return r; 750 } 751 752 return 0; 753 } 754 755 /** 756 * sdma_v3_0_rlc_resume - setup and start the async dma engines 757 * 758 * @adev: amdgpu_device pointer 759 * 760 * Set up the compute DMA queues and enable them (VI). 761 * Returns 0 for success, error for failure. 762 */ 763 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev) 764 { 765 /* XXX todo */ 766 return 0; 767 } 768 769 /** 770 * sdma_v3_0_start - setup and start the async dma engines 771 * 772 * @adev: amdgpu_device pointer 773 * 774 * Set up the DMA engines and enable them (VI). 775 * Returns 0 for success, error for failure. 776 */ 777 static int sdma_v3_0_start(struct amdgpu_device *adev) 778 { 779 int r; 780 781 /* disable sdma engine before programing it */ 782 sdma_v3_0_ctx_switch_enable(adev, false); 783 sdma_v3_0_enable(adev, false); 784 785 /* start the gfx rings and rlc compute queues */ 786 r = sdma_v3_0_gfx_resume(adev); 787 if (r) 788 return r; 789 r = sdma_v3_0_rlc_resume(adev); 790 if (r) 791 return r; 792 793 return 0; 794 } 795 796 /** 797 * sdma_v3_0_ring_test_ring - simple async dma engine test 798 * 799 * @ring: amdgpu_ring structure holding ring information 800 * 801 * Test the DMA engine by writing using it to write an 802 * value to memory. (VI). 803 * Returns 0 for success, error for failure. 804 */ 805 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) 806 { 807 struct amdgpu_device *adev = ring->adev; 808 unsigned i; 809 unsigned index; 810 int r; 811 u32 tmp; 812 u64 gpu_addr; 813 814 r = amdgpu_device_wb_get(adev, &index); 815 if (r) 816 return r; 817 818 gpu_addr = adev->wb.gpu_addr + (index * 4); 819 tmp = 0xCAFEDEAD; 820 adev->wb.wb[index] = cpu_to_le32(tmp); 821 822 r = amdgpu_ring_alloc(ring, 5); 823 if (r) 824 goto error_free_wb; 825 826 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 827 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 828 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 829 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 830 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 831 amdgpu_ring_write(ring, 0xDEADBEEF); 832 amdgpu_ring_commit(ring); 833 834 for (i = 0; i < adev->usec_timeout; i++) { 835 tmp = le32_to_cpu(adev->wb.wb[index]); 836 if (tmp == 0xDEADBEEF) 837 break; 838 udelay(1); 839 } 840 841 if (i >= adev->usec_timeout) 842 r = -ETIMEDOUT; 843 844 error_free_wb: 845 amdgpu_device_wb_free(adev, index); 846 return r; 847 } 848 849 /** 850 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine 851 * 852 * @ring: amdgpu_ring structure holding ring information 853 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 854 * 855 * Test a simple IB in the DMA ring (VI). 856 * Returns 0 on success, error on failure. 857 */ 858 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 859 { 860 struct amdgpu_device *adev = ring->adev; 861 struct amdgpu_ib ib; 862 struct dma_fence *f = NULL; 863 unsigned index; 864 u32 tmp = 0; 865 u64 gpu_addr; 866 long r; 867 868 r = amdgpu_device_wb_get(adev, &index); 869 if (r) 870 return r; 871 872 gpu_addr = adev->wb.gpu_addr + (index * 4); 873 tmp = 0xCAFEDEAD; 874 adev->wb.wb[index] = cpu_to_le32(tmp); 875 memset(&ib, 0, sizeof(ib)); 876 r = amdgpu_ib_get(adev, NULL, 256, 877 AMDGPU_IB_POOL_DIRECT, &ib); 878 if (r) 879 goto err0; 880 881 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 882 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 883 ib.ptr[1] = lower_32_bits(gpu_addr); 884 ib.ptr[2] = upper_32_bits(gpu_addr); 885 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); 886 ib.ptr[4] = 0xDEADBEEF; 887 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 888 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 889 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 890 ib.length_dw = 8; 891 892 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 893 if (r) 894 goto err1; 895 896 r = dma_fence_wait_timeout(f, false, timeout); 897 if (r == 0) { 898 r = -ETIMEDOUT; 899 goto err1; 900 } else if (r < 0) { 901 goto err1; 902 } 903 tmp = le32_to_cpu(adev->wb.wb[index]); 904 if (tmp == 0xDEADBEEF) 905 r = 0; 906 else 907 r = -EINVAL; 908 err1: 909 amdgpu_ib_free(&ib, NULL); 910 dma_fence_put(f); 911 err0: 912 amdgpu_device_wb_free(adev, index); 913 return r; 914 } 915 916 /** 917 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART 918 * 919 * @ib: indirect buffer to fill with commands 920 * @pe: addr of the page entry 921 * @src: src addr to copy from 922 * @count: number of page entries to update 923 * 924 * Update PTEs by copying them from the GART using sDMA (CIK). 925 */ 926 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib, 927 uint64_t pe, uint64_t src, 928 unsigned count) 929 { 930 unsigned bytes = count * 8; 931 932 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 933 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 934 ib->ptr[ib->length_dw++] = bytes; 935 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 936 ib->ptr[ib->length_dw++] = lower_32_bits(src); 937 ib->ptr[ib->length_dw++] = upper_32_bits(src); 938 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 939 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 940 } 941 942 /** 943 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually 944 * 945 * @ib: indirect buffer to fill with commands 946 * @pe: addr of the page entry 947 * @value: dst addr to write into pe 948 * @count: number of page entries to update 949 * @incr: increase next addr by incr bytes 950 * 951 * Update PTEs by writing them manually using sDMA (CIK). 952 */ 953 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 954 uint64_t value, unsigned count, 955 uint32_t incr) 956 { 957 unsigned ndw = count * 2; 958 959 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 960 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 961 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 962 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 963 ib->ptr[ib->length_dw++] = ndw; 964 for (; ndw > 0; ndw -= 2) { 965 ib->ptr[ib->length_dw++] = lower_32_bits(value); 966 ib->ptr[ib->length_dw++] = upper_32_bits(value); 967 value += incr; 968 } 969 } 970 971 /** 972 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA 973 * 974 * @ib: indirect buffer to fill with commands 975 * @pe: addr of the page entry 976 * @addr: dst addr to write into pe 977 * @count: number of page entries to update 978 * @incr: increase next addr by incr bytes 979 * @flags: access flags 980 * 981 * Update the page tables using sDMA (CIK). 982 */ 983 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, 984 uint64_t addr, unsigned count, 985 uint32_t incr, uint64_t flags) 986 { 987 /* for physically contiguous pages (vram) */ 988 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); 989 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 990 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 991 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 992 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 993 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 994 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 995 ib->ptr[ib->length_dw++] = incr; /* increment size */ 996 ib->ptr[ib->length_dw++] = 0; 997 ib->ptr[ib->length_dw++] = count; /* number of entries */ 998 } 999 1000 /** 1001 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw 1002 * 1003 * @ring: amdgpu_ring structure holding ring information 1004 * @ib: indirect buffer to fill with padding 1005 * 1006 */ 1007 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1008 { 1009 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1010 u32 pad_count; 1011 int i; 1012 1013 pad_count = (-ib->length_dw) & 7; 1014 for (i = 0; i < pad_count; i++) 1015 if (sdma && sdma->burst_nop && (i == 0)) 1016 ib->ptr[ib->length_dw++] = 1017 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1018 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1019 else 1020 ib->ptr[ib->length_dw++] = 1021 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1022 } 1023 1024 /** 1025 * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline 1026 * 1027 * @ring: amdgpu_ring pointer 1028 * 1029 * Make sure all previous operations are completed (CIK). 1030 */ 1031 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1032 { 1033 uint32_t seq = ring->fence_drv.sync_seq; 1034 uint64_t addr = ring->fence_drv.gpu_addr; 1035 1036 /* wait for idle */ 1037 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1038 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1039 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1040 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1041 amdgpu_ring_write(ring, addr & 0xfffffffc); 1042 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1043 amdgpu_ring_write(ring, seq); /* reference */ 1044 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1045 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1046 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1047 } 1048 1049 /** 1050 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA 1051 * 1052 * @ring: amdgpu_ring pointer 1053 * @vmid: vmid number to use 1054 * @pd_addr: address 1055 * 1056 * Update the page table base and flush the VM TLB 1057 * using sDMA (VI). 1058 */ 1059 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1060 unsigned vmid, uint64_t pd_addr) 1061 { 1062 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1063 1064 /* wait for flush */ 1065 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1066 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1067 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ 1068 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 1069 amdgpu_ring_write(ring, 0); 1070 amdgpu_ring_write(ring, 0); /* reference */ 1071 amdgpu_ring_write(ring, 0); /* mask */ 1072 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1073 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 1074 } 1075 1076 static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring, 1077 uint32_t reg, uint32_t val) 1078 { 1079 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1080 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1081 amdgpu_ring_write(ring, reg); 1082 amdgpu_ring_write(ring, val); 1083 } 1084 1085 static int sdma_v3_0_early_init(struct amdgpu_ip_block *ip_block) 1086 { 1087 struct amdgpu_device *adev = ip_block->adev; 1088 int r; 1089 1090 switch (adev->asic_type) { 1091 case CHIP_STONEY: 1092 adev->sdma.num_instances = 1; 1093 break; 1094 default: 1095 adev->sdma.num_instances = SDMA_MAX_INSTANCE; 1096 break; 1097 } 1098 1099 r = sdma_v3_0_init_microcode(adev); 1100 if (r) 1101 return r; 1102 1103 sdma_v3_0_set_ring_funcs(adev); 1104 sdma_v3_0_set_buffer_funcs(adev); 1105 sdma_v3_0_set_vm_pte_funcs(adev); 1106 sdma_v3_0_set_irq_funcs(adev); 1107 1108 return 0; 1109 } 1110 1111 static int sdma_v3_0_sw_init(struct amdgpu_ip_block *ip_block) 1112 { 1113 struct amdgpu_ring *ring; 1114 int r, i; 1115 struct amdgpu_device *adev = ip_block->adev; 1116 1117 /* SDMA trap event */ 1118 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP, 1119 &adev->sdma.trap_irq); 1120 if (r) 1121 return r; 1122 1123 /* SDMA Privileged inst */ 1124 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241, 1125 &adev->sdma.illegal_inst_irq); 1126 if (r) 1127 return r; 1128 1129 /* SDMA Privileged inst */ 1130 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE, 1131 &adev->sdma.illegal_inst_irq); 1132 if (r) 1133 return r; 1134 1135 for (i = 0; i < adev->sdma.num_instances; i++) { 1136 ring = &adev->sdma.instance[i].ring; 1137 ring->ring_obj = NULL; 1138 if (!amdgpu_sriov_vf(adev)) { 1139 ring->use_doorbell = true; 1140 ring->doorbell_index = adev->doorbell_index.sdma_engine[i]; 1141 } else { 1142 ring->use_pollmem = true; 1143 } 1144 1145 sprintf(ring->name, "sdma%d", i); 1146 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1147 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 : 1148 AMDGPU_SDMA_IRQ_INSTANCE1, 1149 AMDGPU_RING_PRIO_DEFAULT, NULL); 1150 if (r) 1151 return r; 1152 } 1153 1154 return r; 1155 } 1156 1157 static int sdma_v3_0_sw_fini(struct amdgpu_ip_block *ip_block) 1158 { 1159 struct amdgpu_device *adev = ip_block->adev; 1160 int i; 1161 1162 for (i = 0; i < adev->sdma.num_instances; i++) 1163 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1164 1165 sdma_v3_0_free_microcode(adev); 1166 return 0; 1167 } 1168 1169 static int sdma_v3_0_hw_init(struct amdgpu_ip_block *ip_block) 1170 { 1171 int r; 1172 struct amdgpu_device *adev = ip_block->adev; 1173 1174 sdma_v3_0_init_golden_registers(adev); 1175 1176 r = sdma_v3_0_start(adev); 1177 if (r) 1178 return r; 1179 1180 return r; 1181 } 1182 1183 static int sdma_v3_0_hw_fini(struct amdgpu_ip_block *ip_block) 1184 { 1185 struct amdgpu_device *adev = ip_block->adev; 1186 1187 sdma_v3_0_ctx_switch_enable(adev, false); 1188 sdma_v3_0_enable(adev, false); 1189 1190 return 0; 1191 } 1192 1193 static int sdma_v3_0_suspend(struct amdgpu_ip_block *ip_block) 1194 { 1195 return sdma_v3_0_hw_fini(ip_block); 1196 } 1197 1198 static int sdma_v3_0_resume(struct amdgpu_ip_block *ip_block) 1199 { 1200 return sdma_v3_0_hw_init(ip_block); 1201 } 1202 1203 static bool sdma_v3_0_is_idle(void *handle) 1204 { 1205 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1206 u32 tmp = RREG32(mmSRBM_STATUS2); 1207 1208 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1209 SRBM_STATUS2__SDMA1_BUSY_MASK)) 1210 return false; 1211 1212 return true; 1213 } 1214 1215 static int sdma_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1216 { 1217 unsigned i; 1218 u32 tmp; 1219 struct amdgpu_device *adev = ip_block->adev; 1220 1221 for (i = 0; i < adev->usec_timeout; i++) { 1222 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1223 SRBM_STATUS2__SDMA1_BUSY_MASK); 1224 1225 if (!tmp) 1226 return 0; 1227 udelay(1); 1228 } 1229 return -ETIMEDOUT; 1230 } 1231 1232 static bool sdma_v3_0_check_soft_reset(struct amdgpu_ip_block *ip_block) 1233 { 1234 struct amdgpu_device *adev = ip_block->adev; 1235 u32 srbm_soft_reset = 0; 1236 u32 tmp = RREG32(mmSRBM_STATUS2); 1237 1238 if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) || 1239 (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) { 1240 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1241 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1242 } 1243 1244 if (srbm_soft_reset) { 1245 adev->sdma.srbm_soft_reset = srbm_soft_reset; 1246 return true; 1247 } else { 1248 adev->sdma.srbm_soft_reset = 0; 1249 return false; 1250 } 1251 } 1252 1253 static int sdma_v3_0_pre_soft_reset(struct amdgpu_ip_block *ip_block) 1254 { 1255 struct amdgpu_device *adev = ip_block->adev; 1256 u32 srbm_soft_reset = 0; 1257 1258 if (!adev->sdma.srbm_soft_reset) 1259 return 0; 1260 1261 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1262 1263 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || 1264 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { 1265 sdma_v3_0_ctx_switch_enable(adev, false); 1266 sdma_v3_0_enable(adev, false); 1267 } 1268 1269 return 0; 1270 } 1271 1272 static int sdma_v3_0_post_soft_reset(struct amdgpu_ip_block *ip_block) 1273 { 1274 struct amdgpu_device *adev = ip_block->adev; 1275 u32 srbm_soft_reset = 0; 1276 1277 if (!adev->sdma.srbm_soft_reset) 1278 return 0; 1279 1280 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1281 1282 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || 1283 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { 1284 sdma_v3_0_gfx_resume(adev); 1285 sdma_v3_0_rlc_resume(adev); 1286 } 1287 1288 return 0; 1289 } 1290 1291 static int sdma_v3_0_soft_reset(struct amdgpu_ip_block *ip_block) 1292 { 1293 struct amdgpu_device *adev = ip_block->adev; 1294 u32 srbm_soft_reset = 0; 1295 u32 tmp; 1296 1297 if (!adev->sdma.srbm_soft_reset) 1298 return 0; 1299 1300 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1301 1302 if (srbm_soft_reset) { 1303 tmp = RREG32(mmSRBM_SOFT_RESET); 1304 tmp |= srbm_soft_reset; 1305 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1306 WREG32(mmSRBM_SOFT_RESET, tmp); 1307 tmp = RREG32(mmSRBM_SOFT_RESET); 1308 1309 udelay(50); 1310 1311 tmp &= ~srbm_soft_reset; 1312 WREG32(mmSRBM_SOFT_RESET, tmp); 1313 tmp = RREG32(mmSRBM_SOFT_RESET); 1314 1315 /* Wait a little for things to settle down */ 1316 udelay(50); 1317 } 1318 1319 return 0; 1320 } 1321 1322 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev, 1323 struct amdgpu_irq_src *source, 1324 unsigned type, 1325 enum amdgpu_interrupt_state state) 1326 { 1327 u32 sdma_cntl; 1328 1329 switch (type) { 1330 case AMDGPU_SDMA_IRQ_INSTANCE0: 1331 switch (state) { 1332 case AMDGPU_IRQ_STATE_DISABLE: 1333 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1334 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1335 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1336 break; 1337 case AMDGPU_IRQ_STATE_ENABLE: 1338 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1339 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1340 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1341 break; 1342 default: 1343 break; 1344 } 1345 break; 1346 case AMDGPU_SDMA_IRQ_INSTANCE1: 1347 switch (state) { 1348 case AMDGPU_IRQ_STATE_DISABLE: 1349 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1350 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1351 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1352 break; 1353 case AMDGPU_IRQ_STATE_ENABLE: 1354 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1355 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1356 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1357 break; 1358 default: 1359 break; 1360 } 1361 break; 1362 default: 1363 break; 1364 } 1365 return 0; 1366 } 1367 1368 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev, 1369 struct amdgpu_irq_src *source, 1370 struct amdgpu_iv_entry *entry) 1371 { 1372 u8 instance_id, queue_id; 1373 1374 instance_id = (entry->ring_id & 0x3) >> 0; 1375 queue_id = (entry->ring_id & 0xc) >> 2; 1376 DRM_DEBUG("IH: SDMA trap\n"); 1377 switch (instance_id) { 1378 case 0: 1379 switch (queue_id) { 1380 case 0: 1381 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1382 break; 1383 case 1: 1384 /* XXX compute */ 1385 break; 1386 case 2: 1387 /* XXX compute */ 1388 break; 1389 } 1390 break; 1391 case 1: 1392 switch (queue_id) { 1393 case 0: 1394 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1395 break; 1396 case 1: 1397 /* XXX compute */ 1398 break; 1399 case 2: 1400 /* XXX compute */ 1401 break; 1402 } 1403 break; 1404 } 1405 return 0; 1406 } 1407 1408 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1409 struct amdgpu_irq_src *source, 1410 struct amdgpu_iv_entry *entry) 1411 { 1412 u8 instance_id, queue_id; 1413 1414 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1415 instance_id = (entry->ring_id & 0x3) >> 0; 1416 queue_id = (entry->ring_id & 0xc) >> 2; 1417 1418 if (instance_id <= 1 && queue_id == 0) 1419 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched); 1420 return 0; 1421 } 1422 1423 static void sdma_v3_0_update_sdma_medium_grain_clock_gating( 1424 struct amdgpu_device *adev, 1425 bool enable) 1426 { 1427 uint32_t temp, data; 1428 int i; 1429 1430 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1431 for (i = 0; i < adev->sdma.num_instances; i++) { 1432 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); 1433 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1434 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1435 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1436 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1437 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1438 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1439 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1440 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1441 if (data != temp) 1442 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); 1443 } 1444 } else { 1445 for (i = 0; i < adev->sdma.num_instances; i++) { 1446 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); 1447 data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1448 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1449 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1450 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1451 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1452 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1453 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1454 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK; 1455 1456 if (data != temp) 1457 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); 1458 } 1459 } 1460 } 1461 1462 static void sdma_v3_0_update_sdma_medium_grain_light_sleep( 1463 struct amdgpu_device *adev, 1464 bool enable) 1465 { 1466 uint32_t temp, data; 1467 int i; 1468 1469 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1470 for (i = 0; i < adev->sdma.num_instances; i++) { 1471 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1472 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1473 1474 if (temp != data) 1475 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1476 } 1477 } else { 1478 for (i = 0; i < adev->sdma.num_instances; i++) { 1479 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1480 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1481 1482 if (temp != data) 1483 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1484 } 1485 } 1486 } 1487 1488 static int sdma_v3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1489 enum amd_clockgating_state state) 1490 { 1491 struct amdgpu_device *adev = ip_block->adev; 1492 1493 if (amdgpu_sriov_vf(adev)) 1494 return 0; 1495 1496 switch (adev->asic_type) { 1497 case CHIP_FIJI: 1498 case CHIP_CARRIZO: 1499 case CHIP_STONEY: 1500 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev, 1501 state == AMD_CG_STATE_GATE); 1502 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev, 1503 state == AMD_CG_STATE_GATE); 1504 break; 1505 default: 1506 break; 1507 } 1508 return 0; 1509 } 1510 1511 static int sdma_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 1512 enum amd_powergating_state state) 1513 { 1514 return 0; 1515 } 1516 1517 static void sdma_v3_0_get_clockgating_state(void *handle, u64 *flags) 1518 { 1519 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1520 int data; 1521 1522 if (amdgpu_sriov_vf(adev)) 1523 *flags = 0; 1524 1525 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1526 data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]); 1527 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK)) 1528 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1529 1530 /* AMD_CG_SUPPORT_SDMA_LS */ 1531 data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]); 1532 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1533 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1534 } 1535 1536 static const struct amd_ip_funcs sdma_v3_0_ip_funcs = { 1537 .name = "sdma_v3_0", 1538 .early_init = sdma_v3_0_early_init, 1539 .sw_init = sdma_v3_0_sw_init, 1540 .sw_fini = sdma_v3_0_sw_fini, 1541 .hw_init = sdma_v3_0_hw_init, 1542 .hw_fini = sdma_v3_0_hw_fini, 1543 .suspend = sdma_v3_0_suspend, 1544 .resume = sdma_v3_0_resume, 1545 .is_idle = sdma_v3_0_is_idle, 1546 .wait_for_idle = sdma_v3_0_wait_for_idle, 1547 .check_soft_reset = sdma_v3_0_check_soft_reset, 1548 .pre_soft_reset = sdma_v3_0_pre_soft_reset, 1549 .post_soft_reset = sdma_v3_0_post_soft_reset, 1550 .soft_reset = sdma_v3_0_soft_reset, 1551 .set_clockgating_state = sdma_v3_0_set_clockgating_state, 1552 .set_powergating_state = sdma_v3_0_set_powergating_state, 1553 .get_clockgating_state = sdma_v3_0_get_clockgating_state, 1554 }; 1555 1556 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { 1557 .type = AMDGPU_RING_TYPE_SDMA, 1558 .align_mask = 0xf, 1559 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1560 .support_64bit_ptrs = false, 1561 .secure_submission_supported = true, 1562 .get_rptr = sdma_v3_0_ring_get_rptr, 1563 .get_wptr = sdma_v3_0_ring_get_wptr, 1564 .set_wptr = sdma_v3_0_ring_set_wptr, 1565 .emit_frame_size = 1566 6 + /* sdma_v3_0_ring_emit_hdp_flush */ 1567 3 + /* hdp invalidate */ 1568 6 + /* sdma_v3_0_ring_emit_pipeline_sync */ 1569 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v3_0_ring_emit_vm_flush */ 1570 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */ 1571 .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */ 1572 .emit_ib = sdma_v3_0_ring_emit_ib, 1573 .emit_fence = sdma_v3_0_ring_emit_fence, 1574 .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync, 1575 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, 1576 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, 1577 .test_ring = sdma_v3_0_ring_test_ring, 1578 .test_ib = sdma_v3_0_ring_test_ib, 1579 .insert_nop = sdma_v3_0_ring_insert_nop, 1580 .pad_ib = sdma_v3_0_ring_pad_ib, 1581 .emit_wreg = sdma_v3_0_ring_emit_wreg, 1582 }; 1583 1584 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev) 1585 { 1586 int i; 1587 1588 for (i = 0; i < adev->sdma.num_instances; i++) { 1589 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs; 1590 adev->sdma.instance[i].ring.me = i; 1591 } 1592 } 1593 1594 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = { 1595 .set = sdma_v3_0_set_trap_irq_state, 1596 .process = sdma_v3_0_process_trap_irq, 1597 }; 1598 1599 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = { 1600 .process = sdma_v3_0_process_illegal_inst_irq, 1601 }; 1602 1603 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev) 1604 { 1605 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1606 adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs; 1607 adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs; 1608 } 1609 1610 /** 1611 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine 1612 * 1613 * @ib: indirect buffer to copy to 1614 * @src_offset: src GPU address 1615 * @dst_offset: dst GPU address 1616 * @byte_count: number of bytes to xfer 1617 * @copy_flags: unused 1618 * 1619 * Copy GPU buffers using the DMA engine (VI). 1620 * Used by the amdgpu ttm implementation to move pages if 1621 * registered as the asic copy callback. 1622 */ 1623 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib, 1624 uint64_t src_offset, 1625 uint64_t dst_offset, 1626 uint32_t byte_count, 1627 uint32_t copy_flags) 1628 { 1629 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1630 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1631 ib->ptr[ib->length_dw++] = byte_count; 1632 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1633 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1634 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1635 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1636 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1637 } 1638 1639 /** 1640 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine 1641 * 1642 * @ib: indirect buffer to copy to 1643 * @src_data: value to write to buffer 1644 * @dst_offset: dst GPU address 1645 * @byte_count: number of bytes to xfer 1646 * 1647 * Fill GPU buffers using the DMA engine (VI). 1648 */ 1649 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib, 1650 uint32_t src_data, 1651 uint64_t dst_offset, 1652 uint32_t byte_count) 1653 { 1654 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1655 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1656 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1657 ib->ptr[ib->length_dw++] = src_data; 1658 ib->ptr[ib->length_dw++] = byte_count; 1659 } 1660 1661 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = { 1662 .copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */ 1663 .copy_num_dw = 7, 1664 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer, 1665 1666 .fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */ 1667 .fill_num_dw = 5, 1668 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer, 1669 }; 1670 1671 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) 1672 { 1673 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs; 1674 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1675 } 1676 1677 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { 1678 .copy_pte_num_dw = 7, 1679 .copy_pte = sdma_v3_0_vm_copy_pte, 1680 1681 .write_pte = sdma_v3_0_vm_write_pte, 1682 .set_pte_pde = sdma_v3_0_vm_set_pte_pde, 1683 }; 1684 1685 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1686 { 1687 unsigned i; 1688 1689 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; 1690 for (i = 0; i < adev->sdma.num_instances; i++) { 1691 adev->vm_manager.vm_pte_scheds[i] = 1692 &adev->sdma.instance[i].ring.sched; 1693 } 1694 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1695 } 1696 1697 const struct amdgpu_ip_block_version sdma_v3_0_ip_block = 1698 { 1699 .type = AMD_IP_BLOCK_TYPE_SDMA, 1700 .major = 3, 1701 .minor = 0, 1702 .rev = 0, 1703 .funcs = &sdma_v3_0_ip_funcs, 1704 }; 1705 1706 const struct amdgpu_ip_block_version sdma_v3_1_ip_block = 1707 { 1708 .type = AMD_IP_BLOCK_TYPE_SDMA, 1709 .major = 3, 1710 .minor = 1, 1711 .rev = 0, 1712 .funcs = &sdma_v3_0_ip_funcs, 1713 }; 1714