1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 #include "vi.h" 30 #include "vid.h" 31 32 #include "oss/oss_3_0_d.h" 33 #include "oss/oss_3_0_sh_mask.h" 34 35 #include "gmc/gmc_8_1_d.h" 36 #include "gmc/gmc_8_1_sh_mask.h" 37 38 #include "gca/gfx_8_0_d.h" 39 #include "gca/gfx_8_0_enum.h" 40 #include "gca/gfx_8_0_sh_mask.h" 41 42 #include "bif/bif_5_0_d.h" 43 #include "bif/bif_5_0_sh_mask.h" 44 45 #include "tonga_sdma_pkt_open.h" 46 47 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev); 48 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); 49 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev); 50 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); 51 52 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); 53 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin"); 54 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin"); 55 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); 56 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); 57 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); 58 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin"); 59 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin"); 60 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin"); 61 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin"); 62 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin"); 63 MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin"); 65 66 67 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 68 { 69 SDMA0_REGISTER_OFFSET, 70 SDMA1_REGISTER_OFFSET 71 }; 72 73 static const u32 golden_settings_tonga_a11[] = 74 { 75 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 76 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 77 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 78 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 79 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 80 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 81 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 82 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 83 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 84 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 85 }; 86 87 static const u32 tonga_mgcg_cgcg_init[] = 88 { 89 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 90 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 91 }; 92 93 static const u32 golden_settings_fiji_a10[] = 94 { 95 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 96 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 97 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 98 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 99 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 100 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 101 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 102 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 103 }; 104 105 static const u32 fiji_mgcg_cgcg_init[] = 106 { 107 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 108 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 109 }; 110 111 static const u32 golden_settings_polaris11_a11[] = 112 { 113 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 114 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 115 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 116 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 117 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 118 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 119 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 120 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 121 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 122 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 123 }; 124 125 static const u32 golden_settings_polaris10_a11[] = 126 { 127 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 128 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 129 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 130 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 131 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 132 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 133 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 134 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 135 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 136 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 137 }; 138 139 static const u32 cz_golden_settings_a11[] = 140 { 141 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 142 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 143 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 144 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 145 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 146 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 147 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 148 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 149 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100, 150 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800, 151 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100, 152 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100, 153 }; 154 155 static const u32 cz_mgcg_cgcg_init[] = 156 { 157 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 158 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 159 }; 160 161 static const u32 stoney_golden_settings_a11[] = 162 { 163 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 164 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 165 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 166 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 167 }; 168 169 static const u32 stoney_mgcg_cgcg_init[] = 170 { 171 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100, 172 }; 173 174 /* 175 * sDMA - System DMA 176 * Starting with CIK, the GPU has new asynchronous 177 * DMA engines. These engines are used for compute 178 * and gfx. There are two DMA engines (SDMA0, SDMA1) 179 * and each one supports 1 ring buffer used for gfx 180 * and 2 queues used for compute. 181 * 182 * The programming model is very similar to the CP 183 * (ring buffer, IBs, etc.), but sDMA has it's own 184 * packet format that is different from the PM4 format 185 * used by the CP. sDMA supports copying data, writing 186 * embedded data, solid fills, and a number of other 187 * things. It also has support for tiling/detiling of 188 * buffers. 189 */ 190 191 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) 192 { 193 switch (adev->asic_type) { 194 case CHIP_FIJI: 195 amdgpu_program_register_sequence(adev, 196 fiji_mgcg_cgcg_init, 197 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); 198 amdgpu_program_register_sequence(adev, 199 golden_settings_fiji_a10, 200 (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); 201 break; 202 case CHIP_TONGA: 203 amdgpu_program_register_sequence(adev, 204 tonga_mgcg_cgcg_init, 205 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); 206 amdgpu_program_register_sequence(adev, 207 golden_settings_tonga_a11, 208 (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); 209 break; 210 case CHIP_POLARIS11: 211 case CHIP_POLARIS12: 212 amdgpu_program_register_sequence(adev, 213 golden_settings_polaris11_a11, 214 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); 215 break; 216 case CHIP_POLARIS10: 217 amdgpu_program_register_sequence(adev, 218 golden_settings_polaris10_a11, 219 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); 220 break; 221 case CHIP_CARRIZO: 222 amdgpu_program_register_sequence(adev, 223 cz_mgcg_cgcg_init, 224 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 225 amdgpu_program_register_sequence(adev, 226 cz_golden_settings_a11, 227 (const u32)ARRAY_SIZE(cz_golden_settings_a11)); 228 break; 229 case CHIP_STONEY: 230 amdgpu_program_register_sequence(adev, 231 stoney_mgcg_cgcg_init, 232 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); 233 amdgpu_program_register_sequence(adev, 234 stoney_golden_settings_a11, 235 (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); 236 break; 237 default: 238 break; 239 } 240 } 241 242 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev) 243 { 244 int i; 245 for (i = 0; i < adev->sdma.num_instances; i++) { 246 release_firmware(adev->sdma.instance[i].fw); 247 adev->sdma.instance[i].fw = NULL; 248 } 249 } 250 251 /** 252 * sdma_v3_0_init_microcode - load ucode images from disk 253 * 254 * @adev: amdgpu_device pointer 255 * 256 * Use the firmware interface to load the ucode images into 257 * the driver (not loaded into hw). 258 * Returns 0 on success, error on failure. 259 */ 260 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) 261 { 262 const char *chip_name; 263 char fw_name[30]; 264 int err = 0, i; 265 struct amdgpu_firmware_info *info = NULL; 266 const struct common_firmware_header *header = NULL; 267 const struct sdma_firmware_header_v1_0 *hdr; 268 269 DRM_DEBUG("\n"); 270 271 switch (adev->asic_type) { 272 case CHIP_TONGA: 273 chip_name = "tonga"; 274 break; 275 case CHIP_FIJI: 276 chip_name = "fiji"; 277 break; 278 case CHIP_POLARIS11: 279 chip_name = "polaris11"; 280 break; 281 case CHIP_POLARIS10: 282 chip_name = "polaris10"; 283 break; 284 case CHIP_POLARIS12: 285 chip_name = "polaris12"; 286 break; 287 case CHIP_CARRIZO: 288 chip_name = "carrizo"; 289 break; 290 case CHIP_STONEY: 291 chip_name = "stoney"; 292 break; 293 default: BUG(); 294 } 295 296 for (i = 0; i < adev->sdma.num_instances; i++) { 297 if (i == 0) 298 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 299 else 300 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 301 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 302 if (err) 303 goto out; 304 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 305 if (err) 306 goto out; 307 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 308 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 309 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 310 if (adev->sdma.instance[i].feature_version >= 20) 311 adev->sdma.instance[i].burst_nop = true; 312 313 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) { 314 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 315 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 316 info->fw = adev->sdma.instance[i].fw; 317 header = (const struct common_firmware_header *)info->fw->data; 318 adev->firmware.fw_size += 319 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 320 } 321 } 322 out: 323 if (err) { 324 pr_err("sdma_v3_0: Failed to load firmware \"%s\"\n", fw_name); 325 for (i = 0; i < adev->sdma.num_instances; i++) { 326 release_firmware(adev->sdma.instance[i].fw); 327 adev->sdma.instance[i].fw = NULL; 328 } 329 } 330 return err; 331 } 332 333 /** 334 * sdma_v3_0_ring_get_rptr - get the current read pointer 335 * 336 * @ring: amdgpu ring pointer 337 * 338 * Get the current rptr from the hardware (VI+). 339 */ 340 static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring) 341 { 342 /* XXX check if swapping is necessary on BE */ 343 return ring->adev->wb.wb[ring->rptr_offs] >> 2; 344 } 345 346 /** 347 * sdma_v3_0_ring_get_wptr - get the current write pointer 348 * 349 * @ring: amdgpu ring pointer 350 * 351 * Get the current wptr from the hardware (VI+). 352 */ 353 static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring) 354 { 355 struct amdgpu_device *adev = ring->adev; 356 u32 wptr; 357 358 if (ring->use_doorbell) { 359 /* XXX check if swapping is necessary on BE */ 360 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; 361 } else { 362 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; 363 364 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2; 365 } 366 367 return wptr; 368 } 369 370 /** 371 * sdma_v3_0_ring_set_wptr - commit the write pointer 372 * 373 * @ring: amdgpu ring pointer 374 * 375 * Write the wptr back to the hardware (VI+). 376 */ 377 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) 378 { 379 struct amdgpu_device *adev = ring->adev; 380 381 if (ring->use_doorbell) { 382 /* XXX check if swapping is necessary on BE */ 383 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr) << 2; 384 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2); 385 } else { 386 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; 387 388 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2); 389 } 390 } 391 392 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 393 { 394 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 395 int i; 396 397 for (i = 0; i < count; i++) 398 if (sdma && sdma->burst_nop && (i == 0)) 399 amdgpu_ring_write(ring, ring->funcs->nop | 400 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 401 else 402 amdgpu_ring_write(ring, ring->funcs->nop); 403 } 404 405 /** 406 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine 407 * 408 * @ring: amdgpu ring pointer 409 * @ib: IB object to schedule 410 * 411 * Schedule an IB in the DMA ring (VI). 412 */ 413 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, 414 struct amdgpu_ib *ib, 415 unsigned vm_id, bool ctx_switch) 416 { 417 u32 vmid = vm_id & 0xf; 418 419 /* IB packet must end on a 8 DW boundary */ 420 sdma_v3_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 421 422 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 423 SDMA_PKT_INDIRECT_HEADER_VMID(vmid)); 424 /* base must be 32 byte aligned */ 425 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 426 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 427 amdgpu_ring_write(ring, ib->length_dw); 428 amdgpu_ring_write(ring, 0); 429 amdgpu_ring_write(ring, 0); 430 431 } 432 433 /** 434 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 435 * 436 * @ring: amdgpu ring pointer 437 * 438 * Emit an hdp flush packet on the requested DMA ring. 439 */ 440 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 441 { 442 u32 ref_and_mask = 0; 443 444 if (ring == &ring->adev->sdma.instance[0].ring) 445 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); 446 else 447 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); 448 449 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 450 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 451 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 452 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 453 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 454 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 455 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 456 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 457 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 458 } 459 460 static void sdma_v3_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 461 { 462 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 463 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 464 amdgpu_ring_write(ring, mmHDP_DEBUG0); 465 amdgpu_ring_write(ring, 1); 466 } 467 468 /** 469 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring 470 * 471 * @ring: amdgpu ring pointer 472 * @fence: amdgpu fence object 473 * 474 * Add a DMA fence packet to the ring to write 475 * the fence seq number and DMA trap packet to generate 476 * an interrupt if needed (VI). 477 */ 478 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 479 unsigned flags) 480 { 481 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 482 /* write the fence */ 483 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 484 amdgpu_ring_write(ring, lower_32_bits(addr)); 485 amdgpu_ring_write(ring, upper_32_bits(addr)); 486 amdgpu_ring_write(ring, lower_32_bits(seq)); 487 488 /* optionally write high bits as well */ 489 if (write64bit) { 490 addr += 4; 491 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 492 amdgpu_ring_write(ring, lower_32_bits(addr)); 493 amdgpu_ring_write(ring, upper_32_bits(addr)); 494 amdgpu_ring_write(ring, upper_32_bits(seq)); 495 } 496 497 /* generate an interrupt */ 498 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 499 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 500 } 501 502 /** 503 * sdma_v3_0_gfx_stop - stop the gfx async dma engines 504 * 505 * @adev: amdgpu_device pointer 506 * 507 * Stop the gfx async dma ring buffers (VI). 508 */ 509 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev) 510 { 511 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 512 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 513 u32 rb_cntl, ib_cntl; 514 int i; 515 516 if ((adev->mman.buffer_funcs_ring == sdma0) || 517 (adev->mman.buffer_funcs_ring == sdma1)) 518 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); 519 520 for (i = 0; i < adev->sdma.num_instances; i++) { 521 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 522 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 523 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 524 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 525 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 526 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 527 } 528 sdma0->ready = false; 529 sdma1->ready = false; 530 } 531 532 /** 533 * sdma_v3_0_rlc_stop - stop the compute async dma engines 534 * 535 * @adev: amdgpu_device pointer 536 * 537 * Stop the compute async dma queues (VI). 538 */ 539 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev) 540 { 541 /* XXX todo */ 542 } 543 544 /** 545 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch 546 * 547 * @adev: amdgpu_device pointer 548 * @enable: enable/disable the DMA MEs context switch. 549 * 550 * Halt or unhalt the async dma engines context switch (VI). 551 */ 552 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 553 { 554 u32 f32_cntl; 555 int i; 556 557 for (i = 0; i < adev->sdma.num_instances; i++) { 558 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); 559 if (enable) 560 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 561 AUTO_CTXSW_ENABLE, 1); 562 else 563 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 564 AUTO_CTXSW_ENABLE, 0); 565 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); 566 } 567 } 568 569 /** 570 * sdma_v3_0_enable - stop the async dma engines 571 * 572 * @adev: amdgpu_device pointer 573 * @enable: enable/disable the DMA MEs. 574 * 575 * Halt or unhalt the async dma engines (VI). 576 */ 577 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable) 578 { 579 u32 f32_cntl; 580 int i; 581 582 if (!enable) { 583 sdma_v3_0_gfx_stop(adev); 584 sdma_v3_0_rlc_stop(adev); 585 } 586 587 for (i = 0; i < adev->sdma.num_instances; i++) { 588 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 589 if (enable) 590 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); 591 else 592 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 593 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); 594 } 595 } 596 597 /** 598 * sdma_v3_0_gfx_resume - setup and start the async dma engines 599 * 600 * @adev: amdgpu_device pointer 601 * 602 * Set up the gfx DMA ring buffers and enable them (VI). 603 * Returns 0 for success, error for failure. 604 */ 605 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) 606 { 607 struct amdgpu_ring *ring; 608 u32 rb_cntl, ib_cntl; 609 u32 rb_bufsz; 610 u32 wb_offset; 611 u32 doorbell; 612 int i, j, r; 613 614 for (i = 0; i < adev->sdma.num_instances; i++) { 615 ring = &adev->sdma.instance[i].ring; 616 amdgpu_ring_clear_ring(ring); 617 wb_offset = (ring->rptr_offs * 4); 618 619 mutex_lock(&adev->srbm_mutex); 620 for (j = 0; j < 16; j++) { 621 vi_srbm_select(adev, 0, 0, 0, j); 622 /* SDMA GFX */ 623 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 624 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 625 } 626 vi_srbm_select(adev, 0, 0, 0, 0); 627 mutex_unlock(&adev->srbm_mutex); 628 629 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], 630 adev->gfx.config.gb_addr_config & 0x70); 631 632 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 633 634 /* Set ring buffer size in dwords */ 635 rb_bufsz = order_base_2(ring->ring_size / 4); 636 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 637 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 638 #ifdef __BIG_ENDIAN 639 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 640 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 641 RPTR_WRITEBACK_SWAP_ENABLE, 1); 642 #endif 643 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 644 645 /* Initialize the ring buffer's read and write pointers */ 646 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 647 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 648 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); 649 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); 650 651 /* set the wb address whether it's enabled or not */ 652 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 653 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 654 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 655 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 656 657 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 658 659 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 660 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 661 662 ring->wptr = 0; 663 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); 664 665 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); 666 667 if (ring->use_doorbell) { 668 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, 669 OFFSET, ring->doorbell_index); 670 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 671 } else { 672 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 673 } 674 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell); 675 676 /* enable DMA RB */ 677 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 678 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 679 680 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 681 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 682 #ifdef __BIG_ENDIAN 683 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 684 #endif 685 /* enable DMA IBs */ 686 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 687 688 ring->ready = true; 689 } 690 691 /* unhalt the MEs */ 692 sdma_v3_0_enable(adev, true); 693 /* enable sdma ring preemption */ 694 sdma_v3_0_ctx_switch_enable(adev, true); 695 696 for (i = 0; i < adev->sdma.num_instances; i++) { 697 ring = &adev->sdma.instance[i].ring; 698 r = amdgpu_ring_test_ring(ring); 699 if (r) { 700 ring->ready = false; 701 return r; 702 } 703 704 if (adev->mman.buffer_funcs_ring == ring) 705 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); 706 } 707 708 return 0; 709 } 710 711 /** 712 * sdma_v3_0_rlc_resume - setup and start the async dma engines 713 * 714 * @adev: amdgpu_device pointer 715 * 716 * Set up the compute DMA queues and enable them (VI). 717 * Returns 0 for success, error for failure. 718 */ 719 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev) 720 { 721 /* XXX todo */ 722 return 0; 723 } 724 725 /** 726 * sdma_v3_0_load_microcode - load the sDMA ME ucode 727 * 728 * @adev: amdgpu_device pointer 729 * 730 * Loads the sDMA0/1 ucode. 731 * Returns 0 for success, -EINVAL if the ucode is not available. 732 */ 733 static int sdma_v3_0_load_microcode(struct amdgpu_device *adev) 734 { 735 const struct sdma_firmware_header_v1_0 *hdr; 736 const __le32 *fw_data; 737 u32 fw_size; 738 int i, j; 739 740 /* halt the MEs */ 741 sdma_v3_0_enable(adev, false); 742 743 for (i = 0; i < adev->sdma.num_instances; i++) { 744 if (!adev->sdma.instance[i].fw) 745 return -EINVAL; 746 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 747 amdgpu_ucode_print_sdma_hdr(&hdr->header); 748 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 749 fw_data = (const __le32 *) 750 (adev->sdma.instance[i].fw->data + 751 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 752 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); 753 for (j = 0; j < fw_size; j++) 754 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); 755 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); 756 } 757 758 return 0; 759 } 760 761 /** 762 * sdma_v3_0_start - setup and start the async dma engines 763 * 764 * @adev: amdgpu_device pointer 765 * 766 * Set up the DMA engines and enable them (VI). 767 * Returns 0 for success, error for failure. 768 */ 769 static int sdma_v3_0_start(struct amdgpu_device *adev) 770 { 771 int r, i; 772 773 if (!adev->pp_enabled) { 774 if (adev->firmware.load_type != AMDGPU_FW_LOAD_SMU) { 775 r = sdma_v3_0_load_microcode(adev); 776 if (r) 777 return r; 778 } else { 779 for (i = 0; i < adev->sdma.num_instances; i++) { 780 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 781 (i == 0) ? 782 AMDGPU_UCODE_ID_SDMA0 : 783 AMDGPU_UCODE_ID_SDMA1); 784 if (r) 785 return -EINVAL; 786 } 787 } 788 } 789 790 /* disable sdma engine before programing it */ 791 sdma_v3_0_ctx_switch_enable(adev, false); 792 sdma_v3_0_enable(adev, false); 793 794 /* start the gfx rings and rlc compute queues */ 795 r = sdma_v3_0_gfx_resume(adev); 796 if (r) 797 return r; 798 r = sdma_v3_0_rlc_resume(adev); 799 if (r) 800 return r; 801 802 return 0; 803 } 804 805 /** 806 * sdma_v3_0_ring_test_ring - simple async dma engine test 807 * 808 * @ring: amdgpu_ring structure holding ring information 809 * 810 * Test the DMA engine by writing using it to write an 811 * value to memory. (VI). 812 * Returns 0 for success, error for failure. 813 */ 814 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) 815 { 816 struct amdgpu_device *adev = ring->adev; 817 unsigned i; 818 unsigned index; 819 int r; 820 u32 tmp; 821 u64 gpu_addr; 822 823 r = amdgpu_wb_get(adev, &index); 824 if (r) { 825 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 826 return r; 827 } 828 829 gpu_addr = adev->wb.gpu_addr + (index * 4); 830 tmp = 0xCAFEDEAD; 831 adev->wb.wb[index] = cpu_to_le32(tmp); 832 833 r = amdgpu_ring_alloc(ring, 5); 834 if (r) { 835 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 836 amdgpu_wb_free(adev, index); 837 return r; 838 } 839 840 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 841 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 842 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 843 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 844 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 845 amdgpu_ring_write(ring, 0xDEADBEEF); 846 amdgpu_ring_commit(ring); 847 848 for (i = 0; i < adev->usec_timeout; i++) { 849 tmp = le32_to_cpu(adev->wb.wb[index]); 850 if (tmp == 0xDEADBEEF) 851 break; 852 DRM_UDELAY(1); 853 } 854 855 if (i < adev->usec_timeout) { 856 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 857 } else { 858 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 859 ring->idx, tmp); 860 r = -EINVAL; 861 } 862 amdgpu_wb_free(adev, index); 863 864 return r; 865 } 866 867 /** 868 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine 869 * 870 * @ring: amdgpu_ring structure holding ring information 871 * 872 * Test a simple IB in the DMA ring (VI). 873 * Returns 0 on success, error on failure. 874 */ 875 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 876 { 877 struct amdgpu_device *adev = ring->adev; 878 struct amdgpu_ib ib; 879 struct dma_fence *f = NULL; 880 unsigned index; 881 u32 tmp = 0; 882 u64 gpu_addr; 883 long r; 884 885 r = amdgpu_wb_get(adev, &index); 886 if (r) { 887 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 888 return r; 889 } 890 891 gpu_addr = adev->wb.gpu_addr + (index * 4); 892 tmp = 0xCAFEDEAD; 893 adev->wb.wb[index] = cpu_to_le32(tmp); 894 memset(&ib, 0, sizeof(ib)); 895 r = amdgpu_ib_get(adev, NULL, 256, &ib); 896 if (r) { 897 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 898 goto err0; 899 } 900 901 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 902 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 903 ib.ptr[1] = lower_32_bits(gpu_addr); 904 ib.ptr[2] = upper_32_bits(gpu_addr); 905 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); 906 ib.ptr[4] = 0xDEADBEEF; 907 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 908 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 909 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 910 ib.length_dw = 8; 911 912 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 913 if (r) 914 goto err1; 915 916 r = dma_fence_wait_timeout(f, false, timeout); 917 if (r == 0) { 918 DRM_ERROR("amdgpu: IB test timed out\n"); 919 r = -ETIMEDOUT; 920 goto err1; 921 } else if (r < 0) { 922 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 923 goto err1; 924 } 925 tmp = le32_to_cpu(adev->wb.wb[index]); 926 if (tmp == 0xDEADBEEF) { 927 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 928 r = 0; 929 } else { 930 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 931 r = -EINVAL; 932 } 933 err1: 934 amdgpu_ib_free(adev, &ib, NULL); 935 dma_fence_put(f); 936 err0: 937 amdgpu_wb_free(adev, index); 938 return r; 939 } 940 941 /** 942 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART 943 * 944 * @ib: indirect buffer to fill with commands 945 * @pe: addr of the page entry 946 * @src: src addr to copy from 947 * @count: number of page entries to update 948 * 949 * Update PTEs by copying them from the GART using sDMA (CIK). 950 */ 951 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib, 952 uint64_t pe, uint64_t src, 953 unsigned count) 954 { 955 unsigned bytes = count * 8; 956 957 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 958 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 959 ib->ptr[ib->length_dw++] = bytes; 960 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 961 ib->ptr[ib->length_dw++] = lower_32_bits(src); 962 ib->ptr[ib->length_dw++] = upper_32_bits(src); 963 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 964 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 965 } 966 967 /** 968 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually 969 * 970 * @ib: indirect buffer to fill with commands 971 * @pe: addr of the page entry 972 * @value: dst addr to write into pe 973 * @count: number of page entries to update 974 * @incr: increase next addr by incr bytes 975 * 976 * Update PTEs by writing them manually using sDMA (CIK). 977 */ 978 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 979 uint64_t value, unsigned count, 980 uint32_t incr) 981 { 982 unsigned ndw = count * 2; 983 984 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 985 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 986 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 987 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 988 ib->ptr[ib->length_dw++] = ndw; 989 for (; ndw > 0; ndw -= 2) { 990 ib->ptr[ib->length_dw++] = lower_32_bits(value); 991 ib->ptr[ib->length_dw++] = upper_32_bits(value); 992 value += incr; 993 } 994 } 995 996 /** 997 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA 998 * 999 * @ib: indirect buffer to fill with commands 1000 * @pe: addr of the page entry 1001 * @addr: dst addr to write into pe 1002 * @count: number of page entries to update 1003 * @incr: increase next addr by incr bytes 1004 * @flags: access flags 1005 * 1006 * Update the page tables using sDMA (CIK). 1007 */ 1008 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, 1009 uint64_t addr, unsigned count, 1010 uint32_t incr, uint64_t flags) 1011 { 1012 /* for physically contiguous pages (vram) */ 1013 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); 1014 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1015 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1016 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1017 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1018 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1019 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1020 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1021 ib->ptr[ib->length_dw++] = 0; 1022 ib->ptr[ib->length_dw++] = count; /* number of entries */ 1023 } 1024 1025 /** 1026 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw 1027 * 1028 * @ib: indirect buffer to fill with padding 1029 * 1030 */ 1031 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1032 { 1033 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 1034 u32 pad_count; 1035 int i; 1036 1037 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 1038 for (i = 0; i < pad_count; i++) 1039 if (sdma && sdma->burst_nop && (i == 0)) 1040 ib->ptr[ib->length_dw++] = 1041 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1042 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1043 else 1044 ib->ptr[ib->length_dw++] = 1045 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1046 } 1047 1048 /** 1049 * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline 1050 * 1051 * @ring: amdgpu_ring pointer 1052 * 1053 * Make sure all previous operations are completed (CIK). 1054 */ 1055 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1056 { 1057 uint32_t seq = ring->fence_drv.sync_seq; 1058 uint64_t addr = ring->fence_drv.gpu_addr; 1059 1060 /* wait for idle */ 1061 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1062 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1063 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1064 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1065 amdgpu_ring_write(ring, addr & 0xfffffffc); 1066 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1067 amdgpu_ring_write(ring, seq); /* reference */ 1068 amdgpu_ring_write(ring, 0xfffffff); /* mask */ 1069 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1070 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1071 } 1072 1073 /** 1074 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA 1075 * 1076 * @ring: amdgpu_ring pointer 1077 * @vm: amdgpu_vm pointer 1078 * 1079 * Update the page table base and flush the VM TLB 1080 * using sDMA (VI). 1081 */ 1082 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1083 unsigned vm_id, uint64_t pd_addr) 1084 { 1085 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1086 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1087 if (vm_id < 8) { 1088 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); 1089 } else { 1090 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); 1091 } 1092 amdgpu_ring_write(ring, pd_addr >> 12); 1093 1094 /* flush TLB */ 1095 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1096 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1097 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 1098 amdgpu_ring_write(ring, 1 << vm_id); 1099 1100 /* wait for flush */ 1101 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1102 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1103 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ 1104 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 1105 amdgpu_ring_write(ring, 0); 1106 amdgpu_ring_write(ring, 0); /* reference */ 1107 amdgpu_ring_write(ring, 0); /* mask */ 1108 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1109 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 1110 } 1111 1112 static int sdma_v3_0_early_init(void *handle) 1113 { 1114 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1115 1116 switch (adev->asic_type) { 1117 case CHIP_STONEY: 1118 adev->sdma.num_instances = 1; 1119 break; 1120 default: 1121 adev->sdma.num_instances = SDMA_MAX_INSTANCE; 1122 break; 1123 } 1124 1125 sdma_v3_0_set_ring_funcs(adev); 1126 sdma_v3_0_set_buffer_funcs(adev); 1127 sdma_v3_0_set_vm_pte_funcs(adev); 1128 sdma_v3_0_set_irq_funcs(adev); 1129 1130 return 0; 1131 } 1132 1133 static int sdma_v3_0_sw_init(void *handle) 1134 { 1135 struct amdgpu_ring *ring; 1136 int r, i; 1137 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1138 1139 /* SDMA trap event */ 1140 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224, 1141 &adev->sdma.trap_irq); 1142 if (r) 1143 return r; 1144 1145 /* SDMA Privileged inst */ 1146 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241, 1147 &adev->sdma.illegal_inst_irq); 1148 if (r) 1149 return r; 1150 1151 /* SDMA Privileged inst */ 1152 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 247, 1153 &adev->sdma.illegal_inst_irq); 1154 if (r) 1155 return r; 1156 1157 r = sdma_v3_0_init_microcode(adev); 1158 if (r) { 1159 DRM_ERROR("Failed to load sdma firmware!\n"); 1160 return r; 1161 } 1162 1163 for (i = 0; i < adev->sdma.num_instances; i++) { 1164 ring = &adev->sdma.instance[i].ring; 1165 ring->ring_obj = NULL; 1166 ring->use_doorbell = true; 1167 ring->doorbell_index = (i == 0) ? 1168 AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1; 1169 1170 sprintf(ring->name, "sdma%d", i); 1171 r = amdgpu_ring_init(adev, ring, 1024, 1172 &adev->sdma.trap_irq, 1173 (i == 0) ? 1174 AMDGPU_SDMA_IRQ_TRAP0 : 1175 AMDGPU_SDMA_IRQ_TRAP1); 1176 if (r) 1177 return r; 1178 } 1179 1180 return r; 1181 } 1182 1183 static int sdma_v3_0_sw_fini(void *handle) 1184 { 1185 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1186 int i; 1187 1188 for (i = 0; i < adev->sdma.num_instances; i++) 1189 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1190 1191 sdma_v3_0_free_microcode(adev); 1192 return 0; 1193 } 1194 1195 static int sdma_v3_0_hw_init(void *handle) 1196 { 1197 int r; 1198 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1199 1200 sdma_v3_0_init_golden_registers(adev); 1201 1202 r = sdma_v3_0_start(adev); 1203 if (r) 1204 return r; 1205 1206 return r; 1207 } 1208 1209 static int sdma_v3_0_hw_fini(void *handle) 1210 { 1211 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1212 1213 sdma_v3_0_ctx_switch_enable(adev, false); 1214 sdma_v3_0_enable(adev, false); 1215 1216 return 0; 1217 } 1218 1219 static int sdma_v3_0_suspend(void *handle) 1220 { 1221 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1222 1223 return sdma_v3_0_hw_fini(adev); 1224 } 1225 1226 static int sdma_v3_0_resume(void *handle) 1227 { 1228 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1229 1230 return sdma_v3_0_hw_init(adev); 1231 } 1232 1233 static bool sdma_v3_0_is_idle(void *handle) 1234 { 1235 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1236 u32 tmp = RREG32(mmSRBM_STATUS2); 1237 1238 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1239 SRBM_STATUS2__SDMA1_BUSY_MASK)) 1240 return false; 1241 1242 return true; 1243 } 1244 1245 static int sdma_v3_0_wait_for_idle(void *handle) 1246 { 1247 unsigned i; 1248 u32 tmp; 1249 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1250 1251 for (i = 0; i < adev->usec_timeout; i++) { 1252 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1253 SRBM_STATUS2__SDMA1_BUSY_MASK); 1254 1255 if (!tmp) 1256 return 0; 1257 udelay(1); 1258 } 1259 return -ETIMEDOUT; 1260 } 1261 1262 static bool sdma_v3_0_check_soft_reset(void *handle) 1263 { 1264 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1265 u32 srbm_soft_reset = 0; 1266 u32 tmp = RREG32(mmSRBM_STATUS2); 1267 1268 if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) || 1269 (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) { 1270 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1271 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1272 } 1273 1274 if (srbm_soft_reset) { 1275 adev->sdma.srbm_soft_reset = srbm_soft_reset; 1276 return true; 1277 } else { 1278 adev->sdma.srbm_soft_reset = 0; 1279 return false; 1280 } 1281 } 1282 1283 static int sdma_v3_0_pre_soft_reset(void *handle) 1284 { 1285 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1286 u32 srbm_soft_reset = 0; 1287 1288 if (!adev->sdma.srbm_soft_reset) 1289 return 0; 1290 1291 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1292 1293 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || 1294 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { 1295 sdma_v3_0_ctx_switch_enable(adev, false); 1296 sdma_v3_0_enable(adev, false); 1297 } 1298 1299 return 0; 1300 } 1301 1302 static int sdma_v3_0_post_soft_reset(void *handle) 1303 { 1304 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1305 u32 srbm_soft_reset = 0; 1306 1307 if (!adev->sdma.srbm_soft_reset) 1308 return 0; 1309 1310 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1311 1312 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || 1313 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { 1314 sdma_v3_0_gfx_resume(adev); 1315 sdma_v3_0_rlc_resume(adev); 1316 } 1317 1318 return 0; 1319 } 1320 1321 static int sdma_v3_0_soft_reset(void *handle) 1322 { 1323 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1324 u32 srbm_soft_reset = 0; 1325 u32 tmp; 1326 1327 if (!adev->sdma.srbm_soft_reset) 1328 return 0; 1329 1330 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1331 1332 if (srbm_soft_reset) { 1333 tmp = RREG32(mmSRBM_SOFT_RESET); 1334 tmp |= srbm_soft_reset; 1335 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1336 WREG32(mmSRBM_SOFT_RESET, tmp); 1337 tmp = RREG32(mmSRBM_SOFT_RESET); 1338 1339 udelay(50); 1340 1341 tmp &= ~srbm_soft_reset; 1342 WREG32(mmSRBM_SOFT_RESET, tmp); 1343 tmp = RREG32(mmSRBM_SOFT_RESET); 1344 1345 /* Wait a little for things to settle down */ 1346 udelay(50); 1347 } 1348 1349 return 0; 1350 } 1351 1352 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev, 1353 struct amdgpu_irq_src *source, 1354 unsigned type, 1355 enum amdgpu_interrupt_state state) 1356 { 1357 u32 sdma_cntl; 1358 1359 switch (type) { 1360 case AMDGPU_SDMA_IRQ_TRAP0: 1361 switch (state) { 1362 case AMDGPU_IRQ_STATE_DISABLE: 1363 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1364 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1365 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1366 break; 1367 case AMDGPU_IRQ_STATE_ENABLE: 1368 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1369 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1370 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1371 break; 1372 default: 1373 break; 1374 } 1375 break; 1376 case AMDGPU_SDMA_IRQ_TRAP1: 1377 switch (state) { 1378 case AMDGPU_IRQ_STATE_DISABLE: 1379 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1380 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1381 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1382 break; 1383 case AMDGPU_IRQ_STATE_ENABLE: 1384 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1385 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1386 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1387 break; 1388 default: 1389 break; 1390 } 1391 break; 1392 default: 1393 break; 1394 } 1395 return 0; 1396 } 1397 1398 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev, 1399 struct amdgpu_irq_src *source, 1400 struct amdgpu_iv_entry *entry) 1401 { 1402 u8 instance_id, queue_id; 1403 1404 instance_id = (entry->ring_id & 0x3) >> 0; 1405 queue_id = (entry->ring_id & 0xc) >> 2; 1406 DRM_DEBUG("IH: SDMA trap\n"); 1407 switch (instance_id) { 1408 case 0: 1409 switch (queue_id) { 1410 case 0: 1411 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1412 break; 1413 case 1: 1414 /* XXX compute */ 1415 break; 1416 case 2: 1417 /* XXX compute */ 1418 break; 1419 } 1420 break; 1421 case 1: 1422 switch (queue_id) { 1423 case 0: 1424 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1425 break; 1426 case 1: 1427 /* XXX compute */ 1428 break; 1429 case 2: 1430 /* XXX compute */ 1431 break; 1432 } 1433 break; 1434 } 1435 return 0; 1436 } 1437 1438 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1439 struct amdgpu_irq_src *source, 1440 struct amdgpu_iv_entry *entry) 1441 { 1442 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1443 schedule_work(&adev->reset_work); 1444 return 0; 1445 } 1446 1447 static void sdma_v3_0_update_sdma_medium_grain_clock_gating( 1448 struct amdgpu_device *adev, 1449 bool enable) 1450 { 1451 uint32_t temp, data; 1452 int i; 1453 1454 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1455 for (i = 0; i < adev->sdma.num_instances; i++) { 1456 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); 1457 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1458 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1459 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1460 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1461 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1462 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1463 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1464 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1465 if (data != temp) 1466 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); 1467 } 1468 } else { 1469 for (i = 0; i < adev->sdma.num_instances; i++) { 1470 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); 1471 data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1472 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1473 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1474 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1475 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1476 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1477 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1478 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK; 1479 1480 if (data != temp) 1481 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); 1482 } 1483 } 1484 } 1485 1486 static void sdma_v3_0_update_sdma_medium_grain_light_sleep( 1487 struct amdgpu_device *adev, 1488 bool enable) 1489 { 1490 uint32_t temp, data; 1491 int i; 1492 1493 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1494 for (i = 0; i < adev->sdma.num_instances; i++) { 1495 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1496 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1497 1498 if (temp != data) 1499 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1500 } 1501 } else { 1502 for (i = 0; i < adev->sdma.num_instances; i++) { 1503 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1504 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1505 1506 if (temp != data) 1507 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1508 } 1509 } 1510 } 1511 1512 static int sdma_v3_0_set_clockgating_state(void *handle, 1513 enum amd_clockgating_state state) 1514 { 1515 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1516 1517 if (amdgpu_sriov_vf(adev)) 1518 return 0; 1519 1520 switch (adev->asic_type) { 1521 case CHIP_FIJI: 1522 case CHIP_CARRIZO: 1523 case CHIP_STONEY: 1524 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev, 1525 state == AMD_CG_STATE_GATE); 1526 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev, 1527 state == AMD_CG_STATE_GATE); 1528 break; 1529 default: 1530 break; 1531 } 1532 return 0; 1533 } 1534 1535 static int sdma_v3_0_set_powergating_state(void *handle, 1536 enum amd_powergating_state state) 1537 { 1538 return 0; 1539 } 1540 1541 static void sdma_v3_0_get_clockgating_state(void *handle, u32 *flags) 1542 { 1543 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1544 int data; 1545 1546 if (amdgpu_sriov_vf(adev)) 1547 *flags = 0; 1548 1549 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1550 data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]); 1551 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK)) 1552 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1553 1554 /* AMD_CG_SUPPORT_SDMA_LS */ 1555 data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]); 1556 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1557 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1558 } 1559 1560 static const struct amd_ip_funcs sdma_v3_0_ip_funcs = { 1561 .name = "sdma_v3_0", 1562 .early_init = sdma_v3_0_early_init, 1563 .late_init = NULL, 1564 .sw_init = sdma_v3_0_sw_init, 1565 .sw_fini = sdma_v3_0_sw_fini, 1566 .hw_init = sdma_v3_0_hw_init, 1567 .hw_fini = sdma_v3_0_hw_fini, 1568 .suspend = sdma_v3_0_suspend, 1569 .resume = sdma_v3_0_resume, 1570 .is_idle = sdma_v3_0_is_idle, 1571 .wait_for_idle = sdma_v3_0_wait_for_idle, 1572 .check_soft_reset = sdma_v3_0_check_soft_reset, 1573 .pre_soft_reset = sdma_v3_0_pre_soft_reset, 1574 .post_soft_reset = sdma_v3_0_post_soft_reset, 1575 .soft_reset = sdma_v3_0_soft_reset, 1576 .set_clockgating_state = sdma_v3_0_set_clockgating_state, 1577 .set_powergating_state = sdma_v3_0_set_powergating_state, 1578 .get_clockgating_state = sdma_v3_0_get_clockgating_state, 1579 }; 1580 1581 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { 1582 .type = AMDGPU_RING_TYPE_SDMA, 1583 .align_mask = 0xf, 1584 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1585 .support_64bit_ptrs = false, 1586 .get_rptr = sdma_v3_0_ring_get_rptr, 1587 .get_wptr = sdma_v3_0_ring_get_wptr, 1588 .set_wptr = sdma_v3_0_ring_set_wptr, 1589 .emit_frame_size = 1590 6 + /* sdma_v3_0_ring_emit_hdp_flush */ 1591 3 + /* sdma_v3_0_ring_emit_hdp_invalidate */ 1592 6 + /* sdma_v3_0_ring_emit_pipeline_sync */ 1593 12 + /* sdma_v3_0_ring_emit_vm_flush */ 1594 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */ 1595 .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */ 1596 .emit_ib = sdma_v3_0_ring_emit_ib, 1597 .emit_fence = sdma_v3_0_ring_emit_fence, 1598 .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync, 1599 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, 1600 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, 1601 .emit_hdp_invalidate = sdma_v3_0_ring_emit_hdp_invalidate, 1602 .test_ring = sdma_v3_0_ring_test_ring, 1603 .test_ib = sdma_v3_0_ring_test_ib, 1604 .insert_nop = sdma_v3_0_ring_insert_nop, 1605 .pad_ib = sdma_v3_0_ring_pad_ib, 1606 }; 1607 1608 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev) 1609 { 1610 int i; 1611 1612 for (i = 0; i < adev->sdma.num_instances; i++) 1613 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs; 1614 } 1615 1616 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = { 1617 .set = sdma_v3_0_set_trap_irq_state, 1618 .process = sdma_v3_0_process_trap_irq, 1619 }; 1620 1621 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = { 1622 .process = sdma_v3_0_process_illegal_inst_irq, 1623 }; 1624 1625 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev) 1626 { 1627 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1628 adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs; 1629 adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs; 1630 } 1631 1632 /** 1633 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine 1634 * 1635 * @ring: amdgpu_ring structure holding ring information 1636 * @src_offset: src GPU address 1637 * @dst_offset: dst GPU address 1638 * @byte_count: number of bytes to xfer 1639 * 1640 * Copy GPU buffers using the DMA engine (VI). 1641 * Used by the amdgpu ttm implementation to move pages if 1642 * registered as the asic copy callback. 1643 */ 1644 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib, 1645 uint64_t src_offset, 1646 uint64_t dst_offset, 1647 uint32_t byte_count) 1648 { 1649 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1650 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1651 ib->ptr[ib->length_dw++] = byte_count; 1652 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1653 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1654 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1655 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1656 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1657 } 1658 1659 /** 1660 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine 1661 * 1662 * @ring: amdgpu_ring structure holding ring information 1663 * @src_data: value to write to buffer 1664 * @dst_offset: dst GPU address 1665 * @byte_count: number of bytes to xfer 1666 * 1667 * Fill GPU buffers using the DMA engine (VI). 1668 */ 1669 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib, 1670 uint32_t src_data, 1671 uint64_t dst_offset, 1672 uint32_t byte_count) 1673 { 1674 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1675 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1676 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1677 ib->ptr[ib->length_dw++] = src_data; 1678 ib->ptr[ib->length_dw++] = byte_count; 1679 } 1680 1681 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = { 1682 .copy_max_bytes = 0x1fffff, 1683 .copy_num_dw = 7, 1684 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer, 1685 1686 .fill_max_bytes = 0x1fffff, 1687 .fill_num_dw = 5, 1688 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer, 1689 }; 1690 1691 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) 1692 { 1693 if (adev->mman.buffer_funcs == NULL) { 1694 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs; 1695 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1696 } 1697 } 1698 1699 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { 1700 .copy_pte = sdma_v3_0_vm_copy_pte, 1701 .write_pte = sdma_v3_0_vm_write_pte, 1702 .set_pte_pde = sdma_v3_0_vm_set_pte_pde, 1703 }; 1704 1705 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1706 { 1707 unsigned i; 1708 1709 if (adev->vm_manager.vm_pte_funcs == NULL) { 1710 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; 1711 for (i = 0; i < adev->sdma.num_instances; i++) 1712 adev->vm_manager.vm_pte_rings[i] = 1713 &adev->sdma.instance[i].ring; 1714 1715 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; 1716 } 1717 } 1718 1719 const struct amdgpu_ip_block_version sdma_v3_0_ip_block = 1720 { 1721 .type = AMD_IP_BLOCK_TYPE_SDMA, 1722 .major = 3, 1723 .minor = 0, 1724 .rev = 0, 1725 .funcs = &sdma_v3_0_ip_funcs, 1726 }; 1727 1728 const struct amdgpu_ip_block_version sdma_v3_1_ip_block = 1729 { 1730 .type = AMD_IP_BLOCK_TYPE_SDMA, 1731 .major = 3, 1732 .minor = 1, 1733 .rev = 0, 1734 .funcs = &sdma_v3_0_ip_funcs, 1735 }; 1736