1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 #include "vi.h" 30 #include "vid.h" 31 32 #include "oss/oss_3_0_d.h" 33 #include "oss/oss_3_0_sh_mask.h" 34 35 #include "gmc/gmc_8_1_d.h" 36 #include "gmc/gmc_8_1_sh_mask.h" 37 38 #include "gca/gfx_8_0_d.h" 39 #include "gca/gfx_8_0_enum.h" 40 #include "gca/gfx_8_0_sh_mask.h" 41 42 #include "bif/bif_5_0_d.h" 43 #include "bif/bif_5_0_sh_mask.h" 44 45 #include "tonga_sdma_pkt_open.h" 46 47 #include "ivsrcid/ivsrcid_vislands30.h" 48 49 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev); 50 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); 51 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev); 52 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); 53 54 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); 55 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin"); 56 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin"); 57 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); 58 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); 59 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); 60 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin"); 61 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin"); 62 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin"); 63 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin"); 65 MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin"); 66 MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin"); 67 MODULE_FIRMWARE("amdgpu/vegam_sdma.bin"); 68 MODULE_FIRMWARE("amdgpu/vegam_sdma1.bin"); 69 70 71 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 72 { 73 SDMA0_REGISTER_OFFSET, 74 SDMA1_REGISTER_OFFSET 75 }; 76 77 static const u32 golden_settings_tonga_a11[] = 78 { 79 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 80 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 81 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 82 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 83 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 84 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 85 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 86 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 87 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 88 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 89 }; 90 91 static const u32 tonga_mgcg_cgcg_init[] = 92 { 93 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 94 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 95 }; 96 97 static const u32 golden_settings_fiji_a10[] = 98 { 99 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 100 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 101 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 102 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 103 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 104 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 105 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 106 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 107 }; 108 109 static const u32 fiji_mgcg_cgcg_init[] = 110 { 111 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 112 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 113 }; 114 115 static const u32 golden_settings_polaris11_a11[] = 116 { 117 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 118 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 119 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 120 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 121 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 122 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 123 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 124 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 125 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 126 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 127 }; 128 129 static const u32 golden_settings_polaris10_a11[] = 130 { 131 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 132 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 133 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 134 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 135 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 136 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 137 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 138 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 139 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 140 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 141 }; 142 143 static const u32 cz_golden_settings_a11[] = 144 { 145 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 146 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 147 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 148 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 149 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 150 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 151 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 152 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 153 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100, 154 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800, 155 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100, 156 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100, 157 }; 158 159 static const u32 cz_mgcg_cgcg_init[] = 160 { 161 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 162 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 163 }; 164 165 static const u32 stoney_golden_settings_a11[] = 166 { 167 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 168 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 169 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 170 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 171 }; 172 173 static const u32 stoney_mgcg_cgcg_init[] = 174 { 175 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100, 176 }; 177 178 /* 179 * sDMA - System DMA 180 * Starting with CIK, the GPU has new asynchronous 181 * DMA engines. These engines are used for compute 182 * and gfx. There are two DMA engines (SDMA0, SDMA1) 183 * and each one supports 1 ring buffer used for gfx 184 * and 2 queues used for compute. 185 * 186 * The programming model is very similar to the CP 187 * (ring buffer, IBs, etc.), but sDMA has it's own 188 * packet format that is different from the PM4 format 189 * used by the CP. sDMA supports copying data, writing 190 * embedded data, solid fills, and a number of other 191 * things. It also has support for tiling/detiling of 192 * buffers. 193 */ 194 195 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) 196 { 197 switch (adev->asic_type) { 198 case CHIP_FIJI: 199 amdgpu_device_program_register_sequence(adev, 200 fiji_mgcg_cgcg_init, 201 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 202 amdgpu_device_program_register_sequence(adev, 203 golden_settings_fiji_a10, 204 ARRAY_SIZE(golden_settings_fiji_a10)); 205 break; 206 case CHIP_TONGA: 207 amdgpu_device_program_register_sequence(adev, 208 tonga_mgcg_cgcg_init, 209 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 210 amdgpu_device_program_register_sequence(adev, 211 golden_settings_tonga_a11, 212 ARRAY_SIZE(golden_settings_tonga_a11)); 213 break; 214 case CHIP_POLARIS11: 215 case CHIP_POLARIS12: 216 case CHIP_VEGAM: 217 amdgpu_device_program_register_sequence(adev, 218 golden_settings_polaris11_a11, 219 ARRAY_SIZE(golden_settings_polaris11_a11)); 220 break; 221 case CHIP_POLARIS10: 222 amdgpu_device_program_register_sequence(adev, 223 golden_settings_polaris10_a11, 224 ARRAY_SIZE(golden_settings_polaris10_a11)); 225 break; 226 case CHIP_CARRIZO: 227 amdgpu_device_program_register_sequence(adev, 228 cz_mgcg_cgcg_init, 229 ARRAY_SIZE(cz_mgcg_cgcg_init)); 230 amdgpu_device_program_register_sequence(adev, 231 cz_golden_settings_a11, 232 ARRAY_SIZE(cz_golden_settings_a11)); 233 break; 234 case CHIP_STONEY: 235 amdgpu_device_program_register_sequence(adev, 236 stoney_mgcg_cgcg_init, 237 ARRAY_SIZE(stoney_mgcg_cgcg_init)); 238 amdgpu_device_program_register_sequence(adev, 239 stoney_golden_settings_a11, 240 ARRAY_SIZE(stoney_golden_settings_a11)); 241 break; 242 default: 243 break; 244 } 245 } 246 247 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev) 248 { 249 int i; 250 for (i = 0; i < adev->sdma.num_instances; i++) { 251 release_firmware(adev->sdma.instance[i].fw); 252 adev->sdma.instance[i].fw = NULL; 253 } 254 } 255 256 /** 257 * sdma_v3_0_init_microcode - load ucode images from disk 258 * 259 * @adev: amdgpu_device pointer 260 * 261 * Use the firmware interface to load the ucode images into 262 * the driver (not loaded into hw). 263 * Returns 0 on success, error on failure. 264 */ 265 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) 266 { 267 const char *chip_name; 268 char fw_name[30]; 269 int err = 0, i; 270 struct amdgpu_firmware_info *info = NULL; 271 const struct common_firmware_header *header = NULL; 272 const struct sdma_firmware_header_v1_0 *hdr; 273 274 DRM_DEBUG("\n"); 275 276 switch (adev->asic_type) { 277 case CHIP_TONGA: 278 chip_name = "tonga"; 279 break; 280 case CHIP_FIJI: 281 chip_name = "fiji"; 282 break; 283 case CHIP_POLARIS10: 284 chip_name = "polaris10"; 285 break; 286 case CHIP_POLARIS11: 287 chip_name = "polaris11"; 288 break; 289 case CHIP_POLARIS12: 290 chip_name = "polaris12"; 291 break; 292 case CHIP_VEGAM: 293 chip_name = "vegam"; 294 break; 295 case CHIP_CARRIZO: 296 chip_name = "carrizo"; 297 break; 298 case CHIP_STONEY: 299 chip_name = "stoney"; 300 break; 301 default: BUG(); 302 } 303 304 for (i = 0; i < adev->sdma.num_instances; i++) { 305 if (i == 0) 306 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 307 else 308 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 309 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 310 if (err) 311 goto out; 312 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 313 if (err) 314 goto out; 315 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 316 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 317 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 318 if (adev->sdma.instance[i].feature_version >= 20) 319 adev->sdma.instance[i].burst_nop = true; 320 321 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 322 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 323 info->fw = adev->sdma.instance[i].fw; 324 header = (const struct common_firmware_header *)info->fw->data; 325 adev->firmware.fw_size += 326 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 327 328 } 329 out: 330 if (err) { 331 pr_err("sdma_v3_0: Failed to load firmware \"%s\"\n", fw_name); 332 for (i = 0; i < adev->sdma.num_instances; i++) { 333 release_firmware(adev->sdma.instance[i].fw); 334 adev->sdma.instance[i].fw = NULL; 335 } 336 } 337 return err; 338 } 339 340 /** 341 * sdma_v3_0_ring_get_rptr - get the current read pointer 342 * 343 * @ring: amdgpu ring pointer 344 * 345 * Get the current rptr from the hardware (VI+). 346 */ 347 static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring) 348 { 349 /* XXX check if swapping is necessary on BE */ 350 return ring->adev->wb.wb[ring->rptr_offs] >> 2; 351 } 352 353 /** 354 * sdma_v3_0_ring_get_wptr - get the current write pointer 355 * 356 * @ring: amdgpu ring pointer 357 * 358 * Get the current wptr from the hardware (VI+). 359 */ 360 static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring) 361 { 362 struct amdgpu_device *adev = ring->adev; 363 u32 wptr; 364 365 if (ring->use_doorbell || ring->use_pollmem) { 366 /* XXX check if swapping is necessary on BE */ 367 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; 368 } else { 369 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; 370 } 371 372 return wptr; 373 } 374 375 /** 376 * sdma_v3_0_ring_set_wptr - commit the write pointer 377 * 378 * @ring: amdgpu ring pointer 379 * 380 * Write the wptr back to the hardware (VI+). 381 */ 382 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) 383 { 384 struct amdgpu_device *adev = ring->adev; 385 386 if (ring->use_doorbell) { 387 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; 388 /* XXX check if swapping is necessary on BE */ 389 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2)); 390 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2); 391 } else if (ring->use_pollmem) { 392 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; 393 394 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2)); 395 } else { 396 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2); 397 } 398 } 399 400 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 401 { 402 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 403 int i; 404 405 for (i = 0; i < count; i++) 406 if (sdma && sdma->burst_nop && (i == 0)) 407 amdgpu_ring_write(ring, ring->funcs->nop | 408 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 409 else 410 amdgpu_ring_write(ring, ring->funcs->nop); 411 } 412 413 /** 414 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine 415 * 416 * @ring: amdgpu ring pointer 417 * @ib: IB object to schedule 418 * 419 * Schedule an IB in the DMA ring (VI). 420 */ 421 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, 422 struct amdgpu_ib *ib, 423 unsigned vmid, bool ctx_switch) 424 { 425 /* IB packet must end on a 8 DW boundary */ 426 sdma_v3_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 427 428 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 429 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 430 /* base must be 32 byte aligned */ 431 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 432 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 433 amdgpu_ring_write(ring, ib->length_dw); 434 amdgpu_ring_write(ring, 0); 435 amdgpu_ring_write(ring, 0); 436 437 } 438 439 /** 440 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 441 * 442 * @ring: amdgpu ring pointer 443 * 444 * Emit an hdp flush packet on the requested DMA ring. 445 */ 446 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 447 { 448 u32 ref_and_mask = 0; 449 450 if (ring->me == 0) 451 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); 452 else 453 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); 454 455 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 456 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 457 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 458 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 459 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 460 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 461 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 462 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 463 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 464 } 465 466 /** 467 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring 468 * 469 * @ring: amdgpu ring pointer 470 * @fence: amdgpu fence object 471 * 472 * Add a DMA fence packet to the ring to write 473 * the fence seq number and DMA trap packet to generate 474 * an interrupt if needed (VI). 475 */ 476 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 477 unsigned flags) 478 { 479 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 480 /* write the fence */ 481 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 482 amdgpu_ring_write(ring, lower_32_bits(addr)); 483 amdgpu_ring_write(ring, upper_32_bits(addr)); 484 amdgpu_ring_write(ring, lower_32_bits(seq)); 485 486 /* optionally write high bits as well */ 487 if (write64bit) { 488 addr += 4; 489 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 490 amdgpu_ring_write(ring, lower_32_bits(addr)); 491 amdgpu_ring_write(ring, upper_32_bits(addr)); 492 amdgpu_ring_write(ring, upper_32_bits(seq)); 493 } 494 495 /* generate an interrupt */ 496 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 497 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 498 } 499 500 /** 501 * sdma_v3_0_gfx_stop - stop the gfx async dma engines 502 * 503 * @adev: amdgpu_device pointer 504 * 505 * Stop the gfx async dma ring buffers (VI). 506 */ 507 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev) 508 { 509 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 510 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 511 u32 rb_cntl, ib_cntl; 512 int i; 513 514 if ((adev->mman.buffer_funcs_ring == sdma0) || 515 (adev->mman.buffer_funcs_ring == sdma1)) 516 amdgpu_ttm_set_buffer_funcs_status(adev, false); 517 518 for (i = 0; i < adev->sdma.num_instances; i++) { 519 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 520 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 521 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 522 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 523 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 524 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 525 } 526 sdma0->ready = false; 527 sdma1->ready = false; 528 } 529 530 /** 531 * sdma_v3_0_rlc_stop - stop the compute async dma engines 532 * 533 * @adev: amdgpu_device pointer 534 * 535 * Stop the compute async dma queues (VI). 536 */ 537 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev) 538 { 539 /* XXX todo */ 540 } 541 542 /** 543 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch 544 * 545 * @adev: amdgpu_device pointer 546 * @enable: enable/disable the DMA MEs context switch. 547 * 548 * Halt or unhalt the async dma engines context switch (VI). 549 */ 550 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 551 { 552 u32 f32_cntl, phase_quantum = 0; 553 int i; 554 555 if (amdgpu_sdma_phase_quantum) { 556 unsigned value = amdgpu_sdma_phase_quantum; 557 unsigned unit = 0; 558 559 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 560 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 561 value = (value + 1) >> 1; 562 unit++; 563 } 564 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 565 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 566 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 567 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 568 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 569 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 570 WARN_ONCE(1, 571 "clamping sdma_phase_quantum to %uK clock cycles\n", 572 value << unit); 573 } 574 phase_quantum = 575 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 576 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 577 } 578 579 for (i = 0; i < adev->sdma.num_instances; i++) { 580 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); 581 if (enable) { 582 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 583 AUTO_CTXSW_ENABLE, 1); 584 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 585 ATC_L1_ENABLE, 1); 586 if (amdgpu_sdma_phase_quantum) { 587 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], 588 phase_quantum); 589 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], 590 phase_quantum); 591 } 592 } else { 593 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 594 AUTO_CTXSW_ENABLE, 0); 595 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 596 ATC_L1_ENABLE, 1); 597 } 598 599 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); 600 } 601 } 602 603 /** 604 * sdma_v3_0_enable - stop the async dma engines 605 * 606 * @adev: amdgpu_device pointer 607 * @enable: enable/disable the DMA MEs. 608 * 609 * Halt or unhalt the async dma engines (VI). 610 */ 611 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable) 612 { 613 u32 f32_cntl; 614 int i; 615 616 if (!enable) { 617 sdma_v3_0_gfx_stop(adev); 618 sdma_v3_0_rlc_stop(adev); 619 } 620 621 for (i = 0; i < adev->sdma.num_instances; i++) { 622 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 623 if (enable) 624 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); 625 else 626 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 627 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); 628 } 629 } 630 631 /** 632 * sdma_v3_0_gfx_resume - setup and start the async dma engines 633 * 634 * @adev: amdgpu_device pointer 635 * 636 * Set up the gfx DMA ring buffers and enable them (VI). 637 * Returns 0 for success, error for failure. 638 */ 639 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) 640 { 641 struct amdgpu_ring *ring; 642 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 643 u32 rb_bufsz; 644 u32 wb_offset; 645 u32 doorbell; 646 u64 wptr_gpu_addr; 647 int i, j, r; 648 649 for (i = 0; i < adev->sdma.num_instances; i++) { 650 ring = &adev->sdma.instance[i].ring; 651 amdgpu_ring_clear_ring(ring); 652 wb_offset = (ring->rptr_offs * 4); 653 654 mutex_lock(&adev->srbm_mutex); 655 for (j = 0; j < 16; j++) { 656 vi_srbm_select(adev, 0, 0, 0, j); 657 /* SDMA GFX */ 658 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 659 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 660 } 661 vi_srbm_select(adev, 0, 0, 0, 0); 662 mutex_unlock(&adev->srbm_mutex); 663 664 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], 665 adev->gfx.config.gb_addr_config & 0x70); 666 667 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 668 669 /* Set ring buffer size in dwords */ 670 rb_bufsz = order_base_2(ring->ring_size / 4); 671 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 672 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 673 #ifdef __BIG_ENDIAN 674 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 675 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 676 RPTR_WRITEBACK_SWAP_ENABLE, 1); 677 #endif 678 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 679 680 /* Initialize the ring buffer's read and write pointers */ 681 ring->wptr = 0; 682 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 683 sdma_v3_0_ring_set_wptr(ring); 684 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); 685 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); 686 687 /* set the wb address whether it's enabled or not */ 688 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 689 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 690 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 691 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 692 693 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 694 695 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 696 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 697 698 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); 699 700 if (ring->use_doorbell) { 701 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, 702 OFFSET, ring->doorbell_index); 703 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 704 } else { 705 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 706 } 707 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell); 708 709 /* setup the wptr shadow polling */ 710 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 711 712 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i], 713 lower_32_bits(wptr_gpu_addr)); 714 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i], 715 upper_32_bits(wptr_gpu_addr)); 716 wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]); 717 if (ring->use_pollmem) { 718 /*wptr polling is not enogh fast, directly clean the wptr register */ 719 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 720 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 721 SDMA0_GFX_RB_WPTR_POLL_CNTL, 722 ENABLE, 1); 723 } else { 724 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 725 SDMA0_GFX_RB_WPTR_POLL_CNTL, 726 ENABLE, 0); 727 } 728 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl); 729 730 /* enable DMA RB */ 731 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 732 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 733 734 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 735 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 736 #ifdef __BIG_ENDIAN 737 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 738 #endif 739 /* enable DMA IBs */ 740 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 741 742 ring->ready = true; 743 } 744 745 /* unhalt the MEs */ 746 sdma_v3_0_enable(adev, true); 747 /* enable sdma ring preemption */ 748 sdma_v3_0_ctx_switch_enable(adev, true); 749 750 for (i = 0; i < adev->sdma.num_instances; i++) { 751 ring = &adev->sdma.instance[i].ring; 752 r = amdgpu_ring_test_ring(ring); 753 if (r) { 754 ring->ready = false; 755 return r; 756 } 757 758 if (adev->mman.buffer_funcs_ring == ring) 759 amdgpu_ttm_set_buffer_funcs_status(adev, true); 760 } 761 762 return 0; 763 } 764 765 /** 766 * sdma_v3_0_rlc_resume - setup and start the async dma engines 767 * 768 * @adev: amdgpu_device pointer 769 * 770 * Set up the compute DMA queues and enable them (VI). 771 * Returns 0 for success, error for failure. 772 */ 773 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev) 774 { 775 /* XXX todo */ 776 return 0; 777 } 778 779 /** 780 * sdma_v3_0_start - setup and start the async dma engines 781 * 782 * @adev: amdgpu_device pointer 783 * 784 * Set up the DMA engines and enable them (VI). 785 * Returns 0 for success, error for failure. 786 */ 787 static int sdma_v3_0_start(struct amdgpu_device *adev) 788 { 789 int r; 790 791 /* disable sdma engine before programing it */ 792 sdma_v3_0_ctx_switch_enable(adev, false); 793 sdma_v3_0_enable(adev, false); 794 795 /* start the gfx rings and rlc compute queues */ 796 r = sdma_v3_0_gfx_resume(adev); 797 if (r) 798 return r; 799 r = sdma_v3_0_rlc_resume(adev); 800 if (r) 801 return r; 802 803 return 0; 804 } 805 806 /** 807 * sdma_v3_0_ring_test_ring - simple async dma engine test 808 * 809 * @ring: amdgpu_ring structure holding ring information 810 * 811 * Test the DMA engine by writing using it to write an 812 * value to memory. (VI). 813 * Returns 0 for success, error for failure. 814 */ 815 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) 816 { 817 struct amdgpu_device *adev = ring->adev; 818 unsigned i; 819 unsigned index; 820 int r; 821 u32 tmp; 822 u64 gpu_addr; 823 824 r = amdgpu_device_wb_get(adev, &index); 825 if (r) { 826 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 827 return r; 828 } 829 830 gpu_addr = adev->wb.gpu_addr + (index * 4); 831 tmp = 0xCAFEDEAD; 832 adev->wb.wb[index] = cpu_to_le32(tmp); 833 834 r = amdgpu_ring_alloc(ring, 5); 835 if (r) { 836 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 837 amdgpu_device_wb_free(adev, index); 838 return r; 839 } 840 841 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 842 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 843 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 844 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 845 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 846 amdgpu_ring_write(ring, 0xDEADBEEF); 847 amdgpu_ring_commit(ring); 848 849 for (i = 0; i < adev->usec_timeout; i++) { 850 tmp = le32_to_cpu(adev->wb.wb[index]); 851 if (tmp == 0xDEADBEEF) 852 break; 853 DRM_UDELAY(1); 854 } 855 856 if (i < adev->usec_timeout) { 857 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); 858 } else { 859 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 860 ring->idx, tmp); 861 r = -EINVAL; 862 } 863 amdgpu_device_wb_free(adev, index); 864 865 return r; 866 } 867 868 /** 869 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine 870 * 871 * @ring: amdgpu_ring structure holding ring information 872 * 873 * Test a simple IB in the DMA ring (VI). 874 * Returns 0 on success, error on failure. 875 */ 876 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 877 { 878 struct amdgpu_device *adev = ring->adev; 879 struct amdgpu_ib ib; 880 struct dma_fence *f = NULL; 881 unsigned index; 882 u32 tmp = 0; 883 u64 gpu_addr; 884 long r; 885 886 r = amdgpu_device_wb_get(adev, &index); 887 if (r) { 888 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 889 return r; 890 } 891 892 gpu_addr = adev->wb.gpu_addr + (index * 4); 893 tmp = 0xCAFEDEAD; 894 adev->wb.wb[index] = cpu_to_le32(tmp); 895 memset(&ib, 0, sizeof(ib)); 896 r = amdgpu_ib_get(adev, NULL, 256, &ib); 897 if (r) { 898 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 899 goto err0; 900 } 901 902 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 903 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 904 ib.ptr[1] = lower_32_bits(gpu_addr); 905 ib.ptr[2] = upper_32_bits(gpu_addr); 906 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); 907 ib.ptr[4] = 0xDEADBEEF; 908 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 909 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 910 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 911 ib.length_dw = 8; 912 913 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 914 if (r) 915 goto err1; 916 917 r = dma_fence_wait_timeout(f, false, timeout); 918 if (r == 0) { 919 DRM_ERROR("amdgpu: IB test timed out\n"); 920 r = -ETIMEDOUT; 921 goto err1; 922 } else if (r < 0) { 923 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 924 goto err1; 925 } 926 tmp = le32_to_cpu(adev->wb.wb[index]); 927 if (tmp == 0xDEADBEEF) { 928 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); 929 r = 0; 930 } else { 931 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 932 r = -EINVAL; 933 } 934 err1: 935 amdgpu_ib_free(adev, &ib, NULL); 936 dma_fence_put(f); 937 err0: 938 amdgpu_device_wb_free(adev, index); 939 return r; 940 } 941 942 /** 943 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART 944 * 945 * @ib: indirect buffer to fill with commands 946 * @pe: addr of the page entry 947 * @src: src addr to copy from 948 * @count: number of page entries to update 949 * 950 * Update PTEs by copying them from the GART using sDMA (CIK). 951 */ 952 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib, 953 uint64_t pe, uint64_t src, 954 unsigned count) 955 { 956 unsigned bytes = count * 8; 957 958 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 959 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 960 ib->ptr[ib->length_dw++] = bytes; 961 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 962 ib->ptr[ib->length_dw++] = lower_32_bits(src); 963 ib->ptr[ib->length_dw++] = upper_32_bits(src); 964 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 965 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 966 } 967 968 /** 969 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually 970 * 971 * @ib: indirect buffer to fill with commands 972 * @pe: addr of the page entry 973 * @value: dst addr to write into pe 974 * @count: number of page entries to update 975 * @incr: increase next addr by incr bytes 976 * 977 * Update PTEs by writing them manually using sDMA (CIK). 978 */ 979 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 980 uint64_t value, unsigned count, 981 uint32_t incr) 982 { 983 unsigned ndw = count * 2; 984 985 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 986 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 987 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 988 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 989 ib->ptr[ib->length_dw++] = ndw; 990 for (; ndw > 0; ndw -= 2) { 991 ib->ptr[ib->length_dw++] = lower_32_bits(value); 992 ib->ptr[ib->length_dw++] = upper_32_bits(value); 993 value += incr; 994 } 995 } 996 997 /** 998 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA 999 * 1000 * @ib: indirect buffer to fill with commands 1001 * @pe: addr of the page entry 1002 * @addr: dst addr to write into pe 1003 * @count: number of page entries to update 1004 * @incr: increase next addr by incr bytes 1005 * @flags: access flags 1006 * 1007 * Update the page tables using sDMA (CIK). 1008 */ 1009 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, 1010 uint64_t addr, unsigned count, 1011 uint32_t incr, uint64_t flags) 1012 { 1013 /* for physically contiguous pages (vram) */ 1014 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); 1015 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1016 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1017 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1018 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1019 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1020 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1021 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1022 ib->ptr[ib->length_dw++] = 0; 1023 ib->ptr[ib->length_dw++] = count; /* number of entries */ 1024 } 1025 1026 /** 1027 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw 1028 * 1029 * @ib: indirect buffer to fill with padding 1030 * 1031 */ 1032 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1033 { 1034 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 1035 u32 pad_count; 1036 int i; 1037 1038 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 1039 for (i = 0; i < pad_count; i++) 1040 if (sdma && sdma->burst_nop && (i == 0)) 1041 ib->ptr[ib->length_dw++] = 1042 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1043 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1044 else 1045 ib->ptr[ib->length_dw++] = 1046 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1047 } 1048 1049 /** 1050 * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline 1051 * 1052 * @ring: amdgpu_ring pointer 1053 * 1054 * Make sure all previous operations are completed (CIK). 1055 */ 1056 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1057 { 1058 uint32_t seq = ring->fence_drv.sync_seq; 1059 uint64_t addr = ring->fence_drv.gpu_addr; 1060 1061 /* wait for idle */ 1062 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1063 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1064 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1065 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1066 amdgpu_ring_write(ring, addr & 0xfffffffc); 1067 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1068 amdgpu_ring_write(ring, seq); /* reference */ 1069 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1070 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1071 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1072 } 1073 1074 /** 1075 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA 1076 * 1077 * @ring: amdgpu_ring pointer 1078 * @vm: amdgpu_vm pointer 1079 * 1080 * Update the page table base and flush the VM TLB 1081 * using sDMA (VI). 1082 */ 1083 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1084 unsigned vmid, uint64_t pd_addr) 1085 { 1086 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1087 1088 /* wait for flush */ 1089 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1090 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1091 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ 1092 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 1093 amdgpu_ring_write(ring, 0); 1094 amdgpu_ring_write(ring, 0); /* reference */ 1095 amdgpu_ring_write(ring, 0); /* mask */ 1096 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1097 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 1098 } 1099 1100 static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring, 1101 uint32_t reg, uint32_t val) 1102 { 1103 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1104 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1105 amdgpu_ring_write(ring, reg); 1106 amdgpu_ring_write(ring, val); 1107 } 1108 1109 static int sdma_v3_0_early_init(void *handle) 1110 { 1111 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1112 1113 switch (adev->asic_type) { 1114 case CHIP_STONEY: 1115 adev->sdma.num_instances = 1; 1116 break; 1117 default: 1118 adev->sdma.num_instances = SDMA_MAX_INSTANCE; 1119 break; 1120 } 1121 1122 sdma_v3_0_set_ring_funcs(adev); 1123 sdma_v3_0_set_buffer_funcs(adev); 1124 sdma_v3_0_set_vm_pte_funcs(adev); 1125 sdma_v3_0_set_irq_funcs(adev); 1126 1127 return 0; 1128 } 1129 1130 static int sdma_v3_0_sw_init(void *handle) 1131 { 1132 struct amdgpu_ring *ring; 1133 int r, i; 1134 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1135 1136 /* SDMA trap event */ 1137 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP, 1138 &adev->sdma.trap_irq); 1139 if (r) 1140 return r; 1141 1142 /* SDMA Privileged inst */ 1143 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241, 1144 &adev->sdma.illegal_inst_irq); 1145 if (r) 1146 return r; 1147 1148 /* SDMA Privileged inst */ 1149 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE, 1150 &adev->sdma.illegal_inst_irq); 1151 if (r) 1152 return r; 1153 1154 r = sdma_v3_0_init_microcode(adev); 1155 if (r) { 1156 DRM_ERROR("Failed to load sdma firmware!\n"); 1157 return r; 1158 } 1159 1160 for (i = 0; i < adev->sdma.num_instances; i++) { 1161 ring = &adev->sdma.instance[i].ring; 1162 ring->ring_obj = NULL; 1163 if (!amdgpu_sriov_vf(adev)) { 1164 ring->use_doorbell = true; 1165 ring->doorbell_index = (i == 0) ? 1166 AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1; 1167 } else { 1168 ring->use_pollmem = true; 1169 } 1170 1171 sprintf(ring->name, "sdma%d", i); 1172 r = amdgpu_ring_init(adev, ring, 1024, 1173 &adev->sdma.trap_irq, 1174 (i == 0) ? 1175 AMDGPU_SDMA_IRQ_TRAP0 : 1176 AMDGPU_SDMA_IRQ_TRAP1); 1177 if (r) 1178 return r; 1179 } 1180 1181 return r; 1182 } 1183 1184 static int sdma_v3_0_sw_fini(void *handle) 1185 { 1186 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1187 int i; 1188 1189 for (i = 0; i < adev->sdma.num_instances; i++) 1190 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1191 1192 sdma_v3_0_free_microcode(adev); 1193 return 0; 1194 } 1195 1196 static int sdma_v3_0_hw_init(void *handle) 1197 { 1198 int r; 1199 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1200 1201 sdma_v3_0_init_golden_registers(adev); 1202 1203 r = sdma_v3_0_start(adev); 1204 if (r) 1205 return r; 1206 1207 return r; 1208 } 1209 1210 static int sdma_v3_0_hw_fini(void *handle) 1211 { 1212 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1213 1214 sdma_v3_0_ctx_switch_enable(adev, false); 1215 sdma_v3_0_enable(adev, false); 1216 1217 return 0; 1218 } 1219 1220 static int sdma_v3_0_suspend(void *handle) 1221 { 1222 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1223 1224 return sdma_v3_0_hw_fini(adev); 1225 } 1226 1227 static int sdma_v3_0_resume(void *handle) 1228 { 1229 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1230 1231 return sdma_v3_0_hw_init(adev); 1232 } 1233 1234 static bool sdma_v3_0_is_idle(void *handle) 1235 { 1236 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1237 u32 tmp = RREG32(mmSRBM_STATUS2); 1238 1239 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1240 SRBM_STATUS2__SDMA1_BUSY_MASK)) 1241 return false; 1242 1243 return true; 1244 } 1245 1246 static int sdma_v3_0_wait_for_idle(void *handle) 1247 { 1248 unsigned i; 1249 u32 tmp; 1250 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1251 1252 for (i = 0; i < adev->usec_timeout; i++) { 1253 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1254 SRBM_STATUS2__SDMA1_BUSY_MASK); 1255 1256 if (!tmp) 1257 return 0; 1258 udelay(1); 1259 } 1260 return -ETIMEDOUT; 1261 } 1262 1263 static bool sdma_v3_0_check_soft_reset(void *handle) 1264 { 1265 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1266 u32 srbm_soft_reset = 0; 1267 u32 tmp = RREG32(mmSRBM_STATUS2); 1268 1269 if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) || 1270 (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) { 1271 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1272 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1273 } 1274 1275 if (srbm_soft_reset) { 1276 adev->sdma.srbm_soft_reset = srbm_soft_reset; 1277 return true; 1278 } else { 1279 adev->sdma.srbm_soft_reset = 0; 1280 return false; 1281 } 1282 } 1283 1284 static int sdma_v3_0_pre_soft_reset(void *handle) 1285 { 1286 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1287 u32 srbm_soft_reset = 0; 1288 1289 if (!adev->sdma.srbm_soft_reset) 1290 return 0; 1291 1292 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1293 1294 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || 1295 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { 1296 sdma_v3_0_ctx_switch_enable(adev, false); 1297 sdma_v3_0_enable(adev, false); 1298 } 1299 1300 return 0; 1301 } 1302 1303 static int sdma_v3_0_post_soft_reset(void *handle) 1304 { 1305 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1306 u32 srbm_soft_reset = 0; 1307 1308 if (!adev->sdma.srbm_soft_reset) 1309 return 0; 1310 1311 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1312 1313 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || 1314 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { 1315 sdma_v3_0_gfx_resume(adev); 1316 sdma_v3_0_rlc_resume(adev); 1317 } 1318 1319 return 0; 1320 } 1321 1322 static int sdma_v3_0_soft_reset(void *handle) 1323 { 1324 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1325 u32 srbm_soft_reset = 0; 1326 u32 tmp; 1327 1328 if (!adev->sdma.srbm_soft_reset) 1329 return 0; 1330 1331 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1332 1333 if (srbm_soft_reset) { 1334 tmp = RREG32(mmSRBM_SOFT_RESET); 1335 tmp |= srbm_soft_reset; 1336 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1337 WREG32(mmSRBM_SOFT_RESET, tmp); 1338 tmp = RREG32(mmSRBM_SOFT_RESET); 1339 1340 udelay(50); 1341 1342 tmp &= ~srbm_soft_reset; 1343 WREG32(mmSRBM_SOFT_RESET, tmp); 1344 tmp = RREG32(mmSRBM_SOFT_RESET); 1345 1346 /* Wait a little for things to settle down */ 1347 udelay(50); 1348 } 1349 1350 return 0; 1351 } 1352 1353 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev, 1354 struct amdgpu_irq_src *source, 1355 unsigned type, 1356 enum amdgpu_interrupt_state state) 1357 { 1358 u32 sdma_cntl; 1359 1360 switch (type) { 1361 case AMDGPU_SDMA_IRQ_TRAP0: 1362 switch (state) { 1363 case AMDGPU_IRQ_STATE_DISABLE: 1364 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1365 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1366 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1367 break; 1368 case AMDGPU_IRQ_STATE_ENABLE: 1369 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1370 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1371 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1372 break; 1373 default: 1374 break; 1375 } 1376 break; 1377 case AMDGPU_SDMA_IRQ_TRAP1: 1378 switch (state) { 1379 case AMDGPU_IRQ_STATE_DISABLE: 1380 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1381 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1382 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1383 break; 1384 case AMDGPU_IRQ_STATE_ENABLE: 1385 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1386 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1387 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1388 break; 1389 default: 1390 break; 1391 } 1392 break; 1393 default: 1394 break; 1395 } 1396 return 0; 1397 } 1398 1399 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev, 1400 struct amdgpu_irq_src *source, 1401 struct amdgpu_iv_entry *entry) 1402 { 1403 u8 instance_id, queue_id; 1404 1405 instance_id = (entry->ring_id & 0x3) >> 0; 1406 queue_id = (entry->ring_id & 0xc) >> 2; 1407 DRM_DEBUG("IH: SDMA trap\n"); 1408 switch (instance_id) { 1409 case 0: 1410 switch (queue_id) { 1411 case 0: 1412 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1413 break; 1414 case 1: 1415 /* XXX compute */ 1416 break; 1417 case 2: 1418 /* XXX compute */ 1419 break; 1420 } 1421 break; 1422 case 1: 1423 switch (queue_id) { 1424 case 0: 1425 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1426 break; 1427 case 1: 1428 /* XXX compute */ 1429 break; 1430 case 2: 1431 /* XXX compute */ 1432 break; 1433 } 1434 break; 1435 } 1436 return 0; 1437 } 1438 1439 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1440 struct amdgpu_irq_src *source, 1441 struct amdgpu_iv_entry *entry) 1442 { 1443 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1444 schedule_work(&adev->reset_work); 1445 return 0; 1446 } 1447 1448 static void sdma_v3_0_update_sdma_medium_grain_clock_gating( 1449 struct amdgpu_device *adev, 1450 bool enable) 1451 { 1452 uint32_t temp, data; 1453 int i; 1454 1455 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1456 for (i = 0; i < adev->sdma.num_instances; i++) { 1457 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); 1458 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1459 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1460 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1461 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1462 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1463 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1464 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1465 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1466 if (data != temp) 1467 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); 1468 } 1469 } else { 1470 for (i = 0; i < adev->sdma.num_instances; i++) { 1471 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); 1472 data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1473 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1474 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1475 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1476 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1477 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1478 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1479 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK; 1480 1481 if (data != temp) 1482 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); 1483 } 1484 } 1485 } 1486 1487 static void sdma_v3_0_update_sdma_medium_grain_light_sleep( 1488 struct amdgpu_device *adev, 1489 bool enable) 1490 { 1491 uint32_t temp, data; 1492 int i; 1493 1494 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1495 for (i = 0; i < adev->sdma.num_instances; i++) { 1496 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1497 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1498 1499 if (temp != data) 1500 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1501 } 1502 } else { 1503 for (i = 0; i < adev->sdma.num_instances; i++) { 1504 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1505 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1506 1507 if (temp != data) 1508 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1509 } 1510 } 1511 } 1512 1513 static int sdma_v3_0_set_clockgating_state(void *handle, 1514 enum amd_clockgating_state state) 1515 { 1516 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1517 1518 if (amdgpu_sriov_vf(adev)) 1519 return 0; 1520 1521 switch (adev->asic_type) { 1522 case CHIP_FIJI: 1523 case CHIP_CARRIZO: 1524 case CHIP_STONEY: 1525 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev, 1526 state == AMD_CG_STATE_GATE); 1527 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev, 1528 state == AMD_CG_STATE_GATE); 1529 break; 1530 default: 1531 break; 1532 } 1533 return 0; 1534 } 1535 1536 static int sdma_v3_0_set_powergating_state(void *handle, 1537 enum amd_powergating_state state) 1538 { 1539 return 0; 1540 } 1541 1542 static void sdma_v3_0_get_clockgating_state(void *handle, u32 *flags) 1543 { 1544 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1545 int data; 1546 1547 if (amdgpu_sriov_vf(adev)) 1548 *flags = 0; 1549 1550 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1551 data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]); 1552 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK)) 1553 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1554 1555 /* AMD_CG_SUPPORT_SDMA_LS */ 1556 data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]); 1557 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1558 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1559 } 1560 1561 static const struct amd_ip_funcs sdma_v3_0_ip_funcs = { 1562 .name = "sdma_v3_0", 1563 .early_init = sdma_v3_0_early_init, 1564 .late_init = NULL, 1565 .sw_init = sdma_v3_0_sw_init, 1566 .sw_fini = sdma_v3_0_sw_fini, 1567 .hw_init = sdma_v3_0_hw_init, 1568 .hw_fini = sdma_v3_0_hw_fini, 1569 .suspend = sdma_v3_0_suspend, 1570 .resume = sdma_v3_0_resume, 1571 .is_idle = sdma_v3_0_is_idle, 1572 .wait_for_idle = sdma_v3_0_wait_for_idle, 1573 .check_soft_reset = sdma_v3_0_check_soft_reset, 1574 .pre_soft_reset = sdma_v3_0_pre_soft_reset, 1575 .post_soft_reset = sdma_v3_0_post_soft_reset, 1576 .soft_reset = sdma_v3_0_soft_reset, 1577 .set_clockgating_state = sdma_v3_0_set_clockgating_state, 1578 .set_powergating_state = sdma_v3_0_set_powergating_state, 1579 .get_clockgating_state = sdma_v3_0_get_clockgating_state, 1580 }; 1581 1582 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { 1583 .type = AMDGPU_RING_TYPE_SDMA, 1584 .align_mask = 0xf, 1585 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1586 .support_64bit_ptrs = false, 1587 .get_rptr = sdma_v3_0_ring_get_rptr, 1588 .get_wptr = sdma_v3_0_ring_get_wptr, 1589 .set_wptr = sdma_v3_0_ring_set_wptr, 1590 .emit_frame_size = 1591 6 + /* sdma_v3_0_ring_emit_hdp_flush */ 1592 3 + /* hdp invalidate */ 1593 6 + /* sdma_v3_0_ring_emit_pipeline_sync */ 1594 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v3_0_ring_emit_vm_flush */ 1595 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */ 1596 .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */ 1597 .emit_ib = sdma_v3_0_ring_emit_ib, 1598 .emit_fence = sdma_v3_0_ring_emit_fence, 1599 .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync, 1600 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, 1601 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, 1602 .test_ring = sdma_v3_0_ring_test_ring, 1603 .test_ib = sdma_v3_0_ring_test_ib, 1604 .insert_nop = sdma_v3_0_ring_insert_nop, 1605 .pad_ib = sdma_v3_0_ring_pad_ib, 1606 .emit_wreg = sdma_v3_0_ring_emit_wreg, 1607 }; 1608 1609 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev) 1610 { 1611 int i; 1612 1613 for (i = 0; i < adev->sdma.num_instances; i++) { 1614 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs; 1615 adev->sdma.instance[i].ring.me = i; 1616 } 1617 } 1618 1619 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = { 1620 .set = sdma_v3_0_set_trap_irq_state, 1621 .process = sdma_v3_0_process_trap_irq, 1622 }; 1623 1624 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = { 1625 .process = sdma_v3_0_process_illegal_inst_irq, 1626 }; 1627 1628 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev) 1629 { 1630 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1631 adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs; 1632 adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs; 1633 } 1634 1635 /** 1636 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine 1637 * 1638 * @ring: amdgpu_ring structure holding ring information 1639 * @src_offset: src GPU address 1640 * @dst_offset: dst GPU address 1641 * @byte_count: number of bytes to xfer 1642 * 1643 * Copy GPU buffers using the DMA engine (VI). 1644 * Used by the amdgpu ttm implementation to move pages if 1645 * registered as the asic copy callback. 1646 */ 1647 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib, 1648 uint64_t src_offset, 1649 uint64_t dst_offset, 1650 uint32_t byte_count) 1651 { 1652 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1653 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1654 ib->ptr[ib->length_dw++] = byte_count; 1655 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1656 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1657 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1658 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1659 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1660 } 1661 1662 /** 1663 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine 1664 * 1665 * @ring: amdgpu_ring structure holding ring information 1666 * @src_data: value to write to buffer 1667 * @dst_offset: dst GPU address 1668 * @byte_count: number of bytes to xfer 1669 * 1670 * Fill GPU buffers using the DMA engine (VI). 1671 */ 1672 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib, 1673 uint32_t src_data, 1674 uint64_t dst_offset, 1675 uint32_t byte_count) 1676 { 1677 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1678 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1679 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1680 ib->ptr[ib->length_dw++] = src_data; 1681 ib->ptr[ib->length_dw++] = byte_count; 1682 } 1683 1684 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = { 1685 .copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */ 1686 .copy_num_dw = 7, 1687 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer, 1688 1689 .fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */ 1690 .fill_num_dw = 5, 1691 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer, 1692 }; 1693 1694 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) 1695 { 1696 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs; 1697 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1698 } 1699 1700 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { 1701 .copy_pte_num_dw = 7, 1702 .copy_pte = sdma_v3_0_vm_copy_pte, 1703 1704 .write_pte = sdma_v3_0_vm_write_pte, 1705 .set_pte_pde = sdma_v3_0_vm_set_pte_pde, 1706 }; 1707 1708 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1709 { 1710 struct drm_gpu_scheduler *sched; 1711 unsigned i; 1712 1713 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; 1714 for (i = 0; i < adev->sdma.num_instances; i++) { 1715 sched = &adev->sdma.instance[i].ring.sched; 1716 adev->vm_manager.vm_pte_rqs[i] = 1717 &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL]; 1718 } 1719 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances; 1720 } 1721 1722 const struct amdgpu_ip_block_version sdma_v3_0_ip_block = 1723 { 1724 .type = AMD_IP_BLOCK_TYPE_SDMA, 1725 .major = 3, 1726 .minor = 0, 1727 .rev = 0, 1728 .funcs = &sdma_v3_0_ip_funcs, 1729 }; 1730 1731 const struct amdgpu_ip_block_version sdma_v3_1_ip_block = 1732 { 1733 .type = AMD_IP_BLOCK_TYPE_SDMA, 1734 .major = 3, 1735 .minor = 1, 1736 .rev = 0, 1737 .funcs = &sdma_v3_0_ip_funcs, 1738 }; 1739