1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 #include "vi.h" 30 #include "vid.h" 31 32 #include "oss/oss_3_0_d.h" 33 #include "oss/oss_3_0_sh_mask.h" 34 35 #include "gmc/gmc_8_1_d.h" 36 #include "gmc/gmc_8_1_sh_mask.h" 37 38 #include "gca/gfx_8_0_d.h" 39 #include "gca/gfx_8_0_enum.h" 40 #include "gca/gfx_8_0_sh_mask.h" 41 42 #include "bif/bif_5_0_d.h" 43 #include "bif/bif_5_0_sh_mask.h" 44 45 #include "tonga_sdma_pkt_open.h" 46 47 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev); 48 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); 49 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev); 50 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); 51 52 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); 53 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin"); 54 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin"); 55 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); 56 57 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 58 { 59 SDMA0_REGISTER_OFFSET, 60 SDMA1_REGISTER_OFFSET 61 }; 62 63 static const u32 golden_settings_tonga_a11[] = 64 { 65 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 66 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 67 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 68 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 69 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 70 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 71 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 72 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 73 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 74 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 75 }; 76 77 static const u32 tonga_mgcg_cgcg_init[] = 78 { 79 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 80 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 81 }; 82 83 static const u32 cz_golden_settings_a11[] = 84 { 85 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 86 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 87 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 88 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 89 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 90 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 91 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 92 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 93 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100, 94 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800, 95 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100, 96 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100, 97 }; 98 99 static const u32 cz_mgcg_cgcg_init[] = 100 { 101 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 102 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 103 }; 104 105 /* 106 * sDMA - System DMA 107 * Starting with CIK, the GPU has new asynchronous 108 * DMA engines. These engines are used for compute 109 * and gfx. There are two DMA engines (SDMA0, SDMA1) 110 * and each one supports 1 ring buffer used for gfx 111 * and 2 queues used for compute. 112 * 113 * The programming model is very similar to the CP 114 * (ring buffer, IBs, etc.), but sDMA has it's own 115 * packet format that is different from the PM4 format 116 * used by the CP. sDMA supports copying data, writing 117 * embedded data, solid fills, and a number of other 118 * things. It also has support for tiling/detiling of 119 * buffers. 120 */ 121 122 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) 123 { 124 switch (adev->asic_type) { 125 case CHIP_TONGA: 126 amdgpu_program_register_sequence(adev, 127 tonga_mgcg_cgcg_init, 128 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); 129 amdgpu_program_register_sequence(adev, 130 golden_settings_tonga_a11, 131 (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); 132 break; 133 case CHIP_CARRIZO: 134 amdgpu_program_register_sequence(adev, 135 cz_mgcg_cgcg_init, 136 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 137 amdgpu_program_register_sequence(adev, 138 cz_golden_settings_a11, 139 (const u32)ARRAY_SIZE(cz_golden_settings_a11)); 140 break; 141 default: 142 break; 143 } 144 } 145 146 /** 147 * sdma_v3_0_init_microcode - load ucode images from disk 148 * 149 * @adev: amdgpu_device pointer 150 * 151 * Use the firmware interface to load the ucode images into 152 * the driver (not loaded into hw). 153 * Returns 0 on success, error on failure. 154 */ 155 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) 156 { 157 const char *chip_name; 158 char fw_name[30]; 159 int err, i; 160 struct amdgpu_firmware_info *info = NULL; 161 const struct common_firmware_header *header = NULL; 162 const struct sdma_firmware_header_v1_0 *hdr; 163 164 DRM_DEBUG("\n"); 165 166 switch (adev->asic_type) { 167 case CHIP_TONGA: 168 chip_name = "tonga"; 169 break; 170 case CHIP_CARRIZO: 171 chip_name = "carrizo"; 172 break; 173 default: BUG(); 174 } 175 176 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 177 if (i == 0) 178 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 179 else 180 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 181 err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev); 182 if (err) 183 goto out; 184 err = amdgpu_ucode_validate(adev->sdma[i].fw); 185 if (err) 186 goto out; 187 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data; 188 adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 189 adev->sdma[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 190 191 if (adev->firmware.smu_load) { 192 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 193 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 194 info->fw = adev->sdma[i].fw; 195 header = (const struct common_firmware_header *)info->fw->data; 196 adev->firmware.fw_size += 197 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 198 } 199 } 200 out: 201 if (err) { 202 printk(KERN_ERR 203 "sdma_v3_0: Failed to load firmware \"%s\"\n", 204 fw_name); 205 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 206 release_firmware(adev->sdma[i].fw); 207 adev->sdma[i].fw = NULL; 208 } 209 } 210 return err; 211 } 212 213 /** 214 * sdma_v3_0_ring_get_rptr - get the current read pointer 215 * 216 * @ring: amdgpu ring pointer 217 * 218 * Get the current rptr from the hardware (VI+). 219 */ 220 static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring) 221 { 222 u32 rptr; 223 224 /* XXX check if swapping is necessary on BE */ 225 rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2; 226 227 return rptr; 228 } 229 230 /** 231 * sdma_v3_0_ring_get_wptr - get the current write pointer 232 * 233 * @ring: amdgpu ring pointer 234 * 235 * Get the current wptr from the hardware (VI+). 236 */ 237 static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring) 238 { 239 struct amdgpu_device *adev = ring->adev; 240 u32 wptr; 241 242 if (ring->use_doorbell) { 243 /* XXX check if swapping is necessary on BE */ 244 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; 245 } else { 246 int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1; 247 248 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2; 249 } 250 251 return wptr; 252 } 253 254 /** 255 * sdma_v3_0_ring_set_wptr - commit the write pointer 256 * 257 * @ring: amdgpu ring pointer 258 * 259 * Write the wptr back to the hardware (VI+). 260 */ 261 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) 262 { 263 struct amdgpu_device *adev = ring->adev; 264 265 if (ring->use_doorbell) { 266 /* XXX check if swapping is necessary on BE */ 267 adev->wb.wb[ring->wptr_offs] = ring->wptr << 2; 268 WDOORBELL32(ring->doorbell_index, ring->wptr << 2); 269 } else { 270 int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1; 271 272 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2); 273 } 274 } 275 276 /** 277 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine 278 * 279 * @ring: amdgpu ring pointer 280 * @ib: IB object to schedule 281 * 282 * Schedule an IB in the DMA ring (VI). 283 */ 284 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, 285 struct amdgpu_ib *ib) 286 { 287 u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf; 288 u32 next_rptr = ring->wptr + 5; 289 290 while ((next_rptr & 7) != 2) 291 next_rptr++; 292 next_rptr += 6; 293 294 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 295 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 296 amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc); 297 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); 298 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 299 amdgpu_ring_write(ring, next_rptr); 300 301 /* IB packet must end on a 8 DW boundary */ 302 while ((ring->wptr & 7) != 2) 303 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_NOP)); 304 305 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 306 SDMA_PKT_INDIRECT_HEADER_VMID(vmid)); 307 /* base must be 32 byte aligned */ 308 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 309 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 310 amdgpu_ring_write(ring, ib->length_dw); 311 amdgpu_ring_write(ring, 0); 312 amdgpu_ring_write(ring, 0); 313 314 } 315 316 /** 317 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 318 * 319 * @ring: amdgpu ring pointer 320 * 321 * Emit an hdp flush packet on the requested DMA ring. 322 */ 323 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 324 { 325 u32 ref_and_mask = 0; 326 327 if (ring == &ring->adev->sdma[0].ring) 328 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); 329 else 330 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); 331 332 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 333 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 334 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 335 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 336 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 337 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 338 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 339 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 340 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 341 } 342 343 /** 344 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring 345 * 346 * @ring: amdgpu ring pointer 347 * @fence: amdgpu fence object 348 * 349 * Add a DMA fence packet to the ring to write 350 * the fence seq number and DMA trap packet to generate 351 * an interrupt if needed (VI). 352 */ 353 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 354 unsigned flags) 355 { 356 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 357 /* write the fence */ 358 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 359 amdgpu_ring_write(ring, lower_32_bits(addr)); 360 amdgpu_ring_write(ring, upper_32_bits(addr)); 361 amdgpu_ring_write(ring, lower_32_bits(seq)); 362 363 /* optionally write high bits as well */ 364 if (write64bit) { 365 addr += 4; 366 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 367 amdgpu_ring_write(ring, lower_32_bits(addr)); 368 amdgpu_ring_write(ring, upper_32_bits(addr)); 369 amdgpu_ring_write(ring, upper_32_bits(seq)); 370 } 371 372 /* generate an interrupt */ 373 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 374 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 375 } 376 377 378 /** 379 * sdma_v3_0_ring_emit_semaphore - emit a semaphore on the dma ring 380 * 381 * @ring: amdgpu_ring structure holding ring information 382 * @semaphore: amdgpu semaphore object 383 * @emit_wait: wait or signal semaphore 384 * 385 * Add a DMA semaphore packet to the ring wait on or signal 386 * other rings (VI). 387 */ 388 static bool sdma_v3_0_ring_emit_semaphore(struct amdgpu_ring *ring, 389 struct amdgpu_semaphore *semaphore, 390 bool emit_wait) 391 { 392 u64 addr = semaphore->gpu_addr; 393 u32 sig = emit_wait ? 0 : 1; 394 395 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) | 396 SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig)); 397 amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8); 398 amdgpu_ring_write(ring, upper_32_bits(addr)); 399 400 return true; 401 } 402 403 /** 404 * sdma_v3_0_gfx_stop - stop the gfx async dma engines 405 * 406 * @adev: amdgpu_device pointer 407 * 408 * Stop the gfx async dma ring buffers (VI). 409 */ 410 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev) 411 { 412 struct amdgpu_ring *sdma0 = &adev->sdma[0].ring; 413 struct amdgpu_ring *sdma1 = &adev->sdma[1].ring; 414 u32 rb_cntl, ib_cntl; 415 int i; 416 417 if ((adev->mman.buffer_funcs_ring == sdma0) || 418 (adev->mman.buffer_funcs_ring == sdma1)) 419 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); 420 421 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 422 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 423 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 424 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 425 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 426 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 427 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 428 } 429 sdma0->ready = false; 430 sdma1->ready = false; 431 } 432 433 /** 434 * sdma_v3_0_rlc_stop - stop the compute async dma engines 435 * 436 * @adev: amdgpu_device pointer 437 * 438 * Stop the compute async dma queues (VI). 439 */ 440 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev) 441 { 442 /* XXX todo */ 443 } 444 445 /** 446 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch 447 * 448 * @adev: amdgpu_device pointer 449 * @enable: enable/disable the DMA MEs context switch. 450 * 451 * Halt or unhalt the async dma engines context switch (VI). 452 */ 453 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 454 { 455 u32 f32_cntl; 456 int i; 457 458 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 459 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); 460 if (enable) 461 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 462 AUTO_CTXSW_ENABLE, 1); 463 else 464 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 465 AUTO_CTXSW_ENABLE, 0); 466 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); 467 } 468 } 469 470 /** 471 * sdma_v3_0_enable - stop the async dma engines 472 * 473 * @adev: amdgpu_device pointer 474 * @enable: enable/disable the DMA MEs. 475 * 476 * Halt or unhalt the async dma engines (VI). 477 */ 478 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable) 479 { 480 u32 f32_cntl; 481 int i; 482 483 if (enable == false) { 484 sdma_v3_0_gfx_stop(adev); 485 sdma_v3_0_rlc_stop(adev); 486 } 487 488 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 489 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 490 if (enable) 491 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); 492 else 493 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 494 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); 495 } 496 } 497 498 /** 499 * sdma_v3_0_gfx_resume - setup and start the async dma engines 500 * 501 * @adev: amdgpu_device pointer 502 * 503 * Set up the gfx DMA ring buffers and enable them (VI). 504 * Returns 0 for success, error for failure. 505 */ 506 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) 507 { 508 struct amdgpu_ring *ring; 509 u32 rb_cntl, ib_cntl; 510 u32 rb_bufsz; 511 u32 wb_offset; 512 u32 doorbell; 513 int i, j, r; 514 515 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 516 ring = &adev->sdma[i].ring; 517 wb_offset = (ring->rptr_offs * 4); 518 519 mutex_lock(&adev->srbm_mutex); 520 for (j = 0; j < 16; j++) { 521 vi_srbm_select(adev, 0, 0, 0, j); 522 /* SDMA GFX */ 523 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 524 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 525 } 526 vi_srbm_select(adev, 0, 0, 0, 0); 527 mutex_unlock(&adev->srbm_mutex); 528 529 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 530 531 /* Set ring buffer size in dwords */ 532 rb_bufsz = order_base_2(ring->ring_size / 4); 533 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 534 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 535 #ifdef __BIG_ENDIAN 536 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 537 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 538 RPTR_WRITEBACK_SWAP_ENABLE, 1); 539 #endif 540 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 541 542 /* Initialize the ring buffer's read and write pointers */ 543 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 544 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 545 546 /* set the wb address whether it's enabled or not */ 547 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 548 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 549 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 550 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 551 552 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 553 554 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 555 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 556 557 ring->wptr = 0; 558 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); 559 560 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); 561 562 if (ring->use_doorbell) { 563 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, 564 OFFSET, ring->doorbell_index); 565 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 566 } else { 567 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 568 } 569 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell); 570 571 /* enable DMA RB */ 572 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 573 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 574 575 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 576 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 577 #ifdef __BIG_ENDIAN 578 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 579 #endif 580 /* enable DMA IBs */ 581 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 582 583 ring->ready = true; 584 585 r = amdgpu_ring_test_ring(ring); 586 if (r) { 587 ring->ready = false; 588 return r; 589 } 590 591 if (adev->mman.buffer_funcs_ring == ring) 592 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); 593 } 594 595 return 0; 596 } 597 598 /** 599 * sdma_v3_0_rlc_resume - setup and start the async dma engines 600 * 601 * @adev: amdgpu_device pointer 602 * 603 * Set up the compute DMA queues and enable them (VI). 604 * Returns 0 for success, error for failure. 605 */ 606 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev) 607 { 608 /* XXX todo */ 609 return 0; 610 } 611 612 /** 613 * sdma_v3_0_load_microcode - load the sDMA ME ucode 614 * 615 * @adev: amdgpu_device pointer 616 * 617 * Loads the sDMA0/1 ucode. 618 * Returns 0 for success, -EINVAL if the ucode is not available. 619 */ 620 static int sdma_v3_0_load_microcode(struct amdgpu_device *adev) 621 { 622 const struct sdma_firmware_header_v1_0 *hdr; 623 const __le32 *fw_data; 624 u32 fw_size; 625 int i, j; 626 627 if (!adev->sdma[0].fw || !adev->sdma[1].fw) 628 return -EINVAL; 629 630 /* halt the MEs */ 631 sdma_v3_0_enable(adev, false); 632 633 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 634 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data; 635 amdgpu_ucode_print_sdma_hdr(&hdr->header); 636 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 637 fw_data = (const __le32 *) 638 (adev->sdma[i].fw->data + 639 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 640 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); 641 for (j = 0; j < fw_size; j++) 642 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); 643 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version); 644 } 645 646 return 0; 647 } 648 649 /** 650 * sdma_v3_0_start - setup and start the async dma engines 651 * 652 * @adev: amdgpu_device pointer 653 * 654 * Set up the DMA engines and enable them (VI). 655 * Returns 0 for success, error for failure. 656 */ 657 static int sdma_v3_0_start(struct amdgpu_device *adev) 658 { 659 int r; 660 661 if (!adev->firmware.smu_load) { 662 r = sdma_v3_0_load_microcode(adev); 663 if (r) 664 return r; 665 } else { 666 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 667 AMDGPU_UCODE_ID_SDMA0); 668 if (r) 669 return -EINVAL; 670 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 671 AMDGPU_UCODE_ID_SDMA1); 672 if (r) 673 return -EINVAL; 674 } 675 676 /* unhalt the MEs */ 677 sdma_v3_0_enable(adev, true); 678 /* enable sdma ring preemption */ 679 sdma_v3_0_ctx_switch_enable(adev, true); 680 681 /* start the gfx rings and rlc compute queues */ 682 r = sdma_v3_0_gfx_resume(adev); 683 if (r) 684 return r; 685 r = sdma_v3_0_rlc_resume(adev); 686 if (r) 687 return r; 688 689 return 0; 690 } 691 692 /** 693 * sdma_v3_0_ring_test_ring - simple async dma engine test 694 * 695 * @ring: amdgpu_ring structure holding ring information 696 * 697 * Test the DMA engine by writing using it to write an 698 * value to memory. (VI). 699 * Returns 0 for success, error for failure. 700 */ 701 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) 702 { 703 struct amdgpu_device *adev = ring->adev; 704 unsigned i; 705 unsigned index; 706 int r; 707 u32 tmp; 708 u64 gpu_addr; 709 710 r = amdgpu_wb_get(adev, &index); 711 if (r) { 712 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 713 return r; 714 } 715 716 gpu_addr = adev->wb.gpu_addr + (index * 4); 717 tmp = 0xCAFEDEAD; 718 adev->wb.wb[index] = cpu_to_le32(tmp); 719 720 r = amdgpu_ring_lock(ring, 5); 721 if (r) { 722 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 723 amdgpu_wb_free(adev, index); 724 return r; 725 } 726 727 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 728 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 729 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 730 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 731 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 732 amdgpu_ring_write(ring, 0xDEADBEEF); 733 amdgpu_ring_unlock_commit(ring); 734 735 for (i = 0; i < adev->usec_timeout; i++) { 736 tmp = le32_to_cpu(adev->wb.wb[index]); 737 if (tmp == 0xDEADBEEF) 738 break; 739 DRM_UDELAY(1); 740 } 741 742 if (i < adev->usec_timeout) { 743 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 744 } else { 745 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 746 ring->idx, tmp); 747 r = -EINVAL; 748 } 749 amdgpu_wb_free(adev, index); 750 751 return r; 752 } 753 754 /** 755 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine 756 * 757 * @ring: amdgpu_ring structure holding ring information 758 * 759 * Test a simple IB in the DMA ring (VI). 760 * Returns 0 on success, error on failure. 761 */ 762 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring) 763 { 764 struct amdgpu_device *adev = ring->adev; 765 struct amdgpu_ib ib; 766 unsigned i; 767 unsigned index; 768 int r; 769 u32 tmp = 0; 770 u64 gpu_addr; 771 772 r = amdgpu_wb_get(adev, &index); 773 if (r) { 774 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 775 return r; 776 } 777 778 gpu_addr = adev->wb.gpu_addr + (index * 4); 779 tmp = 0xCAFEDEAD; 780 adev->wb.wb[index] = cpu_to_le32(tmp); 781 782 r = amdgpu_ib_get(ring, NULL, 256, &ib); 783 if (r) { 784 amdgpu_wb_free(adev, index); 785 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); 786 return r; 787 } 788 789 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 790 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 791 ib.ptr[1] = lower_32_bits(gpu_addr); 792 ib.ptr[2] = upper_32_bits(gpu_addr); 793 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); 794 ib.ptr[4] = 0xDEADBEEF; 795 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 796 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 797 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 798 ib.length_dw = 8; 799 800 r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED); 801 if (r) { 802 amdgpu_ib_free(adev, &ib); 803 amdgpu_wb_free(adev, index); 804 DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r); 805 return r; 806 } 807 r = amdgpu_fence_wait(ib.fence, false); 808 if (r) { 809 amdgpu_ib_free(adev, &ib); 810 amdgpu_wb_free(adev, index); 811 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 812 return r; 813 } 814 for (i = 0; i < adev->usec_timeout; i++) { 815 tmp = le32_to_cpu(adev->wb.wb[index]); 816 if (tmp == 0xDEADBEEF) 817 break; 818 DRM_UDELAY(1); 819 } 820 if (i < adev->usec_timeout) { 821 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", 822 ib.fence->ring->idx, i); 823 } else { 824 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 825 r = -EINVAL; 826 } 827 amdgpu_ib_free(adev, &ib); 828 amdgpu_wb_free(adev, index); 829 return r; 830 } 831 832 /** 833 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART 834 * 835 * @ib: indirect buffer to fill with commands 836 * @pe: addr of the page entry 837 * @src: src addr to copy from 838 * @count: number of page entries to update 839 * 840 * Update PTEs by copying them from the GART using sDMA (CIK). 841 */ 842 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib, 843 uint64_t pe, uint64_t src, 844 unsigned count) 845 { 846 while (count) { 847 unsigned bytes = count * 8; 848 if (bytes > 0x1FFFF8) 849 bytes = 0x1FFFF8; 850 851 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 852 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 853 ib->ptr[ib->length_dw++] = bytes; 854 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 855 ib->ptr[ib->length_dw++] = lower_32_bits(src); 856 ib->ptr[ib->length_dw++] = upper_32_bits(src); 857 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 858 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 859 860 pe += bytes; 861 src += bytes; 862 count -= bytes / 8; 863 } 864 } 865 866 /** 867 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually 868 * 869 * @ib: indirect buffer to fill with commands 870 * @pe: addr of the page entry 871 * @addr: dst addr to write into pe 872 * @count: number of page entries to update 873 * @incr: increase next addr by incr bytes 874 * @flags: access flags 875 * 876 * Update PTEs by writing them manually using sDMA (CIK). 877 */ 878 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, 879 uint64_t pe, 880 uint64_t addr, unsigned count, 881 uint32_t incr, uint32_t flags) 882 { 883 uint64_t value; 884 unsigned ndw; 885 886 while (count) { 887 ndw = count * 2; 888 if (ndw > 0xFFFFE) 889 ndw = 0xFFFFE; 890 891 /* for non-physically contiguous pages (system) */ 892 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 893 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 894 ib->ptr[ib->length_dw++] = pe; 895 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 896 ib->ptr[ib->length_dw++] = ndw; 897 for (; ndw > 0; ndw -= 2, --count, pe += 8) { 898 if (flags & AMDGPU_PTE_SYSTEM) { 899 value = amdgpu_vm_map_gart(ib->ring->adev, addr); 900 value &= 0xFFFFFFFFFFFFF000ULL; 901 } else if (flags & AMDGPU_PTE_VALID) { 902 value = addr; 903 } else { 904 value = 0; 905 } 906 addr += incr; 907 value |= flags; 908 ib->ptr[ib->length_dw++] = value; 909 ib->ptr[ib->length_dw++] = upper_32_bits(value); 910 } 911 } 912 } 913 914 /** 915 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA 916 * 917 * @ib: indirect buffer to fill with commands 918 * @pe: addr of the page entry 919 * @addr: dst addr to write into pe 920 * @count: number of page entries to update 921 * @incr: increase next addr by incr bytes 922 * @flags: access flags 923 * 924 * Update the page tables using sDMA (CIK). 925 */ 926 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, 927 uint64_t pe, 928 uint64_t addr, unsigned count, 929 uint32_t incr, uint32_t flags) 930 { 931 uint64_t value; 932 unsigned ndw; 933 934 while (count) { 935 ndw = count; 936 if (ndw > 0x7FFFF) 937 ndw = 0x7FFFF; 938 939 if (flags & AMDGPU_PTE_VALID) 940 value = addr; 941 else 942 value = 0; 943 944 /* for physically contiguous pages (vram) */ 945 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); 946 ib->ptr[ib->length_dw++] = pe; /* dst addr */ 947 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 948 ib->ptr[ib->length_dw++] = flags; /* mask */ 949 ib->ptr[ib->length_dw++] = 0; 950 ib->ptr[ib->length_dw++] = value; /* value */ 951 ib->ptr[ib->length_dw++] = upper_32_bits(value); 952 ib->ptr[ib->length_dw++] = incr; /* increment size */ 953 ib->ptr[ib->length_dw++] = 0; 954 ib->ptr[ib->length_dw++] = ndw; /* number of entries */ 955 956 pe += ndw * 8; 957 addr += ndw * incr; 958 count -= ndw; 959 } 960 } 961 962 /** 963 * sdma_v3_0_vm_pad_ib - pad the IB to the required number of dw 964 * 965 * @ib: indirect buffer to fill with padding 966 * 967 */ 968 static void sdma_v3_0_vm_pad_ib(struct amdgpu_ib *ib) 969 { 970 while (ib->length_dw & 0x7) 971 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 972 } 973 974 /** 975 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA 976 * 977 * @ring: amdgpu_ring pointer 978 * @vm: amdgpu_vm pointer 979 * 980 * Update the page table base and flush the VM TLB 981 * using sDMA (VI). 982 */ 983 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 984 unsigned vm_id, uint64_t pd_addr) 985 { 986 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 987 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 988 if (vm_id < 8) { 989 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); 990 } else { 991 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); 992 } 993 amdgpu_ring_write(ring, pd_addr >> 12); 994 995 /* flush TLB */ 996 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 997 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 998 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 999 amdgpu_ring_write(ring, 1 << vm_id); 1000 1001 /* wait for flush */ 1002 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1003 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1004 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ 1005 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 1006 amdgpu_ring_write(ring, 0); 1007 amdgpu_ring_write(ring, 0); /* reference */ 1008 amdgpu_ring_write(ring, 0); /* mask */ 1009 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1010 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 1011 } 1012 1013 static int sdma_v3_0_early_init(void *handle) 1014 { 1015 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1016 1017 sdma_v3_0_set_ring_funcs(adev); 1018 sdma_v3_0_set_buffer_funcs(adev); 1019 sdma_v3_0_set_vm_pte_funcs(adev); 1020 sdma_v3_0_set_irq_funcs(adev); 1021 1022 return 0; 1023 } 1024 1025 static int sdma_v3_0_sw_init(void *handle) 1026 { 1027 struct amdgpu_ring *ring; 1028 int r; 1029 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1030 1031 /* SDMA trap event */ 1032 r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq); 1033 if (r) 1034 return r; 1035 1036 /* SDMA Privileged inst */ 1037 r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq); 1038 if (r) 1039 return r; 1040 1041 /* SDMA Privileged inst */ 1042 r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq); 1043 if (r) 1044 return r; 1045 1046 r = sdma_v3_0_init_microcode(adev); 1047 if (r) { 1048 DRM_ERROR("Failed to load sdma firmware!\n"); 1049 return r; 1050 } 1051 1052 ring = &adev->sdma[0].ring; 1053 ring->ring_obj = NULL; 1054 ring->use_doorbell = true; 1055 ring->doorbell_index = AMDGPU_DOORBELL_sDMA_ENGINE0; 1056 1057 ring = &adev->sdma[1].ring; 1058 ring->ring_obj = NULL; 1059 ring->use_doorbell = true; 1060 ring->doorbell_index = AMDGPU_DOORBELL_sDMA_ENGINE1; 1061 1062 ring = &adev->sdma[0].ring; 1063 sprintf(ring->name, "sdma0"); 1064 r = amdgpu_ring_init(adev, ring, 256 * 1024, 1065 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, 1066 &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0, 1067 AMDGPU_RING_TYPE_SDMA); 1068 if (r) 1069 return r; 1070 1071 ring = &adev->sdma[1].ring; 1072 sprintf(ring->name, "sdma1"); 1073 r = amdgpu_ring_init(adev, ring, 256 * 1024, 1074 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, 1075 &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1, 1076 AMDGPU_RING_TYPE_SDMA); 1077 if (r) 1078 return r; 1079 1080 return r; 1081 } 1082 1083 static int sdma_v3_0_sw_fini(void *handle) 1084 { 1085 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1086 1087 amdgpu_ring_fini(&adev->sdma[0].ring); 1088 amdgpu_ring_fini(&adev->sdma[1].ring); 1089 1090 return 0; 1091 } 1092 1093 static int sdma_v3_0_hw_init(void *handle) 1094 { 1095 int r; 1096 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1097 1098 sdma_v3_0_init_golden_registers(adev); 1099 1100 r = sdma_v3_0_start(adev); 1101 if (r) 1102 return r; 1103 1104 return r; 1105 } 1106 1107 static int sdma_v3_0_hw_fini(void *handle) 1108 { 1109 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1110 1111 sdma_v3_0_ctx_switch_enable(adev, false); 1112 sdma_v3_0_enable(adev, false); 1113 1114 return 0; 1115 } 1116 1117 static int sdma_v3_0_suspend(void *handle) 1118 { 1119 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1120 1121 return sdma_v3_0_hw_fini(adev); 1122 } 1123 1124 static int sdma_v3_0_resume(void *handle) 1125 { 1126 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1127 1128 return sdma_v3_0_hw_init(adev); 1129 } 1130 1131 static bool sdma_v3_0_is_idle(void *handle) 1132 { 1133 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1134 u32 tmp = RREG32(mmSRBM_STATUS2); 1135 1136 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1137 SRBM_STATUS2__SDMA1_BUSY_MASK)) 1138 return false; 1139 1140 return true; 1141 } 1142 1143 static int sdma_v3_0_wait_for_idle(void *handle) 1144 { 1145 unsigned i; 1146 u32 tmp; 1147 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1148 1149 for (i = 0; i < adev->usec_timeout; i++) { 1150 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1151 SRBM_STATUS2__SDMA1_BUSY_MASK); 1152 1153 if (!tmp) 1154 return 0; 1155 udelay(1); 1156 } 1157 return -ETIMEDOUT; 1158 } 1159 1160 static void sdma_v3_0_print_status(void *handle) 1161 { 1162 int i, j; 1163 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1164 1165 dev_info(adev->dev, "VI SDMA registers\n"); 1166 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", 1167 RREG32(mmSRBM_STATUS2)); 1168 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 1169 dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n", 1170 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i])); 1171 dev_info(adev->dev, " SDMA%d_F32_CNTL=0x%08X\n", 1172 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i])); 1173 dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n", 1174 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i])); 1175 dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n", 1176 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i])); 1177 dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n", 1178 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i])); 1179 dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n", 1180 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i])); 1181 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n", 1182 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i])); 1183 dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n", 1184 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i])); 1185 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n", 1186 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i])); 1187 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n", 1188 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i])); 1189 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n", 1190 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i])); 1191 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n", 1192 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i])); 1193 dev_info(adev->dev, " SDMA%d_GFX_DOORBELL=0x%08X\n", 1194 i, RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i])); 1195 mutex_lock(&adev->srbm_mutex); 1196 for (j = 0; j < 16; j++) { 1197 vi_srbm_select(adev, 0, 0, 0, j); 1198 dev_info(adev->dev, " VM %d:\n", j); 1199 dev_info(adev->dev, " SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n", 1200 i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i])); 1201 dev_info(adev->dev, " SDMA%d_GFX_APE1_CNTL=0x%08X\n", 1202 i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i])); 1203 } 1204 vi_srbm_select(adev, 0, 0, 0, 0); 1205 mutex_unlock(&adev->srbm_mutex); 1206 } 1207 } 1208 1209 static int sdma_v3_0_soft_reset(void *handle) 1210 { 1211 u32 srbm_soft_reset = 0; 1212 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1213 u32 tmp = RREG32(mmSRBM_STATUS2); 1214 1215 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { 1216 /* sdma0 */ 1217 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); 1218 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); 1219 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); 1220 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1221 } 1222 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) { 1223 /* sdma1 */ 1224 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); 1225 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); 1226 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); 1227 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1228 } 1229 1230 if (srbm_soft_reset) { 1231 sdma_v3_0_print_status((void *)adev); 1232 1233 tmp = RREG32(mmSRBM_SOFT_RESET); 1234 tmp |= srbm_soft_reset; 1235 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1236 WREG32(mmSRBM_SOFT_RESET, tmp); 1237 tmp = RREG32(mmSRBM_SOFT_RESET); 1238 1239 udelay(50); 1240 1241 tmp &= ~srbm_soft_reset; 1242 WREG32(mmSRBM_SOFT_RESET, tmp); 1243 tmp = RREG32(mmSRBM_SOFT_RESET); 1244 1245 /* Wait a little for things to settle down */ 1246 udelay(50); 1247 1248 sdma_v3_0_print_status((void *)adev); 1249 } 1250 1251 return 0; 1252 } 1253 1254 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev, 1255 struct amdgpu_irq_src *source, 1256 unsigned type, 1257 enum amdgpu_interrupt_state state) 1258 { 1259 u32 sdma_cntl; 1260 1261 switch (type) { 1262 case AMDGPU_SDMA_IRQ_TRAP0: 1263 switch (state) { 1264 case AMDGPU_IRQ_STATE_DISABLE: 1265 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1266 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1267 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1268 break; 1269 case AMDGPU_IRQ_STATE_ENABLE: 1270 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1271 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1272 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1273 break; 1274 default: 1275 break; 1276 } 1277 break; 1278 case AMDGPU_SDMA_IRQ_TRAP1: 1279 switch (state) { 1280 case AMDGPU_IRQ_STATE_DISABLE: 1281 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1282 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1283 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1284 break; 1285 case AMDGPU_IRQ_STATE_ENABLE: 1286 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1287 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1288 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1289 break; 1290 default: 1291 break; 1292 } 1293 break; 1294 default: 1295 break; 1296 } 1297 return 0; 1298 } 1299 1300 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev, 1301 struct amdgpu_irq_src *source, 1302 struct amdgpu_iv_entry *entry) 1303 { 1304 u8 instance_id, queue_id; 1305 1306 instance_id = (entry->ring_id & 0x3) >> 0; 1307 queue_id = (entry->ring_id & 0xc) >> 2; 1308 DRM_DEBUG("IH: SDMA trap\n"); 1309 switch (instance_id) { 1310 case 0: 1311 switch (queue_id) { 1312 case 0: 1313 amdgpu_fence_process(&adev->sdma[0].ring); 1314 break; 1315 case 1: 1316 /* XXX compute */ 1317 break; 1318 case 2: 1319 /* XXX compute */ 1320 break; 1321 } 1322 break; 1323 case 1: 1324 switch (queue_id) { 1325 case 0: 1326 amdgpu_fence_process(&adev->sdma[1].ring); 1327 break; 1328 case 1: 1329 /* XXX compute */ 1330 break; 1331 case 2: 1332 /* XXX compute */ 1333 break; 1334 } 1335 break; 1336 } 1337 return 0; 1338 } 1339 1340 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1341 struct amdgpu_irq_src *source, 1342 struct amdgpu_iv_entry *entry) 1343 { 1344 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1345 schedule_work(&adev->reset_work); 1346 return 0; 1347 } 1348 1349 static int sdma_v3_0_set_clockgating_state(void *handle, 1350 enum amd_clockgating_state state) 1351 { 1352 return 0; 1353 } 1354 1355 static int sdma_v3_0_set_powergating_state(void *handle, 1356 enum amd_powergating_state state) 1357 { 1358 return 0; 1359 } 1360 1361 const struct amd_ip_funcs sdma_v3_0_ip_funcs = { 1362 .early_init = sdma_v3_0_early_init, 1363 .late_init = NULL, 1364 .sw_init = sdma_v3_0_sw_init, 1365 .sw_fini = sdma_v3_0_sw_fini, 1366 .hw_init = sdma_v3_0_hw_init, 1367 .hw_fini = sdma_v3_0_hw_fini, 1368 .suspend = sdma_v3_0_suspend, 1369 .resume = sdma_v3_0_resume, 1370 .is_idle = sdma_v3_0_is_idle, 1371 .wait_for_idle = sdma_v3_0_wait_for_idle, 1372 .soft_reset = sdma_v3_0_soft_reset, 1373 .print_status = sdma_v3_0_print_status, 1374 .set_clockgating_state = sdma_v3_0_set_clockgating_state, 1375 .set_powergating_state = sdma_v3_0_set_powergating_state, 1376 }; 1377 1378 /** 1379 * sdma_v3_0_ring_is_lockup - Check if the DMA engine is locked up 1380 * 1381 * @ring: amdgpu_ring structure holding ring information 1382 * 1383 * Check if the async DMA engine is locked up (VI). 1384 * Returns true if the engine appears to be locked up, false if not. 1385 */ 1386 static bool sdma_v3_0_ring_is_lockup(struct amdgpu_ring *ring) 1387 { 1388 1389 if (sdma_v3_0_is_idle(ring->adev)) { 1390 amdgpu_ring_lockup_update(ring); 1391 return false; 1392 } 1393 return amdgpu_ring_test_lockup(ring); 1394 } 1395 1396 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { 1397 .get_rptr = sdma_v3_0_ring_get_rptr, 1398 .get_wptr = sdma_v3_0_ring_get_wptr, 1399 .set_wptr = sdma_v3_0_ring_set_wptr, 1400 .parse_cs = NULL, 1401 .emit_ib = sdma_v3_0_ring_emit_ib, 1402 .emit_fence = sdma_v3_0_ring_emit_fence, 1403 .emit_semaphore = sdma_v3_0_ring_emit_semaphore, 1404 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, 1405 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, 1406 .test_ring = sdma_v3_0_ring_test_ring, 1407 .test_ib = sdma_v3_0_ring_test_ib, 1408 .is_lockup = sdma_v3_0_ring_is_lockup, 1409 }; 1410 1411 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev) 1412 { 1413 adev->sdma[0].ring.funcs = &sdma_v3_0_ring_funcs; 1414 adev->sdma[1].ring.funcs = &sdma_v3_0_ring_funcs; 1415 } 1416 1417 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = { 1418 .set = sdma_v3_0_set_trap_irq_state, 1419 .process = sdma_v3_0_process_trap_irq, 1420 }; 1421 1422 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = { 1423 .process = sdma_v3_0_process_illegal_inst_irq, 1424 }; 1425 1426 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev) 1427 { 1428 adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1429 adev->sdma_trap_irq.funcs = &sdma_v3_0_trap_irq_funcs; 1430 adev->sdma_illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs; 1431 } 1432 1433 /** 1434 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine 1435 * 1436 * @ring: amdgpu_ring structure holding ring information 1437 * @src_offset: src GPU address 1438 * @dst_offset: dst GPU address 1439 * @byte_count: number of bytes to xfer 1440 * 1441 * Copy GPU buffers using the DMA engine (VI). 1442 * Used by the amdgpu ttm implementation to move pages if 1443 * registered as the asic copy callback. 1444 */ 1445 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ring *ring, 1446 uint64_t src_offset, 1447 uint64_t dst_offset, 1448 uint32_t byte_count) 1449 { 1450 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1451 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR)); 1452 amdgpu_ring_write(ring, byte_count); 1453 amdgpu_ring_write(ring, 0); /* src/dst endian swap */ 1454 amdgpu_ring_write(ring, lower_32_bits(src_offset)); 1455 amdgpu_ring_write(ring, upper_32_bits(src_offset)); 1456 amdgpu_ring_write(ring, lower_32_bits(dst_offset)); 1457 amdgpu_ring_write(ring, upper_32_bits(dst_offset)); 1458 } 1459 1460 /** 1461 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine 1462 * 1463 * @ring: amdgpu_ring structure holding ring information 1464 * @src_data: value to write to buffer 1465 * @dst_offset: dst GPU address 1466 * @byte_count: number of bytes to xfer 1467 * 1468 * Fill GPU buffers using the DMA engine (VI). 1469 */ 1470 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ring *ring, 1471 uint32_t src_data, 1472 uint64_t dst_offset, 1473 uint32_t byte_count) 1474 { 1475 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL)); 1476 amdgpu_ring_write(ring, lower_32_bits(dst_offset)); 1477 amdgpu_ring_write(ring, upper_32_bits(dst_offset)); 1478 amdgpu_ring_write(ring, src_data); 1479 amdgpu_ring_write(ring, byte_count); 1480 } 1481 1482 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = { 1483 .copy_max_bytes = 0x1fffff, 1484 .copy_num_dw = 7, 1485 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer, 1486 1487 .fill_max_bytes = 0x1fffff, 1488 .fill_num_dw = 5, 1489 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer, 1490 }; 1491 1492 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) 1493 { 1494 if (adev->mman.buffer_funcs == NULL) { 1495 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs; 1496 adev->mman.buffer_funcs_ring = &adev->sdma[0].ring; 1497 } 1498 } 1499 1500 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { 1501 .copy_pte = sdma_v3_0_vm_copy_pte, 1502 .write_pte = sdma_v3_0_vm_write_pte, 1503 .set_pte_pde = sdma_v3_0_vm_set_pte_pde, 1504 .pad_ib = sdma_v3_0_vm_pad_ib, 1505 }; 1506 1507 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1508 { 1509 if (adev->vm_manager.vm_pte_funcs == NULL) { 1510 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; 1511 adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring; 1512 } 1513 } 1514