1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 25 #include <linux/delay.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 #include "vi.h" 33 #include "vid.h" 34 35 #include "oss/oss_3_0_d.h" 36 #include "oss/oss_3_0_sh_mask.h" 37 38 #include "gmc/gmc_8_1_d.h" 39 #include "gmc/gmc_8_1_sh_mask.h" 40 41 #include "gca/gfx_8_0_d.h" 42 #include "gca/gfx_8_0_enum.h" 43 #include "gca/gfx_8_0_sh_mask.h" 44 45 #include "bif/bif_5_0_d.h" 46 #include "bif/bif_5_0_sh_mask.h" 47 48 #include "tonga_sdma_pkt_open.h" 49 50 #include "ivsrcid/ivsrcid_vislands30.h" 51 52 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev); 53 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); 54 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); 55 56 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); 57 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin"); 58 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin"); 59 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); 60 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); 61 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); 62 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin"); 63 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin"); 65 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin"); 66 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin"); 67 MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin"); 68 MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin"); 69 MODULE_FIRMWARE("amdgpu/vegam_sdma.bin"); 70 MODULE_FIRMWARE("amdgpu/vegam_sdma1.bin"); 71 72 73 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 74 { 75 SDMA0_REGISTER_OFFSET, 76 SDMA1_REGISTER_OFFSET 77 }; 78 79 static const u32 golden_settings_tonga_a11[] = 80 { 81 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 82 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 83 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 84 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 85 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 86 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 87 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 88 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 89 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 90 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 91 }; 92 93 static const u32 tonga_mgcg_cgcg_init[] = 94 { 95 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 96 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 97 }; 98 99 static const u32 golden_settings_fiji_a10[] = 100 { 101 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 102 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 103 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 104 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 105 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 106 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 107 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 108 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 109 }; 110 111 static const u32 fiji_mgcg_cgcg_init[] = 112 { 113 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 114 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 115 }; 116 117 static const u32 golden_settings_polaris11_a11[] = 118 { 119 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 120 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 121 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 122 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 123 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 124 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 125 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 126 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 127 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 128 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 129 }; 130 131 static const u32 golden_settings_polaris10_a11[] = 132 { 133 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 134 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 135 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 136 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 137 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 138 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 139 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 140 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 141 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 142 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 143 }; 144 145 static const u32 cz_golden_settings_a11[] = 146 { 147 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 148 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 149 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 150 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 151 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 152 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 153 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 154 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 155 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100, 156 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800, 157 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100, 158 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100, 159 }; 160 161 static const u32 cz_mgcg_cgcg_init[] = 162 { 163 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 164 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 165 }; 166 167 static const u32 stoney_golden_settings_a11[] = 168 { 169 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 170 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 171 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 172 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 173 }; 174 175 static const u32 stoney_mgcg_cgcg_init[] = 176 { 177 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100, 178 }; 179 180 /* 181 * sDMA - System DMA 182 * Starting with CIK, the GPU has new asynchronous 183 * DMA engines. These engines are used for compute 184 * and gfx. There are two DMA engines (SDMA0, SDMA1) 185 * and each one supports 1 ring buffer used for gfx 186 * and 2 queues used for compute. 187 * 188 * The programming model is very similar to the CP 189 * (ring buffer, IBs, etc.), but sDMA has it's own 190 * packet format that is different from the PM4 format 191 * used by the CP. sDMA supports copying data, writing 192 * embedded data, solid fills, and a number of other 193 * things. It also has support for tiling/detiling of 194 * buffers. 195 */ 196 197 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) 198 { 199 switch (adev->asic_type) { 200 case CHIP_FIJI: 201 amdgpu_device_program_register_sequence(adev, 202 fiji_mgcg_cgcg_init, 203 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 204 amdgpu_device_program_register_sequence(adev, 205 golden_settings_fiji_a10, 206 ARRAY_SIZE(golden_settings_fiji_a10)); 207 break; 208 case CHIP_TONGA: 209 amdgpu_device_program_register_sequence(adev, 210 tonga_mgcg_cgcg_init, 211 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 212 amdgpu_device_program_register_sequence(adev, 213 golden_settings_tonga_a11, 214 ARRAY_SIZE(golden_settings_tonga_a11)); 215 break; 216 case CHIP_POLARIS11: 217 case CHIP_POLARIS12: 218 case CHIP_VEGAM: 219 amdgpu_device_program_register_sequence(adev, 220 golden_settings_polaris11_a11, 221 ARRAY_SIZE(golden_settings_polaris11_a11)); 222 break; 223 case CHIP_POLARIS10: 224 amdgpu_device_program_register_sequence(adev, 225 golden_settings_polaris10_a11, 226 ARRAY_SIZE(golden_settings_polaris10_a11)); 227 break; 228 case CHIP_CARRIZO: 229 amdgpu_device_program_register_sequence(adev, 230 cz_mgcg_cgcg_init, 231 ARRAY_SIZE(cz_mgcg_cgcg_init)); 232 amdgpu_device_program_register_sequence(adev, 233 cz_golden_settings_a11, 234 ARRAY_SIZE(cz_golden_settings_a11)); 235 break; 236 case CHIP_STONEY: 237 amdgpu_device_program_register_sequence(adev, 238 stoney_mgcg_cgcg_init, 239 ARRAY_SIZE(stoney_mgcg_cgcg_init)); 240 amdgpu_device_program_register_sequence(adev, 241 stoney_golden_settings_a11, 242 ARRAY_SIZE(stoney_golden_settings_a11)); 243 break; 244 default: 245 break; 246 } 247 } 248 249 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev) 250 { 251 int i; 252 253 for (i = 0; i < adev->sdma.num_instances; i++) 254 amdgpu_ucode_release(&adev->sdma.instance[i].fw); 255 } 256 257 /** 258 * sdma_v3_0_init_microcode - load ucode images from disk 259 * 260 * @adev: amdgpu_device pointer 261 * 262 * Use the firmware interface to load the ucode images into 263 * the driver (not loaded into hw). 264 * Returns 0 on success, error on failure. 265 */ 266 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) 267 { 268 const char *chip_name; 269 int err = 0, i; 270 struct amdgpu_firmware_info *info = NULL; 271 const struct common_firmware_header *header = NULL; 272 const struct sdma_firmware_header_v1_0 *hdr; 273 274 DRM_DEBUG("\n"); 275 276 switch (adev->asic_type) { 277 case CHIP_TONGA: 278 chip_name = "tonga"; 279 break; 280 case CHIP_FIJI: 281 chip_name = "fiji"; 282 break; 283 case CHIP_POLARIS10: 284 chip_name = "polaris10"; 285 break; 286 case CHIP_POLARIS11: 287 chip_name = "polaris11"; 288 break; 289 case CHIP_POLARIS12: 290 chip_name = "polaris12"; 291 break; 292 case CHIP_VEGAM: 293 chip_name = "vegam"; 294 break; 295 case CHIP_CARRIZO: 296 chip_name = "carrizo"; 297 break; 298 case CHIP_STONEY: 299 chip_name = "stoney"; 300 break; 301 default: 302 return -EINVAL; 303 } 304 305 for (i = 0; i < adev->sdma.num_instances; i++) { 306 if (i == 0) 307 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw, 308 AMDGPU_UCODE_REQUIRED, 309 "amdgpu/%s_sdma.bin", chip_name); 310 else 311 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw, 312 AMDGPU_UCODE_REQUIRED, 313 "amdgpu/%s_sdma1.bin", chip_name); 314 if (err) 315 goto out; 316 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 317 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 318 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 319 if (adev->sdma.instance[i].feature_version >= 20) 320 adev->sdma.instance[i].burst_nop = true; 321 322 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 323 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 324 info->fw = adev->sdma.instance[i].fw; 325 header = (const struct common_firmware_header *)info->fw->data; 326 adev->firmware.fw_size += 327 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 328 329 } 330 out: 331 if (err) { 332 pr_err("sdma_v3_0: Failed to load firmware \"%s_sdma%s.bin\"\n", 333 chip_name, i == 0 ? "" : "1"); 334 for (i = 0; i < adev->sdma.num_instances; i++) 335 amdgpu_ucode_release(&adev->sdma.instance[i].fw); 336 } 337 return err; 338 } 339 340 /** 341 * sdma_v3_0_ring_get_rptr - get the current read pointer 342 * 343 * @ring: amdgpu ring pointer 344 * 345 * Get the current rptr from the hardware (VI+). 346 */ 347 static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring) 348 { 349 /* XXX check if swapping is necessary on BE */ 350 return *ring->rptr_cpu_addr >> 2; 351 } 352 353 /** 354 * sdma_v3_0_ring_get_wptr - get the current write pointer 355 * 356 * @ring: amdgpu ring pointer 357 * 358 * Get the current wptr from the hardware (VI+). 359 */ 360 static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring) 361 { 362 struct amdgpu_device *adev = ring->adev; 363 u32 wptr; 364 365 if (ring->use_doorbell || ring->use_pollmem) { 366 /* XXX check if swapping is necessary on BE */ 367 wptr = *ring->wptr_cpu_addr >> 2; 368 } else { 369 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; 370 } 371 372 return wptr; 373 } 374 375 /** 376 * sdma_v3_0_ring_set_wptr - commit the write pointer 377 * 378 * @ring: amdgpu ring pointer 379 * 380 * Write the wptr back to the hardware (VI+). 381 */ 382 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) 383 { 384 struct amdgpu_device *adev = ring->adev; 385 386 if (ring->use_doorbell) { 387 u32 *wb = (u32 *)ring->wptr_cpu_addr; 388 /* XXX check if swapping is necessary on BE */ 389 WRITE_ONCE(*wb, ring->wptr << 2); 390 WDOORBELL32(ring->doorbell_index, ring->wptr << 2); 391 } else if (ring->use_pollmem) { 392 u32 *wb = (u32 *)ring->wptr_cpu_addr; 393 394 WRITE_ONCE(*wb, ring->wptr << 2); 395 } else { 396 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2); 397 } 398 } 399 400 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 401 { 402 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 403 int i; 404 405 for (i = 0; i < count; i++) 406 if (sdma && sdma->burst_nop && (i == 0)) 407 amdgpu_ring_write(ring, ring->funcs->nop | 408 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 409 else 410 amdgpu_ring_write(ring, ring->funcs->nop); 411 } 412 413 /** 414 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine 415 * 416 * @ring: amdgpu ring pointer 417 * @job: job to retrieve vmid from 418 * @ib: IB object to schedule 419 * @flags: unused 420 * 421 * Schedule an IB in the DMA ring (VI). 422 */ 423 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, 424 struct amdgpu_job *job, 425 struct amdgpu_ib *ib, 426 uint32_t flags) 427 { 428 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 429 430 /* IB packet must end on a 8 DW boundary */ 431 sdma_v3_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 432 433 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 434 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 435 /* base must be 32 byte aligned */ 436 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 437 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 438 amdgpu_ring_write(ring, ib->length_dw); 439 amdgpu_ring_write(ring, 0); 440 amdgpu_ring_write(ring, 0); 441 442 } 443 444 /** 445 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 446 * 447 * @ring: amdgpu ring pointer 448 * 449 * Emit an hdp flush packet on the requested DMA ring. 450 */ 451 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 452 { 453 u32 ref_and_mask = 0; 454 455 if (ring->me == 0) 456 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); 457 else 458 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); 459 460 /* Hang workaround */ 461 amdgpu_ring_write(ring, SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP)); 462 463 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 464 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 465 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 466 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 467 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 468 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 469 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 470 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 471 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 472 } 473 474 /** 475 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring 476 * 477 * @ring: amdgpu ring pointer 478 * @addr: address 479 * @seq: sequence number 480 * @flags: fence related flags 481 * 482 * Add a DMA fence packet to the ring to write 483 * the fence seq number and DMA trap packet to generate 484 * an interrupt if needed (VI). 485 */ 486 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 487 unsigned flags) 488 { 489 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 490 491 /* Hang workaround */ 492 amdgpu_ring_write(ring, SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP)); 493 494 /* write the fence */ 495 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 496 amdgpu_ring_write(ring, lower_32_bits(addr)); 497 amdgpu_ring_write(ring, upper_32_bits(addr)); 498 amdgpu_ring_write(ring, lower_32_bits(seq)); 499 500 /* optionally write high bits as well */ 501 if (write64bit) { 502 /* Hang workaround */ 503 amdgpu_ring_write(ring, SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP)); 504 505 addr += 4; 506 507 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 508 amdgpu_ring_write(ring, lower_32_bits(addr)); 509 amdgpu_ring_write(ring, upper_32_bits(addr)); 510 amdgpu_ring_write(ring, upper_32_bits(seq)); 511 } 512 513 /* generate an interrupt */ 514 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 515 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 516 } 517 518 /** 519 * sdma_v3_0_gfx_stop - stop the gfx async dma engines 520 * 521 * @adev: amdgpu_device pointer 522 * 523 * Stop the gfx async dma ring buffers (VI). 524 */ 525 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev) 526 { 527 u32 rb_cntl, ib_cntl; 528 int i; 529 530 for (i = 0; i < adev->sdma.num_instances; i++) { 531 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 532 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 533 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 534 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 535 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 536 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 537 } 538 } 539 540 /** 541 * sdma_v3_0_rlc_stop - stop the compute async dma engines 542 * 543 * @adev: amdgpu_device pointer 544 * 545 * Stop the compute async dma queues (VI). 546 */ 547 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev) 548 { 549 /* XXX todo */ 550 } 551 552 /** 553 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch 554 * 555 * @adev: amdgpu_device pointer 556 * @enable: enable/disable the DMA MEs context switch. 557 * 558 * Halt or unhalt the async dma engines context switch (VI). 559 */ 560 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 561 { 562 u32 f32_cntl, phase_quantum = 0; 563 int i; 564 565 if (amdgpu_sdma_phase_quantum) { 566 unsigned value = amdgpu_sdma_phase_quantum; 567 unsigned unit = 0; 568 569 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 570 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 571 value = (value + 1) >> 1; 572 unit++; 573 } 574 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 575 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 576 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 577 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 578 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 579 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 580 WARN_ONCE(1, 581 "clamping sdma_phase_quantum to %uK clock cycles\n", 582 value << unit); 583 } 584 phase_quantum = 585 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 586 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 587 } 588 589 for (i = 0; i < adev->sdma.num_instances; i++) { 590 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); 591 if (enable) { 592 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 593 AUTO_CTXSW_ENABLE, 1); 594 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 595 ATC_L1_ENABLE, 1); 596 if (amdgpu_sdma_phase_quantum) { 597 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], 598 phase_quantum); 599 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], 600 phase_quantum); 601 } 602 } else { 603 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 604 AUTO_CTXSW_ENABLE, 0); 605 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 606 ATC_L1_ENABLE, 1); 607 } 608 609 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); 610 } 611 } 612 613 /** 614 * sdma_v3_0_enable - stop the async dma engines 615 * 616 * @adev: amdgpu_device pointer 617 * @enable: enable/disable the DMA MEs. 618 * 619 * Halt or unhalt the async dma engines (VI). 620 */ 621 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable) 622 { 623 u32 f32_cntl; 624 int i; 625 626 if (!enable) { 627 sdma_v3_0_gfx_stop(adev); 628 sdma_v3_0_rlc_stop(adev); 629 } 630 631 for (i = 0; i < adev->sdma.num_instances; i++) { 632 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 633 if (enable) 634 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); 635 else 636 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 637 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); 638 } 639 } 640 641 /** 642 * sdma_v3_0_gfx_resume - setup and start the async dma engines 643 * 644 * @adev: amdgpu_device pointer 645 * 646 * Set up the gfx DMA ring buffers and enable them (VI). 647 * Returns 0 for success, error for failure. 648 */ 649 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) 650 { 651 struct amdgpu_ring *ring; 652 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 653 u32 rb_bufsz; 654 u32 doorbell; 655 u64 wptr_gpu_addr; 656 int i, j, r; 657 658 for (i = 0; i < adev->sdma.num_instances; i++) { 659 ring = &adev->sdma.instance[i].ring; 660 amdgpu_ring_clear_ring(ring); 661 662 mutex_lock(&adev->srbm_mutex); 663 for (j = 0; j < 16; j++) { 664 vi_srbm_select(adev, 0, 0, 0, j); 665 /* SDMA GFX */ 666 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 667 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 668 } 669 vi_srbm_select(adev, 0, 0, 0, 0); 670 mutex_unlock(&adev->srbm_mutex); 671 672 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], 673 adev->gfx.config.gb_addr_config & 0x70); 674 675 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 676 677 /* Set ring buffer size in dwords */ 678 rb_bufsz = order_base_2(ring->ring_size / 4); 679 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 680 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 681 #ifdef __BIG_ENDIAN 682 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 683 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 684 RPTR_WRITEBACK_SWAP_ENABLE, 1); 685 #endif 686 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 687 688 /* Initialize the ring buffer's read and write pointers */ 689 ring->wptr = 0; 690 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 691 sdma_v3_0_ring_set_wptr(ring); 692 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); 693 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); 694 695 /* set the wb address whether it's enabled or not */ 696 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 697 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 698 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 699 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 700 701 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 702 703 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 704 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 705 706 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); 707 708 if (ring->use_doorbell) { 709 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, 710 OFFSET, ring->doorbell_index); 711 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 712 } else { 713 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 714 } 715 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell); 716 717 /* setup the wptr shadow polling */ 718 wptr_gpu_addr = ring->wptr_gpu_addr; 719 720 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i], 721 lower_32_bits(wptr_gpu_addr)); 722 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i], 723 upper_32_bits(wptr_gpu_addr)); 724 wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]); 725 if (ring->use_pollmem) { 726 /*wptr polling is not enough fast, directly clean the wptr register */ 727 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 728 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 729 SDMA0_GFX_RB_WPTR_POLL_CNTL, 730 ENABLE, 1); 731 } else { 732 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 733 SDMA0_GFX_RB_WPTR_POLL_CNTL, 734 ENABLE, 0); 735 } 736 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl); 737 738 /* enable DMA RB */ 739 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 740 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 741 742 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 743 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 744 #ifdef __BIG_ENDIAN 745 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 746 #endif 747 /* enable DMA IBs */ 748 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 749 } 750 751 /* unhalt the MEs */ 752 sdma_v3_0_enable(adev, true); 753 /* enable sdma ring preemption */ 754 sdma_v3_0_ctx_switch_enable(adev, true); 755 756 for (i = 0; i < adev->sdma.num_instances; i++) { 757 ring = &adev->sdma.instance[i].ring; 758 r = amdgpu_ring_test_helper(ring); 759 if (r) 760 return r; 761 } 762 763 return 0; 764 } 765 766 /** 767 * sdma_v3_0_rlc_resume - setup and start the async dma engines 768 * 769 * @adev: amdgpu_device pointer 770 * 771 * Set up the compute DMA queues and enable them (VI). 772 * Returns 0 for success, error for failure. 773 */ 774 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev) 775 { 776 /* XXX todo */ 777 return 0; 778 } 779 780 /** 781 * sdma_v3_0_start - setup and start the async dma engines 782 * 783 * @adev: amdgpu_device pointer 784 * 785 * Set up the DMA engines and enable them (VI). 786 * Returns 0 for success, error for failure. 787 */ 788 static int sdma_v3_0_start(struct amdgpu_device *adev) 789 { 790 int r; 791 792 /* disable sdma engine before programing it */ 793 sdma_v3_0_ctx_switch_enable(adev, false); 794 sdma_v3_0_enable(adev, false); 795 796 /* start the gfx rings and rlc compute queues */ 797 r = sdma_v3_0_gfx_resume(adev); 798 if (r) 799 return r; 800 r = sdma_v3_0_rlc_resume(adev); 801 if (r) 802 return r; 803 804 return 0; 805 } 806 807 /** 808 * sdma_v3_0_ring_test_ring - simple async dma engine test 809 * 810 * @ring: amdgpu_ring structure holding ring information 811 * 812 * Test the DMA engine by writing using it to write an 813 * value to memory. (VI). 814 * Returns 0 for success, error for failure. 815 */ 816 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) 817 { 818 struct amdgpu_device *adev = ring->adev; 819 unsigned i; 820 unsigned index; 821 int r; 822 u32 tmp; 823 u64 gpu_addr; 824 825 r = amdgpu_wb_get(adev, &index); 826 if (r) 827 return r; 828 829 gpu_addr = adev->wb.gpu_addr + (index * 4); 830 tmp = 0xCAFEDEAD; 831 adev->wb.wb[index] = cpu_to_le32(tmp); 832 833 r = amdgpu_ring_alloc(ring, 5); 834 if (r) 835 goto error_free_wb; 836 837 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 838 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 839 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 840 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 841 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 842 amdgpu_ring_write(ring, 0xDEADBEEF); 843 amdgpu_ring_commit(ring); 844 845 for (i = 0; i < adev->usec_timeout; i++) { 846 tmp = le32_to_cpu(adev->wb.wb[index]); 847 if (tmp == 0xDEADBEEF) 848 break; 849 udelay(1); 850 } 851 852 if (i >= adev->usec_timeout) 853 r = -ETIMEDOUT; 854 855 error_free_wb: 856 amdgpu_wb_free(adev, index); 857 return r; 858 } 859 860 /** 861 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine 862 * 863 * @ring: amdgpu_ring structure holding ring information 864 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 865 * 866 * Test a simple IB in the DMA ring (VI). 867 * Returns 0 on success, error on failure. 868 */ 869 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 870 { 871 struct amdgpu_device *adev = ring->adev; 872 struct amdgpu_ib ib; 873 struct dma_fence *f = NULL; 874 unsigned index; 875 u32 tmp = 0; 876 u64 gpu_addr; 877 long r; 878 879 r = amdgpu_wb_get(adev, &index); 880 if (r) 881 return r; 882 883 gpu_addr = adev->wb.gpu_addr + (index * 4); 884 tmp = 0xCAFEDEAD; 885 adev->wb.wb[index] = cpu_to_le32(tmp); 886 memset(&ib, 0, sizeof(ib)); 887 r = amdgpu_ib_get(adev, NULL, 256, 888 AMDGPU_IB_POOL_DIRECT, &ib); 889 if (r) 890 goto err0; 891 892 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 893 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 894 ib.ptr[1] = lower_32_bits(gpu_addr); 895 ib.ptr[2] = upper_32_bits(gpu_addr); 896 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); 897 ib.ptr[4] = 0xDEADBEEF; 898 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 899 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 900 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 901 ib.length_dw = 8; 902 903 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 904 if (r) 905 goto err1; 906 907 r = dma_fence_wait_timeout(f, false, timeout); 908 if (r == 0) { 909 r = -ETIMEDOUT; 910 goto err1; 911 } else if (r < 0) { 912 goto err1; 913 } 914 tmp = le32_to_cpu(adev->wb.wb[index]); 915 if (tmp == 0xDEADBEEF) 916 r = 0; 917 else 918 r = -EINVAL; 919 err1: 920 amdgpu_ib_free(&ib, NULL); 921 dma_fence_put(f); 922 err0: 923 amdgpu_wb_free(adev, index); 924 return r; 925 } 926 927 /** 928 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART 929 * 930 * @ib: indirect buffer to fill with commands 931 * @pe: addr of the page entry 932 * @src: src addr to copy from 933 * @count: number of page entries to update 934 * 935 * Update PTEs by copying them from the GART using sDMA (CIK). 936 */ 937 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib, 938 uint64_t pe, uint64_t src, 939 unsigned count) 940 { 941 unsigned bytes = count * 8; 942 943 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 944 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 945 ib->ptr[ib->length_dw++] = bytes; 946 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 947 ib->ptr[ib->length_dw++] = lower_32_bits(src); 948 ib->ptr[ib->length_dw++] = upper_32_bits(src); 949 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 950 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 951 } 952 953 /** 954 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually 955 * 956 * @ib: indirect buffer to fill with commands 957 * @pe: addr of the page entry 958 * @value: dst addr to write into pe 959 * @count: number of page entries to update 960 * @incr: increase next addr by incr bytes 961 * 962 * Update PTEs by writing them manually using sDMA (CIK). 963 */ 964 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 965 uint64_t value, unsigned count, 966 uint32_t incr) 967 { 968 unsigned ndw = count * 2; 969 970 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 971 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 972 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 973 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 974 ib->ptr[ib->length_dw++] = ndw; 975 for (; ndw > 0; ndw -= 2) { 976 ib->ptr[ib->length_dw++] = lower_32_bits(value); 977 ib->ptr[ib->length_dw++] = upper_32_bits(value); 978 value += incr; 979 } 980 } 981 982 /** 983 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA 984 * 985 * @ib: indirect buffer to fill with commands 986 * @pe: addr of the page entry 987 * @addr: dst addr to write into pe 988 * @count: number of page entries to update 989 * @incr: increase next addr by incr bytes 990 * @flags: access flags 991 * 992 * Update the page tables using sDMA (CIK). 993 */ 994 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, 995 uint64_t addr, unsigned count, 996 uint32_t incr, uint64_t flags) 997 { 998 /* for physically contiguous pages (vram) */ 999 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); 1000 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1001 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1002 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1003 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1004 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1005 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1006 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1007 ib->ptr[ib->length_dw++] = 0; 1008 ib->ptr[ib->length_dw++] = count; /* number of entries */ 1009 } 1010 1011 /** 1012 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw 1013 * 1014 * @ring: amdgpu_ring structure holding ring information 1015 * @ib: indirect buffer to fill with padding 1016 * 1017 */ 1018 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1019 { 1020 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1021 u32 pad_count; 1022 int i; 1023 1024 pad_count = (-ib->length_dw) & 7; 1025 for (i = 0; i < pad_count; i++) 1026 if (sdma && sdma->burst_nop && (i == 0)) 1027 ib->ptr[ib->length_dw++] = 1028 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1029 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1030 else 1031 ib->ptr[ib->length_dw++] = 1032 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1033 } 1034 1035 /** 1036 * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline 1037 * 1038 * @ring: amdgpu_ring pointer 1039 * 1040 * Make sure all previous operations are completed (CIK). 1041 */ 1042 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1043 { 1044 uint32_t seq = ring->fence_drv.sync_seq; 1045 uint64_t addr = ring->fence_drv.gpu_addr; 1046 1047 /* Hang workaround */ 1048 amdgpu_ring_write(ring, SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP)); 1049 1050 /* wait for idle */ 1051 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1052 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1053 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1054 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1055 amdgpu_ring_write(ring, addr & 0xfffffffc); 1056 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1057 amdgpu_ring_write(ring, seq); /* reference */ 1058 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1059 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1060 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1061 } 1062 1063 /** 1064 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA 1065 * 1066 * @ring: amdgpu_ring pointer 1067 * @vmid: vmid number to use 1068 * @pd_addr: address 1069 * 1070 * Update the page table base and flush the VM TLB 1071 * using sDMA (VI). 1072 */ 1073 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1074 unsigned vmid, uint64_t pd_addr) 1075 { 1076 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1077 1078 /* Hang workaround */ 1079 amdgpu_ring_write(ring, SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP)); 1080 1081 /* wait for flush */ 1082 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1083 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1084 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ 1085 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 1086 amdgpu_ring_write(ring, 0); 1087 amdgpu_ring_write(ring, 0); /* reference */ 1088 amdgpu_ring_write(ring, 0); /* mask */ 1089 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1090 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 1091 } 1092 1093 static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring, 1094 uint32_t reg, uint32_t val) 1095 { 1096 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1097 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1098 amdgpu_ring_write(ring, reg); 1099 amdgpu_ring_write(ring, val); 1100 } 1101 1102 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { 1103 .copy_pte_num_dw = 7, 1104 .copy_pte = sdma_v3_0_vm_copy_pte, 1105 1106 .write_pte = sdma_v3_0_vm_write_pte, 1107 .set_pte_pde = sdma_v3_0_vm_set_pte_pde, 1108 }; 1109 1110 static int sdma_v3_0_early_init(struct amdgpu_ip_block *ip_block) 1111 { 1112 struct amdgpu_device *adev = ip_block->adev; 1113 int r; 1114 1115 switch (adev->asic_type) { 1116 case CHIP_STONEY: 1117 adev->sdma.num_instances = 1; 1118 break; 1119 default: 1120 adev->sdma.num_instances = SDMA_MAX_INSTANCE; 1121 break; 1122 } 1123 1124 r = sdma_v3_0_init_microcode(adev); 1125 if (r) 1126 return r; 1127 1128 sdma_v3_0_set_ring_funcs(adev); 1129 amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v3_0_vm_pte_funcs); 1130 sdma_v3_0_set_irq_funcs(adev); 1131 1132 return 0; 1133 } 1134 1135 static int sdma_v3_0_sw_init(struct amdgpu_ip_block *ip_block) 1136 { 1137 struct amdgpu_ring *ring; 1138 int r, i; 1139 struct amdgpu_device *adev = ip_block->adev; 1140 1141 /* SDMA trap event */ 1142 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP, 1143 &adev->sdma.trap_irq); 1144 if (r) 1145 return r; 1146 1147 /* SDMA Privileged inst */ 1148 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241, 1149 &adev->sdma.illegal_inst_irq); 1150 if (r) 1151 return r; 1152 1153 /* SDMA Privileged inst */ 1154 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE, 1155 &adev->sdma.illegal_inst_irq); 1156 if (r) 1157 return r; 1158 1159 for (i = 0; i < adev->sdma.num_instances; i++) { 1160 ring = &adev->sdma.instance[i].ring; 1161 ring->ring_obj = NULL; 1162 if (!amdgpu_sriov_vf(adev)) { 1163 ring->use_doorbell = true; 1164 ring->doorbell_index = adev->doorbell_index.sdma_engine[i]; 1165 } else { 1166 ring->use_pollmem = true; 1167 } 1168 1169 sprintf(ring->name, "sdma%d", i); 1170 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1171 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 : 1172 AMDGPU_SDMA_IRQ_INSTANCE1, 1173 AMDGPU_RING_PRIO_DEFAULT, NULL); 1174 if (r) 1175 return r; 1176 } 1177 1178 return r; 1179 } 1180 1181 static int sdma_v3_0_sw_fini(struct amdgpu_ip_block *ip_block) 1182 { 1183 struct amdgpu_device *adev = ip_block->adev; 1184 int i; 1185 1186 for (i = 0; i < adev->sdma.num_instances; i++) 1187 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1188 1189 sdma_v3_0_free_microcode(adev); 1190 return 0; 1191 } 1192 1193 static int sdma_v3_0_hw_init(struct amdgpu_ip_block *ip_block) 1194 { 1195 int r; 1196 struct amdgpu_device *adev = ip_block->adev; 1197 1198 sdma_v3_0_init_golden_registers(adev); 1199 1200 r = sdma_v3_0_start(adev); 1201 if (r) 1202 return r; 1203 1204 sdma_v3_0_set_buffer_funcs(adev); 1205 1206 return 0; 1207 } 1208 1209 static int sdma_v3_0_hw_fini(struct amdgpu_ip_block *ip_block) 1210 { 1211 struct amdgpu_device *adev = ip_block->adev; 1212 1213 sdma_v3_0_ctx_switch_enable(adev, false); 1214 sdma_v3_0_enable(adev, false); 1215 1216 return 0; 1217 } 1218 1219 static int sdma_v3_0_suspend(struct amdgpu_ip_block *ip_block) 1220 { 1221 return sdma_v3_0_hw_fini(ip_block); 1222 } 1223 1224 static int sdma_v3_0_resume(struct amdgpu_ip_block *ip_block) 1225 { 1226 return sdma_v3_0_hw_init(ip_block); 1227 } 1228 1229 static bool sdma_v3_0_is_idle(struct amdgpu_ip_block *ip_block) 1230 { 1231 struct amdgpu_device *adev = ip_block->adev; 1232 u32 tmp = RREG32(mmSRBM_STATUS2); 1233 1234 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1235 SRBM_STATUS2__SDMA1_BUSY_MASK)) 1236 return false; 1237 1238 return true; 1239 } 1240 1241 static int sdma_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1242 { 1243 unsigned i; 1244 u32 tmp; 1245 struct amdgpu_device *adev = ip_block->adev; 1246 1247 for (i = 0; i < adev->usec_timeout; i++) { 1248 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1249 SRBM_STATUS2__SDMA1_BUSY_MASK); 1250 1251 if (!tmp) 1252 return 0; 1253 udelay(1); 1254 } 1255 return -ETIMEDOUT; 1256 } 1257 1258 static int sdma_v3_0_soft_reset(struct amdgpu_ip_block *ip_block) 1259 { 1260 struct amdgpu_device *adev = ip_block->adev; 1261 u32 srbm_soft_reset = 0; 1262 u32 tmp; 1263 1264 if (!adev->sdma.srbm_soft_reset) 1265 return 0; 1266 1267 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1268 1269 if (srbm_soft_reset) { 1270 tmp = RREG32(mmSRBM_SOFT_RESET); 1271 tmp |= srbm_soft_reset; 1272 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1273 WREG32(mmSRBM_SOFT_RESET, tmp); 1274 tmp = RREG32(mmSRBM_SOFT_RESET); 1275 1276 udelay(50); 1277 1278 tmp &= ~srbm_soft_reset; 1279 WREG32(mmSRBM_SOFT_RESET, tmp); 1280 tmp = RREG32(mmSRBM_SOFT_RESET); 1281 1282 /* Wait a little for things to settle down */ 1283 udelay(50); 1284 } 1285 1286 return 0; 1287 } 1288 1289 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev, 1290 struct amdgpu_irq_src *source, 1291 unsigned type, 1292 enum amdgpu_interrupt_state state) 1293 { 1294 u32 sdma_cntl; 1295 1296 switch (type) { 1297 case AMDGPU_SDMA_IRQ_INSTANCE0: 1298 switch (state) { 1299 case AMDGPU_IRQ_STATE_DISABLE: 1300 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1301 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1302 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1303 break; 1304 case AMDGPU_IRQ_STATE_ENABLE: 1305 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1306 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1307 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1308 break; 1309 default: 1310 break; 1311 } 1312 break; 1313 case AMDGPU_SDMA_IRQ_INSTANCE1: 1314 switch (state) { 1315 case AMDGPU_IRQ_STATE_DISABLE: 1316 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1317 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1318 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1319 break; 1320 case AMDGPU_IRQ_STATE_ENABLE: 1321 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1322 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1323 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1324 break; 1325 default: 1326 break; 1327 } 1328 break; 1329 default: 1330 break; 1331 } 1332 return 0; 1333 } 1334 1335 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev, 1336 struct amdgpu_irq_src *source, 1337 struct amdgpu_iv_entry *entry) 1338 { 1339 u8 instance_id, queue_id; 1340 1341 instance_id = (entry->ring_id & 0x3) >> 0; 1342 queue_id = (entry->ring_id & 0xc) >> 2; 1343 DRM_DEBUG("IH: SDMA trap\n"); 1344 switch (instance_id) { 1345 case 0: 1346 switch (queue_id) { 1347 case 0: 1348 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1349 break; 1350 case 1: 1351 /* XXX compute */ 1352 break; 1353 case 2: 1354 /* XXX compute */ 1355 break; 1356 } 1357 break; 1358 case 1: 1359 switch (queue_id) { 1360 case 0: 1361 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1362 break; 1363 case 1: 1364 /* XXX compute */ 1365 break; 1366 case 2: 1367 /* XXX compute */ 1368 break; 1369 } 1370 break; 1371 } 1372 return 0; 1373 } 1374 1375 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1376 struct amdgpu_irq_src *source, 1377 struct amdgpu_iv_entry *entry) 1378 { 1379 u8 instance_id, queue_id; 1380 1381 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1382 instance_id = (entry->ring_id & 0x3) >> 0; 1383 queue_id = (entry->ring_id & 0xc) >> 2; 1384 1385 if (instance_id <= 1 && queue_id == 0) 1386 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched); 1387 return 0; 1388 } 1389 1390 static void sdma_v3_0_update_sdma_medium_grain_clock_gating( 1391 struct amdgpu_device *adev, 1392 bool enable) 1393 { 1394 uint32_t temp, data; 1395 int i; 1396 1397 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1398 for (i = 0; i < adev->sdma.num_instances; i++) { 1399 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); 1400 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1401 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1402 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1403 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1404 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1405 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1406 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1407 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1408 if (data != temp) 1409 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); 1410 } 1411 } else { 1412 for (i = 0; i < adev->sdma.num_instances; i++) { 1413 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); 1414 data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1415 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1416 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1417 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1418 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1419 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1420 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1421 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK; 1422 1423 if (data != temp) 1424 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); 1425 } 1426 } 1427 } 1428 1429 static void sdma_v3_0_update_sdma_medium_grain_light_sleep( 1430 struct amdgpu_device *adev, 1431 bool enable) 1432 { 1433 uint32_t temp, data; 1434 int i; 1435 1436 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1437 for (i = 0; i < adev->sdma.num_instances; i++) { 1438 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1439 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1440 1441 if (temp != data) 1442 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1443 } 1444 } else { 1445 for (i = 0; i < adev->sdma.num_instances; i++) { 1446 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1447 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1448 1449 if (temp != data) 1450 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1451 } 1452 } 1453 } 1454 1455 static int sdma_v3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1456 enum amd_clockgating_state state) 1457 { 1458 struct amdgpu_device *adev = ip_block->adev; 1459 1460 if (amdgpu_sriov_vf(adev)) 1461 return 0; 1462 1463 switch (adev->asic_type) { 1464 case CHIP_FIJI: 1465 case CHIP_CARRIZO: 1466 case CHIP_STONEY: 1467 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev, 1468 state == AMD_CG_STATE_GATE); 1469 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev, 1470 state == AMD_CG_STATE_GATE); 1471 break; 1472 default: 1473 break; 1474 } 1475 return 0; 1476 } 1477 1478 static int sdma_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 1479 enum amd_powergating_state state) 1480 { 1481 return 0; 1482 } 1483 1484 static void sdma_v3_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1485 { 1486 struct amdgpu_device *adev = ip_block->adev; 1487 int data; 1488 1489 if (amdgpu_sriov_vf(adev)) 1490 *flags = 0; 1491 1492 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1493 data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]); 1494 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK)) 1495 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1496 1497 /* AMD_CG_SUPPORT_SDMA_LS */ 1498 data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]); 1499 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1500 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1501 } 1502 1503 static const struct amd_ip_funcs sdma_v3_0_ip_funcs = { 1504 .name = "sdma_v3_0", 1505 .early_init = sdma_v3_0_early_init, 1506 .sw_init = sdma_v3_0_sw_init, 1507 .sw_fini = sdma_v3_0_sw_fini, 1508 .hw_init = sdma_v3_0_hw_init, 1509 .hw_fini = sdma_v3_0_hw_fini, 1510 .suspend = sdma_v3_0_suspend, 1511 .resume = sdma_v3_0_resume, 1512 .is_idle = sdma_v3_0_is_idle, 1513 .wait_for_idle = sdma_v3_0_wait_for_idle, 1514 .soft_reset = sdma_v3_0_soft_reset, 1515 .set_clockgating_state = sdma_v3_0_set_clockgating_state, 1516 .set_powergating_state = sdma_v3_0_set_powergating_state, 1517 .get_clockgating_state = sdma_v3_0_get_clockgating_state, 1518 }; 1519 1520 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { 1521 .type = AMDGPU_RING_TYPE_SDMA, 1522 .align_mask = 0xf, 1523 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1524 .support_64bit_ptrs = false, 1525 .secure_submission_supported = true, 1526 .get_rptr = sdma_v3_0_ring_get_rptr, 1527 .get_wptr = sdma_v3_0_ring_get_wptr, 1528 .set_wptr = sdma_v3_0_ring_set_wptr, 1529 .emit_frame_size = 1530 6 + 1 + /* sdma_v3_0_ring_emit_hdp_flush */ 1531 3 + /* hdp invalidate */ 1532 6 + 1 + /* sdma_v3_0_ring_emit_pipeline_sync */ 1533 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + 1 + /* sdma_v3_0_ring_emit_vm_flush */ 1534 (10 + 1) * 3, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */ 1535 .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */ 1536 .emit_ib = sdma_v3_0_ring_emit_ib, 1537 .emit_fence = sdma_v3_0_ring_emit_fence, 1538 .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync, 1539 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, 1540 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, 1541 .test_ring = sdma_v3_0_ring_test_ring, 1542 .test_ib = sdma_v3_0_ring_test_ib, 1543 .insert_nop = sdma_v3_0_ring_insert_nop, 1544 .pad_ib = sdma_v3_0_ring_pad_ib, 1545 .emit_wreg = sdma_v3_0_ring_emit_wreg, 1546 }; 1547 1548 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev) 1549 { 1550 int i; 1551 1552 for (i = 0; i < adev->sdma.num_instances; i++) { 1553 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs; 1554 adev->sdma.instance[i].ring.me = i; 1555 } 1556 } 1557 1558 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = { 1559 .set = sdma_v3_0_set_trap_irq_state, 1560 .process = sdma_v3_0_process_trap_irq, 1561 }; 1562 1563 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = { 1564 .process = sdma_v3_0_process_illegal_inst_irq, 1565 }; 1566 1567 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev) 1568 { 1569 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1570 adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs; 1571 adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs; 1572 } 1573 1574 /** 1575 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine 1576 * 1577 * @ib: indirect buffer to copy to 1578 * @src_offset: src GPU address 1579 * @dst_offset: dst GPU address 1580 * @byte_count: number of bytes to xfer 1581 * @copy_flags: unused 1582 * 1583 * Copy GPU buffers using the DMA engine (VI). 1584 * Used by the amdgpu ttm implementation to move pages if 1585 * registered as the asic copy callback. 1586 */ 1587 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib, 1588 uint64_t src_offset, 1589 uint64_t dst_offset, 1590 uint32_t byte_count, 1591 uint32_t copy_flags) 1592 { 1593 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1594 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1595 ib->ptr[ib->length_dw++] = byte_count; 1596 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1597 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1598 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1599 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1600 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1601 } 1602 1603 /** 1604 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine 1605 * 1606 * @ib: indirect buffer to copy to 1607 * @src_data: value to write to buffer 1608 * @dst_offset: dst GPU address 1609 * @byte_count: number of bytes to xfer 1610 * 1611 * Fill GPU buffers using the DMA engine (VI). 1612 */ 1613 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib, 1614 uint32_t src_data, 1615 uint64_t dst_offset, 1616 uint32_t byte_count) 1617 { 1618 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1619 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1620 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1621 ib->ptr[ib->length_dw++] = src_data; 1622 ib->ptr[ib->length_dw++] = byte_count; 1623 } 1624 1625 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = { 1626 .copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */ 1627 .copy_num_dw = 7, 1628 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer, 1629 1630 .fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */ 1631 .fill_num_dw = 5, 1632 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer, 1633 }; 1634 1635 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) 1636 { 1637 amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v3_0_buffer_funcs); 1638 } 1639 1640 const struct amdgpu_ip_block_version sdma_v3_0_ip_block = 1641 { 1642 .type = AMD_IP_BLOCK_TYPE_SDMA, 1643 .major = 3, 1644 .minor = 0, 1645 .rev = 0, 1646 .funcs = &sdma_v3_0_ip_funcs, 1647 }; 1648 1649 const struct amdgpu_ip_block_version sdma_v3_1_ip_block = 1650 { 1651 .type = AMD_IP_BLOCK_TYPE_SDMA, 1652 .major = 3, 1653 .minor = 1, 1654 .rev = 0, 1655 .funcs = &sdma_v3_0_ip_funcs, 1656 }; 1657