1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 #include "vi.h" 30 #include "vid.h" 31 32 #include "oss/oss_3_0_d.h" 33 #include "oss/oss_3_0_sh_mask.h" 34 35 #include "gmc/gmc_8_1_d.h" 36 #include "gmc/gmc_8_1_sh_mask.h" 37 38 #include "gca/gfx_8_0_d.h" 39 #include "gca/gfx_8_0_enum.h" 40 #include "gca/gfx_8_0_sh_mask.h" 41 42 #include "bif/bif_5_0_d.h" 43 #include "bif/bif_5_0_sh_mask.h" 44 45 #include "tonga_sdma_pkt_open.h" 46 47 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev); 48 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); 49 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev); 50 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); 51 52 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); 53 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin"); 54 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin"); 55 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); 56 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); 57 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); 58 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin"); 59 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin"); 60 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin"); 61 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin"); 62 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin"); 63 64 65 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 66 { 67 SDMA0_REGISTER_OFFSET, 68 SDMA1_REGISTER_OFFSET 69 }; 70 71 static const u32 golden_settings_tonga_a11[] = 72 { 73 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 74 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 75 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 76 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 77 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 78 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 79 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 80 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 81 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 82 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 83 }; 84 85 static const u32 tonga_mgcg_cgcg_init[] = 86 { 87 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 88 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 89 }; 90 91 static const u32 golden_settings_fiji_a10[] = 92 { 93 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 94 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 95 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 96 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 97 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 98 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 99 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 100 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 101 }; 102 103 static const u32 fiji_mgcg_cgcg_init[] = 104 { 105 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 106 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 107 }; 108 109 static const u32 golden_settings_polaris11_a11[] = 110 { 111 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 112 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 113 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 114 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 115 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 116 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 117 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 118 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 119 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 120 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 121 }; 122 123 static const u32 golden_settings_polaris10_a11[] = 124 { 125 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 126 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 127 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 128 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 129 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 130 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 131 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 132 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 133 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 134 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 135 }; 136 137 static const u32 cz_golden_settings_a11[] = 138 { 139 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 140 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 141 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 142 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 143 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 144 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 145 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 146 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 147 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100, 148 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800, 149 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100, 150 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100, 151 }; 152 153 static const u32 cz_mgcg_cgcg_init[] = 154 { 155 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 156 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 157 }; 158 159 static const u32 stoney_golden_settings_a11[] = 160 { 161 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 162 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 163 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 164 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 165 }; 166 167 static const u32 stoney_mgcg_cgcg_init[] = 168 { 169 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100, 170 }; 171 172 /* 173 * sDMA - System DMA 174 * Starting with CIK, the GPU has new asynchronous 175 * DMA engines. These engines are used for compute 176 * and gfx. There are two DMA engines (SDMA0, SDMA1) 177 * and each one supports 1 ring buffer used for gfx 178 * and 2 queues used for compute. 179 * 180 * The programming model is very similar to the CP 181 * (ring buffer, IBs, etc.), but sDMA has it's own 182 * packet format that is different from the PM4 format 183 * used by the CP. sDMA supports copying data, writing 184 * embedded data, solid fills, and a number of other 185 * things. It also has support for tiling/detiling of 186 * buffers. 187 */ 188 189 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) 190 { 191 switch (adev->asic_type) { 192 case CHIP_FIJI: 193 amdgpu_program_register_sequence(adev, 194 fiji_mgcg_cgcg_init, 195 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); 196 amdgpu_program_register_sequence(adev, 197 golden_settings_fiji_a10, 198 (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); 199 break; 200 case CHIP_TONGA: 201 amdgpu_program_register_sequence(adev, 202 tonga_mgcg_cgcg_init, 203 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); 204 amdgpu_program_register_sequence(adev, 205 golden_settings_tonga_a11, 206 (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); 207 break; 208 case CHIP_POLARIS11: 209 amdgpu_program_register_sequence(adev, 210 golden_settings_polaris11_a11, 211 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); 212 break; 213 case CHIP_POLARIS10: 214 amdgpu_program_register_sequence(adev, 215 golden_settings_polaris10_a11, 216 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); 217 break; 218 case CHIP_CARRIZO: 219 amdgpu_program_register_sequence(adev, 220 cz_mgcg_cgcg_init, 221 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 222 amdgpu_program_register_sequence(adev, 223 cz_golden_settings_a11, 224 (const u32)ARRAY_SIZE(cz_golden_settings_a11)); 225 break; 226 case CHIP_STONEY: 227 amdgpu_program_register_sequence(adev, 228 stoney_mgcg_cgcg_init, 229 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); 230 amdgpu_program_register_sequence(adev, 231 stoney_golden_settings_a11, 232 (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); 233 break; 234 default: 235 break; 236 } 237 } 238 239 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev) 240 { 241 int i; 242 for (i = 0; i < adev->sdma.num_instances; i++) { 243 release_firmware(adev->sdma.instance[i].fw); 244 adev->sdma.instance[i].fw = NULL; 245 } 246 } 247 248 /** 249 * sdma_v3_0_init_microcode - load ucode images from disk 250 * 251 * @adev: amdgpu_device pointer 252 * 253 * Use the firmware interface to load the ucode images into 254 * the driver (not loaded into hw). 255 * Returns 0 on success, error on failure. 256 */ 257 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) 258 { 259 const char *chip_name; 260 char fw_name[30]; 261 int err = 0, i; 262 struct amdgpu_firmware_info *info = NULL; 263 const struct common_firmware_header *header = NULL; 264 const struct sdma_firmware_header_v1_0 *hdr; 265 266 DRM_DEBUG("\n"); 267 268 switch (adev->asic_type) { 269 case CHIP_TONGA: 270 chip_name = "tonga"; 271 break; 272 case CHIP_FIJI: 273 chip_name = "fiji"; 274 break; 275 case CHIP_POLARIS11: 276 chip_name = "polaris11"; 277 break; 278 case CHIP_POLARIS10: 279 chip_name = "polaris10"; 280 break; 281 case CHIP_CARRIZO: 282 chip_name = "carrizo"; 283 break; 284 case CHIP_STONEY: 285 chip_name = "stoney"; 286 break; 287 default: BUG(); 288 } 289 290 for (i = 0; i < adev->sdma.num_instances; i++) { 291 if (i == 0) 292 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 293 else 294 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 295 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 296 if (err) 297 goto out; 298 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 299 if (err) 300 goto out; 301 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 302 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 303 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 304 if (adev->sdma.instance[i].feature_version >= 20) 305 adev->sdma.instance[i].burst_nop = true; 306 307 if (adev->firmware.smu_load) { 308 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 309 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 310 info->fw = adev->sdma.instance[i].fw; 311 header = (const struct common_firmware_header *)info->fw->data; 312 adev->firmware.fw_size += 313 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 314 } 315 } 316 out: 317 if (err) { 318 printk(KERN_ERR 319 "sdma_v3_0: Failed to load firmware \"%s\"\n", 320 fw_name); 321 for (i = 0; i < adev->sdma.num_instances; i++) { 322 release_firmware(adev->sdma.instance[i].fw); 323 adev->sdma.instance[i].fw = NULL; 324 } 325 } 326 return err; 327 } 328 329 /** 330 * sdma_v3_0_ring_get_rptr - get the current read pointer 331 * 332 * @ring: amdgpu ring pointer 333 * 334 * Get the current rptr from the hardware (VI+). 335 */ 336 static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring) 337 { 338 /* XXX check if swapping is necessary on BE */ 339 return ring->adev->wb.wb[ring->rptr_offs] >> 2; 340 } 341 342 /** 343 * sdma_v3_0_ring_get_wptr - get the current write pointer 344 * 345 * @ring: amdgpu ring pointer 346 * 347 * Get the current wptr from the hardware (VI+). 348 */ 349 static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring) 350 { 351 struct amdgpu_device *adev = ring->adev; 352 u32 wptr; 353 354 if (ring->use_doorbell) { 355 /* XXX check if swapping is necessary on BE */ 356 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; 357 } else { 358 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; 359 360 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2; 361 } 362 363 return wptr; 364 } 365 366 /** 367 * sdma_v3_0_ring_set_wptr - commit the write pointer 368 * 369 * @ring: amdgpu ring pointer 370 * 371 * Write the wptr back to the hardware (VI+). 372 */ 373 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) 374 { 375 struct amdgpu_device *adev = ring->adev; 376 377 if (ring->use_doorbell) { 378 /* XXX check if swapping is necessary on BE */ 379 adev->wb.wb[ring->wptr_offs] = ring->wptr << 2; 380 WDOORBELL32(ring->doorbell_index, ring->wptr << 2); 381 } else { 382 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; 383 384 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2); 385 } 386 } 387 388 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 389 { 390 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 391 int i; 392 393 for (i = 0; i < count; i++) 394 if (sdma && sdma->burst_nop && (i == 0)) 395 amdgpu_ring_write(ring, ring->nop | 396 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 397 else 398 amdgpu_ring_write(ring, ring->nop); 399 } 400 401 /** 402 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine 403 * 404 * @ring: amdgpu ring pointer 405 * @ib: IB object to schedule 406 * 407 * Schedule an IB in the DMA ring (VI). 408 */ 409 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, 410 struct amdgpu_ib *ib, 411 unsigned vm_id, bool ctx_switch) 412 { 413 u32 vmid = vm_id & 0xf; 414 415 /* IB packet must end on a 8 DW boundary */ 416 sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8); 417 418 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 419 SDMA_PKT_INDIRECT_HEADER_VMID(vmid)); 420 /* base must be 32 byte aligned */ 421 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 422 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 423 amdgpu_ring_write(ring, ib->length_dw); 424 amdgpu_ring_write(ring, 0); 425 amdgpu_ring_write(ring, 0); 426 427 } 428 429 /** 430 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 431 * 432 * @ring: amdgpu ring pointer 433 * 434 * Emit an hdp flush packet on the requested DMA ring. 435 */ 436 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 437 { 438 u32 ref_and_mask = 0; 439 440 if (ring == &ring->adev->sdma.instance[0].ring) 441 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); 442 else 443 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); 444 445 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 446 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 447 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 448 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 449 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 450 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 451 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 452 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 453 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 454 } 455 456 static void sdma_v3_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 457 { 458 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 459 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 460 amdgpu_ring_write(ring, mmHDP_DEBUG0); 461 amdgpu_ring_write(ring, 1); 462 } 463 464 /** 465 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring 466 * 467 * @ring: amdgpu ring pointer 468 * @fence: amdgpu fence object 469 * 470 * Add a DMA fence packet to the ring to write 471 * the fence seq number and DMA trap packet to generate 472 * an interrupt if needed (VI). 473 */ 474 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 475 unsigned flags) 476 { 477 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 478 /* write the fence */ 479 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 480 amdgpu_ring_write(ring, lower_32_bits(addr)); 481 amdgpu_ring_write(ring, upper_32_bits(addr)); 482 amdgpu_ring_write(ring, lower_32_bits(seq)); 483 484 /* optionally write high bits as well */ 485 if (write64bit) { 486 addr += 4; 487 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 488 amdgpu_ring_write(ring, lower_32_bits(addr)); 489 amdgpu_ring_write(ring, upper_32_bits(addr)); 490 amdgpu_ring_write(ring, upper_32_bits(seq)); 491 } 492 493 /* generate an interrupt */ 494 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 495 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 496 } 497 498 /** 499 * sdma_v3_0_gfx_stop - stop the gfx async dma engines 500 * 501 * @adev: amdgpu_device pointer 502 * 503 * Stop the gfx async dma ring buffers (VI). 504 */ 505 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev) 506 { 507 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 508 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 509 u32 rb_cntl, ib_cntl; 510 int i; 511 512 if ((adev->mman.buffer_funcs_ring == sdma0) || 513 (adev->mman.buffer_funcs_ring == sdma1)) 514 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); 515 516 for (i = 0; i < adev->sdma.num_instances; i++) { 517 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 518 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 519 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 520 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 521 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 522 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 523 } 524 sdma0->ready = false; 525 sdma1->ready = false; 526 } 527 528 /** 529 * sdma_v3_0_rlc_stop - stop the compute async dma engines 530 * 531 * @adev: amdgpu_device pointer 532 * 533 * Stop the compute async dma queues (VI). 534 */ 535 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev) 536 { 537 /* XXX todo */ 538 } 539 540 /** 541 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch 542 * 543 * @adev: amdgpu_device pointer 544 * @enable: enable/disable the DMA MEs context switch. 545 * 546 * Halt or unhalt the async dma engines context switch (VI). 547 */ 548 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 549 { 550 u32 f32_cntl; 551 int i; 552 553 for (i = 0; i < adev->sdma.num_instances; i++) { 554 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); 555 if (enable) 556 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 557 AUTO_CTXSW_ENABLE, 1); 558 else 559 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 560 AUTO_CTXSW_ENABLE, 0); 561 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); 562 } 563 } 564 565 /** 566 * sdma_v3_0_enable - stop the async dma engines 567 * 568 * @adev: amdgpu_device pointer 569 * @enable: enable/disable the DMA MEs. 570 * 571 * Halt or unhalt the async dma engines (VI). 572 */ 573 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable) 574 { 575 u32 f32_cntl; 576 int i; 577 578 if (!enable) { 579 sdma_v3_0_gfx_stop(adev); 580 sdma_v3_0_rlc_stop(adev); 581 } 582 583 for (i = 0; i < adev->sdma.num_instances; i++) { 584 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 585 if (enable) 586 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); 587 else 588 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 589 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); 590 } 591 } 592 593 /** 594 * sdma_v3_0_gfx_resume - setup and start the async dma engines 595 * 596 * @adev: amdgpu_device pointer 597 * 598 * Set up the gfx DMA ring buffers and enable them (VI). 599 * Returns 0 for success, error for failure. 600 */ 601 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) 602 { 603 struct amdgpu_ring *ring; 604 u32 rb_cntl, ib_cntl; 605 u32 rb_bufsz; 606 u32 wb_offset; 607 u32 doorbell; 608 int i, j, r; 609 610 for (i = 0; i < adev->sdma.num_instances; i++) { 611 ring = &adev->sdma.instance[i].ring; 612 wb_offset = (ring->rptr_offs * 4); 613 614 mutex_lock(&adev->srbm_mutex); 615 for (j = 0; j < 16; j++) { 616 vi_srbm_select(adev, 0, 0, 0, j); 617 /* SDMA GFX */ 618 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 619 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 620 } 621 vi_srbm_select(adev, 0, 0, 0, 0); 622 mutex_unlock(&adev->srbm_mutex); 623 624 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], 625 adev->gfx.config.gb_addr_config & 0x70); 626 627 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 628 629 /* Set ring buffer size in dwords */ 630 rb_bufsz = order_base_2(ring->ring_size / 4); 631 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 632 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 633 #ifdef __BIG_ENDIAN 634 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 635 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 636 RPTR_WRITEBACK_SWAP_ENABLE, 1); 637 #endif 638 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 639 640 /* Initialize the ring buffer's read and write pointers */ 641 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 642 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 643 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); 644 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); 645 646 /* set the wb address whether it's enabled or not */ 647 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 648 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 649 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 650 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 651 652 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 653 654 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 655 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 656 657 ring->wptr = 0; 658 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); 659 660 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); 661 662 if (ring->use_doorbell) { 663 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, 664 OFFSET, ring->doorbell_index); 665 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 666 } else { 667 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 668 } 669 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell); 670 671 /* enable DMA RB */ 672 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 673 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 674 675 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 676 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 677 #ifdef __BIG_ENDIAN 678 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 679 #endif 680 /* enable DMA IBs */ 681 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 682 683 ring->ready = true; 684 } 685 686 /* unhalt the MEs */ 687 sdma_v3_0_enable(adev, true); 688 /* enable sdma ring preemption */ 689 sdma_v3_0_ctx_switch_enable(adev, true); 690 691 for (i = 0; i < adev->sdma.num_instances; i++) { 692 ring = &adev->sdma.instance[i].ring; 693 r = amdgpu_ring_test_ring(ring); 694 if (r) { 695 ring->ready = false; 696 return r; 697 } 698 699 if (adev->mman.buffer_funcs_ring == ring) 700 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); 701 } 702 703 return 0; 704 } 705 706 /** 707 * sdma_v3_0_rlc_resume - setup and start the async dma engines 708 * 709 * @adev: amdgpu_device pointer 710 * 711 * Set up the compute DMA queues and enable them (VI). 712 * Returns 0 for success, error for failure. 713 */ 714 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev) 715 { 716 /* XXX todo */ 717 return 0; 718 } 719 720 /** 721 * sdma_v3_0_load_microcode - load the sDMA ME ucode 722 * 723 * @adev: amdgpu_device pointer 724 * 725 * Loads the sDMA0/1 ucode. 726 * Returns 0 for success, -EINVAL if the ucode is not available. 727 */ 728 static int sdma_v3_0_load_microcode(struct amdgpu_device *adev) 729 { 730 const struct sdma_firmware_header_v1_0 *hdr; 731 const __le32 *fw_data; 732 u32 fw_size; 733 int i, j; 734 735 /* halt the MEs */ 736 sdma_v3_0_enable(adev, false); 737 738 for (i = 0; i < adev->sdma.num_instances; i++) { 739 if (!adev->sdma.instance[i].fw) 740 return -EINVAL; 741 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 742 amdgpu_ucode_print_sdma_hdr(&hdr->header); 743 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 744 fw_data = (const __le32 *) 745 (adev->sdma.instance[i].fw->data + 746 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 747 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); 748 for (j = 0; j < fw_size; j++) 749 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); 750 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); 751 } 752 753 return 0; 754 } 755 756 /** 757 * sdma_v3_0_start - setup and start the async dma engines 758 * 759 * @adev: amdgpu_device pointer 760 * 761 * Set up the DMA engines and enable them (VI). 762 * Returns 0 for success, error for failure. 763 */ 764 static int sdma_v3_0_start(struct amdgpu_device *adev) 765 { 766 int r, i; 767 768 if (!adev->pp_enabled) { 769 if (!adev->firmware.smu_load) { 770 r = sdma_v3_0_load_microcode(adev); 771 if (r) 772 return r; 773 } else { 774 for (i = 0; i < adev->sdma.num_instances; i++) { 775 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 776 (i == 0) ? 777 AMDGPU_UCODE_ID_SDMA0 : 778 AMDGPU_UCODE_ID_SDMA1); 779 if (r) 780 return -EINVAL; 781 } 782 } 783 } 784 785 /* disble sdma engine before programing it */ 786 sdma_v3_0_ctx_switch_enable(adev, false); 787 sdma_v3_0_enable(adev, false); 788 789 /* start the gfx rings and rlc compute queues */ 790 r = sdma_v3_0_gfx_resume(adev); 791 if (r) 792 return r; 793 r = sdma_v3_0_rlc_resume(adev); 794 if (r) 795 return r; 796 797 return 0; 798 } 799 800 /** 801 * sdma_v3_0_ring_test_ring - simple async dma engine test 802 * 803 * @ring: amdgpu_ring structure holding ring information 804 * 805 * Test the DMA engine by writing using it to write an 806 * value to memory. (VI). 807 * Returns 0 for success, error for failure. 808 */ 809 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) 810 { 811 struct amdgpu_device *adev = ring->adev; 812 unsigned i; 813 unsigned index; 814 int r; 815 u32 tmp; 816 u64 gpu_addr; 817 818 r = amdgpu_wb_get(adev, &index); 819 if (r) { 820 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 821 return r; 822 } 823 824 gpu_addr = adev->wb.gpu_addr + (index * 4); 825 tmp = 0xCAFEDEAD; 826 adev->wb.wb[index] = cpu_to_le32(tmp); 827 828 r = amdgpu_ring_alloc(ring, 5); 829 if (r) { 830 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 831 amdgpu_wb_free(adev, index); 832 return r; 833 } 834 835 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 836 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 837 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 838 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 839 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 840 amdgpu_ring_write(ring, 0xDEADBEEF); 841 amdgpu_ring_commit(ring); 842 843 for (i = 0; i < adev->usec_timeout; i++) { 844 tmp = le32_to_cpu(adev->wb.wb[index]); 845 if (tmp == 0xDEADBEEF) 846 break; 847 DRM_UDELAY(1); 848 } 849 850 if (i < adev->usec_timeout) { 851 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 852 } else { 853 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 854 ring->idx, tmp); 855 r = -EINVAL; 856 } 857 amdgpu_wb_free(adev, index); 858 859 return r; 860 } 861 862 /** 863 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine 864 * 865 * @ring: amdgpu_ring structure holding ring information 866 * 867 * Test a simple IB in the DMA ring (VI). 868 * Returns 0 on success, error on failure. 869 */ 870 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 871 { 872 struct amdgpu_device *adev = ring->adev; 873 struct amdgpu_ib ib; 874 struct fence *f = NULL; 875 unsigned index; 876 u32 tmp = 0; 877 u64 gpu_addr; 878 long r; 879 880 r = amdgpu_wb_get(adev, &index); 881 if (r) { 882 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 883 return r; 884 } 885 886 gpu_addr = adev->wb.gpu_addr + (index * 4); 887 tmp = 0xCAFEDEAD; 888 adev->wb.wb[index] = cpu_to_le32(tmp); 889 memset(&ib, 0, sizeof(ib)); 890 r = amdgpu_ib_get(adev, NULL, 256, &ib); 891 if (r) { 892 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 893 goto err0; 894 } 895 896 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 897 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 898 ib.ptr[1] = lower_32_bits(gpu_addr); 899 ib.ptr[2] = upper_32_bits(gpu_addr); 900 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); 901 ib.ptr[4] = 0xDEADBEEF; 902 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 903 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 904 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 905 ib.length_dw = 8; 906 907 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f); 908 if (r) 909 goto err1; 910 911 r = fence_wait_timeout(f, false, timeout); 912 if (r == 0) { 913 DRM_ERROR("amdgpu: IB test timed out\n"); 914 r = -ETIMEDOUT; 915 goto err1; 916 } else if (r < 0) { 917 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 918 goto err1; 919 } 920 tmp = le32_to_cpu(adev->wb.wb[index]); 921 if (tmp == 0xDEADBEEF) { 922 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 923 r = 0; 924 } else { 925 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 926 r = -EINVAL; 927 } 928 err1: 929 amdgpu_ib_free(adev, &ib, NULL); 930 fence_put(f); 931 err0: 932 amdgpu_wb_free(adev, index); 933 return r; 934 } 935 936 /** 937 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART 938 * 939 * @ib: indirect buffer to fill with commands 940 * @pe: addr of the page entry 941 * @src: src addr to copy from 942 * @count: number of page entries to update 943 * 944 * Update PTEs by copying them from the GART using sDMA (CIK). 945 */ 946 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib, 947 uint64_t pe, uint64_t src, 948 unsigned count) 949 { 950 unsigned bytes = count * 8; 951 952 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 953 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 954 ib->ptr[ib->length_dw++] = bytes; 955 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 956 ib->ptr[ib->length_dw++] = lower_32_bits(src); 957 ib->ptr[ib->length_dw++] = upper_32_bits(src); 958 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 959 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 960 } 961 962 /** 963 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually 964 * 965 * @ib: indirect buffer to fill with commands 966 * @pe: addr of the page entry 967 * @value: dst addr to write into pe 968 * @count: number of page entries to update 969 * @incr: increase next addr by incr bytes 970 * 971 * Update PTEs by writing them manually using sDMA (CIK). 972 */ 973 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 974 uint64_t value, unsigned count, 975 uint32_t incr) 976 { 977 unsigned ndw = count * 2; 978 979 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 980 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 981 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 982 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 983 ib->ptr[ib->length_dw++] = ndw; 984 for (; ndw > 0; ndw -= 2, --count, pe += 8) { 985 ib->ptr[ib->length_dw++] = lower_32_bits(value); 986 ib->ptr[ib->length_dw++] = upper_32_bits(value); 987 value += incr; 988 } 989 } 990 991 /** 992 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA 993 * 994 * @ib: indirect buffer to fill with commands 995 * @pe: addr of the page entry 996 * @addr: dst addr to write into pe 997 * @count: number of page entries to update 998 * @incr: increase next addr by incr bytes 999 * @flags: access flags 1000 * 1001 * Update the page tables using sDMA (CIK). 1002 */ 1003 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, 1004 uint64_t addr, unsigned count, 1005 uint32_t incr, uint32_t flags) 1006 { 1007 /* for physically contiguous pages (vram) */ 1008 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); 1009 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1010 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1011 ib->ptr[ib->length_dw++] = flags; /* mask */ 1012 ib->ptr[ib->length_dw++] = 0; 1013 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1014 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1015 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1016 ib->ptr[ib->length_dw++] = 0; 1017 ib->ptr[ib->length_dw++] = count; /* number of entries */ 1018 } 1019 1020 /** 1021 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw 1022 * 1023 * @ib: indirect buffer to fill with padding 1024 * 1025 */ 1026 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1027 { 1028 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 1029 u32 pad_count; 1030 int i; 1031 1032 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 1033 for (i = 0; i < pad_count; i++) 1034 if (sdma && sdma->burst_nop && (i == 0)) 1035 ib->ptr[ib->length_dw++] = 1036 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1037 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1038 else 1039 ib->ptr[ib->length_dw++] = 1040 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1041 } 1042 1043 /** 1044 * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline 1045 * 1046 * @ring: amdgpu_ring pointer 1047 * 1048 * Make sure all previous operations are completed (CIK). 1049 */ 1050 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1051 { 1052 uint32_t seq = ring->fence_drv.sync_seq; 1053 uint64_t addr = ring->fence_drv.gpu_addr; 1054 1055 /* wait for idle */ 1056 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1057 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1058 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1059 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1060 amdgpu_ring_write(ring, addr & 0xfffffffc); 1061 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1062 amdgpu_ring_write(ring, seq); /* reference */ 1063 amdgpu_ring_write(ring, 0xfffffff); /* mask */ 1064 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1065 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1066 } 1067 1068 /** 1069 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA 1070 * 1071 * @ring: amdgpu_ring pointer 1072 * @vm: amdgpu_vm pointer 1073 * 1074 * Update the page table base and flush the VM TLB 1075 * using sDMA (VI). 1076 */ 1077 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1078 unsigned vm_id, uint64_t pd_addr) 1079 { 1080 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1081 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1082 if (vm_id < 8) { 1083 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); 1084 } else { 1085 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); 1086 } 1087 amdgpu_ring_write(ring, pd_addr >> 12); 1088 1089 /* flush TLB */ 1090 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1091 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1092 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 1093 amdgpu_ring_write(ring, 1 << vm_id); 1094 1095 /* wait for flush */ 1096 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1097 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1098 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ 1099 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 1100 amdgpu_ring_write(ring, 0); 1101 amdgpu_ring_write(ring, 0); /* reference */ 1102 amdgpu_ring_write(ring, 0); /* mask */ 1103 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1104 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 1105 } 1106 1107 static unsigned sdma_v3_0_ring_get_emit_ib_size(struct amdgpu_ring *ring) 1108 { 1109 return 1110 7 + 6; /* sdma_v3_0_ring_emit_ib */ 1111 } 1112 1113 static unsigned sdma_v3_0_ring_get_dma_frame_size(struct amdgpu_ring *ring) 1114 { 1115 return 1116 6 + /* sdma_v3_0_ring_emit_hdp_flush */ 1117 3 + /* sdma_v3_0_ring_emit_hdp_invalidate */ 1118 6 + /* sdma_v3_0_ring_emit_pipeline_sync */ 1119 12 + /* sdma_v3_0_ring_emit_vm_flush */ 1120 10 + 10 + 10; /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */ 1121 } 1122 1123 static int sdma_v3_0_early_init(void *handle) 1124 { 1125 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1126 1127 switch (adev->asic_type) { 1128 case CHIP_STONEY: 1129 adev->sdma.num_instances = 1; 1130 break; 1131 default: 1132 adev->sdma.num_instances = SDMA_MAX_INSTANCE; 1133 break; 1134 } 1135 1136 sdma_v3_0_set_ring_funcs(adev); 1137 sdma_v3_0_set_buffer_funcs(adev); 1138 sdma_v3_0_set_vm_pte_funcs(adev); 1139 sdma_v3_0_set_irq_funcs(adev); 1140 1141 return 0; 1142 } 1143 1144 static int sdma_v3_0_sw_init(void *handle) 1145 { 1146 struct amdgpu_ring *ring; 1147 int r, i; 1148 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1149 1150 /* SDMA trap event */ 1151 r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq); 1152 if (r) 1153 return r; 1154 1155 /* SDMA Privileged inst */ 1156 r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq); 1157 if (r) 1158 return r; 1159 1160 /* SDMA Privileged inst */ 1161 r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq); 1162 if (r) 1163 return r; 1164 1165 r = sdma_v3_0_init_microcode(adev); 1166 if (r) { 1167 DRM_ERROR("Failed to load sdma firmware!\n"); 1168 return r; 1169 } 1170 1171 for (i = 0; i < adev->sdma.num_instances; i++) { 1172 ring = &adev->sdma.instance[i].ring; 1173 ring->ring_obj = NULL; 1174 ring->use_doorbell = true; 1175 ring->doorbell_index = (i == 0) ? 1176 AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1; 1177 1178 sprintf(ring->name, "sdma%d", i); 1179 r = amdgpu_ring_init(adev, ring, 1024, 1180 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, 1181 &adev->sdma.trap_irq, 1182 (i == 0) ? 1183 AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1, 1184 AMDGPU_RING_TYPE_SDMA); 1185 if (r) 1186 return r; 1187 } 1188 1189 return r; 1190 } 1191 1192 static int sdma_v3_0_sw_fini(void *handle) 1193 { 1194 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1195 int i; 1196 1197 for (i = 0; i < adev->sdma.num_instances; i++) 1198 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1199 1200 sdma_v3_0_free_microcode(adev); 1201 return 0; 1202 } 1203 1204 static int sdma_v3_0_hw_init(void *handle) 1205 { 1206 int r; 1207 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1208 1209 sdma_v3_0_init_golden_registers(adev); 1210 1211 r = sdma_v3_0_start(adev); 1212 if (r) 1213 return r; 1214 1215 return r; 1216 } 1217 1218 static int sdma_v3_0_hw_fini(void *handle) 1219 { 1220 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1221 1222 sdma_v3_0_ctx_switch_enable(adev, false); 1223 sdma_v3_0_enable(adev, false); 1224 1225 return 0; 1226 } 1227 1228 static int sdma_v3_0_suspend(void *handle) 1229 { 1230 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1231 1232 return sdma_v3_0_hw_fini(adev); 1233 } 1234 1235 static int sdma_v3_0_resume(void *handle) 1236 { 1237 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1238 1239 return sdma_v3_0_hw_init(adev); 1240 } 1241 1242 static bool sdma_v3_0_is_idle(void *handle) 1243 { 1244 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1245 u32 tmp = RREG32(mmSRBM_STATUS2); 1246 1247 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1248 SRBM_STATUS2__SDMA1_BUSY_MASK)) 1249 return false; 1250 1251 return true; 1252 } 1253 1254 static int sdma_v3_0_wait_for_idle(void *handle) 1255 { 1256 unsigned i; 1257 u32 tmp; 1258 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1259 1260 for (i = 0; i < adev->usec_timeout; i++) { 1261 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1262 SRBM_STATUS2__SDMA1_BUSY_MASK); 1263 1264 if (!tmp) 1265 return 0; 1266 udelay(1); 1267 } 1268 return -ETIMEDOUT; 1269 } 1270 1271 static bool sdma_v3_0_check_soft_reset(void *handle) 1272 { 1273 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1274 u32 srbm_soft_reset = 0; 1275 u32 tmp = RREG32(mmSRBM_STATUS2); 1276 1277 if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) || 1278 (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) { 1279 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1280 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1281 } 1282 1283 if (srbm_soft_reset) { 1284 adev->sdma.srbm_soft_reset = srbm_soft_reset; 1285 return true; 1286 } else { 1287 adev->sdma.srbm_soft_reset = 0; 1288 return false; 1289 } 1290 } 1291 1292 static int sdma_v3_0_pre_soft_reset(void *handle) 1293 { 1294 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1295 u32 srbm_soft_reset = 0; 1296 1297 if (!adev->sdma.srbm_soft_reset) 1298 return 0; 1299 1300 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1301 1302 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || 1303 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { 1304 sdma_v3_0_ctx_switch_enable(adev, false); 1305 sdma_v3_0_enable(adev, false); 1306 } 1307 1308 return 0; 1309 } 1310 1311 static int sdma_v3_0_post_soft_reset(void *handle) 1312 { 1313 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1314 u32 srbm_soft_reset = 0; 1315 1316 if (!adev->sdma.srbm_soft_reset) 1317 return 0; 1318 1319 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1320 1321 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || 1322 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { 1323 sdma_v3_0_gfx_resume(adev); 1324 sdma_v3_0_rlc_resume(adev); 1325 } 1326 1327 return 0; 1328 } 1329 1330 static int sdma_v3_0_soft_reset(void *handle) 1331 { 1332 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1333 u32 srbm_soft_reset = 0; 1334 u32 tmp; 1335 1336 if (!adev->sdma.srbm_soft_reset) 1337 return 0; 1338 1339 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1340 1341 if (srbm_soft_reset) { 1342 tmp = RREG32(mmSRBM_SOFT_RESET); 1343 tmp |= srbm_soft_reset; 1344 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1345 WREG32(mmSRBM_SOFT_RESET, tmp); 1346 tmp = RREG32(mmSRBM_SOFT_RESET); 1347 1348 udelay(50); 1349 1350 tmp &= ~srbm_soft_reset; 1351 WREG32(mmSRBM_SOFT_RESET, tmp); 1352 tmp = RREG32(mmSRBM_SOFT_RESET); 1353 1354 /* Wait a little for things to settle down */ 1355 udelay(50); 1356 } 1357 1358 return 0; 1359 } 1360 1361 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev, 1362 struct amdgpu_irq_src *source, 1363 unsigned type, 1364 enum amdgpu_interrupt_state state) 1365 { 1366 u32 sdma_cntl; 1367 1368 switch (type) { 1369 case AMDGPU_SDMA_IRQ_TRAP0: 1370 switch (state) { 1371 case AMDGPU_IRQ_STATE_DISABLE: 1372 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1373 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1374 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1375 break; 1376 case AMDGPU_IRQ_STATE_ENABLE: 1377 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1378 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1379 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1380 break; 1381 default: 1382 break; 1383 } 1384 break; 1385 case AMDGPU_SDMA_IRQ_TRAP1: 1386 switch (state) { 1387 case AMDGPU_IRQ_STATE_DISABLE: 1388 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1389 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1390 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1391 break; 1392 case AMDGPU_IRQ_STATE_ENABLE: 1393 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1394 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1395 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1396 break; 1397 default: 1398 break; 1399 } 1400 break; 1401 default: 1402 break; 1403 } 1404 return 0; 1405 } 1406 1407 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev, 1408 struct amdgpu_irq_src *source, 1409 struct amdgpu_iv_entry *entry) 1410 { 1411 u8 instance_id, queue_id; 1412 1413 instance_id = (entry->ring_id & 0x3) >> 0; 1414 queue_id = (entry->ring_id & 0xc) >> 2; 1415 DRM_DEBUG("IH: SDMA trap\n"); 1416 switch (instance_id) { 1417 case 0: 1418 switch (queue_id) { 1419 case 0: 1420 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1421 break; 1422 case 1: 1423 /* XXX compute */ 1424 break; 1425 case 2: 1426 /* XXX compute */ 1427 break; 1428 } 1429 break; 1430 case 1: 1431 switch (queue_id) { 1432 case 0: 1433 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1434 break; 1435 case 1: 1436 /* XXX compute */ 1437 break; 1438 case 2: 1439 /* XXX compute */ 1440 break; 1441 } 1442 break; 1443 } 1444 return 0; 1445 } 1446 1447 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1448 struct amdgpu_irq_src *source, 1449 struct amdgpu_iv_entry *entry) 1450 { 1451 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1452 schedule_work(&adev->reset_work); 1453 return 0; 1454 } 1455 1456 static void sdma_v3_0_update_sdma_medium_grain_clock_gating( 1457 struct amdgpu_device *adev, 1458 bool enable) 1459 { 1460 uint32_t temp, data; 1461 int i; 1462 1463 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1464 for (i = 0; i < adev->sdma.num_instances; i++) { 1465 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); 1466 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1467 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1468 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1469 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1470 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1471 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1472 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1473 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1474 if (data != temp) 1475 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); 1476 } 1477 } else { 1478 for (i = 0; i < adev->sdma.num_instances; i++) { 1479 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); 1480 data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1481 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1482 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1483 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1484 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1485 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1486 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1487 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK; 1488 1489 if (data != temp) 1490 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); 1491 } 1492 } 1493 } 1494 1495 static void sdma_v3_0_update_sdma_medium_grain_light_sleep( 1496 struct amdgpu_device *adev, 1497 bool enable) 1498 { 1499 uint32_t temp, data; 1500 int i; 1501 1502 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1503 for (i = 0; i < adev->sdma.num_instances; i++) { 1504 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1505 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1506 1507 if (temp != data) 1508 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1509 } 1510 } else { 1511 for (i = 0; i < adev->sdma.num_instances; i++) { 1512 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1513 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1514 1515 if (temp != data) 1516 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1517 } 1518 } 1519 } 1520 1521 static int sdma_v3_0_set_clockgating_state(void *handle, 1522 enum amd_clockgating_state state) 1523 { 1524 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1525 1526 switch (adev->asic_type) { 1527 case CHIP_FIJI: 1528 case CHIP_CARRIZO: 1529 case CHIP_STONEY: 1530 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev, 1531 state == AMD_CG_STATE_GATE ? true : false); 1532 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev, 1533 state == AMD_CG_STATE_GATE ? true : false); 1534 break; 1535 default: 1536 break; 1537 } 1538 return 0; 1539 } 1540 1541 static int sdma_v3_0_set_powergating_state(void *handle, 1542 enum amd_powergating_state state) 1543 { 1544 return 0; 1545 } 1546 1547 const struct amd_ip_funcs sdma_v3_0_ip_funcs = { 1548 .name = "sdma_v3_0", 1549 .early_init = sdma_v3_0_early_init, 1550 .late_init = NULL, 1551 .sw_init = sdma_v3_0_sw_init, 1552 .sw_fini = sdma_v3_0_sw_fini, 1553 .hw_init = sdma_v3_0_hw_init, 1554 .hw_fini = sdma_v3_0_hw_fini, 1555 .suspend = sdma_v3_0_suspend, 1556 .resume = sdma_v3_0_resume, 1557 .is_idle = sdma_v3_0_is_idle, 1558 .wait_for_idle = sdma_v3_0_wait_for_idle, 1559 .check_soft_reset = sdma_v3_0_check_soft_reset, 1560 .pre_soft_reset = sdma_v3_0_pre_soft_reset, 1561 .post_soft_reset = sdma_v3_0_post_soft_reset, 1562 .soft_reset = sdma_v3_0_soft_reset, 1563 .set_clockgating_state = sdma_v3_0_set_clockgating_state, 1564 .set_powergating_state = sdma_v3_0_set_powergating_state, 1565 }; 1566 1567 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { 1568 .get_rptr = sdma_v3_0_ring_get_rptr, 1569 .get_wptr = sdma_v3_0_ring_get_wptr, 1570 .set_wptr = sdma_v3_0_ring_set_wptr, 1571 .parse_cs = NULL, 1572 .emit_ib = sdma_v3_0_ring_emit_ib, 1573 .emit_fence = sdma_v3_0_ring_emit_fence, 1574 .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync, 1575 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, 1576 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, 1577 .emit_hdp_invalidate = sdma_v3_0_ring_emit_hdp_invalidate, 1578 .test_ring = sdma_v3_0_ring_test_ring, 1579 .test_ib = sdma_v3_0_ring_test_ib, 1580 .insert_nop = sdma_v3_0_ring_insert_nop, 1581 .pad_ib = sdma_v3_0_ring_pad_ib, 1582 .get_emit_ib_size = sdma_v3_0_ring_get_emit_ib_size, 1583 .get_dma_frame_size = sdma_v3_0_ring_get_dma_frame_size, 1584 }; 1585 1586 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev) 1587 { 1588 int i; 1589 1590 for (i = 0; i < adev->sdma.num_instances; i++) 1591 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs; 1592 } 1593 1594 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = { 1595 .set = sdma_v3_0_set_trap_irq_state, 1596 .process = sdma_v3_0_process_trap_irq, 1597 }; 1598 1599 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = { 1600 .process = sdma_v3_0_process_illegal_inst_irq, 1601 }; 1602 1603 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev) 1604 { 1605 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1606 adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs; 1607 adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs; 1608 } 1609 1610 /** 1611 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine 1612 * 1613 * @ring: amdgpu_ring structure holding ring information 1614 * @src_offset: src GPU address 1615 * @dst_offset: dst GPU address 1616 * @byte_count: number of bytes to xfer 1617 * 1618 * Copy GPU buffers using the DMA engine (VI). 1619 * Used by the amdgpu ttm implementation to move pages if 1620 * registered as the asic copy callback. 1621 */ 1622 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib, 1623 uint64_t src_offset, 1624 uint64_t dst_offset, 1625 uint32_t byte_count) 1626 { 1627 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1628 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1629 ib->ptr[ib->length_dw++] = byte_count; 1630 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1631 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1632 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1633 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1634 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1635 } 1636 1637 /** 1638 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine 1639 * 1640 * @ring: amdgpu_ring structure holding ring information 1641 * @src_data: value to write to buffer 1642 * @dst_offset: dst GPU address 1643 * @byte_count: number of bytes to xfer 1644 * 1645 * Fill GPU buffers using the DMA engine (VI). 1646 */ 1647 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib, 1648 uint32_t src_data, 1649 uint64_t dst_offset, 1650 uint32_t byte_count) 1651 { 1652 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1653 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1654 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1655 ib->ptr[ib->length_dw++] = src_data; 1656 ib->ptr[ib->length_dw++] = byte_count; 1657 } 1658 1659 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = { 1660 .copy_max_bytes = 0x1fffff, 1661 .copy_num_dw = 7, 1662 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer, 1663 1664 .fill_max_bytes = 0x1fffff, 1665 .fill_num_dw = 5, 1666 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer, 1667 }; 1668 1669 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) 1670 { 1671 if (adev->mman.buffer_funcs == NULL) { 1672 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs; 1673 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1674 } 1675 } 1676 1677 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { 1678 .copy_pte = sdma_v3_0_vm_copy_pte, 1679 .write_pte = sdma_v3_0_vm_write_pte, 1680 .set_pte_pde = sdma_v3_0_vm_set_pte_pde, 1681 }; 1682 1683 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1684 { 1685 unsigned i; 1686 1687 if (adev->vm_manager.vm_pte_funcs == NULL) { 1688 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; 1689 for (i = 0; i < adev->sdma.num_instances; i++) 1690 adev->vm_manager.vm_pte_rings[i] = 1691 &adev->sdma.instance[i].ring; 1692 1693 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; 1694 } 1695 } 1696