1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 25 #include <linux/delay.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 #include "vi.h" 33 #include "vid.h" 34 35 #include "oss/oss_3_0_d.h" 36 #include "oss/oss_3_0_sh_mask.h" 37 38 #include "gmc/gmc_8_1_d.h" 39 #include "gmc/gmc_8_1_sh_mask.h" 40 41 #include "gca/gfx_8_0_d.h" 42 #include "gca/gfx_8_0_enum.h" 43 #include "gca/gfx_8_0_sh_mask.h" 44 45 #include "bif/bif_5_0_d.h" 46 #include "bif/bif_5_0_sh_mask.h" 47 48 #include "tonga_sdma_pkt_open.h" 49 50 #include "ivsrcid/ivsrcid_vislands30.h" 51 52 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev); 53 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); 54 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); 55 56 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); 57 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin"); 58 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin"); 59 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); 60 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); 61 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); 62 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin"); 63 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin"); 65 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin"); 66 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin"); 67 MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin"); 68 MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin"); 69 MODULE_FIRMWARE("amdgpu/vegam_sdma.bin"); 70 MODULE_FIRMWARE("amdgpu/vegam_sdma1.bin"); 71 72 73 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 74 { 75 SDMA0_REGISTER_OFFSET, 76 SDMA1_REGISTER_OFFSET 77 }; 78 79 static const u32 golden_settings_tonga_a11[] = 80 { 81 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 82 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 83 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 84 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 85 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 86 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 87 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 88 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 89 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 90 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 91 }; 92 93 static const u32 tonga_mgcg_cgcg_init[] = 94 { 95 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 96 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 97 }; 98 99 static const u32 golden_settings_fiji_a10[] = 100 { 101 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 102 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 103 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 104 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 105 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 106 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 107 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 108 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 109 }; 110 111 static const u32 fiji_mgcg_cgcg_init[] = 112 { 113 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 114 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 115 }; 116 117 static const u32 golden_settings_polaris11_a11[] = 118 { 119 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 120 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 121 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 122 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 123 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 124 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 125 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 126 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 127 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 128 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 129 }; 130 131 static const u32 golden_settings_polaris10_a11[] = 132 { 133 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 134 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 135 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 136 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 137 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 138 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 139 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 140 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 141 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 142 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 143 }; 144 145 static const u32 cz_golden_settings_a11[] = 146 { 147 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 148 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 149 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 150 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 151 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 152 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 153 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 154 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 155 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100, 156 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800, 157 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100, 158 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100, 159 }; 160 161 static const u32 cz_mgcg_cgcg_init[] = 162 { 163 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 164 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 165 }; 166 167 static const u32 stoney_golden_settings_a11[] = 168 { 169 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 170 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 171 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 172 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 173 }; 174 175 static const u32 stoney_mgcg_cgcg_init[] = 176 { 177 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100, 178 }; 179 180 /* 181 * sDMA - System DMA 182 * Starting with CIK, the GPU has new asynchronous 183 * DMA engines. These engines are used for compute 184 * and gfx. There are two DMA engines (SDMA0, SDMA1) 185 * and each one supports 1 ring buffer used for gfx 186 * and 2 queues used for compute. 187 * 188 * The programming model is very similar to the CP 189 * (ring buffer, IBs, etc.), but sDMA has it's own 190 * packet format that is different from the PM4 format 191 * used by the CP. sDMA supports copying data, writing 192 * embedded data, solid fills, and a number of other 193 * things. It also has support for tiling/detiling of 194 * buffers. 195 */ 196 197 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) 198 { 199 switch (adev->asic_type) { 200 case CHIP_FIJI: 201 amdgpu_device_program_register_sequence(adev, 202 fiji_mgcg_cgcg_init, 203 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 204 amdgpu_device_program_register_sequence(adev, 205 golden_settings_fiji_a10, 206 ARRAY_SIZE(golden_settings_fiji_a10)); 207 break; 208 case CHIP_TONGA: 209 amdgpu_device_program_register_sequence(adev, 210 tonga_mgcg_cgcg_init, 211 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 212 amdgpu_device_program_register_sequence(adev, 213 golden_settings_tonga_a11, 214 ARRAY_SIZE(golden_settings_tonga_a11)); 215 break; 216 case CHIP_POLARIS11: 217 case CHIP_POLARIS12: 218 case CHIP_VEGAM: 219 amdgpu_device_program_register_sequence(adev, 220 golden_settings_polaris11_a11, 221 ARRAY_SIZE(golden_settings_polaris11_a11)); 222 break; 223 case CHIP_POLARIS10: 224 amdgpu_device_program_register_sequence(adev, 225 golden_settings_polaris10_a11, 226 ARRAY_SIZE(golden_settings_polaris10_a11)); 227 break; 228 case CHIP_CARRIZO: 229 amdgpu_device_program_register_sequence(adev, 230 cz_mgcg_cgcg_init, 231 ARRAY_SIZE(cz_mgcg_cgcg_init)); 232 amdgpu_device_program_register_sequence(adev, 233 cz_golden_settings_a11, 234 ARRAY_SIZE(cz_golden_settings_a11)); 235 break; 236 case CHIP_STONEY: 237 amdgpu_device_program_register_sequence(adev, 238 stoney_mgcg_cgcg_init, 239 ARRAY_SIZE(stoney_mgcg_cgcg_init)); 240 amdgpu_device_program_register_sequence(adev, 241 stoney_golden_settings_a11, 242 ARRAY_SIZE(stoney_golden_settings_a11)); 243 break; 244 default: 245 break; 246 } 247 } 248 249 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev) 250 { 251 int i; 252 253 for (i = 0; i < adev->sdma.num_instances; i++) 254 amdgpu_ucode_release(&adev->sdma.instance[i].fw); 255 } 256 257 /** 258 * sdma_v3_0_init_microcode - load ucode images from disk 259 * 260 * @adev: amdgpu_device pointer 261 * 262 * Use the firmware interface to load the ucode images into 263 * the driver (not loaded into hw). 264 * Returns 0 on success, error on failure. 265 */ 266 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) 267 { 268 const char *chip_name; 269 int err = 0, i; 270 struct amdgpu_firmware_info *info = NULL; 271 const struct common_firmware_header *header = NULL; 272 const struct sdma_firmware_header_v1_0 *hdr; 273 274 DRM_DEBUG("\n"); 275 276 switch (adev->asic_type) { 277 case CHIP_TONGA: 278 chip_name = "tonga"; 279 break; 280 case CHIP_FIJI: 281 chip_name = "fiji"; 282 break; 283 case CHIP_POLARIS10: 284 chip_name = "polaris10"; 285 break; 286 case CHIP_POLARIS11: 287 chip_name = "polaris11"; 288 break; 289 case CHIP_POLARIS12: 290 chip_name = "polaris12"; 291 break; 292 case CHIP_VEGAM: 293 chip_name = "vegam"; 294 break; 295 case CHIP_CARRIZO: 296 chip_name = "carrizo"; 297 break; 298 case CHIP_STONEY: 299 chip_name = "stoney"; 300 break; 301 default: BUG(); 302 } 303 304 for (i = 0; i < adev->sdma.num_instances; i++) { 305 if (i == 0) 306 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw, 307 AMDGPU_UCODE_REQUIRED, 308 "amdgpu/%s_sdma.bin", chip_name); 309 else 310 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw, 311 AMDGPU_UCODE_REQUIRED, 312 "amdgpu/%s_sdma1.bin", chip_name); 313 if (err) 314 goto out; 315 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 316 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 317 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 318 if (adev->sdma.instance[i].feature_version >= 20) 319 adev->sdma.instance[i].burst_nop = true; 320 321 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 322 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 323 info->fw = adev->sdma.instance[i].fw; 324 header = (const struct common_firmware_header *)info->fw->data; 325 adev->firmware.fw_size += 326 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 327 328 } 329 out: 330 if (err) { 331 pr_err("sdma_v3_0: Failed to load firmware \"%s_sdma%s.bin\"\n", 332 chip_name, i == 0 ? "" : "1"); 333 for (i = 0; i < adev->sdma.num_instances; i++) 334 amdgpu_ucode_release(&adev->sdma.instance[i].fw); 335 } 336 return err; 337 } 338 339 /** 340 * sdma_v3_0_ring_get_rptr - get the current read pointer 341 * 342 * @ring: amdgpu ring pointer 343 * 344 * Get the current rptr from the hardware (VI+). 345 */ 346 static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring) 347 { 348 /* XXX check if swapping is necessary on BE */ 349 return *ring->rptr_cpu_addr >> 2; 350 } 351 352 /** 353 * sdma_v3_0_ring_get_wptr - get the current write pointer 354 * 355 * @ring: amdgpu ring pointer 356 * 357 * Get the current wptr from the hardware (VI+). 358 */ 359 static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring) 360 { 361 struct amdgpu_device *adev = ring->adev; 362 u32 wptr; 363 364 if (ring->use_doorbell || ring->use_pollmem) { 365 /* XXX check if swapping is necessary on BE */ 366 wptr = *ring->wptr_cpu_addr >> 2; 367 } else { 368 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; 369 } 370 371 return wptr; 372 } 373 374 /** 375 * sdma_v3_0_ring_set_wptr - commit the write pointer 376 * 377 * @ring: amdgpu ring pointer 378 * 379 * Write the wptr back to the hardware (VI+). 380 */ 381 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) 382 { 383 struct amdgpu_device *adev = ring->adev; 384 385 if (ring->use_doorbell) { 386 u32 *wb = (u32 *)ring->wptr_cpu_addr; 387 /* XXX check if swapping is necessary on BE */ 388 WRITE_ONCE(*wb, ring->wptr << 2); 389 WDOORBELL32(ring->doorbell_index, ring->wptr << 2); 390 } else if (ring->use_pollmem) { 391 u32 *wb = (u32 *)ring->wptr_cpu_addr; 392 393 WRITE_ONCE(*wb, ring->wptr << 2); 394 } else { 395 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2); 396 } 397 } 398 399 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 400 { 401 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 402 int i; 403 404 for (i = 0; i < count; i++) 405 if (sdma && sdma->burst_nop && (i == 0)) 406 amdgpu_ring_write(ring, ring->funcs->nop | 407 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 408 else 409 amdgpu_ring_write(ring, ring->funcs->nop); 410 } 411 412 /** 413 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine 414 * 415 * @ring: amdgpu ring pointer 416 * @job: job to retrieve vmid from 417 * @ib: IB object to schedule 418 * @flags: unused 419 * 420 * Schedule an IB in the DMA ring (VI). 421 */ 422 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, 423 struct amdgpu_job *job, 424 struct amdgpu_ib *ib, 425 uint32_t flags) 426 { 427 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 428 429 /* IB packet must end on a 8 DW boundary */ 430 sdma_v3_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 431 432 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 433 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 434 /* base must be 32 byte aligned */ 435 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 436 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 437 amdgpu_ring_write(ring, ib->length_dw); 438 amdgpu_ring_write(ring, 0); 439 amdgpu_ring_write(ring, 0); 440 441 } 442 443 /** 444 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 445 * 446 * @ring: amdgpu ring pointer 447 * 448 * Emit an hdp flush packet on the requested DMA ring. 449 */ 450 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 451 { 452 u32 ref_and_mask = 0; 453 454 if (ring->me == 0) 455 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); 456 else 457 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); 458 459 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 460 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 461 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 462 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 463 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 464 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 465 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 466 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 467 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 468 } 469 470 /** 471 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring 472 * 473 * @ring: amdgpu ring pointer 474 * @addr: address 475 * @seq: sequence number 476 * @flags: fence related flags 477 * 478 * Add a DMA fence packet to the ring to write 479 * the fence seq number and DMA trap packet to generate 480 * an interrupt if needed (VI). 481 */ 482 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 483 unsigned flags) 484 { 485 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 486 /* write the fence */ 487 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 488 amdgpu_ring_write(ring, lower_32_bits(addr)); 489 amdgpu_ring_write(ring, upper_32_bits(addr)); 490 amdgpu_ring_write(ring, lower_32_bits(seq)); 491 492 /* optionally write high bits as well */ 493 if (write64bit) { 494 addr += 4; 495 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 496 amdgpu_ring_write(ring, lower_32_bits(addr)); 497 amdgpu_ring_write(ring, upper_32_bits(addr)); 498 amdgpu_ring_write(ring, upper_32_bits(seq)); 499 } 500 501 /* generate an interrupt */ 502 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 503 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 504 } 505 506 /** 507 * sdma_v3_0_gfx_stop - stop the gfx async dma engines 508 * 509 * @adev: amdgpu_device pointer 510 * 511 * Stop the gfx async dma ring buffers (VI). 512 */ 513 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev) 514 { 515 u32 rb_cntl, ib_cntl; 516 int i; 517 518 for (i = 0; i < adev->sdma.num_instances; i++) { 519 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 520 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 521 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 522 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 523 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 524 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 525 } 526 } 527 528 /** 529 * sdma_v3_0_rlc_stop - stop the compute async dma engines 530 * 531 * @adev: amdgpu_device pointer 532 * 533 * Stop the compute async dma queues (VI). 534 */ 535 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev) 536 { 537 /* XXX todo */ 538 } 539 540 /** 541 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch 542 * 543 * @adev: amdgpu_device pointer 544 * @enable: enable/disable the DMA MEs context switch. 545 * 546 * Halt or unhalt the async dma engines context switch (VI). 547 */ 548 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 549 { 550 u32 f32_cntl, phase_quantum = 0; 551 int i; 552 553 if (amdgpu_sdma_phase_quantum) { 554 unsigned value = amdgpu_sdma_phase_quantum; 555 unsigned unit = 0; 556 557 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 558 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 559 value = (value + 1) >> 1; 560 unit++; 561 } 562 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 563 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 564 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 565 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 566 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 567 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 568 WARN_ONCE(1, 569 "clamping sdma_phase_quantum to %uK clock cycles\n", 570 value << unit); 571 } 572 phase_quantum = 573 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 574 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 575 } 576 577 for (i = 0; i < adev->sdma.num_instances; i++) { 578 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); 579 if (enable) { 580 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 581 AUTO_CTXSW_ENABLE, 1); 582 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 583 ATC_L1_ENABLE, 1); 584 if (amdgpu_sdma_phase_quantum) { 585 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], 586 phase_quantum); 587 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], 588 phase_quantum); 589 } 590 } else { 591 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 592 AUTO_CTXSW_ENABLE, 0); 593 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 594 ATC_L1_ENABLE, 1); 595 } 596 597 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); 598 } 599 } 600 601 /** 602 * sdma_v3_0_enable - stop the async dma engines 603 * 604 * @adev: amdgpu_device pointer 605 * @enable: enable/disable the DMA MEs. 606 * 607 * Halt or unhalt the async dma engines (VI). 608 */ 609 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable) 610 { 611 u32 f32_cntl; 612 int i; 613 614 if (!enable) { 615 sdma_v3_0_gfx_stop(adev); 616 sdma_v3_0_rlc_stop(adev); 617 } 618 619 for (i = 0; i < adev->sdma.num_instances; i++) { 620 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 621 if (enable) 622 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); 623 else 624 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 625 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); 626 } 627 } 628 629 /** 630 * sdma_v3_0_gfx_resume - setup and start the async dma engines 631 * 632 * @adev: amdgpu_device pointer 633 * 634 * Set up the gfx DMA ring buffers and enable them (VI). 635 * Returns 0 for success, error for failure. 636 */ 637 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) 638 { 639 struct amdgpu_ring *ring; 640 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 641 u32 rb_bufsz; 642 u32 doorbell; 643 u64 wptr_gpu_addr; 644 int i, j, r; 645 646 for (i = 0; i < adev->sdma.num_instances; i++) { 647 ring = &adev->sdma.instance[i].ring; 648 amdgpu_ring_clear_ring(ring); 649 650 mutex_lock(&adev->srbm_mutex); 651 for (j = 0; j < 16; j++) { 652 vi_srbm_select(adev, 0, 0, 0, j); 653 /* SDMA GFX */ 654 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 655 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 656 } 657 vi_srbm_select(adev, 0, 0, 0, 0); 658 mutex_unlock(&adev->srbm_mutex); 659 660 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], 661 adev->gfx.config.gb_addr_config & 0x70); 662 663 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 664 665 /* Set ring buffer size in dwords */ 666 rb_bufsz = order_base_2(ring->ring_size / 4); 667 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 668 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 669 #ifdef __BIG_ENDIAN 670 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 671 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 672 RPTR_WRITEBACK_SWAP_ENABLE, 1); 673 #endif 674 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 675 676 /* Initialize the ring buffer's read and write pointers */ 677 ring->wptr = 0; 678 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 679 sdma_v3_0_ring_set_wptr(ring); 680 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); 681 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); 682 683 /* set the wb address whether it's enabled or not */ 684 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 685 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 686 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 687 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 688 689 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 690 691 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 692 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 693 694 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); 695 696 if (ring->use_doorbell) { 697 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, 698 OFFSET, ring->doorbell_index); 699 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 700 } else { 701 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 702 } 703 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell); 704 705 /* setup the wptr shadow polling */ 706 wptr_gpu_addr = ring->wptr_gpu_addr; 707 708 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i], 709 lower_32_bits(wptr_gpu_addr)); 710 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i], 711 upper_32_bits(wptr_gpu_addr)); 712 wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]); 713 if (ring->use_pollmem) { 714 /*wptr polling is not enough fast, directly clean the wptr register */ 715 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 716 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 717 SDMA0_GFX_RB_WPTR_POLL_CNTL, 718 ENABLE, 1); 719 } else { 720 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 721 SDMA0_GFX_RB_WPTR_POLL_CNTL, 722 ENABLE, 0); 723 } 724 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl); 725 726 /* enable DMA RB */ 727 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 728 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 729 730 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 731 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 732 #ifdef __BIG_ENDIAN 733 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 734 #endif 735 /* enable DMA IBs */ 736 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 737 } 738 739 /* unhalt the MEs */ 740 sdma_v3_0_enable(adev, true); 741 /* enable sdma ring preemption */ 742 sdma_v3_0_ctx_switch_enable(adev, true); 743 744 for (i = 0; i < adev->sdma.num_instances; i++) { 745 ring = &adev->sdma.instance[i].ring; 746 r = amdgpu_ring_test_helper(ring); 747 if (r) 748 return r; 749 } 750 751 return 0; 752 } 753 754 /** 755 * sdma_v3_0_rlc_resume - setup and start the async dma engines 756 * 757 * @adev: amdgpu_device pointer 758 * 759 * Set up the compute DMA queues and enable them (VI). 760 * Returns 0 for success, error for failure. 761 */ 762 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev) 763 { 764 /* XXX todo */ 765 return 0; 766 } 767 768 /** 769 * sdma_v3_0_start - setup and start the async dma engines 770 * 771 * @adev: amdgpu_device pointer 772 * 773 * Set up the DMA engines and enable them (VI). 774 * Returns 0 for success, error for failure. 775 */ 776 static int sdma_v3_0_start(struct amdgpu_device *adev) 777 { 778 int r; 779 780 /* disable sdma engine before programing it */ 781 sdma_v3_0_ctx_switch_enable(adev, false); 782 sdma_v3_0_enable(adev, false); 783 784 /* start the gfx rings and rlc compute queues */ 785 r = sdma_v3_0_gfx_resume(adev); 786 if (r) 787 return r; 788 r = sdma_v3_0_rlc_resume(adev); 789 if (r) 790 return r; 791 792 return 0; 793 } 794 795 /** 796 * sdma_v3_0_ring_test_ring - simple async dma engine test 797 * 798 * @ring: amdgpu_ring structure holding ring information 799 * 800 * Test the DMA engine by writing using it to write an 801 * value to memory. (VI). 802 * Returns 0 for success, error for failure. 803 */ 804 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) 805 { 806 struct amdgpu_device *adev = ring->adev; 807 unsigned i; 808 unsigned index; 809 int r; 810 u32 tmp; 811 u64 gpu_addr; 812 813 r = amdgpu_device_wb_get(adev, &index); 814 if (r) 815 return r; 816 817 gpu_addr = adev->wb.gpu_addr + (index * 4); 818 tmp = 0xCAFEDEAD; 819 adev->wb.wb[index] = cpu_to_le32(tmp); 820 821 r = amdgpu_ring_alloc(ring, 5); 822 if (r) 823 goto error_free_wb; 824 825 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 826 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 827 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 828 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 829 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 830 amdgpu_ring_write(ring, 0xDEADBEEF); 831 amdgpu_ring_commit(ring); 832 833 for (i = 0; i < adev->usec_timeout; i++) { 834 tmp = le32_to_cpu(adev->wb.wb[index]); 835 if (tmp == 0xDEADBEEF) 836 break; 837 udelay(1); 838 } 839 840 if (i >= adev->usec_timeout) 841 r = -ETIMEDOUT; 842 843 error_free_wb: 844 amdgpu_device_wb_free(adev, index); 845 return r; 846 } 847 848 /** 849 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine 850 * 851 * @ring: amdgpu_ring structure holding ring information 852 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 853 * 854 * Test a simple IB in the DMA ring (VI). 855 * Returns 0 on success, error on failure. 856 */ 857 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 858 { 859 struct amdgpu_device *adev = ring->adev; 860 struct amdgpu_ib ib; 861 struct dma_fence *f = NULL; 862 unsigned index; 863 u32 tmp = 0; 864 u64 gpu_addr; 865 long r; 866 867 r = amdgpu_device_wb_get(adev, &index); 868 if (r) 869 return r; 870 871 gpu_addr = adev->wb.gpu_addr + (index * 4); 872 tmp = 0xCAFEDEAD; 873 adev->wb.wb[index] = cpu_to_le32(tmp); 874 memset(&ib, 0, sizeof(ib)); 875 r = amdgpu_ib_get(adev, NULL, 256, 876 AMDGPU_IB_POOL_DIRECT, &ib); 877 if (r) 878 goto err0; 879 880 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 881 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 882 ib.ptr[1] = lower_32_bits(gpu_addr); 883 ib.ptr[2] = upper_32_bits(gpu_addr); 884 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); 885 ib.ptr[4] = 0xDEADBEEF; 886 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 887 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 888 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 889 ib.length_dw = 8; 890 891 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 892 if (r) 893 goto err1; 894 895 r = dma_fence_wait_timeout(f, false, timeout); 896 if (r == 0) { 897 r = -ETIMEDOUT; 898 goto err1; 899 } else if (r < 0) { 900 goto err1; 901 } 902 tmp = le32_to_cpu(adev->wb.wb[index]); 903 if (tmp == 0xDEADBEEF) 904 r = 0; 905 else 906 r = -EINVAL; 907 err1: 908 amdgpu_ib_free(&ib, NULL); 909 dma_fence_put(f); 910 err0: 911 amdgpu_device_wb_free(adev, index); 912 return r; 913 } 914 915 /** 916 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART 917 * 918 * @ib: indirect buffer to fill with commands 919 * @pe: addr of the page entry 920 * @src: src addr to copy from 921 * @count: number of page entries to update 922 * 923 * Update PTEs by copying them from the GART using sDMA (CIK). 924 */ 925 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib, 926 uint64_t pe, uint64_t src, 927 unsigned count) 928 { 929 unsigned bytes = count * 8; 930 931 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 932 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 933 ib->ptr[ib->length_dw++] = bytes; 934 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 935 ib->ptr[ib->length_dw++] = lower_32_bits(src); 936 ib->ptr[ib->length_dw++] = upper_32_bits(src); 937 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 938 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 939 } 940 941 /** 942 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually 943 * 944 * @ib: indirect buffer to fill with commands 945 * @pe: addr of the page entry 946 * @value: dst addr to write into pe 947 * @count: number of page entries to update 948 * @incr: increase next addr by incr bytes 949 * 950 * Update PTEs by writing them manually using sDMA (CIK). 951 */ 952 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 953 uint64_t value, unsigned count, 954 uint32_t incr) 955 { 956 unsigned ndw = count * 2; 957 958 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 959 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 960 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 961 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 962 ib->ptr[ib->length_dw++] = ndw; 963 for (; ndw > 0; ndw -= 2) { 964 ib->ptr[ib->length_dw++] = lower_32_bits(value); 965 ib->ptr[ib->length_dw++] = upper_32_bits(value); 966 value += incr; 967 } 968 } 969 970 /** 971 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA 972 * 973 * @ib: indirect buffer to fill with commands 974 * @pe: addr of the page entry 975 * @addr: dst addr to write into pe 976 * @count: number of page entries to update 977 * @incr: increase next addr by incr bytes 978 * @flags: access flags 979 * 980 * Update the page tables using sDMA (CIK). 981 */ 982 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, 983 uint64_t addr, unsigned count, 984 uint32_t incr, uint64_t flags) 985 { 986 /* for physically contiguous pages (vram) */ 987 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); 988 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 989 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 990 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 991 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 992 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 993 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 994 ib->ptr[ib->length_dw++] = incr; /* increment size */ 995 ib->ptr[ib->length_dw++] = 0; 996 ib->ptr[ib->length_dw++] = count; /* number of entries */ 997 } 998 999 /** 1000 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw 1001 * 1002 * @ring: amdgpu_ring structure holding ring information 1003 * @ib: indirect buffer to fill with padding 1004 * 1005 */ 1006 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1007 { 1008 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1009 u32 pad_count; 1010 int i; 1011 1012 pad_count = (-ib->length_dw) & 7; 1013 for (i = 0; i < pad_count; i++) 1014 if (sdma && sdma->burst_nop && (i == 0)) 1015 ib->ptr[ib->length_dw++] = 1016 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1017 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1018 else 1019 ib->ptr[ib->length_dw++] = 1020 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1021 } 1022 1023 /** 1024 * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline 1025 * 1026 * @ring: amdgpu_ring pointer 1027 * 1028 * Make sure all previous operations are completed (CIK). 1029 */ 1030 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1031 { 1032 uint32_t seq = ring->fence_drv.sync_seq; 1033 uint64_t addr = ring->fence_drv.gpu_addr; 1034 1035 /* wait for idle */ 1036 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1037 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1038 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1039 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1040 amdgpu_ring_write(ring, addr & 0xfffffffc); 1041 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1042 amdgpu_ring_write(ring, seq); /* reference */ 1043 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1044 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1045 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1046 } 1047 1048 /** 1049 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA 1050 * 1051 * @ring: amdgpu_ring pointer 1052 * @vmid: vmid number to use 1053 * @pd_addr: address 1054 * 1055 * Update the page table base and flush the VM TLB 1056 * using sDMA (VI). 1057 */ 1058 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1059 unsigned vmid, uint64_t pd_addr) 1060 { 1061 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1062 1063 /* wait for flush */ 1064 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1065 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1066 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ 1067 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 1068 amdgpu_ring_write(ring, 0); 1069 amdgpu_ring_write(ring, 0); /* reference */ 1070 amdgpu_ring_write(ring, 0); /* mask */ 1071 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1072 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 1073 } 1074 1075 static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring, 1076 uint32_t reg, uint32_t val) 1077 { 1078 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1079 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1080 amdgpu_ring_write(ring, reg); 1081 amdgpu_ring_write(ring, val); 1082 } 1083 1084 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { 1085 .copy_pte_num_dw = 7, 1086 .copy_pte = sdma_v3_0_vm_copy_pte, 1087 1088 .write_pte = sdma_v3_0_vm_write_pte, 1089 .set_pte_pde = sdma_v3_0_vm_set_pte_pde, 1090 }; 1091 1092 static int sdma_v3_0_early_init(struct amdgpu_ip_block *ip_block) 1093 { 1094 struct amdgpu_device *adev = ip_block->adev; 1095 int r; 1096 1097 switch (adev->asic_type) { 1098 case CHIP_STONEY: 1099 adev->sdma.num_instances = 1; 1100 break; 1101 default: 1102 adev->sdma.num_instances = SDMA_MAX_INSTANCE; 1103 break; 1104 } 1105 1106 r = sdma_v3_0_init_microcode(adev); 1107 if (r) 1108 return r; 1109 1110 sdma_v3_0_set_ring_funcs(adev); 1111 sdma_v3_0_set_buffer_funcs(adev); 1112 amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v3_0_vm_pte_funcs); 1113 sdma_v3_0_set_irq_funcs(adev); 1114 1115 return 0; 1116 } 1117 1118 static int sdma_v3_0_sw_init(struct amdgpu_ip_block *ip_block) 1119 { 1120 struct amdgpu_ring *ring; 1121 int r, i; 1122 struct amdgpu_device *adev = ip_block->adev; 1123 1124 /* SDMA trap event */ 1125 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP, 1126 &adev->sdma.trap_irq); 1127 if (r) 1128 return r; 1129 1130 /* SDMA Privileged inst */ 1131 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241, 1132 &adev->sdma.illegal_inst_irq); 1133 if (r) 1134 return r; 1135 1136 /* SDMA Privileged inst */ 1137 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE, 1138 &adev->sdma.illegal_inst_irq); 1139 if (r) 1140 return r; 1141 1142 for (i = 0; i < adev->sdma.num_instances; i++) { 1143 ring = &adev->sdma.instance[i].ring; 1144 ring->ring_obj = NULL; 1145 if (!amdgpu_sriov_vf(adev)) { 1146 ring->use_doorbell = true; 1147 ring->doorbell_index = adev->doorbell_index.sdma_engine[i]; 1148 } else { 1149 ring->use_pollmem = true; 1150 } 1151 1152 sprintf(ring->name, "sdma%d", i); 1153 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1154 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 : 1155 AMDGPU_SDMA_IRQ_INSTANCE1, 1156 AMDGPU_RING_PRIO_DEFAULT, NULL); 1157 if (r) 1158 return r; 1159 } 1160 1161 return r; 1162 } 1163 1164 static int sdma_v3_0_sw_fini(struct amdgpu_ip_block *ip_block) 1165 { 1166 struct amdgpu_device *adev = ip_block->adev; 1167 int i; 1168 1169 for (i = 0; i < adev->sdma.num_instances; i++) 1170 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1171 1172 sdma_v3_0_free_microcode(adev); 1173 return 0; 1174 } 1175 1176 static int sdma_v3_0_hw_init(struct amdgpu_ip_block *ip_block) 1177 { 1178 int r; 1179 struct amdgpu_device *adev = ip_block->adev; 1180 1181 sdma_v3_0_init_golden_registers(adev); 1182 1183 r = sdma_v3_0_start(adev); 1184 if (r) 1185 return r; 1186 1187 return r; 1188 } 1189 1190 static int sdma_v3_0_hw_fini(struct amdgpu_ip_block *ip_block) 1191 { 1192 struct amdgpu_device *adev = ip_block->adev; 1193 1194 sdma_v3_0_ctx_switch_enable(adev, false); 1195 sdma_v3_0_enable(adev, false); 1196 1197 return 0; 1198 } 1199 1200 static int sdma_v3_0_suspend(struct amdgpu_ip_block *ip_block) 1201 { 1202 return sdma_v3_0_hw_fini(ip_block); 1203 } 1204 1205 static int sdma_v3_0_resume(struct amdgpu_ip_block *ip_block) 1206 { 1207 return sdma_v3_0_hw_init(ip_block); 1208 } 1209 1210 static bool sdma_v3_0_is_idle(struct amdgpu_ip_block *ip_block) 1211 { 1212 struct amdgpu_device *adev = ip_block->adev; 1213 u32 tmp = RREG32(mmSRBM_STATUS2); 1214 1215 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1216 SRBM_STATUS2__SDMA1_BUSY_MASK)) 1217 return false; 1218 1219 return true; 1220 } 1221 1222 static int sdma_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1223 { 1224 unsigned i; 1225 u32 tmp; 1226 struct amdgpu_device *adev = ip_block->adev; 1227 1228 for (i = 0; i < adev->usec_timeout; i++) { 1229 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1230 SRBM_STATUS2__SDMA1_BUSY_MASK); 1231 1232 if (!tmp) 1233 return 0; 1234 udelay(1); 1235 } 1236 return -ETIMEDOUT; 1237 } 1238 1239 static bool sdma_v3_0_check_soft_reset(struct amdgpu_ip_block *ip_block) 1240 { 1241 struct amdgpu_device *adev = ip_block->adev; 1242 u32 srbm_soft_reset = 0; 1243 u32 tmp = RREG32(mmSRBM_STATUS2); 1244 1245 if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) || 1246 (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) { 1247 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1248 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1249 } 1250 1251 if (srbm_soft_reset) { 1252 adev->sdma.srbm_soft_reset = srbm_soft_reset; 1253 return true; 1254 } else { 1255 adev->sdma.srbm_soft_reset = 0; 1256 return false; 1257 } 1258 } 1259 1260 static int sdma_v3_0_pre_soft_reset(struct amdgpu_ip_block *ip_block) 1261 { 1262 struct amdgpu_device *adev = ip_block->adev; 1263 u32 srbm_soft_reset = 0; 1264 1265 if (!adev->sdma.srbm_soft_reset) 1266 return 0; 1267 1268 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1269 1270 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || 1271 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { 1272 sdma_v3_0_ctx_switch_enable(adev, false); 1273 sdma_v3_0_enable(adev, false); 1274 } 1275 1276 return 0; 1277 } 1278 1279 static int sdma_v3_0_post_soft_reset(struct amdgpu_ip_block *ip_block) 1280 { 1281 struct amdgpu_device *adev = ip_block->adev; 1282 u32 srbm_soft_reset = 0; 1283 1284 if (!adev->sdma.srbm_soft_reset) 1285 return 0; 1286 1287 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1288 1289 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || 1290 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { 1291 sdma_v3_0_gfx_resume(adev); 1292 sdma_v3_0_rlc_resume(adev); 1293 } 1294 1295 return 0; 1296 } 1297 1298 static int sdma_v3_0_soft_reset(struct amdgpu_ip_block *ip_block) 1299 { 1300 struct amdgpu_device *adev = ip_block->adev; 1301 u32 srbm_soft_reset = 0; 1302 u32 tmp; 1303 1304 if (!adev->sdma.srbm_soft_reset) 1305 return 0; 1306 1307 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1308 1309 if (srbm_soft_reset) { 1310 tmp = RREG32(mmSRBM_SOFT_RESET); 1311 tmp |= srbm_soft_reset; 1312 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1313 WREG32(mmSRBM_SOFT_RESET, tmp); 1314 tmp = RREG32(mmSRBM_SOFT_RESET); 1315 1316 udelay(50); 1317 1318 tmp &= ~srbm_soft_reset; 1319 WREG32(mmSRBM_SOFT_RESET, tmp); 1320 tmp = RREG32(mmSRBM_SOFT_RESET); 1321 1322 /* Wait a little for things to settle down */ 1323 udelay(50); 1324 } 1325 1326 return 0; 1327 } 1328 1329 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev, 1330 struct amdgpu_irq_src *source, 1331 unsigned type, 1332 enum amdgpu_interrupt_state state) 1333 { 1334 u32 sdma_cntl; 1335 1336 switch (type) { 1337 case AMDGPU_SDMA_IRQ_INSTANCE0: 1338 switch (state) { 1339 case AMDGPU_IRQ_STATE_DISABLE: 1340 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1341 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1342 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1343 break; 1344 case AMDGPU_IRQ_STATE_ENABLE: 1345 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1346 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1347 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1348 break; 1349 default: 1350 break; 1351 } 1352 break; 1353 case AMDGPU_SDMA_IRQ_INSTANCE1: 1354 switch (state) { 1355 case AMDGPU_IRQ_STATE_DISABLE: 1356 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1357 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1358 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1359 break; 1360 case AMDGPU_IRQ_STATE_ENABLE: 1361 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1362 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1363 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1364 break; 1365 default: 1366 break; 1367 } 1368 break; 1369 default: 1370 break; 1371 } 1372 return 0; 1373 } 1374 1375 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev, 1376 struct amdgpu_irq_src *source, 1377 struct amdgpu_iv_entry *entry) 1378 { 1379 u8 instance_id, queue_id; 1380 1381 instance_id = (entry->ring_id & 0x3) >> 0; 1382 queue_id = (entry->ring_id & 0xc) >> 2; 1383 DRM_DEBUG("IH: SDMA trap\n"); 1384 switch (instance_id) { 1385 case 0: 1386 switch (queue_id) { 1387 case 0: 1388 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1389 break; 1390 case 1: 1391 /* XXX compute */ 1392 break; 1393 case 2: 1394 /* XXX compute */ 1395 break; 1396 } 1397 break; 1398 case 1: 1399 switch (queue_id) { 1400 case 0: 1401 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1402 break; 1403 case 1: 1404 /* XXX compute */ 1405 break; 1406 case 2: 1407 /* XXX compute */ 1408 break; 1409 } 1410 break; 1411 } 1412 return 0; 1413 } 1414 1415 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1416 struct amdgpu_irq_src *source, 1417 struct amdgpu_iv_entry *entry) 1418 { 1419 u8 instance_id, queue_id; 1420 1421 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1422 instance_id = (entry->ring_id & 0x3) >> 0; 1423 queue_id = (entry->ring_id & 0xc) >> 2; 1424 1425 if (instance_id <= 1 && queue_id == 0) 1426 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched); 1427 return 0; 1428 } 1429 1430 static void sdma_v3_0_update_sdma_medium_grain_clock_gating( 1431 struct amdgpu_device *adev, 1432 bool enable) 1433 { 1434 uint32_t temp, data; 1435 int i; 1436 1437 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1438 for (i = 0; i < adev->sdma.num_instances; i++) { 1439 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); 1440 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1441 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1442 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1443 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1444 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1445 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1446 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1447 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1448 if (data != temp) 1449 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); 1450 } 1451 } else { 1452 for (i = 0; i < adev->sdma.num_instances; i++) { 1453 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); 1454 data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1455 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1456 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1457 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1458 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1459 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1460 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1461 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK; 1462 1463 if (data != temp) 1464 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); 1465 } 1466 } 1467 } 1468 1469 static void sdma_v3_0_update_sdma_medium_grain_light_sleep( 1470 struct amdgpu_device *adev, 1471 bool enable) 1472 { 1473 uint32_t temp, data; 1474 int i; 1475 1476 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1477 for (i = 0; i < adev->sdma.num_instances; i++) { 1478 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1479 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1480 1481 if (temp != data) 1482 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1483 } 1484 } else { 1485 for (i = 0; i < adev->sdma.num_instances; i++) { 1486 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1487 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1488 1489 if (temp != data) 1490 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1491 } 1492 } 1493 } 1494 1495 static int sdma_v3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1496 enum amd_clockgating_state state) 1497 { 1498 struct amdgpu_device *adev = ip_block->adev; 1499 1500 if (amdgpu_sriov_vf(adev)) 1501 return 0; 1502 1503 switch (adev->asic_type) { 1504 case CHIP_FIJI: 1505 case CHIP_CARRIZO: 1506 case CHIP_STONEY: 1507 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev, 1508 state == AMD_CG_STATE_GATE); 1509 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev, 1510 state == AMD_CG_STATE_GATE); 1511 break; 1512 default: 1513 break; 1514 } 1515 return 0; 1516 } 1517 1518 static int sdma_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 1519 enum amd_powergating_state state) 1520 { 1521 return 0; 1522 } 1523 1524 static void sdma_v3_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1525 { 1526 struct amdgpu_device *adev = ip_block->adev; 1527 int data; 1528 1529 if (amdgpu_sriov_vf(adev)) 1530 *flags = 0; 1531 1532 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1533 data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]); 1534 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK)) 1535 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1536 1537 /* AMD_CG_SUPPORT_SDMA_LS */ 1538 data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]); 1539 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1540 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1541 } 1542 1543 static const struct amd_ip_funcs sdma_v3_0_ip_funcs = { 1544 .name = "sdma_v3_0", 1545 .early_init = sdma_v3_0_early_init, 1546 .sw_init = sdma_v3_0_sw_init, 1547 .sw_fini = sdma_v3_0_sw_fini, 1548 .hw_init = sdma_v3_0_hw_init, 1549 .hw_fini = sdma_v3_0_hw_fini, 1550 .suspend = sdma_v3_0_suspend, 1551 .resume = sdma_v3_0_resume, 1552 .is_idle = sdma_v3_0_is_idle, 1553 .wait_for_idle = sdma_v3_0_wait_for_idle, 1554 .check_soft_reset = sdma_v3_0_check_soft_reset, 1555 .pre_soft_reset = sdma_v3_0_pre_soft_reset, 1556 .post_soft_reset = sdma_v3_0_post_soft_reset, 1557 .soft_reset = sdma_v3_0_soft_reset, 1558 .set_clockgating_state = sdma_v3_0_set_clockgating_state, 1559 .set_powergating_state = sdma_v3_0_set_powergating_state, 1560 .get_clockgating_state = sdma_v3_0_get_clockgating_state, 1561 }; 1562 1563 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { 1564 .type = AMDGPU_RING_TYPE_SDMA, 1565 .align_mask = 0xf, 1566 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1567 .support_64bit_ptrs = false, 1568 .secure_submission_supported = true, 1569 .get_rptr = sdma_v3_0_ring_get_rptr, 1570 .get_wptr = sdma_v3_0_ring_get_wptr, 1571 .set_wptr = sdma_v3_0_ring_set_wptr, 1572 .emit_frame_size = 1573 6 + /* sdma_v3_0_ring_emit_hdp_flush */ 1574 3 + /* hdp invalidate */ 1575 6 + /* sdma_v3_0_ring_emit_pipeline_sync */ 1576 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v3_0_ring_emit_vm_flush */ 1577 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */ 1578 .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */ 1579 .emit_ib = sdma_v3_0_ring_emit_ib, 1580 .emit_fence = sdma_v3_0_ring_emit_fence, 1581 .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync, 1582 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, 1583 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, 1584 .test_ring = sdma_v3_0_ring_test_ring, 1585 .test_ib = sdma_v3_0_ring_test_ib, 1586 .insert_nop = sdma_v3_0_ring_insert_nop, 1587 .pad_ib = sdma_v3_0_ring_pad_ib, 1588 .emit_wreg = sdma_v3_0_ring_emit_wreg, 1589 }; 1590 1591 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev) 1592 { 1593 int i; 1594 1595 for (i = 0; i < adev->sdma.num_instances; i++) { 1596 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs; 1597 adev->sdma.instance[i].ring.me = i; 1598 } 1599 } 1600 1601 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = { 1602 .set = sdma_v3_0_set_trap_irq_state, 1603 .process = sdma_v3_0_process_trap_irq, 1604 }; 1605 1606 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = { 1607 .process = sdma_v3_0_process_illegal_inst_irq, 1608 }; 1609 1610 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev) 1611 { 1612 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1613 adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs; 1614 adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs; 1615 } 1616 1617 /** 1618 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine 1619 * 1620 * @ib: indirect buffer to copy to 1621 * @src_offset: src GPU address 1622 * @dst_offset: dst GPU address 1623 * @byte_count: number of bytes to xfer 1624 * @copy_flags: unused 1625 * 1626 * Copy GPU buffers using the DMA engine (VI). 1627 * Used by the amdgpu ttm implementation to move pages if 1628 * registered as the asic copy callback. 1629 */ 1630 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib, 1631 uint64_t src_offset, 1632 uint64_t dst_offset, 1633 uint32_t byte_count, 1634 uint32_t copy_flags) 1635 { 1636 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1637 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1638 ib->ptr[ib->length_dw++] = byte_count; 1639 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1640 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1641 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1642 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1643 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1644 } 1645 1646 /** 1647 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine 1648 * 1649 * @ib: indirect buffer to copy to 1650 * @src_data: value to write to buffer 1651 * @dst_offset: dst GPU address 1652 * @byte_count: number of bytes to xfer 1653 * 1654 * Fill GPU buffers using the DMA engine (VI). 1655 */ 1656 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib, 1657 uint32_t src_data, 1658 uint64_t dst_offset, 1659 uint32_t byte_count) 1660 { 1661 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1662 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1663 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1664 ib->ptr[ib->length_dw++] = src_data; 1665 ib->ptr[ib->length_dw++] = byte_count; 1666 } 1667 1668 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = { 1669 .copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */ 1670 .copy_num_dw = 7, 1671 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer, 1672 1673 .fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */ 1674 .fill_num_dw = 5, 1675 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer, 1676 }; 1677 1678 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) 1679 { 1680 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs; 1681 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1682 } 1683 1684 const struct amdgpu_ip_block_version sdma_v3_0_ip_block = 1685 { 1686 .type = AMD_IP_BLOCK_TYPE_SDMA, 1687 .major = 3, 1688 .minor = 0, 1689 .rev = 0, 1690 .funcs = &sdma_v3_0_ip_funcs, 1691 }; 1692 1693 const struct amdgpu_ip_block_version sdma_v3_1_ip_block = 1694 { 1695 .type = AMD_IP_BLOCK_TYPE_SDMA, 1696 .major = 3, 1697 .minor = 1, 1698 .rev = 0, 1699 .funcs = &sdma_v3_0_ip_funcs, 1700 }; 1701