1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 25 #include <linux/delay.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 #include "vi.h" 33 #include "vid.h" 34 35 #include "oss/oss_3_0_d.h" 36 #include "oss/oss_3_0_sh_mask.h" 37 38 #include "gmc/gmc_8_1_d.h" 39 #include "gmc/gmc_8_1_sh_mask.h" 40 41 #include "gca/gfx_8_0_d.h" 42 #include "gca/gfx_8_0_enum.h" 43 #include "gca/gfx_8_0_sh_mask.h" 44 45 #include "bif/bif_5_0_d.h" 46 #include "bif/bif_5_0_sh_mask.h" 47 48 #include "tonga_sdma_pkt_open.h" 49 50 #include "ivsrcid/ivsrcid_vislands30.h" 51 52 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev); 53 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); 54 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); 55 56 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); 57 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin"); 58 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin"); 59 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); 60 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); 61 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); 62 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin"); 63 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin"); 65 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin"); 66 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin"); 67 MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin"); 68 MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin"); 69 MODULE_FIRMWARE("amdgpu/vegam_sdma.bin"); 70 MODULE_FIRMWARE("amdgpu/vegam_sdma1.bin"); 71 72 73 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 74 { 75 SDMA0_REGISTER_OFFSET, 76 SDMA1_REGISTER_OFFSET 77 }; 78 79 static const u32 golden_settings_tonga_a11[] = 80 { 81 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 82 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 83 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 84 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 85 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 86 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 87 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 88 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 89 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 90 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 91 }; 92 93 static const u32 tonga_mgcg_cgcg_init[] = 94 { 95 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 96 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 97 }; 98 99 static const u32 golden_settings_fiji_a10[] = 100 { 101 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 102 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 103 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 104 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 105 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 106 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 107 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 108 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 109 }; 110 111 static const u32 fiji_mgcg_cgcg_init[] = 112 { 113 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 114 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 115 }; 116 117 static const u32 golden_settings_polaris11_a11[] = 118 { 119 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 120 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 121 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 122 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 123 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 124 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 125 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 126 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 127 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 128 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 129 }; 130 131 static const u32 golden_settings_polaris10_a11[] = 132 { 133 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 134 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 135 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 136 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 137 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 138 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 139 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 140 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 141 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 142 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 143 }; 144 145 static const u32 cz_golden_settings_a11[] = 146 { 147 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 148 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 149 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 150 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 151 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 152 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 153 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 154 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 155 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100, 156 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800, 157 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100, 158 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100, 159 }; 160 161 static const u32 cz_mgcg_cgcg_init[] = 162 { 163 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 164 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 165 }; 166 167 static const u32 stoney_golden_settings_a11[] = 168 { 169 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 170 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 171 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 172 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 173 }; 174 175 static const u32 stoney_mgcg_cgcg_init[] = 176 { 177 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100, 178 }; 179 180 /* 181 * sDMA - System DMA 182 * Starting with CIK, the GPU has new asynchronous 183 * DMA engines. These engines are used for compute 184 * and gfx. There are two DMA engines (SDMA0, SDMA1) 185 * and each one supports 1 ring buffer used for gfx 186 * and 2 queues used for compute. 187 * 188 * The programming model is very similar to the CP 189 * (ring buffer, IBs, etc.), but sDMA has it's own 190 * packet format that is different from the PM4 format 191 * used by the CP. sDMA supports copying data, writing 192 * embedded data, solid fills, and a number of other 193 * things. It also has support for tiling/detiling of 194 * buffers. 195 */ 196 197 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) 198 { 199 switch (adev->asic_type) { 200 case CHIP_FIJI: 201 amdgpu_device_program_register_sequence(adev, 202 fiji_mgcg_cgcg_init, 203 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 204 amdgpu_device_program_register_sequence(adev, 205 golden_settings_fiji_a10, 206 ARRAY_SIZE(golden_settings_fiji_a10)); 207 break; 208 case CHIP_TONGA: 209 amdgpu_device_program_register_sequence(adev, 210 tonga_mgcg_cgcg_init, 211 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 212 amdgpu_device_program_register_sequence(adev, 213 golden_settings_tonga_a11, 214 ARRAY_SIZE(golden_settings_tonga_a11)); 215 break; 216 case CHIP_POLARIS11: 217 case CHIP_POLARIS12: 218 case CHIP_VEGAM: 219 amdgpu_device_program_register_sequence(adev, 220 golden_settings_polaris11_a11, 221 ARRAY_SIZE(golden_settings_polaris11_a11)); 222 break; 223 case CHIP_POLARIS10: 224 amdgpu_device_program_register_sequence(adev, 225 golden_settings_polaris10_a11, 226 ARRAY_SIZE(golden_settings_polaris10_a11)); 227 break; 228 case CHIP_CARRIZO: 229 amdgpu_device_program_register_sequence(adev, 230 cz_mgcg_cgcg_init, 231 ARRAY_SIZE(cz_mgcg_cgcg_init)); 232 amdgpu_device_program_register_sequence(adev, 233 cz_golden_settings_a11, 234 ARRAY_SIZE(cz_golden_settings_a11)); 235 break; 236 case CHIP_STONEY: 237 amdgpu_device_program_register_sequence(adev, 238 stoney_mgcg_cgcg_init, 239 ARRAY_SIZE(stoney_mgcg_cgcg_init)); 240 amdgpu_device_program_register_sequence(adev, 241 stoney_golden_settings_a11, 242 ARRAY_SIZE(stoney_golden_settings_a11)); 243 break; 244 default: 245 break; 246 } 247 } 248 249 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev) 250 { 251 int i; 252 253 for (i = 0; i < adev->sdma.num_instances; i++) 254 amdgpu_ucode_release(&adev->sdma.instance[i].fw); 255 } 256 257 /** 258 * sdma_v3_0_init_microcode - load ucode images from disk 259 * 260 * @adev: amdgpu_device pointer 261 * 262 * Use the firmware interface to load the ucode images into 263 * the driver (not loaded into hw). 264 * Returns 0 on success, error on failure. 265 */ 266 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) 267 { 268 const char *chip_name; 269 int err = 0, i; 270 struct amdgpu_firmware_info *info = NULL; 271 const struct common_firmware_header *header = NULL; 272 const struct sdma_firmware_header_v1_0 *hdr; 273 274 DRM_DEBUG("\n"); 275 276 switch (adev->asic_type) { 277 case CHIP_TONGA: 278 chip_name = "tonga"; 279 break; 280 case CHIP_FIJI: 281 chip_name = "fiji"; 282 break; 283 case CHIP_POLARIS10: 284 chip_name = "polaris10"; 285 break; 286 case CHIP_POLARIS11: 287 chip_name = "polaris11"; 288 break; 289 case CHIP_POLARIS12: 290 chip_name = "polaris12"; 291 break; 292 case CHIP_VEGAM: 293 chip_name = "vegam"; 294 break; 295 case CHIP_CARRIZO: 296 chip_name = "carrizo"; 297 break; 298 case CHIP_STONEY: 299 chip_name = "stoney"; 300 break; 301 default: 302 return -EINVAL; 303 } 304 305 for (i = 0; i < adev->sdma.num_instances; i++) { 306 if (i == 0) 307 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw, 308 AMDGPU_UCODE_REQUIRED, 309 "amdgpu/%s_sdma.bin", chip_name); 310 else 311 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw, 312 AMDGPU_UCODE_REQUIRED, 313 "amdgpu/%s_sdma1.bin", chip_name); 314 if (err) 315 goto out; 316 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 317 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 318 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 319 if (adev->sdma.instance[i].feature_version >= 20) 320 adev->sdma.instance[i].burst_nop = true; 321 322 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 323 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 324 info->fw = adev->sdma.instance[i].fw; 325 header = (const struct common_firmware_header *)info->fw->data; 326 adev->firmware.fw_size += 327 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 328 329 } 330 out: 331 if (err) { 332 pr_err("sdma_v3_0: Failed to load firmware \"%s_sdma%s.bin\"\n", 333 chip_name, i == 0 ? "" : "1"); 334 for (i = 0; i < adev->sdma.num_instances; i++) 335 amdgpu_ucode_release(&adev->sdma.instance[i].fw); 336 } 337 return err; 338 } 339 340 /** 341 * sdma_v3_0_ring_get_rptr - get the current read pointer 342 * 343 * @ring: amdgpu ring pointer 344 * 345 * Get the current rptr from the hardware (VI+). 346 */ 347 static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring) 348 { 349 /* XXX check if swapping is necessary on BE */ 350 return *ring->rptr_cpu_addr >> 2; 351 } 352 353 /** 354 * sdma_v3_0_ring_get_wptr - get the current write pointer 355 * 356 * @ring: amdgpu ring pointer 357 * 358 * Get the current wptr from the hardware (VI+). 359 */ 360 static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring) 361 { 362 struct amdgpu_device *adev = ring->adev; 363 u32 wptr; 364 365 if (ring->use_doorbell || ring->use_pollmem) { 366 /* XXX check if swapping is necessary on BE */ 367 wptr = *ring->wptr_cpu_addr >> 2; 368 } else { 369 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; 370 } 371 372 return wptr; 373 } 374 375 /** 376 * sdma_v3_0_ring_set_wptr - commit the write pointer 377 * 378 * @ring: amdgpu ring pointer 379 * 380 * Write the wptr back to the hardware (VI+). 381 */ 382 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) 383 { 384 struct amdgpu_device *adev = ring->adev; 385 386 if (ring->use_doorbell) { 387 u32 *wb = (u32 *)ring->wptr_cpu_addr; 388 /* XXX check if swapping is necessary on BE */ 389 WRITE_ONCE(*wb, ring->wptr << 2); 390 WDOORBELL32(ring->doorbell_index, ring->wptr << 2); 391 } else if (ring->use_pollmem) { 392 u32 *wb = (u32 *)ring->wptr_cpu_addr; 393 394 WRITE_ONCE(*wb, ring->wptr << 2); 395 } else { 396 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2); 397 } 398 } 399 400 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 401 { 402 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 403 int i; 404 405 for (i = 0; i < count; i++) 406 if (sdma && sdma->burst_nop && (i == 0)) 407 amdgpu_ring_write(ring, ring->funcs->nop | 408 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 409 else 410 amdgpu_ring_write(ring, ring->funcs->nop); 411 } 412 413 /** 414 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine 415 * 416 * @ring: amdgpu ring pointer 417 * @job: job to retrieve vmid from 418 * @ib: IB object to schedule 419 * @flags: unused 420 * 421 * Schedule an IB in the DMA ring (VI). 422 */ 423 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, 424 struct amdgpu_job *job, 425 struct amdgpu_ib *ib, 426 uint32_t flags) 427 { 428 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 429 430 /* IB packet must end on a 8 DW boundary */ 431 sdma_v3_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 432 433 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 434 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 435 /* base must be 32 byte aligned */ 436 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 437 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 438 amdgpu_ring_write(ring, ib->length_dw); 439 amdgpu_ring_write(ring, 0); 440 amdgpu_ring_write(ring, 0); 441 442 } 443 444 /** 445 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 446 * 447 * @ring: amdgpu ring pointer 448 * 449 * Emit an hdp flush packet on the requested DMA ring. 450 */ 451 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 452 { 453 u32 ref_and_mask = 0; 454 455 if (ring->me == 0) 456 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); 457 else 458 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); 459 460 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 461 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 462 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 463 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 464 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 465 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 466 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 467 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 468 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 469 } 470 471 /** 472 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring 473 * 474 * @ring: amdgpu ring pointer 475 * @addr: address 476 * @seq: sequence number 477 * @flags: fence related flags 478 * 479 * Add a DMA fence packet to the ring to write 480 * the fence seq number and DMA trap packet to generate 481 * an interrupt if needed (VI). 482 */ 483 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 484 unsigned flags) 485 { 486 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 487 /* write the fence */ 488 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 489 amdgpu_ring_write(ring, lower_32_bits(addr)); 490 amdgpu_ring_write(ring, upper_32_bits(addr)); 491 amdgpu_ring_write(ring, lower_32_bits(seq)); 492 493 /* optionally write high bits as well */ 494 if (write64bit) { 495 addr += 4; 496 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 497 amdgpu_ring_write(ring, lower_32_bits(addr)); 498 amdgpu_ring_write(ring, upper_32_bits(addr)); 499 amdgpu_ring_write(ring, upper_32_bits(seq)); 500 } 501 502 /* generate an interrupt */ 503 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 504 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 505 } 506 507 /** 508 * sdma_v3_0_gfx_stop - stop the gfx async dma engines 509 * 510 * @adev: amdgpu_device pointer 511 * 512 * Stop the gfx async dma ring buffers (VI). 513 */ 514 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev) 515 { 516 u32 rb_cntl, ib_cntl; 517 int i; 518 519 for (i = 0; i < adev->sdma.num_instances; i++) { 520 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 521 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 522 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 523 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 524 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 525 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 526 } 527 } 528 529 /** 530 * sdma_v3_0_rlc_stop - stop the compute async dma engines 531 * 532 * @adev: amdgpu_device pointer 533 * 534 * Stop the compute async dma queues (VI). 535 */ 536 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev) 537 { 538 /* XXX todo */ 539 } 540 541 /** 542 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch 543 * 544 * @adev: amdgpu_device pointer 545 * @enable: enable/disable the DMA MEs context switch. 546 * 547 * Halt or unhalt the async dma engines context switch (VI). 548 */ 549 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 550 { 551 u32 f32_cntl, phase_quantum = 0; 552 int i; 553 554 if (amdgpu_sdma_phase_quantum) { 555 unsigned value = amdgpu_sdma_phase_quantum; 556 unsigned unit = 0; 557 558 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 559 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 560 value = (value + 1) >> 1; 561 unit++; 562 } 563 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 564 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 565 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 566 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 567 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 568 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 569 WARN_ONCE(1, 570 "clamping sdma_phase_quantum to %uK clock cycles\n", 571 value << unit); 572 } 573 phase_quantum = 574 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 575 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 576 } 577 578 for (i = 0; i < adev->sdma.num_instances; i++) { 579 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); 580 if (enable) { 581 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 582 AUTO_CTXSW_ENABLE, 1); 583 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 584 ATC_L1_ENABLE, 1); 585 if (amdgpu_sdma_phase_quantum) { 586 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], 587 phase_quantum); 588 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], 589 phase_quantum); 590 } 591 } else { 592 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 593 AUTO_CTXSW_ENABLE, 0); 594 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 595 ATC_L1_ENABLE, 1); 596 } 597 598 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); 599 } 600 } 601 602 /** 603 * sdma_v3_0_enable - stop the async dma engines 604 * 605 * @adev: amdgpu_device pointer 606 * @enable: enable/disable the DMA MEs. 607 * 608 * Halt or unhalt the async dma engines (VI). 609 */ 610 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable) 611 { 612 u32 f32_cntl; 613 int i; 614 615 if (!enable) { 616 sdma_v3_0_gfx_stop(adev); 617 sdma_v3_0_rlc_stop(adev); 618 } 619 620 for (i = 0; i < adev->sdma.num_instances; i++) { 621 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 622 if (enable) 623 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); 624 else 625 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 626 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); 627 } 628 } 629 630 /** 631 * sdma_v3_0_gfx_resume - setup and start the async dma engines 632 * 633 * @adev: amdgpu_device pointer 634 * 635 * Set up the gfx DMA ring buffers and enable them (VI). 636 * Returns 0 for success, error for failure. 637 */ 638 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) 639 { 640 struct amdgpu_ring *ring; 641 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 642 u32 rb_bufsz; 643 u32 doorbell; 644 u64 wptr_gpu_addr; 645 int i, j, r; 646 647 for (i = 0; i < adev->sdma.num_instances; i++) { 648 ring = &adev->sdma.instance[i].ring; 649 amdgpu_ring_clear_ring(ring); 650 651 mutex_lock(&adev->srbm_mutex); 652 for (j = 0; j < 16; j++) { 653 vi_srbm_select(adev, 0, 0, 0, j); 654 /* SDMA GFX */ 655 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 656 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 657 } 658 vi_srbm_select(adev, 0, 0, 0, 0); 659 mutex_unlock(&adev->srbm_mutex); 660 661 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], 662 adev->gfx.config.gb_addr_config & 0x70); 663 664 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 665 666 /* Set ring buffer size in dwords */ 667 rb_bufsz = order_base_2(ring->ring_size / 4); 668 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 669 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 670 #ifdef __BIG_ENDIAN 671 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 672 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 673 RPTR_WRITEBACK_SWAP_ENABLE, 1); 674 #endif 675 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 676 677 /* Initialize the ring buffer's read and write pointers */ 678 ring->wptr = 0; 679 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 680 sdma_v3_0_ring_set_wptr(ring); 681 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); 682 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); 683 684 /* set the wb address whether it's enabled or not */ 685 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 686 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 687 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 688 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 689 690 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 691 692 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 693 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 694 695 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); 696 697 if (ring->use_doorbell) { 698 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, 699 OFFSET, ring->doorbell_index); 700 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 701 } else { 702 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 703 } 704 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell); 705 706 /* setup the wptr shadow polling */ 707 wptr_gpu_addr = ring->wptr_gpu_addr; 708 709 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i], 710 lower_32_bits(wptr_gpu_addr)); 711 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i], 712 upper_32_bits(wptr_gpu_addr)); 713 wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]); 714 if (ring->use_pollmem) { 715 /*wptr polling is not enough fast, directly clean the wptr register */ 716 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 717 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 718 SDMA0_GFX_RB_WPTR_POLL_CNTL, 719 ENABLE, 1); 720 } else { 721 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 722 SDMA0_GFX_RB_WPTR_POLL_CNTL, 723 ENABLE, 0); 724 } 725 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl); 726 727 /* enable DMA RB */ 728 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 729 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 730 731 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 732 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 733 #ifdef __BIG_ENDIAN 734 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 735 #endif 736 /* enable DMA IBs */ 737 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 738 } 739 740 /* unhalt the MEs */ 741 sdma_v3_0_enable(adev, true); 742 /* enable sdma ring preemption */ 743 sdma_v3_0_ctx_switch_enable(adev, true); 744 745 for (i = 0; i < adev->sdma.num_instances; i++) { 746 ring = &adev->sdma.instance[i].ring; 747 r = amdgpu_ring_test_helper(ring); 748 if (r) 749 return r; 750 } 751 752 return 0; 753 } 754 755 /** 756 * sdma_v3_0_rlc_resume - setup and start the async dma engines 757 * 758 * @adev: amdgpu_device pointer 759 * 760 * Set up the compute DMA queues and enable them (VI). 761 * Returns 0 for success, error for failure. 762 */ 763 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev) 764 { 765 /* XXX todo */ 766 return 0; 767 } 768 769 /** 770 * sdma_v3_0_start - setup and start the async dma engines 771 * 772 * @adev: amdgpu_device pointer 773 * 774 * Set up the DMA engines and enable them (VI). 775 * Returns 0 for success, error for failure. 776 */ 777 static int sdma_v3_0_start(struct amdgpu_device *adev) 778 { 779 int r; 780 781 /* disable sdma engine before programing it */ 782 sdma_v3_0_ctx_switch_enable(adev, false); 783 sdma_v3_0_enable(adev, false); 784 785 /* start the gfx rings and rlc compute queues */ 786 r = sdma_v3_0_gfx_resume(adev); 787 if (r) 788 return r; 789 r = sdma_v3_0_rlc_resume(adev); 790 if (r) 791 return r; 792 793 return 0; 794 } 795 796 /** 797 * sdma_v3_0_ring_test_ring - simple async dma engine test 798 * 799 * @ring: amdgpu_ring structure holding ring information 800 * 801 * Test the DMA engine by writing using it to write an 802 * value to memory. (VI). 803 * Returns 0 for success, error for failure. 804 */ 805 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) 806 { 807 struct amdgpu_device *adev = ring->adev; 808 unsigned i; 809 unsigned index; 810 int r; 811 u32 tmp; 812 u64 gpu_addr; 813 814 r = amdgpu_wb_get(adev, &index); 815 if (r) 816 return r; 817 818 gpu_addr = adev->wb.gpu_addr + (index * 4); 819 tmp = 0xCAFEDEAD; 820 adev->wb.wb[index] = cpu_to_le32(tmp); 821 822 r = amdgpu_ring_alloc(ring, 5); 823 if (r) 824 goto error_free_wb; 825 826 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 827 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 828 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 829 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 830 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 831 amdgpu_ring_write(ring, 0xDEADBEEF); 832 amdgpu_ring_commit(ring); 833 834 for (i = 0; i < adev->usec_timeout; i++) { 835 tmp = le32_to_cpu(adev->wb.wb[index]); 836 if (tmp == 0xDEADBEEF) 837 break; 838 udelay(1); 839 } 840 841 if (i >= adev->usec_timeout) 842 r = -ETIMEDOUT; 843 844 error_free_wb: 845 amdgpu_wb_free(adev, index); 846 return r; 847 } 848 849 /** 850 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine 851 * 852 * @ring: amdgpu_ring structure holding ring information 853 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 854 * 855 * Test a simple IB in the DMA ring (VI). 856 * Returns 0 on success, error on failure. 857 */ 858 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 859 { 860 struct amdgpu_device *adev = ring->adev; 861 struct amdgpu_ib ib; 862 struct dma_fence *f = NULL; 863 unsigned index; 864 u32 tmp = 0; 865 u64 gpu_addr; 866 long r; 867 868 r = amdgpu_wb_get(adev, &index); 869 if (r) 870 return r; 871 872 gpu_addr = adev->wb.gpu_addr + (index * 4); 873 tmp = 0xCAFEDEAD; 874 adev->wb.wb[index] = cpu_to_le32(tmp); 875 memset(&ib, 0, sizeof(ib)); 876 r = amdgpu_ib_get(adev, NULL, 256, 877 AMDGPU_IB_POOL_DIRECT, &ib); 878 if (r) 879 goto err0; 880 881 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 882 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 883 ib.ptr[1] = lower_32_bits(gpu_addr); 884 ib.ptr[2] = upper_32_bits(gpu_addr); 885 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); 886 ib.ptr[4] = 0xDEADBEEF; 887 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 888 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 889 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 890 ib.length_dw = 8; 891 892 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 893 if (r) 894 goto err1; 895 896 r = dma_fence_wait_timeout(f, false, timeout); 897 if (r == 0) { 898 r = -ETIMEDOUT; 899 goto err1; 900 } else if (r < 0) { 901 goto err1; 902 } 903 tmp = le32_to_cpu(adev->wb.wb[index]); 904 if (tmp == 0xDEADBEEF) 905 r = 0; 906 else 907 r = -EINVAL; 908 err1: 909 amdgpu_ib_free(&ib, NULL); 910 dma_fence_put(f); 911 err0: 912 amdgpu_wb_free(adev, index); 913 return r; 914 } 915 916 /** 917 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART 918 * 919 * @ib: indirect buffer to fill with commands 920 * @pe: addr of the page entry 921 * @src: src addr to copy from 922 * @count: number of page entries to update 923 * 924 * Update PTEs by copying them from the GART using sDMA (CIK). 925 */ 926 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib, 927 uint64_t pe, uint64_t src, 928 unsigned count) 929 { 930 unsigned bytes = count * 8; 931 932 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 933 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 934 ib->ptr[ib->length_dw++] = bytes; 935 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 936 ib->ptr[ib->length_dw++] = lower_32_bits(src); 937 ib->ptr[ib->length_dw++] = upper_32_bits(src); 938 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 939 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 940 } 941 942 /** 943 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually 944 * 945 * @ib: indirect buffer to fill with commands 946 * @pe: addr of the page entry 947 * @value: dst addr to write into pe 948 * @count: number of page entries to update 949 * @incr: increase next addr by incr bytes 950 * 951 * Update PTEs by writing them manually using sDMA (CIK). 952 */ 953 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 954 uint64_t value, unsigned count, 955 uint32_t incr) 956 { 957 unsigned ndw = count * 2; 958 959 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 960 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 961 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 962 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 963 ib->ptr[ib->length_dw++] = ndw; 964 for (; ndw > 0; ndw -= 2) { 965 ib->ptr[ib->length_dw++] = lower_32_bits(value); 966 ib->ptr[ib->length_dw++] = upper_32_bits(value); 967 value += incr; 968 } 969 } 970 971 /** 972 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA 973 * 974 * @ib: indirect buffer to fill with commands 975 * @pe: addr of the page entry 976 * @addr: dst addr to write into pe 977 * @count: number of page entries to update 978 * @incr: increase next addr by incr bytes 979 * @flags: access flags 980 * 981 * Update the page tables using sDMA (CIK). 982 */ 983 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, 984 uint64_t addr, unsigned count, 985 uint32_t incr, uint64_t flags) 986 { 987 /* for physically contiguous pages (vram) */ 988 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); 989 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 990 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 991 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 992 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 993 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 994 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 995 ib->ptr[ib->length_dw++] = incr; /* increment size */ 996 ib->ptr[ib->length_dw++] = 0; 997 ib->ptr[ib->length_dw++] = count; /* number of entries */ 998 } 999 1000 /** 1001 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw 1002 * 1003 * @ring: amdgpu_ring structure holding ring information 1004 * @ib: indirect buffer to fill with padding 1005 * 1006 */ 1007 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1008 { 1009 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1010 u32 pad_count; 1011 int i; 1012 1013 pad_count = (-ib->length_dw) & 7; 1014 for (i = 0; i < pad_count; i++) 1015 if (sdma && sdma->burst_nop && (i == 0)) 1016 ib->ptr[ib->length_dw++] = 1017 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1018 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1019 else 1020 ib->ptr[ib->length_dw++] = 1021 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1022 } 1023 1024 /** 1025 * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline 1026 * 1027 * @ring: amdgpu_ring pointer 1028 * 1029 * Make sure all previous operations are completed (CIK). 1030 */ 1031 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1032 { 1033 uint32_t seq = ring->fence_drv.sync_seq; 1034 uint64_t addr = ring->fence_drv.gpu_addr; 1035 1036 /* wait for idle */ 1037 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1038 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1039 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1040 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1041 amdgpu_ring_write(ring, addr & 0xfffffffc); 1042 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1043 amdgpu_ring_write(ring, seq); /* reference */ 1044 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1045 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1046 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1047 } 1048 1049 /** 1050 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA 1051 * 1052 * @ring: amdgpu_ring pointer 1053 * @vmid: vmid number to use 1054 * @pd_addr: address 1055 * 1056 * Update the page table base and flush the VM TLB 1057 * using sDMA (VI). 1058 */ 1059 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1060 unsigned vmid, uint64_t pd_addr) 1061 { 1062 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1063 1064 /* wait for flush */ 1065 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1066 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1067 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ 1068 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 1069 amdgpu_ring_write(ring, 0); 1070 amdgpu_ring_write(ring, 0); /* reference */ 1071 amdgpu_ring_write(ring, 0); /* mask */ 1072 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1073 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 1074 } 1075 1076 static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring, 1077 uint32_t reg, uint32_t val) 1078 { 1079 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1080 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1081 amdgpu_ring_write(ring, reg); 1082 amdgpu_ring_write(ring, val); 1083 } 1084 1085 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { 1086 .copy_pte_num_dw = 7, 1087 .copy_pte = sdma_v3_0_vm_copy_pte, 1088 1089 .write_pte = sdma_v3_0_vm_write_pte, 1090 .set_pte_pde = sdma_v3_0_vm_set_pte_pde, 1091 }; 1092 1093 static int sdma_v3_0_early_init(struct amdgpu_ip_block *ip_block) 1094 { 1095 struct amdgpu_device *adev = ip_block->adev; 1096 int r; 1097 1098 switch (adev->asic_type) { 1099 case CHIP_STONEY: 1100 adev->sdma.num_instances = 1; 1101 break; 1102 default: 1103 adev->sdma.num_instances = SDMA_MAX_INSTANCE; 1104 break; 1105 } 1106 1107 r = sdma_v3_0_init_microcode(adev); 1108 if (r) 1109 return r; 1110 1111 sdma_v3_0_set_ring_funcs(adev); 1112 amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v3_0_vm_pte_funcs); 1113 sdma_v3_0_set_irq_funcs(adev); 1114 1115 return 0; 1116 } 1117 1118 static int sdma_v3_0_sw_init(struct amdgpu_ip_block *ip_block) 1119 { 1120 struct amdgpu_ring *ring; 1121 int r, i; 1122 struct amdgpu_device *adev = ip_block->adev; 1123 1124 /* SDMA trap event */ 1125 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP, 1126 &adev->sdma.trap_irq); 1127 if (r) 1128 return r; 1129 1130 /* SDMA Privileged inst */ 1131 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241, 1132 &adev->sdma.illegal_inst_irq); 1133 if (r) 1134 return r; 1135 1136 /* SDMA Privileged inst */ 1137 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE, 1138 &adev->sdma.illegal_inst_irq); 1139 if (r) 1140 return r; 1141 1142 for (i = 0; i < adev->sdma.num_instances; i++) { 1143 ring = &adev->sdma.instance[i].ring; 1144 ring->ring_obj = NULL; 1145 if (!amdgpu_sriov_vf(adev)) { 1146 ring->use_doorbell = true; 1147 ring->doorbell_index = adev->doorbell_index.sdma_engine[i]; 1148 } else { 1149 ring->use_pollmem = true; 1150 } 1151 1152 sprintf(ring->name, "sdma%d", i); 1153 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1154 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 : 1155 AMDGPU_SDMA_IRQ_INSTANCE1, 1156 AMDGPU_RING_PRIO_DEFAULT, NULL); 1157 if (r) 1158 return r; 1159 } 1160 1161 return r; 1162 } 1163 1164 static int sdma_v3_0_sw_fini(struct amdgpu_ip_block *ip_block) 1165 { 1166 struct amdgpu_device *adev = ip_block->adev; 1167 int i; 1168 1169 for (i = 0; i < adev->sdma.num_instances; i++) 1170 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1171 1172 sdma_v3_0_free_microcode(adev); 1173 return 0; 1174 } 1175 1176 static int sdma_v3_0_hw_init(struct amdgpu_ip_block *ip_block) 1177 { 1178 int r; 1179 struct amdgpu_device *adev = ip_block->adev; 1180 1181 sdma_v3_0_init_golden_registers(adev); 1182 1183 r = sdma_v3_0_start(adev); 1184 if (r) 1185 return r; 1186 1187 sdma_v3_0_set_buffer_funcs(adev); 1188 1189 return 0; 1190 } 1191 1192 static int sdma_v3_0_hw_fini(struct amdgpu_ip_block *ip_block) 1193 { 1194 struct amdgpu_device *adev = ip_block->adev; 1195 1196 sdma_v3_0_ctx_switch_enable(adev, false); 1197 sdma_v3_0_enable(adev, false); 1198 1199 return 0; 1200 } 1201 1202 static int sdma_v3_0_suspend(struct amdgpu_ip_block *ip_block) 1203 { 1204 return sdma_v3_0_hw_fini(ip_block); 1205 } 1206 1207 static int sdma_v3_0_resume(struct amdgpu_ip_block *ip_block) 1208 { 1209 return sdma_v3_0_hw_init(ip_block); 1210 } 1211 1212 static bool sdma_v3_0_is_idle(struct amdgpu_ip_block *ip_block) 1213 { 1214 struct amdgpu_device *adev = ip_block->adev; 1215 u32 tmp = RREG32(mmSRBM_STATUS2); 1216 1217 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1218 SRBM_STATUS2__SDMA1_BUSY_MASK)) 1219 return false; 1220 1221 return true; 1222 } 1223 1224 static int sdma_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1225 { 1226 unsigned i; 1227 u32 tmp; 1228 struct amdgpu_device *adev = ip_block->adev; 1229 1230 for (i = 0; i < adev->usec_timeout; i++) { 1231 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1232 SRBM_STATUS2__SDMA1_BUSY_MASK); 1233 1234 if (!tmp) 1235 return 0; 1236 udelay(1); 1237 } 1238 return -ETIMEDOUT; 1239 } 1240 1241 static int sdma_v3_0_soft_reset(struct amdgpu_ip_block *ip_block) 1242 { 1243 struct amdgpu_device *adev = ip_block->adev; 1244 u32 srbm_soft_reset = 0; 1245 u32 tmp; 1246 1247 if (!adev->sdma.srbm_soft_reset) 1248 return 0; 1249 1250 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1251 1252 if (srbm_soft_reset) { 1253 tmp = RREG32(mmSRBM_SOFT_RESET); 1254 tmp |= srbm_soft_reset; 1255 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1256 WREG32(mmSRBM_SOFT_RESET, tmp); 1257 tmp = RREG32(mmSRBM_SOFT_RESET); 1258 1259 udelay(50); 1260 1261 tmp &= ~srbm_soft_reset; 1262 WREG32(mmSRBM_SOFT_RESET, tmp); 1263 tmp = RREG32(mmSRBM_SOFT_RESET); 1264 1265 /* Wait a little for things to settle down */ 1266 udelay(50); 1267 } 1268 1269 return 0; 1270 } 1271 1272 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev, 1273 struct amdgpu_irq_src *source, 1274 unsigned type, 1275 enum amdgpu_interrupt_state state) 1276 { 1277 u32 sdma_cntl; 1278 1279 switch (type) { 1280 case AMDGPU_SDMA_IRQ_INSTANCE0: 1281 switch (state) { 1282 case AMDGPU_IRQ_STATE_DISABLE: 1283 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1284 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1285 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1286 break; 1287 case AMDGPU_IRQ_STATE_ENABLE: 1288 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1289 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1290 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1291 break; 1292 default: 1293 break; 1294 } 1295 break; 1296 case AMDGPU_SDMA_IRQ_INSTANCE1: 1297 switch (state) { 1298 case AMDGPU_IRQ_STATE_DISABLE: 1299 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1300 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1301 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1302 break; 1303 case AMDGPU_IRQ_STATE_ENABLE: 1304 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1305 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1306 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1307 break; 1308 default: 1309 break; 1310 } 1311 break; 1312 default: 1313 break; 1314 } 1315 return 0; 1316 } 1317 1318 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev, 1319 struct amdgpu_irq_src *source, 1320 struct amdgpu_iv_entry *entry) 1321 { 1322 u8 instance_id, queue_id; 1323 1324 instance_id = (entry->ring_id & 0x3) >> 0; 1325 queue_id = (entry->ring_id & 0xc) >> 2; 1326 DRM_DEBUG("IH: SDMA trap\n"); 1327 switch (instance_id) { 1328 case 0: 1329 switch (queue_id) { 1330 case 0: 1331 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1332 break; 1333 case 1: 1334 /* XXX compute */ 1335 break; 1336 case 2: 1337 /* XXX compute */ 1338 break; 1339 } 1340 break; 1341 case 1: 1342 switch (queue_id) { 1343 case 0: 1344 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1345 break; 1346 case 1: 1347 /* XXX compute */ 1348 break; 1349 case 2: 1350 /* XXX compute */ 1351 break; 1352 } 1353 break; 1354 } 1355 return 0; 1356 } 1357 1358 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1359 struct amdgpu_irq_src *source, 1360 struct amdgpu_iv_entry *entry) 1361 { 1362 u8 instance_id, queue_id; 1363 1364 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1365 instance_id = (entry->ring_id & 0x3) >> 0; 1366 queue_id = (entry->ring_id & 0xc) >> 2; 1367 1368 if (instance_id <= 1 && queue_id == 0) 1369 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched); 1370 return 0; 1371 } 1372 1373 static void sdma_v3_0_update_sdma_medium_grain_clock_gating( 1374 struct amdgpu_device *adev, 1375 bool enable) 1376 { 1377 uint32_t temp, data; 1378 int i; 1379 1380 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1381 for (i = 0; i < adev->sdma.num_instances; i++) { 1382 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); 1383 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1384 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1385 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1386 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1387 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1388 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1389 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1390 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1391 if (data != temp) 1392 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); 1393 } 1394 } else { 1395 for (i = 0; i < adev->sdma.num_instances; i++) { 1396 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); 1397 data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1398 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1399 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1400 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1401 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1402 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1403 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1404 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK; 1405 1406 if (data != temp) 1407 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); 1408 } 1409 } 1410 } 1411 1412 static void sdma_v3_0_update_sdma_medium_grain_light_sleep( 1413 struct amdgpu_device *adev, 1414 bool enable) 1415 { 1416 uint32_t temp, data; 1417 int i; 1418 1419 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1420 for (i = 0; i < adev->sdma.num_instances; i++) { 1421 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1422 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1423 1424 if (temp != data) 1425 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1426 } 1427 } else { 1428 for (i = 0; i < adev->sdma.num_instances; i++) { 1429 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1430 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1431 1432 if (temp != data) 1433 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1434 } 1435 } 1436 } 1437 1438 static int sdma_v3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1439 enum amd_clockgating_state state) 1440 { 1441 struct amdgpu_device *adev = ip_block->adev; 1442 1443 if (amdgpu_sriov_vf(adev)) 1444 return 0; 1445 1446 switch (adev->asic_type) { 1447 case CHIP_FIJI: 1448 case CHIP_CARRIZO: 1449 case CHIP_STONEY: 1450 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev, 1451 state == AMD_CG_STATE_GATE); 1452 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev, 1453 state == AMD_CG_STATE_GATE); 1454 break; 1455 default: 1456 break; 1457 } 1458 return 0; 1459 } 1460 1461 static int sdma_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 1462 enum amd_powergating_state state) 1463 { 1464 return 0; 1465 } 1466 1467 static void sdma_v3_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1468 { 1469 struct amdgpu_device *adev = ip_block->adev; 1470 int data; 1471 1472 if (amdgpu_sriov_vf(adev)) 1473 *flags = 0; 1474 1475 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1476 data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]); 1477 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK)) 1478 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1479 1480 /* AMD_CG_SUPPORT_SDMA_LS */ 1481 data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]); 1482 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1483 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1484 } 1485 1486 static const struct amd_ip_funcs sdma_v3_0_ip_funcs = { 1487 .name = "sdma_v3_0", 1488 .early_init = sdma_v3_0_early_init, 1489 .sw_init = sdma_v3_0_sw_init, 1490 .sw_fini = sdma_v3_0_sw_fini, 1491 .hw_init = sdma_v3_0_hw_init, 1492 .hw_fini = sdma_v3_0_hw_fini, 1493 .suspend = sdma_v3_0_suspend, 1494 .resume = sdma_v3_0_resume, 1495 .is_idle = sdma_v3_0_is_idle, 1496 .wait_for_idle = sdma_v3_0_wait_for_idle, 1497 .soft_reset = sdma_v3_0_soft_reset, 1498 .set_clockgating_state = sdma_v3_0_set_clockgating_state, 1499 .set_powergating_state = sdma_v3_0_set_powergating_state, 1500 .get_clockgating_state = sdma_v3_0_get_clockgating_state, 1501 }; 1502 1503 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { 1504 .type = AMDGPU_RING_TYPE_SDMA, 1505 .align_mask = 0xf, 1506 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1507 .support_64bit_ptrs = false, 1508 .secure_submission_supported = true, 1509 .get_rptr = sdma_v3_0_ring_get_rptr, 1510 .get_wptr = sdma_v3_0_ring_get_wptr, 1511 .set_wptr = sdma_v3_0_ring_set_wptr, 1512 .emit_frame_size = 1513 6 + /* sdma_v3_0_ring_emit_hdp_flush */ 1514 3 + /* hdp invalidate */ 1515 6 + /* sdma_v3_0_ring_emit_pipeline_sync */ 1516 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v3_0_ring_emit_vm_flush */ 1517 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */ 1518 .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */ 1519 .emit_ib = sdma_v3_0_ring_emit_ib, 1520 .emit_fence = sdma_v3_0_ring_emit_fence, 1521 .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync, 1522 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, 1523 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, 1524 .test_ring = sdma_v3_0_ring_test_ring, 1525 .test_ib = sdma_v3_0_ring_test_ib, 1526 .insert_nop = sdma_v3_0_ring_insert_nop, 1527 .pad_ib = sdma_v3_0_ring_pad_ib, 1528 .emit_wreg = sdma_v3_0_ring_emit_wreg, 1529 }; 1530 1531 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev) 1532 { 1533 int i; 1534 1535 for (i = 0; i < adev->sdma.num_instances; i++) { 1536 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs; 1537 adev->sdma.instance[i].ring.me = i; 1538 } 1539 } 1540 1541 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = { 1542 .set = sdma_v3_0_set_trap_irq_state, 1543 .process = sdma_v3_0_process_trap_irq, 1544 }; 1545 1546 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = { 1547 .process = sdma_v3_0_process_illegal_inst_irq, 1548 }; 1549 1550 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev) 1551 { 1552 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1553 adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs; 1554 adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs; 1555 } 1556 1557 /** 1558 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine 1559 * 1560 * @ib: indirect buffer to copy to 1561 * @src_offset: src GPU address 1562 * @dst_offset: dst GPU address 1563 * @byte_count: number of bytes to xfer 1564 * @copy_flags: unused 1565 * 1566 * Copy GPU buffers using the DMA engine (VI). 1567 * Used by the amdgpu ttm implementation to move pages if 1568 * registered as the asic copy callback. 1569 */ 1570 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib, 1571 uint64_t src_offset, 1572 uint64_t dst_offset, 1573 uint32_t byte_count, 1574 uint32_t copy_flags) 1575 { 1576 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1577 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1578 ib->ptr[ib->length_dw++] = byte_count; 1579 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1580 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1581 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1582 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1583 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1584 } 1585 1586 /** 1587 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine 1588 * 1589 * @ib: indirect buffer to copy to 1590 * @src_data: value to write to buffer 1591 * @dst_offset: dst GPU address 1592 * @byte_count: number of bytes to xfer 1593 * 1594 * Fill GPU buffers using the DMA engine (VI). 1595 */ 1596 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib, 1597 uint32_t src_data, 1598 uint64_t dst_offset, 1599 uint32_t byte_count) 1600 { 1601 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1602 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1603 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1604 ib->ptr[ib->length_dw++] = src_data; 1605 ib->ptr[ib->length_dw++] = byte_count; 1606 } 1607 1608 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = { 1609 .copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */ 1610 .copy_num_dw = 7, 1611 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer, 1612 1613 .fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */ 1614 .fill_num_dw = 5, 1615 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer, 1616 }; 1617 1618 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) 1619 { 1620 amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v3_0_buffer_funcs); 1621 } 1622 1623 const struct amdgpu_ip_block_version sdma_v3_0_ip_block = 1624 { 1625 .type = AMD_IP_BLOCK_TYPE_SDMA, 1626 .major = 3, 1627 .minor = 0, 1628 .rev = 0, 1629 .funcs = &sdma_v3_0_ip_funcs, 1630 }; 1631 1632 const struct amdgpu_ip_block_version sdma_v3_1_ip_block = 1633 { 1634 .type = AMD_IP_BLOCK_TYPE_SDMA, 1635 .major = 3, 1636 .minor = 1, 1637 .rev = 0, 1638 .funcs = &sdma_v3_0_ip_funcs, 1639 }; 1640