1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 25 #include <linux/delay.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 #include "vi.h" 33 #include "vid.h" 34 35 #include "oss/oss_3_0_d.h" 36 #include "oss/oss_3_0_sh_mask.h" 37 38 #include "gmc/gmc_8_1_d.h" 39 #include "gmc/gmc_8_1_sh_mask.h" 40 41 #include "gca/gfx_8_0_d.h" 42 #include "gca/gfx_8_0_enum.h" 43 #include "gca/gfx_8_0_sh_mask.h" 44 45 #include "bif/bif_5_0_d.h" 46 #include "bif/bif_5_0_sh_mask.h" 47 48 #include "tonga_sdma_pkt_open.h" 49 50 #include "ivsrcid/ivsrcid_vislands30.h" 51 52 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev); 53 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); 54 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev); 55 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); 56 57 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); 58 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin"); 59 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin"); 60 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); 61 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); 62 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); 63 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin"); 65 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin"); 66 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin"); 67 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin"); 68 MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin"); 69 MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin"); 70 MODULE_FIRMWARE("amdgpu/vegam_sdma.bin"); 71 MODULE_FIRMWARE("amdgpu/vegam_sdma1.bin"); 72 73 74 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 75 { 76 SDMA0_REGISTER_OFFSET, 77 SDMA1_REGISTER_OFFSET 78 }; 79 80 static const u32 golden_settings_tonga_a11[] = 81 { 82 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 83 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 84 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 85 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 86 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 87 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 88 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 89 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 90 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 91 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 92 }; 93 94 static const u32 tonga_mgcg_cgcg_init[] = 95 { 96 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 97 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 98 }; 99 100 static const u32 golden_settings_fiji_a10[] = 101 { 102 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 103 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 104 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 105 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 106 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 107 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 108 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 109 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 110 }; 111 112 static const u32 fiji_mgcg_cgcg_init[] = 113 { 114 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 115 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 116 }; 117 118 static const u32 golden_settings_polaris11_a11[] = 119 { 120 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 121 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 122 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 123 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 124 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 125 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 126 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 127 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 128 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 129 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 130 }; 131 132 static const u32 golden_settings_polaris10_a11[] = 133 { 134 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 135 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 136 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 137 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 138 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 139 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 140 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 141 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 142 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 143 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 144 }; 145 146 static const u32 cz_golden_settings_a11[] = 147 { 148 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 149 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 150 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 151 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 152 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 153 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 154 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 155 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 156 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100, 157 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800, 158 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100, 159 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100, 160 }; 161 162 static const u32 cz_mgcg_cgcg_init[] = 163 { 164 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 165 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 166 }; 167 168 static const u32 stoney_golden_settings_a11[] = 169 { 170 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 171 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 172 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 173 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 174 }; 175 176 static const u32 stoney_mgcg_cgcg_init[] = 177 { 178 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100, 179 }; 180 181 /* 182 * sDMA - System DMA 183 * Starting with CIK, the GPU has new asynchronous 184 * DMA engines. These engines are used for compute 185 * and gfx. There are two DMA engines (SDMA0, SDMA1) 186 * and each one supports 1 ring buffer used for gfx 187 * and 2 queues used for compute. 188 * 189 * The programming model is very similar to the CP 190 * (ring buffer, IBs, etc.), but sDMA has it's own 191 * packet format that is different from the PM4 format 192 * used by the CP. sDMA supports copying data, writing 193 * embedded data, solid fills, and a number of other 194 * things. It also has support for tiling/detiling of 195 * buffers. 196 */ 197 198 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) 199 { 200 switch (adev->asic_type) { 201 case CHIP_FIJI: 202 amdgpu_device_program_register_sequence(adev, 203 fiji_mgcg_cgcg_init, 204 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 205 amdgpu_device_program_register_sequence(adev, 206 golden_settings_fiji_a10, 207 ARRAY_SIZE(golden_settings_fiji_a10)); 208 break; 209 case CHIP_TONGA: 210 amdgpu_device_program_register_sequence(adev, 211 tonga_mgcg_cgcg_init, 212 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 213 amdgpu_device_program_register_sequence(adev, 214 golden_settings_tonga_a11, 215 ARRAY_SIZE(golden_settings_tonga_a11)); 216 break; 217 case CHIP_POLARIS11: 218 case CHIP_POLARIS12: 219 case CHIP_VEGAM: 220 amdgpu_device_program_register_sequence(adev, 221 golden_settings_polaris11_a11, 222 ARRAY_SIZE(golden_settings_polaris11_a11)); 223 break; 224 case CHIP_POLARIS10: 225 amdgpu_device_program_register_sequence(adev, 226 golden_settings_polaris10_a11, 227 ARRAY_SIZE(golden_settings_polaris10_a11)); 228 break; 229 case CHIP_CARRIZO: 230 amdgpu_device_program_register_sequence(adev, 231 cz_mgcg_cgcg_init, 232 ARRAY_SIZE(cz_mgcg_cgcg_init)); 233 amdgpu_device_program_register_sequence(adev, 234 cz_golden_settings_a11, 235 ARRAY_SIZE(cz_golden_settings_a11)); 236 break; 237 case CHIP_STONEY: 238 amdgpu_device_program_register_sequence(adev, 239 stoney_mgcg_cgcg_init, 240 ARRAY_SIZE(stoney_mgcg_cgcg_init)); 241 amdgpu_device_program_register_sequence(adev, 242 stoney_golden_settings_a11, 243 ARRAY_SIZE(stoney_golden_settings_a11)); 244 break; 245 default: 246 break; 247 } 248 } 249 250 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev) 251 { 252 int i; 253 for (i = 0; i < adev->sdma.num_instances; i++) { 254 release_firmware(adev->sdma.instance[i].fw); 255 adev->sdma.instance[i].fw = NULL; 256 } 257 } 258 259 /** 260 * sdma_v3_0_init_microcode - load ucode images from disk 261 * 262 * @adev: amdgpu_device pointer 263 * 264 * Use the firmware interface to load the ucode images into 265 * the driver (not loaded into hw). 266 * Returns 0 on success, error on failure. 267 */ 268 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) 269 { 270 const char *chip_name; 271 char fw_name[30]; 272 int err = 0, i; 273 struct amdgpu_firmware_info *info = NULL; 274 const struct common_firmware_header *header = NULL; 275 const struct sdma_firmware_header_v1_0 *hdr; 276 277 DRM_DEBUG("\n"); 278 279 switch (adev->asic_type) { 280 case CHIP_TONGA: 281 chip_name = "tonga"; 282 break; 283 case CHIP_FIJI: 284 chip_name = "fiji"; 285 break; 286 case CHIP_POLARIS10: 287 chip_name = "polaris10"; 288 break; 289 case CHIP_POLARIS11: 290 chip_name = "polaris11"; 291 break; 292 case CHIP_POLARIS12: 293 chip_name = "polaris12"; 294 break; 295 case CHIP_VEGAM: 296 chip_name = "vegam"; 297 break; 298 case CHIP_CARRIZO: 299 chip_name = "carrizo"; 300 break; 301 case CHIP_STONEY: 302 chip_name = "stoney"; 303 break; 304 default: BUG(); 305 } 306 307 for (i = 0; i < adev->sdma.num_instances; i++) { 308 if (i == 0) 309 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 310 else 311 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 312 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 313 if (err) 314 goto out; 315 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 316 if (err) 317 goto out; 318 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 319 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 320 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 321 if (adev->sdma.instance[i].feature_version >= 20) 322 adev->sdma.instance[i].burst_nop = true; 323 324 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 325 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 326 info->fw = adev->sdma.instance[i].fw; 327 header = (const struct common_firmware_header *)info->fw->data; 328 adev->firmware.fw_size += 329 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 330 331 } 332 out: 333 if (err) { 334 pr_err("sdma_v3_0: Failed to load firmware \"%s\"\n", fw_name); 335 for (i = 0; i < adev->sdma.num_instances; i++) { 336 release_firmware(adev->sdma.instance[i].fw); 337 adev->sdma.instance[i].fw = NULL; 338 } 339 } 340 return err; 341 } 342 343 /** 344 * sdma_v3_0_ring_get_rptr - get the current read pointer 345 * 346 * @ring: amdgpu ring pointer 347 * 348 * Get the current rptr from the hardware (VI+). 349 */ 350 static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring) 351 { 352 /* XXX check if swapping is necessary on BE */ 353 return ring->adev->wb.wb[ring->rptr_offs] >> 2; 354 } 355 356 /** 357 * sdma_v3_0_ring_get_wptr - get the current write pointer 358 * 359 * @ring: amdgpu ring pointer 360 * 361 * Get the current wptr from the hardware (VI+). 362 */ 363 static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring) 364 { 365 struct amdgpu_device *adev = ring->adev; 366 u32 wptr; 367 368 if (ring->use_doorbell || ring->use_pollmem) { 369 /* XXX check if swapping is necessary on BE */ 370 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; 371 } else { 372 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; 373 } 374 375 return wptr; 376 } 377 378 /** 379 * sdma_v3_0_ring_set_wptr - commit the write pointer 380 * 381 * @ring: amdgpu ring pointer 382 * 383 * Write the wptr back to the hardware (VI+). 384 */ 385 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) 386 { 387 struct amdgpu_device *adev = ring->adev; 388 389 if (ring->use_doorbell) { 390 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; 391 /* XXX check if swapping is necessary on BE */ 392 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2)); 393 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2); 394 } else if (ring->use_pollmem) { 395 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; 396 397 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2)); 398 } else { 399 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2); 400 } 401 } 402 403 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 404 { 405 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 406 int i; 407 408 for (i = 0; i < count; i++) 409 if (sdma && sdma->burst_nop && (i == 0)) 410 amdgpu_ring_write(ring, ring->funcs->nop | 411 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 412 else 413 amdgpu_ring_write(ring, ring->funcs->nop); 414 } 415 416 /** 417 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine 418 * 419 * @ring: amdgpu ring pointer 420 * @job: job to retrieve vmid from 421 * @ib: IB object to schedule 422 * @flags: unused 423 * 424 * Schedule an IB in the DMA ring (VI). 425 */ 426 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, 427 struct amdgpu_job *job, 428 struct amdgpu_ib *ib, 429 uint32_t flags) 430 { 431 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 432 433 /* IB packet must end on a 8 DW boundary */ 434 sdma_v3_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 435 436 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 437 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 438 /* base must be 32 byte aligned */ 439 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 440 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 441 amdgpu_ring_write(ring, ib->length_dw); 442 amdgpu_ring_write(ring, 0); 443 amdgpu_ring_write(ring, 0); 444 445 } 446 447 /** 448 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 449 * 450 * @ring: amdgpu ring pointer 451 * 452 * Emit an hdp flush packet on the requested DMA ring. 453 */ 454 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 455 { 456 u32 ref_and_mask = 0; 457 458 if (ring->me == 0) 459 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); 460 else 461 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); 462 463 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 464 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 465 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 466 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 467 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 468 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 469 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 470 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 471 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 472 } 473 474 /** 475 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring 476 * 477 * @ring: amdgpu ring pointer 478 * @addr: address 479 * @seq: sequence number 480 * @flags: fence related flags 481 * 482 * Add a DMA fence packet to the ring to write 483 * the fence seq number and DMA trap packet to generate 484 * an interrupt if needed (VI). 485 */ 486 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 487 unsigned flags) 488 { 489 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 490 /* write the fence */ 491 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 492 amdgpu_ring_write(ring, lower_32_bits(addr)); 493 amdgpu_ring_write(ring, upper_32_bits(addr)); 494 amdgpu_ring_write(ring, lower_32_bits(seq)); 495 496 /* optionally write high bits as well */ 497 if (write64bit) { 498 addr += 4; 499 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 500 amdgpu_ring_write(ring, lower_32_bits(addr)); 501 amdgpu_ring_write(ring, upper_32_bits(addr)); 502 amdgpu_ring_write(ring, upper_32_bits(seq)); 503 } 504 505 /* generate an interrupt */ 506 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 507 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 508 } 509 510 /** 511 * sdma_v3_0_gfx_stop - stop the gfx async dma engines 512 * 513 * @adev: amdgpu_device pointer 514 * 515 * Stop the gfx async dma ring buffers (VI). 516 */ 517 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev) 518 { 519 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 520 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 521 u32 rb_cntl, ib_cntl; 522 int i; 523 524 if ((adev->mman.buffer_funcs_ring == sdma0) || 525 (adev->mman.buffer_funcs_ring == sdma1)) 526 amdgpu_ttm_set_buffer_funcs_status(adev, false); 527 528 for (i = 0; i < adev->sdma.num_instances; i++) { 529 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 530 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 531 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 532 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 533 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 534 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 535 } 536 } 537 538 /** 539 * sdma_v3_0_rlc_stop - stop the compute async dma engines 540 * 541 * @adev: amdgpu_device pointer 542 * 543 * Stop the compute async dma queues (VI). 544 */ 545 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev) 546 { 547 /* XXX todo */ 548 } 549 550 /** 551 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch 552 * 553 * @adev: amdgpu_device pointer 554 * @enable: enable/disable the DMA MEs context switch. 555 * 556 * Halt or unhalt the async dma engines context switch (VI). 557 */ 558 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 559 { 560 u32 f32_cntl, phase_quantum = 0; 561 int i; 562 563 if (amdgpu_sdma_phase_quantum) { 564 unsigned value = amdgpu_sdma_phase_quantum; 565 unsigned unit = 0; 566 567 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 568 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 569 value = (value + 1) >> 1; 570 unit++; 571 } 572 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 573 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 574 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 575 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 576 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 577 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 578 WARN_ONCE(1, 579 "clamping sdma_phase_quantum to %uK clock cycles\n", 580 value << unit); 581 } 582 phase_quantum = 583 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 584 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 585 } 586 587 for (i = 0; i < adev->sdma.num_instances; i++) { 588 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); 589 if (enable) { 590 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 591 AUTO_CTXSW_ENABLE, 1); 592 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 593 ATC_L1_ENABLE, 1); 594 if (amdgpu_sdma_phase_quantum) { 595 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], 596 phase_quantum); 597 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], 598 phase_quantum); 599 } 600 } else { 601 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 602 AUTO_CTXSW_ENABLE, 0); 603 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 604 ATC_L1_ENABLE, 1); 605 } 606 607 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); 608 } 609 } 610 611 /** 612 * sdma_v3_0_enable - stop the async dma engines 613 * 614 * @adev: amdgpu_device pointer 615 * @enable: enable/disable the DMA MEs. 616 * 617 * Halt or unhalt the async dma engines (VI). 618 */ 619 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable) 620 { 621 u32 f32_cntl; 622 int i; 623 624 if (!enable) { 625 sdma_v3_0_gfx_stop(adev); 626 sdma_v3_0_rlc_stop(adev); 627 } 628 629 for (i = 0; i < adev->sdma.num_instances; i++) { 630 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 631 if (enable) 632 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); 633 else 634 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 635 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); 636 } 637 } 638 639 /** 640 * sdma_v3_0_gfx_resume - setup and start the async dma engines 641 * 642 * @adev: amdgpu_device pointer 643 * 644 * Set up the gfx DMA ring buffers and enable them (VI). 645 * Returns 0 for success, error for failure. 646 */ 647 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) 648 { 649 struct amdgpu_ring *ring; 650 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 651 u32 rb_bufsz; 652 u32 wb_offset; 653 u32 doorbell; 654 u64 wptr_gpu_addr; 655 int i, j, r; 656 657 for (i = 0; i < adev->sdma.num_instances; i++) { 658 ring = &adev->sdma.instance[i].ring; 659 amdgpu_ring_clear_ring(ring); 660 wb_offset = (ring->rptr_offs * 4); 661 662 mutex_lock(&adev->srbm_mutex); 663 for (j = 0; j < 16; j++) { 664 vi_srbm_select(adev, 0, 0, 0, j); 665 /* SDMA GFX */ 666 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 667 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 668 } 669 vi_srbm_select(adev, 0, 0, 0, 0); 670 mutex_unlock(&adev->srbm_mutex); 671 672 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], 673 adev->gfx.config.gb_addr_config & 0x70); 674 675 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 676 677 /* Set ring buffer size in dwords */ 678 rb_bufsz = order_base_2(ring->ring_size / 4); 679 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 680 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 681 #ifdef __BIG_ENDIAN 682 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 683 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 684 RPTR_WRITEBACK_SWAP_ENABLE, 1); 685 #endif 686 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 687 688 /* Initialize the ring buffer's read and write pointers */ 689 ring->wptr = 0; 690 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 691 sdma_v3_0_ring_set_wptr(ring); 692 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); 693 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); 694 695 /* set the wb address whether it's enabled or not */ 696 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 697 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 698 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 699 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 700 701 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 702 703 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 704 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 705 706 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); 707 708 if (ring->use_doorbell) { 709 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, 710 OFFSET, ring->doorbell_index); 711 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 712 } else { 713 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 714 } 715 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell); 716 717 /* setup the wptr shadow polling */ 718 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 719 720 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i], 721 lower_32_bits(wptr_gpu_addr)); 722 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i], 723 upper_32_bits(wptr_gpu_addr)); 724 wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]); 725 if (ring->use_pollmem) { 726 /*wptr polling is not enogh fast, directly clean the wptr register */ 727 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 728 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 729 SDMA0_GFX_RB_WPTR_POLL_CNTL, 730 ENABLE, 1); 731 } else { 732 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 733 SDMA0_GFX_RB_WPTR_POLL_CNTL, 734 ENABLE, 0); 735 } 736 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl); 737 738 /* enable DMA RB */ 739 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 740 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 741 742 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 743 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 744 #ifdef __BIG_ENDIAN 745 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 746 #endif 747 /* enable DMA IBs */ 748 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 749 750 ring->sched.ready = true; 751 } 752 753 /* unhalt the MEs */ 754 sdma_v3_0_enable(adev, true); 755 /* enable sdma ring preemption */ 756 sdma_v3_0_ctx_switch_enable(adev, true); 757 758 for (i = 0; i < adev->sdma.num_instances; i++) { 759 ring = &adev->sdma.instance[i].ring; 760 r = amdgpu_ring_test_helper(ring); 761 if (r) 762 return r; 763 764 if (adev->mman.buffer_funcs_ring == ring) 765 amdgpu_ttm_set_buffer_funcs_status(adev, true); 766 } 767 768 return 0; 769 } 770 771 /** 772 * sdma_v3_0_rlc_resume - setup and start the async dma engines 773 * 774 * @adev: amdgpu_device pointer 775 * 776 * Set up the compute DMA queues and enable them (VI). 777 * Returns 0 for success, error for failure. 778 */ 779 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev) 780 { 781 /* XXX todo */ 782 return 0; 783 } 784 785 /** 786 * sdma_v3_0_start - setup and start the async dma engines 787 * 788 * @adev: amdgpu_device pointer 789 * 790 * Set up the DMA engines and enable them (VI). 791 * Returns 0 for success, error for failure. 792 */ 793 static int sdma_v3_0_start(struct amdgpu_device *adev) 794 { 795 int r; 796 797 /* disable sdma engine before programing it */ 798 sdma_v3_0_ctx_switch_enable(adev, false); 799 sdma_v3_0_enable(adev, false); 800 801 /* start the gfx rings and rlc compute queues */ 802 r = sdma_v3_0_gfx_resume(adev); 803 if (r) 804 return r; 805 r = sdma_v3_0_rlc_resume(adev); 806 if (r) 807 return r; 808 809 return 0; 810 } 811 812 /** 813 * sdma_v3_0_ring_test_ring - simple async dma engine test 814 * 815 * @ring: amdgpu_ring structure holding ring information 816 * 817 * Test the DMA engine by writing using it to write an 818 * value to memory. (VI). 819 * Returns 0 for success, error for failure. 820 */ 821 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) 822 { 823 struct amdgpu_device *adev = ring->adev; 824 unsigned i; 825 unsigned index; 826 int r; 827 u32 tmp; 828 u64 gpu_addr; 829 830 r = amdgpu_device_wb_get(adev, &index); 831 if (r) 832 return r; 833 834 gpu_addr = adev->wb.gpu_addr + (index * 4); 835 tmp = 0xCAFEDEAD; 836 adev->wb.wb[index] = cpu_to_le32(tmp); 837 838 r = amdgpu_ring_alloc(ring, 5); 839 if (r) 840 goto error_free_wb; 841 842 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 843 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 844 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 845 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 846 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 847 amdgpu_ring_write(ring, 0xDEADBEEF); 848 amdgpu_ring_commit(ring); 849 850 for (i = 0; i < adev->usec_timeout; i++) { 851 tmp = le32_to_cpu(adev->wb.wb[index]); 852 if (tmp == 0xDEADBEEF) 853 break; 854 udelay(1); 855 } 856 857 if (i >= adev->usec_timeout) 858 r = -ETIMEDOUT; 859 860 error_free_wb: 861 amdgpu_device_wb_free(adev, index); 862 return r; 863 } 864 865 /** 866 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine 867 * 868 * @ring: amdgpu_ring structure holding ring information 869 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 870 * 871 * Test a simple IB in the DMA ring (VI). 872 * Returns 0 on success, error on failure. 873 */ 874 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 875 { 876 struct amdgpu_device *adev = ring->adev; 877 struct amdgpu_ib ib; 878 struct dma_fence *f = NULL; 879 unsigned index; 880 u32 tmp = 0; 881 u64 gpu_addr; 882 long r; 883 884 r = amdgpu_device_wb_get(adev, &index); 885 if (r) 886 return r; 887 888 gpu_addr = adev->wb.gpu_addr + (index * 4); 889 tmp = 0xCAFEDEAD; 890 adev->wb.wb[index] = cpu_to_le32(tmp); 891 memset(&ib, 0, sizeof(ib)); 892 r = amdgpu_ib_get(adev, NULL, 256, 893 AMDGPU_IB_POOL_DIRECT, &ib); 894 if (r) 895 goto err0; 896 897 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 898 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 899 ib.ptr[1] = lower_32_bits(gpu_addr); 900 ib.ptr[2] = upper_32_bits(gpu_addr); 901 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); 902 ib.ptr[4] = 0xDEADBEEF; 903 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 904 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 905 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 906 ib.length_dw = 8; 907 908 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 909 if (r) 910 goto err1; 911 912 r = dma_fence_wait_timeout(f, false, timeout); 913 if (r == 0) { 914 r = -ETIMEDOUT; 915 goto err1; 916 } else if (r < 0) { 917 goto err1; 918 } 919 tmp = le32_to_cpu(adev->wb.wb[index]); 920 if (tmp == 0xDEADBEEF) 921 r = 0; 922 else 923 r = -EINVAL; 924 err1: 925 amdgpu_ib_free(adev, &ib, NULL); 926 dma_fence_put(f); 927 err0: 928 amdgpu_device_wb_free(adev, index); 929 return r; 930 } 931 932 /** 933 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART 934 * 935 * @ib: indirect buffer to fill with commands 936 * @pe: addr of the page entry 937 * @src: src addr to copy from 938 * @count: number of page entries to update 939 * 940 * Update PTEs by copying them from the GART using sDMA (CIK). 941 */ 942 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib, 943 uint64_t pe, uint64_t src, 944 unsigned count) 945 { 946 unsigned bytes = count * 8; 947 948 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 949 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 950 ib->ptr[ib->length_dw++] = bytes; 951 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 952 ib->ptr[ib->length_dw++] = lower_32_bits(src); 953 ib->ptr[ib->length_dw++] = upper_32_bits(src); 954 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 955 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 956 } 957 958 /** 959 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually 960 * 961 * @ib: indirect buffer to fill with commands 962 * @pe: addr of the page entry 963 * @value: dst addr to write into pe 964 * @count: number of page entries to update 965 * @incr: increase next addr by incr bytes 966 * 967 * Update PTEs by writing them manually using sDMA (CIK). 968 */ 969 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 970 uint64_t value, unsigned count, 971 uint32_t incr) 972 { 973 unsigned ndw = count * 2; 974 975 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 976 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 977 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 978 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 979 ib->ptr[ib->length_dw++] = ndw; 980 for (; ndw > 0; ndw -= 2) { 981 ib->ptr[ib->length_dw++] = lower_32_bits(value); 982 ib->ptr[ib->length_dw++] = upper_32_bits(value); 983 value += incr; 984 } 985 } 986 987 /** 988 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA 989 * 990 * @ib: indirect buffer to fill with commands 991 * @pe: addr of the page entry 992 * @addr: dst addr to write into pe 993 * @count: number of page entries to update 994 * @incr: increase next addr by incr bytes 995 * @flags: access flags 996 * 997 * Update the page tables using sDMA (CIK). 998 */ 999 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, 1000 uint64_t addr, unsigned count, 1001 uint32_t incr, uint64_t flags) 1002 { 1003 /* for physically contiguous pages (vram) */ 1004 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); 1005 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1006 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1007 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1008 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1009 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1010 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1011 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1012 ib->ptr[ib->length_dw++] = 0; 1013 ib->ptr[ib->length_dw++] = count; /* number of entries */ 1014 } 1015 1016 /** 1017 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw 1018 * 1019 * @ring: amdgpu_ring structure holding ring information 1020 * @ib: indirect buffer to fill with padding 1021 * 1022 */ 1023 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1024 { 1025 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1026 u32 pad_count; 1027 int i; 1028 1029 pad_count = (-ib->length_dw) & 7; 1030 for (i = 0; i < pad_count; i++) 1031 if (sdma && sdma->burst_nop && (i == 0)) 1032 ib->ptr[ib->length_dw++] = 1033 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1034 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1035 else 1036 ib->ptr[ib->length_dw++] = 1037 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1038 } 1039 1040 /** 1041 * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline 1042 * 1043 * @ring: amdgpu_ring pointer 1044 * 1045 * Make sure all previous operations are completed (CIK). 1046 */ 1047 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1048 { 1049 uint32_t seq = ring->fence_drv.sync_seq; 1050 uint64_t addr = ring->fence_drv.gpu_addr; 1051 1052 /* wait for idle */ 1053 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1054 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1055 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1056 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1057 amdgpu_ring_write(ring, addr & 0xfffffffc); 1058 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1059 amdgpu_ring_write(ring, seq); /* reference */ 1060 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1061 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1062 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1063 } 1064 1065 /** 1066 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA 1067 * 1068 * @ring: amdgpu_ring pointer 1069 * @vmid: vmid number to use 1070 * @pd_addr: address 1071 * 1072 * Update the page table base and flush the VM TLB 1073 * using sDMA (VI). 1074 */ 1075 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1076 unsigned vmid, uint64_t pd_addr) 1077 { 1078 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1079 1080 /* wait for flush */ 1081 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1082 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1083 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ 1084 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 1085 amdgpu_ring_write(ring, 0); 1086 amdgpu_ring_write(ring, 0); /* reference */ 1087 amdgpu_ring_write(ring, 0); /* mask */ 1088 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1089 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 1090 } 1091 1092 static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring, 1093 uint32_t reg, uint32_t val) 1094 { 1095 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1096 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1097 amdgpu_ring_write(ring, reg); 1098 amdgpu_ring_write(ring, val); 1099 } 1100 1101 static int sdma_v3_0_early_init(void *handle) 1102 { 1103 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1104 1105 switch (adev->asic_type) { 1106 case CHIP_STONEY: 1107 adev->sdma.num_instances = 1; 1108 break; 1109 default: 1110 adev->sdma.num_instances = SDMA_MAX_INSTANCE; 1111 break; 1112 } 1113 1114 sdma_v3_0_set_ring_funcs(adev); 1115 sdma_v3_0_set_buffer_funcs(adev); 1116 sdma_v3_0_set_vm_pte_funcs(adev); 1117 sdma_v3_0_set_irq_funcs(adev); 1118 1119 return 0; 1120 } 1121 1122 static int sdma_v3_0_sw_init(void *handle) 1123 { 1124 struct amdgpu_ring *ring; 1125 int r, i; 1126 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1127 1128 /* SDMA trap event */ 1129 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP, 1130 &adev->sdma.trap_irq); 1131 if (r) 1132 return r; 1133 1134 /* SDMA Privileged inst */ 1135 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241, 1136 &adev->sdma.illegal_inst_irq); 1137 if (r) 1138 return r; 1139 1140 /* SDMA Privileged inst */ 1141 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE, 1142 &adev->sdma.illegal_inst_irq); 1143 if (r) 1144 return r; 1145 1146 r = sdma_v3_0_init_microcode(adev); 1147 if (r) { 1148 DRM_ERROR("Failed to load sdma firmware!\n"); 1149 return r; 1150 } 1151 1152 for (i = 0; i < adev->sdma.num_instances; i++) { 1153 ring = &adev->sdma.instance[i].ring; 1154 ring->ring_obj = NULL; 1155 if (!amdgpu_sriov_vf(adev)) { 1156 ring->use_doorbell = true; 1157 ring->doorbell_index = adev->doorbell_index.sdma_engine[i]; 1158 } else { 1159 ring->use_pollmem = true; 1160 } 1161 1162 sprintf(ring->name, "sdma%d", i); 1163 r = amdgpu_ring_init(adev, ring, 1024, 1164 &adev->sdma.trap_irq, 1165 (i == 0) ? 1166 AMDGPU_SDMA_IRQ_INSTANCE0 : 1167 AMDGPU_SDMA_IRQ_INSTANCE1, 1168 AMDGPU_RING_PRIO_DEFAULT); 1169 if (r) 1170 return r; 1171 } 1172 1173 return r; 1174 } 1175 1176 static int sdma_v3_0_sw_fini(void *handle) 1177 { 1178 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1179 int i; 1180 1181 for (i = 0; i < adev->sdma.num_instances; i++) 1182 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1183 1184 sdma_v3_0_free_microcode(adev); 1185 return 0; 1186 } 1187 1188 static int sdma_v3_0_hw_init(void *handle) 1189 { 1190 int r; 1191 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1192 1193 sdma_v3_0_init_golden_registers(adev); 1194 1195 r = sdma_v3_0_start(adev); 1196 if (r) 1197 return r; 1198 1199 return r; 1200 } 1201 1202 static int sdma_v3_0_hw_fini(void *handle) 1203 { 1204 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1205 1206 sdma_v3_0_ctx_switch_enable(adev, false); 1207 sdma_v3_0_enable(adev, false); 1208 1209 return 0; 1210 } 1211 1212 static int sdma_v3_0_suspend(void *handle) 1213 { 1214 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1215 1216 return sdma_v3_0_hw_fini(adev); 1217 } 1218 1219 static int sdma_v3_0_resume(void *handle) 1220 { 1221 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1222 1223 return sdma_v3_0_hw_init(adev); 1224 } 1225 1226 static bool sdma_v3_0_is_idle(void *handle) 1227 { 1228 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1229 u32 tmp = RREG32(mmSRBM_STATUS2); 1230 1231 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1232 SRBM_STATUS2__SDMA1_BUSY_MASK)) 1233 return false; 1234 1235 return true; 1236 } 1237 1238 static int sdma_v3_0_wait_for_idle(void *handle) 1239 { 1240 unsigned i; 1241 u32 tmp; 1242 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1243 1244 for (i = 0; i < adev->usec_timeout; i++) { 1245 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1246 SRBM_STATUS2__SDMA1_BUSY_MASK); 1247 1248 if (!tmp) 1249 return 0; 1250 udelay(1); 1251 } 1252 return -ETIMEDOUT; 1253 } 1254 1255 static bool sdma_v3_0_check_soft_reset(void *handle) 1256 { 1257 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1258 u32 srbm_soft_reset = 0; 1259 u32 tmp = RREG32(mmSRBM_STATUS2); 1260 1261 if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) || 1262 (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) { 1263 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1264 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1265 } 1266 1267 if (srbm_soft_reset) { 1268 adev->sdma.srbm_soft_reset = srbm_soft_reset; 1269 return true; 1270 } else { 1271 adev->sdma.srbm_soft_reset = 0; 1272 return false; 1273 } 1274 } 1275 1276 static int sdma_v3_0_pre_soft_reset(void *handle) 1277 { 1278 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1279 u32 srbm_soft_reset = 0; 1280 1281 if (!adev->sdma.srbm_soft_reset) 1282 return 0; 1283 1284 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1285 1286 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || 1287 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { 1288 sdma_v3_0_ctx_switch_enable(adev, false); 1289 sdma_v3_0_enable(adev, false); 1290 } 1291 1292 return 0; 1293 } 1294 1295 static int sdma_v3_0_post_soft_reset(void *handle) 1296 { 1297 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1298 u32 srbm_soft_reset = 0; 1299 1300 if (!adev->sdma.srbm_soft_reset) 1301 return 0; 1302 1303 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1304 1305 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || 1306 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { 1307 sdma_v3_0_gfx_resume(adev); 1308 sdma_v3_0_rlc_resume(adev); 1309 } 1310 1311 return 0; 1312 } 1313 1314 static int sdma_v3_0_soft_reset(void *handle) 1315 { 1316 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1317 u32 srbm_soft_reset = 0; 1318 u32 tmp; 1319 1320 if (!adev->sdma.srbm_soft_reset) 1321 return 0; 1322 1323 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1324 1325 if (srbm_soft_reset) { 1326 tmp = RREG32(mmSRBM_SOFT_RESET); 1327 tmp |= srbm_soft_reset; 1328 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1329 WREG32(mmSRBM_SOFT_RESET, tmp); 1330 tmp = RREG32(mmSRBM_SOFT_RESET); 1331 1332 udelay(50); 1333 1334 tmp &= ~srbm_soft_reset; 1335 WREG32(mmSRBM_SOFT_RESET, tmp); 1336 tmp = RREG32(mmSRBM_SOFT_RESET); 1337 1338 /* Wait a little for things to settle down */ 1339 udelay(50); 1340 } 1341 1342 return 0; 1343 } 1344 1345 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev, 1346 struct amdgpu_irq_src *source, 1347 unsigned type, 1348 enum amdgpu_interrupt_state state) 1349 { 1350 u32 sdma_cntl; 1351 1352 switch (type) { 1353 case AMDGPU_SDMA_IRQ_INSTANCE0: 1354 switch (state) { 1355 case AMDGPU_IRQ_STATE_DISABLE: 1356 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1357 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1358 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1359 break; 1360 case AMDGPU_IRQ_STATE_ENABLE: 1361 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1362 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1363 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1364 break; 1365 default: 1366 break; 1367 } 1368 break; 1369 case AMDGPU_SDMA_IRQ_INSTANCE1: 1370 switch (state) { 1371 case AMDGPU_IRQ_STATE_DISABLE: 1372 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1373 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1374 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1375 break; 1376 case AMDGPU_IRQ_STATE_ENABLE: 1377 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1378 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1379 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1380 break; 1381 default: 1382 break; 1383 } 1384 break; 1385 default: 1386 break; 1387 } 1388 return 0; 1389 } 1390 1391 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev, 1392 struct amdgpu_irq_src *source, 1393 struct amdgpu_iv_entry *entry) 1394 { 1395 u8 instance_id, queue_id; 1396 1397 instance_id = (entry->ring_id & 0x3) >> 0; 1398 queue_id = (entry->ring_id & 0xc) >> 2; 1399 DRM_DEBUG("IH: SDMA trap\n"); 1400 switch (instance_id) { 1401 case 0: 1402 switch (queue_id) { 1403 case 0: 1404 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1405 break; 1406 case 1: 1407 /* XXX compute */ 1408 break; 1409 case 2: 1410 /* XXX compute */ 1411 break; 1412 } 1413 break; 1414 case 1: 1415 switch (queue_id) { 1416 case 0: 1417 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1418 break; 1419 case 1: 1420 /* XXX compute */ 1421 break; 1422 case 2: 1423 /* XXX compute */ 1424 break; 1425 } 1426 break; 1427 } 1428 return 0; 1429 } 1430 1431 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1432 struct amdgpu_irq_src *source, 1433 struct amdgpu_iv_entry *entry) 1434 { 1435 u8 instance_id, queue_id; 1436 1437 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1438 instance_id = (entry->ring_id & 0x3) >> 0; 1439 queue_id = (entry->ring_id & 0xc) >> 2; 1440 1441 if (instance_id <= 1 && queue_id == 0) 1442 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched); 1443 return 0; 1444 } 1445 1446 static void sdma_v3_0_update_sdma_medium_grain_clock_gating( 1447 struct amdgpu_device *adev, 1448 bool enable) 1449 { 1450 uint32_t temp, data; 1451 int i; 1452 1453 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1454 for (i = 0; i < adev->sdma.num_instances; i++) { 1455 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); 1456 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1457 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1458 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1459 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1460 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1461 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1462 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1463 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1464 if (data != temp) 1465 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); 1466 } 1467 } else { 1468 for (i = 0; i < adev->sdma.num_instances; i++) { 1469 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); 1470 data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1471 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1472 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1473 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1474 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1475 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1476 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1477 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK; 1478 1479 if (data != temp) 1480 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); 1481 } 1482 } 1483 } 1484 1485 static void sdma_v3_0_update_sdma_medium_grain_light_sleep( 1486 struct amdgpu_device *adev, 1487 bool enable) 1488 { 1489 uint32_t temp, data; 1490 int i; 1491 1492 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1493 for (i = 0; i < adev->sdma.num_instances; i++) { 1494 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1495 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1496 1497 if (temp != data) 1498 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1499 } 1500 } else { 1501 for (i = 0; i < adev->sdma.num_instances; i++) { 1502 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1503 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1504 1505 if (temp != data) 1506 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1507 } 1508 } 1509 } 1510 1511 static int sdma_v3_0_set_clockgating_state(void *handle, 1512 enum amd_clockgating_state state) 1513 { 1514 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1515 1516 if (amdgpu_sriov_vf(adev)) 1517 return 0; 1518 1519 switch (adev->asic_type) { 1520 case CHIP_FIJI: 1521 case CHIP_CARRIZO: 1522 case CHIP_STONEY: 1523 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev, 1524 state == AMD_CG_STATE_GATE); 1525 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev, 1526 state == AMD_CG_STATE_GATE); 1527 break; 1528 default: 1529 break; 1530 } 1531 return 0; 1532 } 1533 1534 static int sdma_v3_0_set_powergating_state(void *handle, 1535 enum amd_powergating_state state) 1536 { 1537 return 0; 1538 } 1539 1540 static void sdma_v3_0_get_clockgating_state(void *handle, u32 *flags) 1541 { 1542 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1543 int data; 1544 1545 if (amdgpu_sriov_vf(adev)) 1546 *flags = 0; 1547 1548 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1549 data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]); 1550 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK)) 1551 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1552 1553 /* AMD_CG_SUPPORT_SDMA_LS */ 1554 data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]); 1555 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1556 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1557 } 1558 1559 static const struct amd_ip_funcs sdma_v3_0_ip_funcs = { 1560 .name = "sdma_v3_0", 1561 .early_init = sdma_v3_0_early_init, 1562 .late_init = NULL, 1563 .sw_init = sdma_v3_0_sw_init, 1564 .sw_fini = sdma_v3_0_sw_fini, 1565 .hw_init = sdma_v3_0_hw_init, 1566 .hw_fini = sdma_v3_0_hw_fini, 1567 .suspend = sdma_v3_0_suspend, 1568 .resume = sdma_v3_0_resume, 1569 .is_idle = sdma_v3_0_is_idle, 1570 .wait_for_idle = sdma_v3_0_wait_for_idle, 1571 .check_soft_reset = sdma_v3_0_check_soft_reset, 1572 .pre_soft_reset = sdma_v3_0_pre_soft_reset, 1573 .post_soft_reset = sdma_v3_0_post_soft_reset, 1574 .soft_reset = sdma_v3_0_soft_reset, 1575 .set_clockgating_state = sdma_v3_0_set_clockgating_state, 1576 .set_powergating_state = sdma_v3_0_set_powergating_state, 1577 .get_clockgating_state = sdma_v3_0_get_clockgating_state, 1578 }; 1579 1580 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { 1581 .type = AMDGPU_RING_TYPE_SDMA, 1582 .align_mask = 0xf, 1583 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1584 .support_64bit_ptrs = false, 1585 .get_rptr = sdma_v3_0_ring_get_rptr, 1586 .get_wptr = sdma_v3_0_ring_get_wptr, 1587 .set_wptr = sdma_v3_0_ring_set_wptr, 1588 .emit_frame_size = 1589 6 + /* sdma_v3_0_ring_emit_hdp_flush */ 1590 3 + /* hdp invalidate */ 1591 6 + /* sdma_v3_0_ring_emit_pipeline_sync */ 1592 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v3_0_ring_emit_vm_flush */ 1593 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */ 1594 .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */ 1595 .emit_ib = sdma_v3_0_ring_emit_ib, 1596 .emit_fence = sdma_v3_0_ring_emit_fence, 1597 .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync, 1598 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, 1599 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, 1600 .test_ring = sdma_v3_0_ring_test_ring, 1601 .test_ib = sdma_v3_0_ring_test_ib, 1602 .insert_nop = sdma_v3_0_ring_insert_nop, 1603 .pad_ib = sdma_v3_0_ring_pad_ib, 1604 .emit_wreg = sdma_v3_0_ring_emit_wreg, 1605 }; 1606 1607 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev) 1608 { 1609 int i; 1610 1611 for (i = 0; i < adev->sdma.num_instances; i++) { 1612 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs; 1613 adev->sdma.instance[i].ring.me = i; 1614 } 1615 } 1616 1617 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = { 1618 .set = sdma_v3_0_set_trap_irq_state, 1619 .process = sdma_v3_0_process_trap_irq, 1620 }; 1621 1622 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = { 1623 .process = sdma_v3_0_process_illegal_inst_irq, 1624 }; 1625 1626 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev) 1627 { 1628 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1629 adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs; 1630 adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs; 1631 } 1632 1633 /** 1634 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine 1635 * 1636 * @ib: indirect buffer to copy to 1637 * @src_offset: src GPU address 1638 * @dst_offset: dst GPU address 1639 * @byte_count: number of bytes to xfer 1640 * @tmz: unused 1641 * 1642 * Copy GPU buffers using the DMA engine (VI). 1643 * Used by the amdgpu ttm implementation to move pages if 1644 * registered as the asic copy callback. 1645 */ 1646 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib, 1647 uint64_t src_offset, 1648 uint64_t dst_offset, 1649 uint32_t byte_count, 1650 bool tmz) 1651 { 1652 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1653 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1654 ib->ptr[ib->length_dw++] = byte_count; 1655 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1656 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1657 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1658 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1659 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1660 } 1661 1662 /** 1663 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine 1664 * 1665 * @ib: indirect buffer to copy to 1666 * @src_data: value to write to buffer 1667 * @dst_offset: dst GPU address 1668 * @byte_count: number of bytes to xfer 1669 * 1670 * Fill GPU buffers using the DMA engine (VI). 1671 */ 1672 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib, 1673 uint32_t src_data, 1674 uint64_t dst_offset, 1675 uint32_t byte_count) 1676 { 1677 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1678 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1679 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1680 ib->ptr[ib->length_dw++] = src_data; 1681 ib->ptr[ib->length_dw++] = byte_count; 1682 } 1683 1684 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = { 1685 .copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */ 1686 .copy_num_dw = 7, 1687 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer, 1688 1689 .fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */ 1690 .fill_num_dw = 5, 1691 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer, 1692 }; 1693 1694 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) 1695 { 1696 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs; 1697 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1698 } 1699 1700 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { 1701 .copy_pte_num_dw = 7, 1702 .copy_pte = sdma_v3_0_vm_copy_pte, 1703 1704 .write_pte = sdma_v3_0_vm_write_pte, 1705 .set_pte_pde = sdma_v3_0_vm_set_pte_pde, 1706 }; 1707 1708 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1709 { 1710 unsigned i; 1711 1712 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; 1713 for (i = 0; i < adev->sdma.num_instances; i++) { 1714 adev->vm_manager.vm_pte_scheds[i] = 1715 &adev->sdma.instance[i].ring.sched; 1716 } 1717 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1718 } 1719 1720 const struct amdgpu_ip_block_version sdma_v3_0_ip_block = 1721 { 1722 .type = AMD_IP_BLOCK_TYPE_SDMA, 1723 .major = 3, 1724 .minor = 0, 1725 .rev = 0, 1726 .funcs = &sdma_v3_0_ip_funcs, 1727 }; 1728 1729 const struct amdgpu_ip_block_version sdma_v3_1_ip_block = 1730 { 1731 .type = AMD_IP_BLOCK_TYPE_SDMA, 1732 .major = 3, 1733 .minor = 1, 1734 .rev = 0, 1735 .funcs = &sdma_v3_0_ip_funcs, 1736 }; 1737