1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 25 #include <linux/delay.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 #include "vi.h" 33 #include "vid.h" 34 35 #include "oss/oss_3_0_d.h" 36 #include "oss/oss_3_0_sh_mask.h" 37 38 #include "gmc/gmc_8_1_d.h" 39 #include "gmc/gmc_8_1_sh_mask.h" 40 41 #include "gca/gfx_8_0_d.h" 42 #include "gca/gfx_8_0_enum.h" 43 #include "gca/gfx_8_0_sh_mask.h" 44 45 #include "bif/bif_5_0_d.h" 46 #include "bif/bif_5_0_sh_mask.h" 47 48 #include "tonga_sdma_pkt_open.h" 49 50 #include "ivsrcid/ivsrcid_vislands30.h" 51 52 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev); 53 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); 54 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev); 55 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); 56 57 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); 58 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin"); 59 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin"); 60 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); 61 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); 62 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); 63 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin"); 64 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin"); 65 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin"); 66 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin"); 67 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin"); 68 MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin"); 69 MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin"); 70 MODULE_FIRMWARE("amdgpu/vegam_sdma.bin"); 71 MODULE_FIRMWARE("amdgpu/vegam_sdma1.bin"); 72 73 74 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 75 { 76 SDMA0_REGISTER_OFFSET, 77 SDMA1_REGISTER_OFFSET 78 }; 79 80 static const u32 golden_settings_tonga_a11[] = 81 { 82 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 83 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 84 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 85 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 86 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 87 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 88 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 89 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 90 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 91 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 92 }; 93 94 static const u32 tonga_mgcg_cgcg_init[] = 95 { 96 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 97 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 98 }; 99 100 static const u32 golden_settings_fiji_a10[] = 101 { 102 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 103 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 104 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 105 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 106 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 107 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 108 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 109 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 110 }; 111 112 static const u32 fiji_mgcg_cgcg_init[] = 113 { 114 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 115 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 116 }; 117 118 static const u32 golden_settings_polaris11_a11[] = 119 { 120 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 121 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 122 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 123 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 124 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 125 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 126 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 127 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 128 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 129 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 130 }; 131 132 static const u32 golden_settings_polaris10_a11[] = 133 { 134 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 135 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 136 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 137 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 138 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 139 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 140 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 141 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 142 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 143 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 144 }; 145 146 static const u32 cz_golden_settings_a11[] = 147 { 148 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 149 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 150 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 151 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 152 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 153 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 154 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 155 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 156 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100, 157 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800, 158 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100, 159 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100, 160 }; 161 162 static const u32 cz_mgcg_cgcg_init[] = 163 { 164 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 165 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 166 }; 167 168 static const u32 stoney_golden_settings_a11[] = 169 { 170 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 171 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 172 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 173 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 174 }; 175 176 static const u32 stoney_mgcg_cgcg_init[] = 177 { 178 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100, 179 }; 180 181 /* 182 * sDMA - System DMA 183 * Starting with CIK, the GPU has new asynchronous 184 * DMA engines. These engines are used for compute 185 * and gfx. There are two DMA engines (SDMA0, SDMA1) 186 * and each one supports 1 ring buffer used for gfx 187 * and 2 queues used for compute. 188 * 189 * The programming model is very similar to the CP 190 * (ring buffer, IBs, etc.), but sDMA has it's own 191 * packet format that is different from the PM4 format 192 * used by the CP. sDMA supports copying data, writing 193 * embedded data, solid fills, and a number of other 194 * things. It also has support for tiling/detiling of 195 * buffers. 196 */ 197 198 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) 199 { 200 switch (adev->asic_type) { 201 case CHIP_FIJI: 202 amdgpu_device_program_register_sequence(adev, 203 fiji_mgcg_cgcg_init, 204 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 205 amdgpu_device_program_register_sequence(adev, 206 golden_settings_fiji_a10, 207 ARRAY_SIZE(golden_settings_fiji_a10)); 208 break; 209 case CHIP_TONGA: 210 amdgpu_device_program_register_sequence(adev, 211 tonga_mgcg_cgcg_init, 212 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 213 amdgpu_device_program_register_sequence(adev, 214 golden_settings_tonga_a11, 215 ARRAY_SIZE(golden_settings_tonga_a11)); 216 break; 217 case CHIP_POLARIS11: 218 case CHIP_POLARIS12: 219 case CHIP_VEGAM: 220 amdgpu_device_program_register_sequence(adev, 221 golden_settings_polaris11_a11, 222 ARRAY_SIZE(golden_settings_polaris11_a11)); 223 break; 224 case CHIP_POLARIS10: 225 amdgpu_device_program_register_sequence(adev, 226 golden_settings_polaris10_a11, 227 ARRAY_SIZE(golden_settings_polaris10_a11)); 228 break; 229 case CHIP_CARRIZO: 230 amdgpu_device_program_register_sequence(adev, 231 cz_mgcg_cgcg_init, 232 ARRAY_SIZE(cz_mgcg_cgcg_init)); 233 amdgpu_device_program_register_sequence(adev, 234 cz_golden_settings_a11, 235 ARRAY_SIZE(cz_golden_settings_a11)); 236 break; 237 case CHIP_STONEY: 238 amdgpu_device_program_register_sequence(adev, 239 stoney_mgcg_cgcg_init, 240 ARRAY_SIZE(stoney_mgcg_cgcg_init)); 241 amdgpu_device_program_register_sequence(adev, 242 stoney_golden_settings_a11, 243 ARRAY_SIZE(stoney_golden_settings_a11)); 244 break; 245 default: 246 break; 247 } 248 } 249 250 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev) 251 { 252 int i; 253 254 for (i = 0; i < adev->sdma.num_instances; i++) 255 amdgpu_ucode_release(&adev->sdma.instance[i].fw); 256 } 257 258 /** 259 * sdma_v3_0_init_microcode - load ucode images from disk 260 * 261 * @adev: amdgpu_device pointer 262 * 263 * Use the firmware interface to load the ucode images into 264 * the driver (not loaded into hw). 265 * Returns 0 on success, error on failure. 266 */ 267 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) 268 { 269 const char *chip_name; 270 char fw_name[30]; 271 int err = 0, i; 272 struct amdgpu_firmware_info *info = NULL; 273 const struct common_firmware_header *header = NULL; 274 const struct sdma_firmware_header_v1_0 *hdr; 275 276 DRM_DEBUG("\n"); 277 278 switch (adev->asic_type) { 279 case CHIP_TONGA: 280 chip_name = "tonga"; 281 break; 282 case CHIP_FIJI: 283 chip_name = "fiji"; 284 break; 285 case CHIP_POLARIS10: 286 chip_name = "polaris10"; 287 break; 288 case CHIP_POLARIS11: 289 chip_name = "polaris11"; 290 break; 291 case CHIP_POLARIS12: 292 chip_name = "polaris12"; 293 break; 294 case CHIP_VEGAM: 295 chip_name = "vegam"; 296 break; 297 case CHIP_CARRIZO: 298 chip_name = "carrizo"; 299 break; 300 case CHIP_STONEY: 301 chip_name = "stoney"; 302 break; 303 default: BUG(); 304 } 305 306 for (i = 0; i < adev->sdma.num_instances; i++) { 307 if (i == 0) 308 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 309 else 310 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 311 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw, fw_name); 312 if (err) 313 goto out; 314 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 315 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 316 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 317 if (adev->sdma.instance[i].feature_version >= 20) 318 adev->sdma.instance[i].burst_nop = true; 319 320 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 321 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 322 info->fw = adev->sdma.instance[i].fw; 323 header = (const struct common_firmware_header *)info->fw->data; 324 adev->firmware.fw_size += 325 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 326 327 } 328 out: 329 if (err) { 330 pr_err("sdma_v3_0: Failed to load firmware \"%s\"\n", fw_name); 331 for (i = 0; i < adev->sdma.num_instances; i++) 332 amdgpu_ucode_release(&adev->sdma.instance[i].fw); 333 } 334 return err; 335 } 336 337 /** 338 * sdma_v3_0_ring_get_rptr - get the current read pointer 339 * 340 * @ring: amdgpu ring pointer 341 * 342 * Get the current rptr from the hardware (VI+). 343 */ 344 static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring) 345 { 346 /* XXX check if swapping is necessary on BE */ 347 return *ring->rptr_cpu_addr >> 2; 348 } 349 350 /** 351 * sdma_v3_0_ring_get_wptr - get the current write pointer 352 * 353 * @ring: amdgpu ring pointer 354 * 355 * Get the current wptr from the hardware (VI+). 356 */ 357 static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring) 358 { 359 struct amdgpu_device *adev = ring->adev; 360 u32 wptr; 361 362 if (ring->use_doorbell || ring->use_pollmem) { 363 /* XXX check if swapping is necessary on BE */ 364 wptr = *ring->wptr_cpu_addr >> 2; 365 } else { 366 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; 367 } 368 369 return wptr; 370 } 371 372 /** 373 * sdma_v3_0_ring_set_wptr - commit the write pointer 374 * 375 * @ring: amdgpu ring pointer 376 * 377 * Write the wptr back to the hardware (VI+). 378 */ 379 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) 380 { 381 struct amdgpu_device *adev = ring->adev; 382 383 if (ring->use_doorbell) { 384 u32 *wb = (u32 *)ring->wptr_cpu_addr; 385 /* XXX check if swapping is necessary on BE */ 386 WRITE_ONCE(*wb, ring->wptr << 2); 387 WDOORBELL32(ring->doorbell_index, ring->wptr << 2); 388 } else if (ring->use_pollmem) { 389 u32 *wb = (u32 *)ring->wptr_cpu_addr; 390 391 WRITE_ONCE(*wb, ring->wptr << 2); 392 } else { 393 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2); 394 } 395 } 396 397 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 398 { 399 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 400 int i; 401 402 for (i = 0; i < count; i++) 403 if (sdma && sdma->burst_nop && (i == 0)) 404 amdgpu_ring_write(ring, ring->funcs->nop | 405 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 406 else 407 amdgpu_ring_write(ring, ring->funcs->nop); 408 } 409 410 /** 411 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine 412 * 413 * @ring: amdgpu ring pointer 414 * @job: job to retrieve vmid from 415 * @ib: IB object to schedule 416 * @flags: unused 417 * 418 * Schedule an IB in the DMA ring (VI). 419 */ 420 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, 421 struct amdgpu_job *job, 422 struct amdgpu_ib *ib, 423 uint32_t flags) 424 { 425 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 426 427 /* IB packet must end on a 8 DW boundary */ 428 sdma_v3_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 429 430 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 431 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 432 /* base must be 32 byte aligned */ 433 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 434 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 435 amdgpu_ring_write(ring, ib->length_dw); 436 amdgpu_ring_write(ring, 0); 437 amdgpu_ring_write(ring, 0); 438 439 } 440 441 /** 442 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 443 * 444 * @ring: amdgpu ring pointer 445 * 446 * Emit an hdp flush packet on the requested DMA ring. 447 */ 448 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 449 { 450 u32 ref_and_mask = 0; 451 452 if (ring->me == 0) 453 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); 454 else 455 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); 456 457 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 458 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 459 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 460 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 461 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 462 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 463 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 464 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 465 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 466 } 467 468 /** 469 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring 470 * 471 * @ring: amdgpu ring pointer 472 * @addr: address 473 * @seq: sequence number 474 * @flags: fence related flags 475 * 476 * Add a DMA fence packet to the ring to write 477 * the fence seq number and DMA trap packet to generate 478 * an interrupt if needed (VI). 479 */ 480 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 481 unsigned flags) 482 { 483 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 484 /* write the fence */ 485 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 486 amdgpu_ring_write(ring, lower_32_bits(addr)); 487 amdgpu_ring_write(ring, upper_32_bits(addr)); 488 amdgpu_ring_write(ring, lower_32_bits(seq)); 489 490 /* optionally write high bits as well */ 491 if (write64bit) { 492 addr += 4; 493 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 494 amdgpu_ring_write(ring, lower_32_bits(addr)); 495 amdgpu_ring_write(ring, upper_32_bits(addr)); 496 amdgpu_ring_write(ring, upper_32_bits(seq)); 497 } 498 499 /* generate an interrupt */ 500 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 501 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 502 } 503 504 /** 505 * sdma_v3_0_gfx_stop - stop the gfx async dma engines 506 * 507 * @adev: amdgpu_device pointer 508 * 509 * Stop the gfx async dma ring buffers (VI). 510 */ 511 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev) 512 { 513 u32 rb_cntl, ib_cntl; 514 int i; 515 516 for (i = 0; i < adev->sdma.num_instances; i++) { 517 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 518 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 519 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 520 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 521 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 522 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 523 } 524 } 525 526 /** 527 * sdma_v3_0_rlc_stop - stop the compute async dma engines 528 * 529 * @adev: amdgpu_device pointer 530 * 531 * Stop the compute async dma queues (VI). 532 */ 533 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev) 534 { 535 /* XXX todo */ 536 } 537 538 /** 539 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch 540 * 541 * @adev: amdgpu_device pointer 542 * @enable: enable/disable the DMA MEs context switch. 543 * 544 * Halt or unhalt the async dma engines context switch (VI). 545 */ 546 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 547 { 548 u32 f32_cntl, phase_quantum = 0; 549 int i; 550 551 if (amdgpu_sdma_phase_quantum) { 552 unsigned value = amdgpu_sdma_phase_quantum; 553 unsigned unit = 0; 554 555 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 556 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 557 value = (value + 1) >> 1; 558 unit++; 559 } 560 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 561 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 562 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 563 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 564 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 565 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 566 WARN_ONCE(1, 567 "clamping sdma_phase_quantum to %uK clock cycles\n", 568 value << unit); 569 } 570 phase_quantum = 571 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 572 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 573 } 574 575 for (i = 0; i < adev->sdma.num_instances; i++) { 576 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); 577 if (enable) { 578 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 579 AUTO_CTXSW_ENABLE, 1); 580 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 581 ATC_L1_ENABLE, 1); 582 if (amdgpu_sdma_phase_quantum) { 583 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], 584 phase_quantum); 585 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], 586 phase_quantum); 587 } 588 } else { 589 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 590 AUTO_CTXSW_ENABLE, 0); 591 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 592 ATC_L1_ENABLE, 1); 593 } 594 595 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); 596 } 597 } 598 599 /** 600 * sdma_v3_0_enable - stop the async dma engines 601 * 602 * @adev: amdgpu_device pointer 603 * @enable: enable/disable the DMA MEs. 604 * 605 * Halt or unhalt the async dma engines (VI). 606 */ 607 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable) 608 { 609 u32 f32_cntl; 610 int i; 611 612 if (!enable) { 613 sdma_v3_0_gfx_stop(adev); 614 sdma_v3_0_rlc_stop(adev); 615 } 616 617 for (i = 0; i < adev->sdma.num_instances; i++) { 618 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 619 if (enable) 620 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); 621 else 622 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 623 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); 624 } 625 } 626 627 /** 628 * sdma_v3_0_gfx_resume - setup and start the async dma engines 629 * 630 * @adev: amdgpu_device pointer 631 * 632 * Set up the gfx DMA ring buffers and enable them (VI). 633 * Returns 0 for success, error for failure. 634 */ 635 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) 636 { 637 struct amdgpu_ring *ring; 638 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 639 u32 rb_bufsz; 640 u32 doorbell; 641 u64 wptr_gpu_addr; 642 int i, j, r; 643 644 for (i = 0; i < adev->sdma.num_instances; i++) { 645 ring = &adev->sdma.instance[i].ring; 646 amdgpu_ring_clear_ring(ring); 647 648 mutex_lock(&adev->srbm_mutex); 649 for (j = 0; j < 16; j++) { 650 vi_srbm_select(adev, 0, 0, 0, j); 651 /* SDMA GFX */ 652 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 653 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 654 } 655 vi_srbm_select(adev, 0, 0, 0, 0); 656 mutex_unlock(&adev->srbm_mutex); 657 658 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], 659 adev->gfx.config.gb_addr_config & 0x70); 660 661 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 662 663 /* Set ring buffer size in dwords */ 664 rb_bufsz = order_base_2(ring->ring_size / 4); 665 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 666 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 667 #ifdef __BIG_ENDIAN 668 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 669 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 670 RPTR_WRITEBACK_SWAP_ENABLE, 1); 671 #endif 672 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 673 674 /* Initialize the ring buffer's read and write pointers */ 675 ring->wptr = 0; 676 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 677 sdma_v3_0_ring_set_wptr(ring); 678 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); 679 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); 680 681 /* set the wb address whether it's enabled or not */ 682 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 683 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 684 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 685 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 686 687 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 688 689 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 690 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 691 692 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); 693 694 if (ring->use_doorbell) { 695 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, 696 OFFSET, ring->doorbell_index); 697 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 698 } else { 699 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 700 } 701 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell); 702 703 /* setup the wptr shadow polling */ 704 wptr_gpu_addr = ring->wptr_gpu_addr; 705 706 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i], 707 lower_32_bits(wptr_gpu_addr)); 708 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i], 709 upper_32_bits(wptr_gpu_addr)); 710 wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]); 711 if (ring->use_pollmem) { 712 /*wptr polling is not enogh fast, directly clean the wptr register */ 713 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 714 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 715 SDMA0_GFX_RB_WPTR_POLL_CNTL, 716 ENABLE, 1); 717 } else { 718 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 719 SDMA0_GFX_RB_WPTR_POLL_CNTL, 720 ENABLE, 0); 721 } 722 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl); 723 724 /* enable DMA RB */ 725 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 726 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 727 728 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 729 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 730 #ifdef __BIG_ENDIAN 731 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 732 #endif 733 /* enable DMA IBs */ 734 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 735 } 736 737 /* unhalt the MEs */ 738 sdma_v3_0_enable(adev, true); 739 /* enable sdma ring preemption */ 740 sdma_v3_0_ctx_switch_enable(adev, true); 741 742 for (i = 0; i < adev->sdma.num_instances; i++) { 743 ring = &adev->sdma.instance[i].ring; 744 r = amdgpu_ring_test_helper(ring); 745 if (r) 746 return r; 747 } 748 749 return 0; 750 } 751 752 /** 753 * sdma_v3_0_rlc_resume - setup and start the async dma engines 754 * 755 * @adev: amdgpu_device pointer 756 * 757 * Set up the compute DMA queues and enable them (VI). 758 * Returns 0 for success, error for failure. 759 */ 760 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev) 761 { 762 /* XXX todo */ 763 return 0; 764 } 765 766 /** 767 * sdma_v3_0_start - setup and start the async dma engines 768 * 769 * @adev: amdgpu_device pointer 770 * 771 * Set up the DMA engines and enable them (VI). 772 * Returns 0 for success, error for failure. 773 */ 774 static int sdma_v3_0_start(struct amdgpu_device *adev) 775 { 776 int r; 777 778 /* disable sdma engine before programing it */ 779 sdma_v3_0_ctx_switch_enable(adev, false); 780 sdma_v3_0_enable(adev, false); 781 782 /* start the gfx rings and rlc compute queues */ 783 r = sdma_v3_0_gfx_resume(adev); 784 if (r) 785 return r; 786 r = sdma_v3_0_rlc_resume(adev); 787 if (r) 788 return r; 789 790 return 0; 791 } 792 793 /** 794 * sdma_v3_0_ring_test_ring - simple async dma engine test 795 * 796 * @ring: amdgpu_ring structure holding ring information 797 * 798 * Test the DMA engine by writing using it to write an 799 * value to memory. (VI). 800 * Returns 0 for success, error for failure. 801 */ 802 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) 803 { 804 struct amdgpu_device *adev = ring->adev; 805 unsigned i; 806 unsigned index; 807 int r; 808 u32 tmp; 809 u64 gpu_addr; 810 811 r = amdgpu_device_wb_get(adev, &index); 812 if (r) 813 return r; 814 815 gpu_addr = adev->wb.gpu_addr + (index * 4); 816 tmp = 0xCAFEDEAD; 817 adev->wb.wb[index] = cpu_to_le32(tmp); 818 819 r = amdgpu_ring_alloc(ring, 5); 820 if (r) 821 goto error_free_wb; 822 823 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 824 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 825 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 826 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 827 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 828 amdgpu_ring_write(ring, 0xDEADBEEF); 829 amdgpu_ring_commit(ring); 830 831 for (i = 0; i < adev->usec_timeout; i++) { 832 tmp = le32_to_cpu(adev->wb.wb[index]); 833 if (tmp == 0xDEADBEEF) 834 break; 835 udelay(1); 836 } 837 838 if (i >= adev->usec_timeout) 839 r = -ETIMEDOUT; 840 841 error_free_wb: 842 amdgpu_device_wb_free(adev, index); 843 return r; 844 } 845 846 /** 847 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine 848 * 849 * @ring: amdgpu_ring structure holding ring information 850 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 851 * 852 * Test a simple IB in the DMA ring (VI). 853 * Returns 0 on success, error on failure. 854 */ 855 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 856 { 857 struct amdgpu_device *adev = ring->adev; 858 struct amdgpu_ib ib; 859 struct dma_fence *f = NULL; 860 unsigned index; 861 u32 tmp = 0; 862 u64 gpu_addr; 863 long r; 864 865 r = amdgpu_device_wb_get(adev, &index); 866 if (r) 867 return r; 868 869 gpu_addr = adev->wb.gpu_addr + (index * 4); 870 tmp = 0xCAFEDEAD; 871 adev->wb.wb[index] = cpu_to_le32(tmp); 872 memset(&ib, 0, sizeof(ib)); 873 r = amdgpu_ib_get(adev, NULL, 256, 874 AMDGPU_IB_POOL_DIRECT, &ib); 875 if (r) 876 goto err0; 877 878 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 879 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 880 ib.ptr[1] = lower_32_bits(gpu_addr); 881 ib.ptr[2] = upper_32_bits(gpu_addr); 882 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); 883 ib.ptr[4] = 0xDEADBEEF; 884 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 885 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 886 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 887 ib.length_dw = 8; 888 889 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 890 if (r) 891 goto err1; 892 893 r = dma_fence_wait_timeout(f, false, timeout); 894 if (r == 0) { 895 r = -ETIMEDOUT; 896 goto err1; 897 } else if (r < 0) { 898 goto err1; 899 } 900 tmp = le32_to_cpu(adev->wb.wb[index]); 901 if (tmp == 0xDEADBEEF) 902 r = 0; 903 else 904 r = -EINVAL; 905 err1: 906 amdgpu_ib_free(adev, &ib, NULL); 907 dma_fence_put(f); 908 err0: 909 amdgpu_device_wb_free(adev, index); 910 return r; 911 } 912 913 /** 914 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART 915 * 916 * @ib: indirect buffer to fill with commands 917 * @pe: addr of the page entry 918 * @src: src addr to copy from 919 * @count: number of page entries to update 920 * 921 * Update PTEs by copying them from the GART using sDMA (CIK). 922 */ 923 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib, 924 uint64_t pe, uint64_t src, 925 unsigned count) 926 { 927 unsigned bytes = count * 8; 928 929 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 930 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 931 ib->ptr[ib->length_dw++] = bytes; 932 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 933 ib->ptr[ib->length_dw++] = lower_32_bits(src); 934 ib->ptr[ib->length_dw++] = upper_32_bits(src); 935 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 936 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 937 } 938 939 /** 940 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually 941 * 942 * @ib: indirect buffer to fill with commands 943 * @pe: addr of the page entry 944 * @value: dst addr to write into pe 945 * @count: number of page entries to update 946 * @incr: increase next addr by incr bytes 947 * 948 * Update PTEs by writing them manually using sDMA (CIK). 949 */ 950 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 951 uint64_t value, unsigned count, 952 uint32_t incr) 953 { 954 unsigned ndw = count * 2; 955 956 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 957 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 958 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 959 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 960 ib->ptr[ib->length_dw++] = ndw; 961 for (; ndw > 0; ndw -= 2) { 962 ib->ptr[ib->length_dw++] = lower_32_bits(value); 963 ib->ptr[ib->length_dw++] = upper_32_bits(value); 964 value += incr; 965 } 966 } 967 968 /** 969 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA 970 * 971 * @ib: indirect buffer to fill with commands 972 * @pe: addr of the page entry 973 * @addr: dst addr to write into pe 974 * @count: number of page entries to update 975 * @incr: increase next addr by incr bytes 976 * @flags: access flags 977 * 978 * Update the page tables using sDMA (CIK). 979 */ 980 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, 981 uint64_t addr, unsigned count, 982 uint32_t incr, uint64_t flags) 983 { 984 /* for physically contiguous pages (vram) */ 985 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); 986 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 987 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 988 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 989 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 990 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 991 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 992 ib->ptr[ib->length_dw++] = incr; /* increment size */ 993 ib->ptr[ib->length_dw++] = 0; 994 ib->ptr[ib->length_dw++] = count; /* number of entries */ 995 } 996 997 /** 998 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw 999 * 1000 * @ring: amdgpu_ring structure holding ring information 1001 * @ib: indirect buffer to fill with padding 1002 * 1003 */ 1004 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1005 { 1006 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1007 u32 pad_count; 1008 int i; 1009 1010 pad_count = (-ib->length_dw) & 7; 1011 for (i = 0; i < pad_count; i++) 1012 if (sdma && sdma->burst_nop && (i == 0)) 1013 ib->ptr[ib->length_dw++] = 1014 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1015 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1016 else 1017 ib->ptr[ib->length_dw++] = 1018 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1019 } 1020 1021 /** 1022 * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline 1023 * 1024 * @ring: amdgpu_ring pointer 1025 * 1026 * Make sure all previous operations are completed (CIK). 1027 */ 1028 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1029 { 1030 uint32_t seq = ring->fence_drv.sync_seq; 1031 uint64_t addr = ring->fence_drv.gpu_addr; 1032 1033 /* wait for idle */ 1034 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1035 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1036 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1037 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1038 amdgpu_ring_write(ring, addr & 0xfffffffc); 1039 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1040 amdgpu_ring_write(ring, seq); /* reference */ 1041 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1042 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1043 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1044 } 1045 1046 /** 1047 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA 1048 * 1049 * @ring: amdgpu_ring pointer 1050 * @vmid: vmid number to use 1051 * @pd_addr: address 1052 * 1053 * Update the page table base and flush the VM TLB 1054 * using sDMA (VI). 1055 */ 1056 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1057 unsigned vmid, uint64_t pd_addr) 1058 { 1059 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1060 1061 /* wait for flush */ 1062 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1063 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1064 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ 1065 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 1066 amdgpu_ring_write(ring, 0); 1067 amdgpu_ring_write(ring, 0); /* reference */ 1068 amdgpu_ring_write(ring, 0); /* mask */ 1069 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1070 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 1071 } 1072 1073 static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring, 1074 uint32_t reg, uint32_t val) 1075 { 1076 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1077 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1078 amdgpu_ring_write(ring, reg); 1079 amdgpu_ring_write(ring, val); 1080 } 1081 1082 static int sdma_v3_0_early_init(void *handle) 1083 { 1084 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1085 int r; 1086 1087 switch (adev->asic_type) { 1088 case CHIP_STONEY: 1089 adev->sdma.num_instances = 1; 1090 break; 1091 default: 1092 adev->sdma.num_instances = SDMA_MAX_INSTANCE; 1093 break; 1094 } 1095 1096 r = sdma_v3_0_init_microcode(adev); 1097 if (r) 1098 return r; 1099 1100 sdma_v3_0_set_ring_funcs(adev); 1101 sdma_v3_0_set_buffer_funcs(adev); 1102 sdma_v3_0_set_vm_pte_funcs(adev); 1103 sdma_v3_0_set_irq_funcs(adev); 1104 1105 return 0; 1106 } 1107 1108 static int sdma_v3_0_sw_init(void *handle) 1109 { 1110 struct amdgpu_ring *ring; 1111 int r, i; 1112 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1113 1114 /* SDMA trap event */ 1115 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP, 1116 &adev->sdma.trap_irq); 1117 if (r) 1118 return r; 1119 1120 /* SDMA Privileged inst */ 1121 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241, 1122 &adev->sdma.illegal_inst_irq); 1123 if (r) 1124 return r; 1125 1126 /* SDMA Privileged inst */ 1127 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE, 1128 &adev->sdma.illegal_inst_irq); 1129 if (r) 1130 return r; 1131 1132 for (i = 0; i < adev->sdma.num_instances; i++) { 1133 ring = &adev->sdma.instance[i].ring; 1134 ring->ring_obj = NULL; 1135 if (!amdgpu_sriov_vf(adev)) { 1136 ring->use_doorbell = true; 1137 ring->doorbell_index = adev->doorbell_index.sdma_engine[i]; 1138 } else { 1139 ring->use_pollmem = true; 1140 } 1141 1142 sprintf(ring->name, "sdma%d", i); 1143 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1144 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 : 1145 AMDGPU_SDMA_IRQ_INSTANCE1, 1146 AMDGPU_RING_PRIO_DEFAULT, NULL); 1147 if (r) 1148 return r; 1149 } 1150 1151 return r; 1152 } 1153 1154 static int sdma_v3_0_sw_fini(void *handle) 1155 { 1156 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1157 int i; 1158 1159 for (i = 0; i < adev->sdma.num_instances; i++) 1160 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1161 1162 sdma_v3_0_free_microcode(adev); 1163 return 0; 1164 } 1165 1166 static int sdma_v3_0_hw_init(void *handle) 1167 { 1168 int r; 1169 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1170 1171 sdma_v3_0_init_golden_registers(adev); 1172 1173 r = sdma_v3_0_start(adev); 1174 if (r) 1175 return r; 1176 1177 return r; 1178 } 1179 1180 static int sdma_v3_0_hw_fini(void *handle) 1181 { 1182 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1183 1184 sdma_v3_0_ctx_switch_enable(adev, false); 1185 sdma_v3_0_enable(adev, false); 1186 1187 return 0; 1188 } 1189 1190 static int sdma_v3_0_suspend(void *handle) 1191 { 1192 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1193 1194 return sdma_v3_0_hw_fini(adev); 1195 } 1196 1197 static int sdma_v3_0_resume(void *handle) 1198 { 1199 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1200 1201 return sdma_v3_0_hw_init(adev); 1202 } 1203 1204 static bool sdma_v3_0_is_idle(void *handle) 1205 { 1206 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1207 u32 tmp = RREG32(mmSRBM_STATUS2); 1208 1209 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1210 SRBM_STATUS2__SDMA1_BUSY_MASK)) 1211 return false; 1212 1213 return true; 1214 } 1215 1216 static int sdma_v3_0_wait_for_idle(void *handle) 1217 { 1218 unsigned i; 1219 u32 tmp; 1220 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1221 1222 for (i = 0; i < adev->usec_timeout; i++) { 1223 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1224 SRBM_STATUS2__SDMA1_BUSY_MASK); 1225 1226 if (!tmp) 1227 return 0; 1228 udelay(1); 1229 } 1230 return -ETIMEDOUT; 1231 } 1232 1233 static bool sdma_v3_0_check_soft_reset(void *handle) 1234 { 1235 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1236 u32 srbm_soft_reset = 0; 1237 u32 tmp = RREG32(mmSRBM_STATUS2); 1238 1239 if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) || 1240 (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) { 1241 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1242 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1243 } 1244 1245 if (srbm_soft_reset) { 1246 adev->sdma.srbm_soft_reset = srbm_soft_reset; 1247 return true; 1248 } else { 1249 adev->sdma.srbm_soft_reset = 0; 1250 return false; 1251 } 1252 } 1253 1254 static int sdma_v3_0_pre_soft_reset(void *handle) 1255 { 1256 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1257 u32 srbm_soft_reset = 0; 1258 1259 if (!adev->sdma.srbm_soft_reset) 1260 return 0; 1261 1262 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1263 1264 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || 1265 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { 1266 sdma_v3_0_ctx_switch_enable(adev, false); 1267 sdma_v3_0_enable(adev, false); 1268 } 1269 1270 return 0; 1271 } 1272 1273 static int sdma_v3_0_post_soft_reset(void *handle) 1274 { 1275 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1276 u32 srbm_soft_reset = 0; 1277 1278 if (!adev->sdma.srbm_soft_reset) 1279 return 0; 1280 1281 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1282 1283 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || 1284 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { 1285 sdma_v3_0_gfx_resume(adev); 1286 sdma_v3_0_rlc_resume(adev); 1287 } 1288 1289 return 0; 1290 } 1291 1292 static int sdma_v3_0_soft_reset(void *handle) 1293 { 1294 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1295 u32 srbm_soft_reset = 0; 1296 u32 tmp; 1297 1298 if (!adev->sdma.srbm_soft_reset) 1299 return 0; 1300 1301 srbm_soft_reset = adev->sdma.srbm_soft_reset; 1302 1303 if (srbm_soft_reset) { 1304 tmp = RREG32(mmSRBM_SOFT_RESET); 1305 tmp |= srbm_soft_reset; 1306 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1307 WREG32(mmSRBM_SOFT_RESET, tmp); 1308 tmp = RREG32(mmSRBM_SOFT_RESET); 1309 1310 udelay(50); 1311 1312 tmp &= ~srbm_soft_reset; 1313 WREG32(mmSRBM_SOFT_RESET, tmp); 1314 tmp = RREG32(mmSRBM_SOFT_RESET); 1315 1316 /* Wait a little for things to settle down */ 1317 udelay(50); 1318 } 1319 1320 return 0; 1321 } 1322 1323 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev, 1324 struct amdgpu_irq_src *source, 1325 unsigned type, 1326 enum amdgpu_interrupt_state state) 1327 { 1328 u32 sdma_cntl; 1329 1330 switch (type) { 1331 case AMDGPU_SDMA_IRQ_INSTANCE0: 1332 switch (state) { 1333 case AMDGPU_IRQ_STATE_DISABLE: 1334 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1335 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1336 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1337 break; 1338 case AMDGPU_IRQ_STATE_ENABLE: 1339 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1340 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1341 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1342 break; 1343 default: 1344 break; 1345 } 1346 break; 1347 case AMDGPU_SDMA_IRQ_INSTANCE1: 1348 switch (state) { 1349 case AMDGPU_IRQ_STATE_DISABLE: 1350 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1351 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1352 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1353 break; 1354 case AMDGPU_IRQ_STATE_ENABLE: 1355 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1356 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1357 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1358 break; 1359 default: 1360 break; 1361 } 1362 break; 1363 default: 1364 break; 1365 } 1366 return 0; 1367 } 1368 1369 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev, 1370 struct amdgpu_irq_src *source, 1371 struct amdgpu_iv_entry *entry) 1372 { 1373 u8 instance_id, queue_id; 1374 1375 instance_id = (entry->ring_id & 0x3) >> 0; 1376 queue_id = (entry->ring_id & 0xc) >> 2; 1377 DRM_DEBUG("IH: SDMA trap\n"); 1378 switch (instance_id) { 1379 case 0: 1380 switch (queue_id) { 1381 case 0: 1382 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1383 break; 1384 case 1: 1385 /* XXX compute */ 1386 break; 1387 case 2: 1388 /* XXX compute */ 1389 break; 1390 } 1391 break; 1392 case 1: 1393 switch (queue_id) { 1394 case 0: 1395 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1396 break; 1397 case 1: 1398 /* XXX compute */ 1399 break; 1400 case 2: 1401 /* XXX compute */ 1402 break; 1403 } 1404 break; 1405 } 1406 return 0; 1407 } 1408 1409 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1410 struct amdgpu_irq_src *source, 1411 struct amdgpu_iv_entry *entry) 1412 { 1413 u8 instance_id, queue_id; 1414 1415 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1416 instance_id = (entry->ring_id & 0x3) >> 0; 1417 queue_id = (entry->ring_id & 0xc) >> 2; 1418 1419 if (instance_id <= 1 && queue_id == 0) 1420 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched); 1421 return 0; 1422 } 1423 1424 static void sdma_v3_0_update_sdma_medium_grain_clock_gating( 1425 struct amdgpu_device *adev, 1426 bool enable) 1427 { 1428 uint32_t temp, data; 1429 int i; 1430 1431 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1432 for (i = 0; i < adev->sdma.num_instances; i++) { 1433 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); 1434 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1435 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1436 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1437 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1438 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1439 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1440 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1441 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1442 if (data != temp) 1443 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); 1444 } 1445 } else { 1446 for (i = 0; i < adev->sdma.num_instances; i++) { 1447 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); 1448 data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1449 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1450 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1451 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1452 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1453 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1454 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1455 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK; 1456 1457 if (data != temp) 1458 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); 1459 } 1460 } 1461 } 1462 1463 static void sdma_v3_0_update_sdma_medium_grain_light_sleep( 1464 struct amdgpu_device *adev, 1465 bool enable) 1466 { 1467 uint32_t temp, data; 1468 int i; 1469 1470 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1471 for (i = 0; i < adev->sdma.num_instances; i++) { 1472 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1473 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1474 1475 if (temp != data) 1476 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1477 } 1478 } else { 1479 for (i = 0; i < adev->sdma.num_instances; i++) { 1480 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1481 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1482 1483 if (temp != data) 1484 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1485 } 1486 } 1487 } 1488 1489 static int sdma_v3_0_set_clockgating_state(void *handle, 1490 enum amd_clockgating_state state) 1491 { 1492 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1493 1494 if (amdgpu_sriov_vf(adev)) 1495 return 0; 1496 1497 switch (adev->asic_type) { 1498 case CHIP_FIJI: 1499 case CHIP_CARRIZO: 1500 case CHIP_STONEY: 1501 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev, 1502 state == AMD_CG_STATE_GATE); 1503 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev, 1504 state == AMD_CG_STATE_GATE); 1505 break; 1506 default: 1507 break; 1508 } 1509 return 0; 1510 } 1511 1512 static int sdma_v3_0_set_powergating_state(void *handle, 1513 enum amd_powergating_state state) 1514 { 1515 return 0; 1516 } 1517 1518 static void sdma_v3_0_get_clockgating_state(void *handle, u64 *flags) 1519 { 1520 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1521 int data; 1522 1523 if (amdgpu_sriov_vf(adev)) 1524 *flags = 0; 1525 1526 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1527 data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]); 1528 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK)) 1529 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1530 1531 /* AMD_CG_SUPPORT_SDMA_LS */ 1532 data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]); 1533 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1534 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1535 } 1536 1537 static const struct amd_ip_funcs sdma_v3_0_ip_funcs = { 1538 .name = "sdma_v3_0", 1539 .early_init = sdma_v3_0_early_init, 1540 .late_init = NULL, 1541 .sw_init = sdma_v3_0_sw_init, 1542 .sw_fini = sdma_v3_0_sw_fini, 1543 .hw_init = sdma_v3_0_hw_init, 1544 .hw_fini = sdma_v3_0_hw_fini, 1545 .suspend = sdma_v3_0_suspend, 1546 .resume = sdma_v3_0_resume, 1547 .is_idle = sdma_v3_0_is_idle, 1548 .wait_for_idle = sdma_v3_0_wait_for_idle, 1549 .check_soft_reset = sdma_v3_0_check_soft_reset, 1550 .pre_soft_reset = sdma_v3_0_pre_soft_reset, 1551 .post_soft_reset = sdma_v3_0_post_soft_reset, 1552 .soft_reset = sdma_v3_0_soft_reset, 1553 .set_clockgating_state = sdma_v3_0_set_clockgating_state, 1554 .set_powergating_state = sdma_v3_0_set_powergating_state, 1555 .get_clockgating_state = sdma_v3_0_get_clockgating_state, 1556 .dump_ip_state = NULL, 1557 .print_ip_state = NULL, 1558 }; 1559 1560 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { 1561 .type = AMDGPU_RING_TYPE_SDMA, 1562 .align_mask = 0xf, 1563 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1564 .support_64bit_ptrs = false, 1565 .secure_submission_supported = true, 1566 .get_rptr = sdma_v3_0_ring_get_rptr, 1567 .get_wptr = sdma_v3_0_ring_get_wptr, 1568 .set_wptr = sdma_v3_0_ring_set_wptr, 1569 .emit_frame_size = 1570 6 + /* sdma_v3_0_ring_emit_hdp_flush */ 1571 3 + /* hdp invalidate */ 1572 6 + /* sdma_v3_0_ring_emit_pipeline_sync */ 1573 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v3_0_ring_emit_vm_flush */ 1574 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */ 1575 .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */ 1576 .emit_ib = sdma_v3_0_ring_emit_ib, 1577 .emit_fence = sdma_v3_0_ring_emit_fence, 1578 .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync, 1579 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, 1580 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, 1581 .test_ring = sdma_v3_0_ring_test_ring, 1582 .test_ib = sdma_v3_0_ring_test_ib, 1583 .insert_nop = sdma_v3_0_ring_insert_nop, 1584 .pad_ib = sdma_v3_0_ring_pad_ib, 1585 .emit_wreg = sdma_v3_0_ring_emit_wreg, 1586 }; 1587 1588 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev) 1589 { 1590 int i; 1591 1592 for (i = 0; i < adev->sdma.num_instances; i++) { 1593 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs; 1594 adev->sdma.instance[i].ring.me = i; 1595 } 1596 } 1597 1598 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = { 1599 .set = sdma_v3_0_set_trap_irq_state, 1600 .process = sdma_v3_0_process_trap_irq, 1601 }; 1602 1603 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = { 1604 .process = sdma_v3_0_process_illegal_inst_irq, 1605 }; 1606 1607 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev) 1608 { 1609 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1610 adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs; 1611 adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs; 1612 } 1613 1614 /** 1615 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine 1616 * 1617 * @ib: indirect buffer to copy to 1618 * @src_offset: src GPU address 1619 * @dst_offset: dst GPU address 1620 * @byte_count: number of bytes to xfer 1621 * @copy_flags: unused 1622 * 1623 * Copy GPU buffers using the DMA engine (VI). 1624 * Used by the amdgpu ttm implementation to move pages if 1625 * registered as the asic copy callback. 1626 */ 1627 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib, 1628 uint64_t src_offset, 1629 uint64_t dst_offset, 1630 uint32_t byte_count, 1631 uint32_t copy_flags) 1632 { 1633 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1634 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1635 ib->ptr[ib->length_dw++] = byte_count; 1636 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1637 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1638 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1639 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1640 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1641 } 1642 1643 /** 1644 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine 1645 * 1646 * @ib: indirect buffer to copy to 1647 * @src_data: value to write to buffer 1648 * @dst_offset: dst GPU address 1649 * @byte_count: number of bytes to xfer 1650 * 1651 * Fill GPU buffers using the DMA engine (VI). 1652 */ 1653 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib, 1654 uint32_t src_data, 1655 uint64_t dst_offset, 1656 uint32_t byte_count) 1657 { 1658 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1659 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1660 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1661 ib->ptr[ib->length_dw++] = src_data; 1662 ib->ptr[ib->length_dw++] = byte_count; 1663 } 1664 1665 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = { 1666 .copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */ 1667 .copy_num_dw = 7, 1668 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer, 1669 1670 .fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */ 1671 .fill_num_dw = 5, 1672 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer, 1673 }; 1674 1675 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) 1676 { 1677 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs; 1678 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1679 } 1680 1681 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { 1682 .copy_pte_num_dw = 7, 1683 .copy_pte = sdma_v3_0_vm_copy_pte, 1684 1685 .write_pte = sdma_v3_0_vm_write_pte, 1686 .set_pte_pde = sdma_v3_0_vm_set_pte_pde, 1687 }; 1688 1689 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1690 { 1691 unsigned i; 1692 1693 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; 1694 for (i = 0; i < adev->sdma.num_instances; i++) { 1695 adev->vm_manager.vm_pte_scheds[i] = 1696 &adev->sdma.instance[i].ring.sched; 1697 } 1698 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1699 } 1700 1701 const struct amdgpu_ip_block_version sdma_v3_0_ip_block = 1702 { 1703 .type = AMD_IP_BLOCK_TYPE_SDMA, 1704 .major = 3, 1705 .minor = 0, 1706 .rev = 0, 1707 .funcs = &sdma_v3_0_ip_funcs, 1708 }; 1709 1710 const struct amdgpu_ip_block_version sdma_v3_1_ip_block = 1711 { 1712 .type = AMD_IP_BLOCK_TYPE_SDMA, 1713 .major = 3, 1714 .minor = 1, 1715 .rev = 0, 1716 .funcs = &sdma_v3_0_ip_funcs, 1717 }; 1718