1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 #include "vi.h" 30 #include "vid.h" 31 32 #include "oss/oss_3_0_d.h" 33 #include "oss/oss_3_0_sh_mask.h" 34 35 #include "gmc/gmc_8_1_d.h" 36 #include "gmc/gmc_8_1_sh_mask.h" 37 38 #include "gca/gfx_8_0_d.h" 39 #include "gca/gfx_8_0_enum.h" 40 #include "gca/gfx_8_0_sh_mask.h" 41 42 #include "bif/bif_5_0_d.h" 43 #include "bif/bif_5_0_sh_mask.h" 44 45 #include "tonga_sdma_pkt_open.h" 46 47 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev); 48 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); 49 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev); 50 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); 51 52 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); 53 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin"); 54 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin"); 55 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); 56 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); 57 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); 58 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin"); 59 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin"); 60 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin"); 61 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin"); 62 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin"); 63 64 65 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 66 { 67 SDMA0_REGISTER_OFFSET, 68 SDMA1_REGISTER_OFFSET 69 }; 70 71 static const u32 golden_settings_tonga_a11[] = 72 { 73 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 74 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 75 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 76 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 77 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 78 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 79 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 80 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 81 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 82 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 83 }; 84 85 static const u32 tonga_mgcg_cgcg_init[] = 86 { 87 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 88 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 89 }; 90 91 static const u32 golden_settings_fiji_a10[] = 92 { 93 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 94 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 95 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 96 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 97 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 98 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 99 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 100 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 101 }; 102 103 static const u32 fiji_mgcg_cgcg_init[] = 104 { 105 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 106 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 107 }; 108 109 static const u32 golden_settings_polaris11_a11[] = 110 { 111 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 112 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 113 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 114 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 115 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 116 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 117 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 118 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 119 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 120 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 121 }; 122 123 static const u32 golden_settings_polaris10_a11[] = 124 { 125 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 126 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 127 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 128 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 129 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 130 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 131 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 132 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 133 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 134 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 135 }; 136 137 static const u32 cz_golden_settings_a11[] = 138 { 139 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 140 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 141 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 142 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 143 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 144 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 145 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 146 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 147 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100, 148 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800, 149 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100, 150 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100, 151 }; 152 153 static const u32 cz_mgcg_cgcg_init[] = 154 { 155 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 156 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 157 }; 158 159 static const u32 stoney_golden_settings_a11[] = 160 { 161 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 162 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 163 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 164 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 165 }; 166 167 static const u32 stoney_mgcg_cgcg_init[] = 168 { 169 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100, 170 }; 171 172 /* 173 * sDMA - System DMA 174 * Starting with CIK, the GPU has new asynchronous 175 * DMA engines. These engines are used for compute 176 * and gfx. There are two DMA engines (SDMA0, SDMA1) 177 * and each one supports 1 ring buffer used for gfx 178 * and 2 queues used for compute. 179 * 180 * The programming model is very similar to the CP 181 * (ring buffer, IBs, etc.), but sDMA has it's own 182 * packet format that is different from the PM4 format 183 * used by the CP. sDMA supports copying data, writing 184 * embedded data, solid fills, and a number of other 185 * things. It also has support for tiling/detiling of 186 * buffers. 187 */ 188 189 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) 190 { 191 switch (adev->asic_type) { 192 case CHIP_FIJI: 193 amdgpu_program_register_sequence(adev, 194 fiji_mgcg_cgcg_init, 195 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); 196 amdgpu_program_register_sequence(adev, 197 golden_settings_fiji_a10, 198 (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); 199 break; 200 case CHIP_TONGA: 201 amdgpu_program_register_sequence(adev, 202 tonga_mgcg_cgcg_init, 203 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); 204 amdgpu_program_register_sequence(adev, 205 golden_settings_tonga_a11, 206 (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); 207 break; 208 case CHIP_POLARIS11: 209 amdgpu_program_register_sequence(adev, 210 golden_settings_polaris11_a11, 211 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); 212 break; 213 case CHIP_POLARIS10: 214 amdgpu_program_register_sequence(adev, 215 golden_settings_polaris10_a11, 216 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); 217 break; 218 case CHIP_CARRIZO: 219 amdgpu_program_register_sequence(adev, 220 cz_mgcg_cgcg_init, 221 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 222 amdgpu_program_register_sequence(adev, 223 cz_golden_settings_a11, 224 (const u32)ARRAY_SIZE(cz_golden_settings_a11)); 225 break; 226 case CHIP_STONEY: 227 amdgpu_program_register_sequence(adev, 228 stoney_mgcg_cgcg_init, 229 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); 230 amdgpu_program_register_sequence(adev, 231 stoney_golden_settings_a11, 232 (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); 233 break; 234 default: 235 break; 236 } 237 } 238 239 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev) 240 { 241 int i; 242 for (i = 0; i < adev->sdma.num_instances; i++) { 243 release_firmware(adev->sdma.instance[i].fw); 244 adev->sdma.instance[i].fw = NULL; 245 } 246 } 247 248 /** 249 * sdma_v3_0_init_microcode - load ucode images from disk 250 * 251 * @adev: amdgpu_device pointer 252 * 253 * Use the firmware interface to load the ucode images into 254 * the driver (not loaded into hw). 255 * Returns 0 on success, error on failure. 256 */ 257 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) 258 { 259 const char *chip_name; 260 char fw_name[30]; 261 int err = 0, i; 262 struct amdgpu_firmware_info *info = NULL; 263 const struct common_firmware_header *header = NULL; 264 const struct sdma_firmware_header_v1_0 *hdr; 265 266 DRM_DEBUG("\n"); 267 268 switch (adev->asic_type) { 269 case CHIP_TONGA: 270 chip_name = "tonga"; 271 break; 272 case CHIP_FIJI: 273 chip_name = "fiji"; 274 break; 275 case CHIP_POLARIS11: 276 chip_name = "polaris11"; 277 break; 278 case CHIP_POLARIS10: 279 chip_name = "polaris10"; 280 break; 281 case CHIP_CARRIZO: 282 chip_name = "carrizo"; 283 break; 284 case CHIP_STONEY: 285 chip_name = "stoney"; 286 break; 287 default: BUG(); 288 } 289 290 for (i = 0; i < adev->sdma.num_instances; i++) { 291 if (i == 0) 292 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 293 else 294 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 295 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 296 if (err) 297 goto out; 298 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 299 if (err) 300 goto out; 301 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 302 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 303 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 304 if (adev->sdma.instance[i].feature_version >= 20) 305 adev->sdma.instance[i].burst_nop = true; 306 307 if (adev->firmware.smu_load) { 308 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 309 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 310 info->fw = adev->sdma.instance[i].fw; 311 header = (const struct common_firmware_header *)info->fw->data; 312 adev->firmware.fw_size += 313 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 314 } 315 } 316 out: 317 if (err) { 318 printk(KERN_ERR 319 "sdma_v3_0: Failed to load firmware \"%s\"\n", 320 fw_name); 321 for (i = 0; i < adev->sdma.num_instances; i++) { 322 release_firmware(adev->sdma.instance[i].fw); 323 adev->sdma.instance[i].fw = NULL; 324 } 325 } 326 return err; 327 } 328 329 /** 330 * sdma_v3_0_ring_get_rptr - get the current read pointer 331 * 332 * @ring: amdgpu ring pointer 333 * 334 * Get the current rptr from the hardware (VI+). 335 */ 336 static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring) 337 { 338 u32 rptr; 339 340 /* XXX check if swapping is necessary on BE */ 341 rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2; 342 343 return rptr; 344 } 345 346 /** 347 * sdma_v3_0_ring_get_wptr - get the current write pointer 348 * 349 * @ring: amdgpu ring pointer 350 * 351 * Get the current wptr from the hardware (VI+). 352 */ 353 static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring) 354 { 355 struct amdgpu_device *adev = ring->adev; 356 u32 wptr; 357 358 if (ring->use_doorbell) { 359 /* XXX check if swapping is necessary on BE */ 360 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; 361 } else { 362 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; 363 364 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2; 365 } 366 367 return wptr; 368 } 369 370 /** 371 * sdma_v3_0_ring_set_wptr - commit the write pointer 372 * 373 * @ring: amdgpu ring pointer 374 * 375 * Write the wptr back to the hardware (VI+). 376 */ 377 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) 378 { 379 struct amdgpu_device *adev = ring->adev; 380 381 if (ring->use_doorbell) { 382 /* XXX check if swapping is necessary on BE */ 383 adev->wb.wb[ring->wptr_offs] = ring->wptr << 2; 384 WDOORBELL32(ring->doorbell_index, ring->wptr << 2); 385 } else { 386 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; 387 388 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2); 389 } 390 } 391 392 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 393 { 394 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 395 int i; 396 397 for (i = 0; i < count; i++) 398 if (sdma && sdma->burst_nop && (i == 0)) 399 amdgpu_ring_write(ring, ring->nop | 400 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 401 else 402 amdgpu_ring_write(ring, ring->nop); 403 } 404 405 /** 406 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine 407 * 408 * @ring: amdgpu ring pointer 409 * @ib: IB object to schedule 410 * 411 * Schedule an IB in the DMA ring (VI). 412 */ 413 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, 414 struct amdgpu_ib *ib, 415 unsigned vm_id, bool ctx_switch) 416 { 417 u32 vmid = vm_id & 0xf; 418 419 /* IB packet must end on a 8 DW boundary */ 420 sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8); 421 422 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 423 SDMA_PKT_INDIRECT_HEADER_VMID(vmid)); 424 /* base must be 32 byte aligned */ 425 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 426 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 427 amdgpu_ring_write(ring, ib->length_dw); 428 amdgpu_ring_write(ring, 0); 429 amdgpu_ring_write(ring, 0); 430 431 } 432 433 /** 434 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 435 * 436 * @ring: amdgpu ring pointer 437 * 438 * Emit an hdp flush packet on the requested DMA ring. 439 */ 440 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 441 { 442 u32 ref_and_mask = 0; 443 444 if (ring == &ring->adev->sdma.instance[0].ring) 445 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); 446 else 447 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); 448 449 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 450 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 451 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 452 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 453 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 454 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 455 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 456 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 457 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 458 } 459 460 static void sdma_v3_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 461 { 462 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 463 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 464 amdgpu_ring_write(ring, mmHDP_DEBUG0); 465 amdgpu_ring_write(ring, 1); 466 } 467 468 /** 469 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring 470 * 471 * @ring: amdgpu ring pointer 472 * @fence: amdgpu fence object 473 * 474 * Add a DMA fence packet to the ring to write 475 * the fence seq number and DMA trap packet to generate 476 * an interrupt if needed (VI). 477 */ 478 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 479 unsigned flags) 480 { 481 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 482 /* write the fence */ 483 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 484 amdgpu_ring_write(ring, lower_32_bits(addr)); 485 amdgpu_ring_write(ring, upper_32_bits(addr)); 486 amdgpu_ring_write(ring, lower_32_bits(seq)); 487 488 /* optionally write high bits as well */ 489 if (write64bit) { 490 addr += 4; 491 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 492 amdgpu_ring_write(ring, lower_32_bits(addr)); 493 amdgpu_ring_write(ring, upper_32_bits(addr)); 494 amdgpu_ring_write(ring, upper_32_bits(seq)); 495 } 496 497 /* generate an interrupt */ 498 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 499 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 500 } 501 502 unsigned init_cond_exec(struct amdgpu_ring *ring) 503 { 504 unsigned ret; 505 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); 506 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 507 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 508 amdgpu_ring_write(ring, 1); 509 ret = ring->wptr;/* this is the offset we need patch later */ 510 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ 511 return ret; 512 } 513 514 void patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 515 { 516 unsigned cur; 517 BUG_ON(ring->ring[offset] != 0x55aa55aa); 518 519 cur = ring->wptr - 1; 520 if (likely(cur > offset)) 521 ring->ring[offset] = cur - offset; 522 else 523 ring->ring[offset] = (ring->ring_size>>2) - offset + cur; 524 } 525 526 527 /** 528 * sdma_v3_0_gfx_stop - stop the gfx async dma engines 529 * 530 * @adev: amdgpu_device pointer 531 * 532 * Stop the gfx async dma ring buffers (VI). 533 */ 534 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev) 535 { 536 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 537 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 538 u32 rb_cntl, ib_cntl; 539 int i; 540 541 if ((adev->mman.buffer_funcs_ring == sdma0) || 542 (adev->mman.buffer_funcs_ring == sdma1)) 543 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); 544 545 for (i = 0; i < adev->sdma.num_instances; i++) { 546 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 547 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 548 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 549 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 550 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 551 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 552 } 553 sdma0->ready = false; 554 sdma1->ready = false; 555 } 556 557 /** 558 * sdma_v3_0_rlc_stop - stop the compute async dma engines 559 * 560 * @adev: amdgpu_device pointer 561 * 562 * Stop the compute async dma queues (VI). 563 */ 564 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev) 565 { 566 /* XXX todo */ 567 } 568 569 /** 570 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch 571 * 572 * @adev: amdgpu_device pointer 573 * @enable: enable/disable the DMA MEs context switch. 574 * 575 * Halt or unhalt the async dma engines context switch (VI). 576 */ 577 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 578 { 579 u32 f32_cntl; 580 int i; 581 582 for (i = 0; i < adev->sdma.num_instances; i++) { 583 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); 584 if (enable) 585 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 586 AUTO_CTXSW_ENABLE, 1); 587 else 588 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 589 AUTO_CTXSW_ENABLE, 0); 590 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); 591 } 592 } 593 594 /** 595 * sdma_v3_0_enable - stop the async dma engines 596 * 597 * @adev: amdgpu_device pointer 598 * @enable: enable/disable the DMA MEs. 599 * 600 * Halt or unhalt the async dma engines (VI). 601 */ 602 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable) 603 { 604 u32 f32_cntl; 605 int i; 606 607 if (!enable) { 608 sdma_v3_0_gfx_stop(adev); 609 sdma_v3_0_rlc_stop(adev); 610 } 611 612 for (i = 0; i < adev->sdma.num_instances; i++) { 613 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 614 if (enable) 615 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); 616 else 617 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 618 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); 619 } 620 } 621 622 /** 623 * sdma_v3_0_gfx_resume - setup and start the async dma engines 624 * 625 * @adev: amdgpu_device pointer 626 * 627 * Set up the gfx DMA ring buffers and enable them (VI). 628 * Returns 0 for success, error for failure. 629 */ 630 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) 631 { 632 struct amdgpu_ring *ring; 633 u32 rb_cntl, ib_cntl; 634 u32 rb_bufsz; 635 u32 wb_offset; 636 u32 doorbell; 637 int i, j, r; 638 639 for (i = 0; i < adev->sdma.num_instances; i++) { 640 ring = &adev->sdma.instance[i].ring; 641 wb_offset = (ring->rptr_offs * 4); 642 643 mutex_lock(&adev->srbm_mutex); 644 for (j = 0; j < 16; j++) { 645 vi_srbm_select(adev, 0, 0, 0, j); 646 /* SDMA GFX */ 647 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 648 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 649 } 650 vi_srbm_select(adev, 0, 0, 0, 0); 651 mutex_unlock(&adev->srbm_mutex); 652 653 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], 654 adev->gfx.config.gb_addr_config & 0x70); 655 656 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 657 658 /* Set ring buffer size in dwords */ 659 rb_bufsz = order_base_2(ring->ring_size / 4); 660 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 661 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 662 #ifdef __BIG_ENDIAN 663 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 664 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 665 RPTR_WRITEBACK_SWAP_ENABLE, 1); 666 #endif 667 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 668 669 /* Initialize the ring buffer's read and write pointers */ 670 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 671 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 672 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); 673 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); 674 675 /* set the wb address whether it's enabled or not */ 676 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 677 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 678 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 679 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 680 681 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 682 683 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 684 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 685 686 ring->wptr = 0; 687 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); 688 689 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); 690 691 if (ring->use_doorbell) { 692 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, 693 OFFSET, ring->doorbell_index); 694 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 695 } else { 696 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 697 } 698 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell); 699 700 /* enable DMA RB */ 701 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 702 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 703 704 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 705 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 706 #ifdef __BIG_ENDIAN 707 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 708 #endif 709 /* enable DMA IBs */ 710 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 711 712 ring->ready = true; 713 } 714 715 /* unhalt the MEs */ 716 sdma_v3_0_enable(adev, true); 717 /* enable sdma ring preemption */ 718 sdma_v3_0_ctx_switch_enable(adev, true); 719 720 for (i = 0; i < adev->sdma.num_instances; i++) { 721 ring = &adev->sdma.instance[i].ring; 722 r = amdgpu_ring_test_ring(ring); 723 if (r) { 724 ring->ready = false; 725 return r; 726 } 727 728 if (adev->mman.buffer_funcs_ring == ring) 729 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); 730 } 731 732 return 0; 733 } 734 735 /** 736 * sdma_v3_0_rlc_resume - setup and start the async dma engines 737 * 738 * @adev: amdgpu_device pointer 739 * 740 * Set up the compute DMA queues and enable them (VI). 741 * Returns 0 for success, error for failure. 742 */ 743 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev) 744 { 745 /* XXX todo */ 746 return 0; 747 } 748 749 /** 750 * sdma_v3_0_load_microcode - load the sDMA ME ucode 751 * 752 * @adev: amdgpu_device pointer 753 * 754 * Loads the sDMA0/1 ucode. 755 * Returns 0 for success, -EINVAL if the ucode is not available. 756 */ 757 static int sdma_v3_0_load_microcode(struct amdgpu_device *adev) 758 { 759 const struct sdma_firmware_header_v1_0 *hdr; 760 const __le32 *fw_data; 761 u32 fw_size; 762 int i, j; 763 764 /* halt the MEs */ 765 sdma_v3_0_enable(adev, false); 766 767 for (i = 0; i < adev->sdma.num_instances; i++) { 768 if (!adev->sdma.instance[i].fw) 769 return -EINVAL; 770 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 771 amdgpu_ucode_print_sdma_hdr(&hdr->header); 772 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 773 fw_data = (const __le32 *) 774 (adev->sdma.instance[i].fw->data + 775 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 776 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); 777 for (j = 0; j < fw_size; j++) 778 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); 779 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); 780 } 781 782 return 0; 783 } 784 785 /** 786 * sdma_v3_0_start - setup and start the async dma engines 787 * 788 * @adev: amdgpu_device pointer 789 * 790 * Set up the DMA engines and enable them (VI). 791 * Returns 0 for success, error for failure. 792 */ 793 static int sdma_v3_0_start(struct amdgpu_device *adev) 794 { 795 int r, i; 796 797 if (!adev->pp_enabled) { 798 if (!adev->firmware.smu_load) { 799 r = sdma_v3_0_load_microcode(adev); 800 if (r) 801 return r; 802 } else { 803 for (i = 0; i < adev->sdma.num_instances; i++) { 804 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 805 (i == 0) ? 806 AMDGPU_UCODE_ID_SDMA0 : 807 AMDGPU_UCODE_ID_SDMA1); 808 if (r) 809 return -EINVAL; 810 } 811 } 812 } 813 814 /* disble sdma engine before programing it */ 815 sdma_v3_0_ctx_switch_enable(adev, false); 816 sdma_v3_0_enable(adev, false); 817 818 /* start the gfx rings and rlc compute queues */ 819 r = sdma_v3_0_gfx_resume(adev); 820 if (r) 821 return r; 822 r = sdma_v3_0_rlc_resume(adev); 823 if (r) 824 return r; 825 826 return 0; 827 } 828 829 /** 830 * sdma_v3_0_ring_test_ring - simple async dma engine test 831 * 832 * @ring: amdgpu_ring structure holding ring information 833 * 834 * Test the DMA engine by writing using it to write an 835 * value to memory. (VI). 836 * Returns 0 for success, error for failure. 837 */ 838 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) 839 { 840 struct amdgpu_device *adev = ring->adev; 841 unsigned i; 842 unsigned index; 843 int r; 844 u32 tmp; 845 u64 gpu_addr; 846 847 r = amdgpu_wb_get(adev, &index); 848 if (r) { 849 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 850 return r; 851 } 852 853 gpu_addr = adev->wb.gpu_addr + (index * 4); 854 tmp = 0xCAFEDEAD; 855 adev->wb.wb[index] = cpu_to_le32(tmp); 856 857 r = amdgpu_ring_alloc(ring, 5); 858 if (r) { 859 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 860 amdgpu_wb_free(adev, index); 861 return r; 862 } 863 864 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 865 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 866 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 867 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 868 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 869 amdgpu_ring_write(ring, 0xDEADBEEF); 870 amdgpu_ring_commit(ring); 871 872 for (i = 0; i < adev->usec_timeout; i++) { 873 tmp = le32_to_cpu(adev->wb.wb[index]); 874 if (tmp == 0xDEADBEEF) 875 break; 876 DRM_UDELAY(1); 877 } 878 879 if (i < adev->usec_timeout) { 880 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 881 } else { 882 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 883 ring->idx, tmp); 884 r = -EINVAL; 885 } 886 amdgpu_wb_free(adev, index); 887 888 return r; 889 } 890 891 /** 892 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine 893 * 894 * @ring: amdgpu_ring structure holding ring information 895 * 896 * Test a simple IB in the DMA ring (VI). 897 * Returns 0 on success, error on failure. 898 */ 899 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 900 { 901 struct amdgpu_device *adev = ring->adev; 902 struct amdgpu_ib ib; 903 struct fence *f = NULL; 904 unsigned index; 905 u32 tmp = 0; 906 u64 gpu_addr; 907 long r; 908 909 r = amdgpu_wb_get(adev, &index); 910 if (r) { 911 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 912 return r; 913 } 914 915 gpu_addr = adev->wb.gpu_addr + (index * 4); 916 tmp = 0xCAFEDEAD; 917 adev->wb.wb[index] = cpu_to_le32(tmp); 918 memset(&ib, 0, sizeof(ib)); 919 r = amdgpu_ib_get(adev, NULL, 256, &ib); 920 if (r) { 921 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 922 goto err0; 923 } 924 925 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 926 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 927 ib.ptr[1] = lower_32_bits(gpu_addr); 928 ib.ptr[2] = upper_32_bits(gpu_addr); 929 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); 930 ib.ptr[4] = 0xDEADBEEF; 931 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 932 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 933 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 934 ib.length_dw = 8; 935 936 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f); 937 if (r) 938 goto err1; 939 940 r = fence_wait_timeout(f, false, timeout); 941 if (r == 0) { 942 DRM_ERROR("amdgpu: IB test timed out\n"); 943 r = -ETIMEDOUT; 944 goto err1; 945 } else if (r < 0) { 946 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 947 goto err1; 948 } 949 tmp = le32_to_cpu(adev->wb.wb[index]); 950 if (tmp == 0xDEADBEEF) { 951 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 952 r = 0; 953 } else { 954 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 955 r = -EINVAL; 956 } 957 err1: 958 amdgpu_ib_free(adev, &ib, NULL); 959 fence_put(f); 960 err0: 961 amdgpu_wb_free(adev, index); 962 return r; 963 } 964 965 /** 966 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART 967 * 968 * @ib: indirect buffer to fill with commands 969 * @pe: addr of the page entry 970 * @src: src addr to copy from 971 * @count: number of page entries to update 972 * 973 * Update PTEs by copying them from the GART using sDMA (CIK). 974 */ 975 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib, 976 uint64_t pe, uint64_t src, 977 unsigned count) 978 { 979 while (count) { 980 unsigned bytes = count * 8; 981 if (bytes > 0x1FFFF8) 982 bytes = 0x1FFFF8; 983 984 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 985 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 986 ib->ptr[ib->length_dw++] = bytes; 987 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 988 ib->ptr[ib->length_dw++] = lower_32_bits(src); 989 ib->ptr[ib->length_dw++] = upper_32_bits(src); 990 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 991 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 992 993 pe += bytes; 994 src += bytes; 995 count -= bytes / 8; 996 } 997 } 998 999 /** 1000 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually 1001 * 1002 * @ib: indirect buffer to fill with commands 1003 * @pe: addr of the page entry 1004 * @addr: dst addr to write into pe 1005 * @count: number of page entries to update 1006 * @incr: increase next addr by incr bytes 1007 * @flags: access flags 1008 * 1009 * Update PTEs by writing them manually using sDMA (CIK). 1010 */ 1011 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, 1012 const dma_addr_t *pages_addr, uint64_t pe, 1013 uint64_t addr, unsigned count, 1014 uint32_t incr, uint32_t flags) 1015 { 1016 uint64_t value; 1017 unsigned ndw; 1018 1019 while (count) { 1020 ndw = count * 2; 1021 if (ndw > 0xFFFFE) 1022 ndw = 0xFFFFE; 1023 1024 /* for non-physically contiguous pages (system) */ 1025 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1026 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1027 ib->ptr[ib->length_dw++] = pe; 1028 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1029 ib->ptr[ib->length_dw++] = ndw; 1030 for (; ndw > 0; ndw -= 2, --count, pe += 8) { 1031 value = amdgpu_vm_map_gart(pages_addr, addr); 1032 addr += incr; 1033 value |= flags; 1034 ib->ptr[ib->length_dw++] = value; 1035 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1036 } 1037 } 1038 } 1039 1040 /** 1041 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA 1042 * 1043 * @ib: indirect buffer to fill with commands 1044 * @pe: addr of the page entry 1045 * @addr: dst addr to write into pe 1046 * @count: number of page entries to update 1047 * @incr: increase next addr by incr bytes 1048 * @flags: access flags 1049 * 1050 * Update the page tables using sDMA (CIK). 1051 */ 1052 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1053 uint64_t pe, 1054 uint64_t addr, unsigned count, 1055 uint32_t incr, uint32_t flags) 1056 { 1057 uint64_t value; 1058 unsigned ndw; 1059 1060 while (count) { 1061 ndw = count; 1062 if (ndw > 0x7FFFF) 1063 ndw = 0x7FFFF; 1064 1065 if (flags & AMDGPU_PTE_VALID) 1066 value = addr; 1067 else 1068 value = 0; 1069 1070 /* for physically contiguous pages (vram) */ 1071 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); 1072 ib->ptr[ib->length_dw++] = pe; /* dst addr */ 1073 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1074 ib->ptr[ib->length_dw++] = flags; /* mask */ 1075 ib->ptr[ib->length_dw++] = 0; 1076 ib->ptr[ib->length_dw++] = value; /* value */ 1077 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1078 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1079 ib->ptr[ib->length_dw++] = 0; 1080 ib->ptr[ib->length_dw++] = ndw; /* number of entries */ 1081 1082 pe += ndw * 8; 1083 addr += ndw * incr; 1084 count -= ndw; 1085 } 1086 } 1087 1088 /** 1089 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw 1090 * 1091 * @ib: indirect buffer to fill with padding 1092 * 1093 */ 1094 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1095 { 1096 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 1097 u32 pad_count; 1098 int i; 1099 1100 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 1101 for (i = 0; i < pad_count; i++) 1102 if (sdma && sdma->burst_nop && (i == 0)) 1103 ib->ptr[ib->length_dw++] = 1104 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1105 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1106 else 1107 ib->ptr[ib->length_dw++] = 1108 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1109 } 1110 1111 /** 1112 * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline 1113 * 1114 * @ring: amdgpu_ring pointer 1115 * 1116 * Make sure all previous operations are completed (CIK). 1117 */ 1118 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1119 { 1120 uint32_t seq = ring->fence_drv.sync_seq; 1121 uint64_t addr = ring->fence_drv.gpu_addr; 1122 1123 /* wait for idle */ 1124 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1125 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1126 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1127 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1128 amdgpu_ring_write(ring, addr & 0xfffffffc); 1129 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1130 amdgpu_ring_write(ring, seq); /* reference */ 1131 amdgpu_ring_write(ring, 0xfffffff); /* mask */ 1132 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1133 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1134 } 1135 1136 /** 1137 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA 1138 * 1139 * @ring: amdgpu_ring pointer 1140 * @vm: amdgpu_vm pointer 1141 * 1142 * Update the page table base and flush the VM TLB 1143 * using sDMA (VI). 1144 */ 1145 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1146 unsigned vm_id, uint64_t pd_addr) 1147 { 1148 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1149 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1150 if (vm_id < 8) { 1151 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); 1152 } else { 1153 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); 1154 } 1155 amdgpu_ring_write(ring, pd_addr >> 12); 1156 1157 /* flush TLB */ 1158 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1159 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1160 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 1161 amdgpu_ring_write(ring, 1 << vm_id); 1162 1163 /* wait for flush */ 1164 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1165 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1166 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ 1167 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 1168 amdgpu_ring_write(ring, 0); 1169 amdgpu_ring_write(ring, 0); /* reference */ 1170 amdgpu_ring_write(ring, 0); /* mask */ 1171 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1172 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 1173 } 1174 1175 static int sdma_v3_0_early_init(void *handle) 1176 { 1177 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1178 1179 switch (adev->asic_type) { 1180 case CHIP_STONEY: 1181 adev->sdma.num_instances = 1; 1182 break; 1183 default: 1184 adev->sdma.num_instances = SDMA_MAX_INSTANCE; 1185 break; 1186 } 1187 1188 sdma_v3_0_set_ring_funcs(adev); 1189 sdma_v3_0_set_buffer_funcs(adev); 1190 sdma_v3_0_set_vm_pte_funcs(adev); 1191 sdma_v3_0_set_irq_funcs(adev); 1192 1193 return 0; 1194 } 1195 1196 static int sdma_v3_0_sw_init(void *handle) 1197 { 1198 struct amdgpu_ring *ring; 1199 int r, i; 1200 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1201 1202 /* SDMA trap event */ 1203 r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq); 1204 if (r) 1205 return r; 1206 1207 /* SDMA Privileged inst */ 1208 r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq); 1209 if (r) 1210 return r; 1211 1212 /* SDMA Privileged inst */ 1213 r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq); 1214 if (r) 1215 return r; 1216 1217 r = sdma_v3_0_init_microcode(adev); 1218 if (r) { 1219 DRM_ERROR("Failed to load sdma firmware!\n"); 1220 return r; 1221 } 1222 1223 for (i = 0; i < adev->sdma.num_instances; i++) { 1224 ring = &adev->sdma.instance[i].ring; 1225 ring->ring_obj = NULL; 1226 ring->use_doorbell = true; 1227 ring->doorbell_index = (i == 0) ? 1228 AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1; 1229 1230 sprintf(ring->name, "sdma%d", i); 1231 r = amdgpu_ring_init(adev, ring, 1024, 1232 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, 1233 &adev->sdma.trap_irq, 1234 (i == 0) ? 1235 AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1, 1236 AMDGPU_RING_TYPE_SDMA); 1237 if (r) 1238 return r; 1239 } 1240 1241 return r; 1242 } 1243 1244 static int sdma_v3_0_sw_fini(void *handle) 1245 { 1246 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1247 int i; 1248 1249 for (i = 0; i < adev->sdma.num_instances; i++) 1250 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1251 1252 sdma_v3_0_free_microcode(adev); 1253 return 0; 1254 } 1255 1256 static int sdma_v3_0_hw_init(void *handle) 1257 { 1258 int r; 1259 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1260 1261 sdma_v3_0_init_golden_registers(adev); 1262 1263 r = sdma_v3_0_start(adev); 1264 if (r) 1265 return r; 1266 1267 return r; 1268 } 1269 1270 static int sdma_v3_0_hw_fini(void *handle) 1271 { 1272 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1273 1274 sdma_v3_0_ctx_switch_enable(adev, false); 1275 sdma_v3_0_enable(adev, false); 1276 1277 return 0; 1278 } 1279 1280 static int sdma_v3_0_suspend(void *handle) 1281 { 1282 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1283 1284 return sdma_v3_0_hw_fini(adev); 1285 } 1286 1287 static int sdma_v3_0_resume(void *handle) 1288 { 1289 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1290 1291 return sdma_v3_0_hw_init(adev); 1292 } 1293 1294 static bool sdma_v3_0_is_idle(void *handle) 1295 { 1296 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1297 u32 tmp = RREG32(mmSRBM_STATUS2); 1298 1299 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1300 SRBM_STATUS2__SDMA1_BUSY_MASK)) 1301 return false; 1302 1303 return true; 1304 } 1305 1306 static int sdma_v3_0_wait_for_idle(void *handle) 1307 { 1308 unsigned i; 1309 u32 tmp; 1310 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1311 1312 for (i = 0; i < adev->usec_timeout; i++) { 1313 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1314 SRBM_STATUS2__SDMA1_BUSY_MASK); 1315 1316 if (!tmp) 1317 return 0; 1318 udelay(1); 1319 } 1320 return -ETIMEDOUT; 1321 } 1322 1323 static int sdma_v3_0_soft_reset(void *handle) 1324 { 1325 u32 srbm_soft_reset = 0; 1326 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1327 u32 tmp = RREG32(mmSRBM_STATUS2); 1328 1329 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { 1330 /* sdma0 */ 1331 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); 1332 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); 1333 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); 1334 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1335 } 1336 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) { 1337 /* sdma1 */ 1338 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); 1339 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); 1340 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); 1341 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1342 } 1343 1344 if (srbm_soft_reset) { 1345 tmp = RREG32(mmSRBM_SOFT_RESET); 1346 tmp |= srbm_soft_reset; 1347 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1348 WREG32(mmSRBM_SOFT_RESET, tmp); 1349 tmp = RREG32(mmSRBM_SOFT_RESET); 1350 1351 udelay(50); 1352 1353 tmp &= ~srbm_soft_reset; 1354 WREG32(mmSRBM_SOFT_RESET, tmp); 1355 tmp = RREG32(mmSRBM_SOFT_RESET); 1356 1357 /* Wait a little for things to settle down */ 1358 udelay(50); 1359 } 1360 1361 return 0; 1362 } 1363 1364 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev, 1365 struct amdgpu_irq_src *source, 1366 unsigned type, 1367 enum amdgpu_interrupt_state state) 1368 { 1369 u32 sdma_cntl; 1370 1371 switch (type) { 1372 case AMDGPU_SDMA_IRQ_TRAP0: 1373 switch (state) { 1374 case AMDGPU_IRQ_STATE_DISABLE: 1375 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1376 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1377 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1378 break; 1379 case AMDGPU_IRQ_STATE_ENABLE: 1380 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1381 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1382 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1383 break; 1384 default: 1385 break; 1386 } 1387 break; 1388 case AMDGPU_SDMA_IRQ_TRAP1: 1389 switch (state) { 1390 case AMDGPU_IRQ_STATE_DISABLE: 1391 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1392 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1393 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1394 break; 1395 case AMDGPU_IRQ_STATE_ENABLE: 1396 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1397 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1398 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1399 break; 1400 default: 1401 break; 1402 } 1403 break; 1404 default: 1405 break; 1406 } 1407 return 0; 1408 } 1409 1410 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev, 1411 struct amdgpu_irq_src *source, 1412 struct amdgpu_iv_entry *entry) 1413 { 1414 u8 instance_id, queue_id; 1415 1416 instance_id = (entry->ring_id & 0x3) >> 0; 1417 queue_id = (entry->ring_id & 0xc) >> 2; 1418 DRM_DEBUG("IH: SDMA trap\n"); 1419 switch (instance_id) { 1420 case 0: 1421 switch (queue_id) { 1422 case 0: 1423 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1424 break; 1425 case 1: 1426 /* XXX compute */ 1427 break; 1428 case 2: 1429 /* XXX compute */ 1430 break; 1431 } 1432 break; 1433 case 1: 1434 switch (queue_id) { 1435 case 0: 1436 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1437 break; 1438 case 1: 1439 /* XXX compute */ 1440 break; 1441 case 2: 1442 /* XXX compute */ 1443 break; 1444 } 1445 break; 1446 } 1447 return 0; 1448 } 1449 1450 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1451 struct amdgpu_irq_src *source, 1452 struct amdgpu_iv_entry *entry) 1453 { 1454 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1455 schedule_work(&adev->reset_work); 1456 return 0; 1457 } 1458 1459 static void sdma_v3_0_update_sdma_medium_grain_clock_gating( 1460 struct amdgpu_device *adev, 1461 bool enable) 1462 { 1463 uint32_t temp, data; 1464 int i; 1465 1466 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1467 for (i = 0; i < adev->sdma.num_instances; i++) { 1468 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); 1469 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1470 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1471 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1472 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1473 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1474 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1475 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1476 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1477 if (data != temp) 1478 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); 1479 } 1480 } else { 1481 for (i = 0; i < adev->sdma.num_instances; i++) { 1482 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); 1483 data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1484 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1485 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1486 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1487 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1488 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1489 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1490 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK; 1491 1492 if (data != temp) 1493 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); 1494 } 1495 } 1496 } 1497 1498 static void sdma_v3_0_update_sdma_medium_grain_light_sleep( 1499 struct amdgpu_device *adev, 1500 bool enable) 1501 { 1502 uint32_t temp, data; 1503 int i; 1504 1505 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1506 for (i = 0; i < adev->sdma.num_instances; i++) { 1507 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1508 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1509 1510 if (temp != data) 1511 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1512 } 1513 } else { 1514 for (i = 0; i < adev->sdma.num_instances; i++) { 1515 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1516 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1517 1518 if (temp != data) 1519 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1520 } 1521 } 1522 } 1523 1524 static int sdma_v3_0_set_clockgating_state(void *handle, 1525 enum amd_clockgating_state state) 1526 { 1527 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1528 1529 switch (adev->asic_type) { 1530 case CHIP_FIJI: 1531 case CHIP_CARRIZO: 1532 case CHIP_STONEY: 1533 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev, 1534 state == AMD_CG_STATE_GATE ? true : false); 1535 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev, 1536 state == AMD_CG_STATE_GATE ? true : false); 1537 break; 1538 default: 1539 break; 1540 } 1541 return 0; 1542 } 1543 1544 static int sdma_v3_0_set_powergating_state(void *handle, 1545 enum amd_powergating_state state) 1546 { 1547 return 0; 1548 } 1549 1550 const struct amd_ip_funcs sdma_v3_0_ip_funcs = { 1551 .name = "sdma_v3_0", 1552 .early_init = sdma_v3_0_early_init, 1553 .late_init = NULL, 1554 .sw_init = sdma_v3_0_sw_init, 1555 .sw_fini = sdma_v3_0_sw_fini, 1556 .hw_init = sdma_v3_0_hw_init, 1557 .hw_fini = sdma_v3_0_hw_fini, 1558 .suspend = sdma_v3_0_suspend, 1559 .resume = sdma_v3_0_resume, 1560 .is_idle = sdma_v3_0_is_idle, 1561 .wait_for_idle = sdma_v3_0_wait_for_idle, 1562 .soft_reset = sdma_v3_0_soft_reset, 1563 .set_clockgating_state = sdma_v3_0_set_clockgating_state, 1564 .set_powergating_state = sdma_v3_0_set_powergating_state, 1565 }; 1566 1567 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { 1568 .get_rptr = sdma_v3_0_ring_get_rptr, 1569 .get_wptr = sdma_v3_0_ring_get_wptr, 1570 .set_wptr = sdma_v3_0_ring_set_wptr, 1571 .parse_cs = NULL, 1572 .emit_ib = sdma_v3_0_ring_emit_ib, 1573 .emit_fence = sdma_v3_0_ring_emit_fence, 1574 .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync, 1575 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, 1576 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, 1577 .emit_hdp_invalidate = sdma_v3_0_ring_emit_hdp_invalidate, 1578 .test_ring = sdma_v3_0_ring_test_ring, 1579 .test_ib = sdma_v3_0_ring_test_ib, 1580 .insert_nop = sdma_v3_0_ring_insert_nop, 1581 .pad_ib = sdma_v3_0_ring_pad_ib, 1582 }; 1583 1584 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev) 1585 { 1586 int i; 1587 1588 for (i = 0; i < adev->sdma.num_instances; i++) 1589 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs; 1590 } 1591 1592 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = { 1593 .set = sdma_v3_0_set_trap_irq_state, 1594 .process = sdma_v3_0_process_trap_irq, 1595 }; 1596 1597 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = { 1598 .process = sdma_v3_0_process_illegal_inst_irq, 1599 }; 1600 1601 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev) 1602 { 1603 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1604 adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs; 1605 adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs; 1606 } 1607 1608 /** 1609 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine 1610 * 1611 * @ring: amdgpu_ring structure holding ring information 1612 * @src_offset: src GPU address 1613 * @dst_offset: dst GPU address 1614 * @byte_count: number of bytes to xfer 1615 * 1616 * Copy GPU buffers using the DMA engine (VI). 1617 * Used by the amdgpu ttm implementation to move pages if 1618 * registered as the asic copy callback. 1619 */ 1620 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib, 1621 uint64_t src_offset, 1622 uint64_t dst_offset, 1623 uint32_t byte_count) 1624 { 1625 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1626 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1627 ib->ptr[ib->length_dw++] = byte_count; 1628 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1629 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1630 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1631 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1632 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1633 } 1634 1635 /** 1636 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine 1637 * 1638 * @ring: amdgpu_ring structure holding ring information 1639 * @src_data: value to write to buffer 1640 * @dst_offset: dst GPU address 1641 * @byte_count: number of bytes to xfer 1642 * 1643 * Fill GPU buffers using the DMA engine (VI). 1644 */ 1645 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib, 1646 uint32_t src_data, 1647 uint64_t dst_offset, 1648 uint32_t byte_count) 1649 { 1650 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1651 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1652 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1653 ib->ptr[ib->length_dw++] = src_data; 1654 ib->ptr[ib->length_dw++] = byte_count; 1655 } 1656 1657 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = { 1658 .copy_max_bytes = 0x1fffff, 1659 .copy_num_dw = 7, 1660 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer, 1661 1662 .fill_max_bytes = 0x1fffff, 1663 .fill_num_dw = 5, 1664 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer, 1665 }; 1666 1667 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) 1668 { 1669 if (adev->mman.buffer_funcs == NULL) { 1670 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs; 1671 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1672 } 1673 } 1674 1675 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { 1676 .copy_pte = sdma_v3_0_vm_copy_pte, 1677 .write_pte = sdma_v3_0_vm_write_pte, 1678 .set_pte_pde = sdma_v3_0_vm_set_pte_pde, 1679 }; 1680 1681 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1682 { 1683 unsigned i; 1684 1685 if (adev->vm_manager.vm_pte_funcs == NULL) { 1686 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; 1687 for (i = 0; i < adev->sdma.num_instances; i++) 1688 adev->vm_manager.vm_pte_rings[i] = 1689 &adev->sdma.instance[i].ring; 1690 1691 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; 1692 } 1693 } 1694