1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 #include "vi.h" 30 #include "vid.h" 31 32 #include "oss/oss_3_0_d.h" 33 #include "oss/oss_3_0_sh_mask.h" 34 35 #include "gmc/gmc_8_1_d.h" 36 #include "gmc/gmc_8_1_sh_mask.h" 37 38 #include "gca/gfx_8_0_d.h" 39 #include "gca/gfx_8_0_enum.h" 40 #include "gca/gfx_8_0_sh_mask.h" 41 42 #include "bif/bif_5_0_d.h" 43 #include "bif/bif_5_0_sh_mask.h" 44 45 #include "tonga_sdma_pkt_open.h" 46 47 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev); 48 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); 49 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev); 50 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); 51 52 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); 53 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin"); 54 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin"); 55 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); 56 57 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 58 { 59 SDMA0_REGISTER_OFFSET, 60 SDMA1_REGISTER_OFFSET 61 }; 62 63 static const u32 golden_settings_tonga_a11[] = 64 { 65 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 66 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 67 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, 68 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 69 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 70 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 71 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 72 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, 73 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, 74 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, 75 }; 76 77 static const u32 tonga_mgcg_cgcg_init[] = 78 { 79 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 80 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 81 }; 82 83 static const u32 cz_golden_settings_a11[] = 84 { 85 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 86 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 87 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, 88 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 89 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, 90 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, 91 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 92 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 93 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100, 94 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800, 95 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100, 96 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100, 97 }; 98 99 static const u32 cz_mgcg_cgcg_init[] = 100 { 101 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 102 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 103 }; 104 105 /* 106 * sDMA - System DMA 107 * Starting with CIK, the GPU has new asynchronous 108 * DMA engines. These engines are used for compute 109 * and gfx. There are two DMA engines (SDMA0, SDMA1) 110 * and each one supports 1 ring buffer used for gfx 111 * and 2 queues used for compute. 112 * 113 * The programming model is very similar to the CP 114 * (ring buffer, IBs, etc.), but sDMA has it's own 115 * packet format that is different from the PM4 format 116 * used by the CP. sDMA supports copying data, writing 117 * embedded data, solid fills, and a number of other 118 * things. It also has support for tiling/detiling of 119 * buffers. 120 */ 121 122 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) 123 { 124 switch (adev->asic_type) { 125 case CHIP_TONGA: 126 amdgpu_program_register_sequence(adev, 127 tonga_mgcg_cgcg_init, 128 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); 129 amdgpu_program_register_sequence(adev, 130 golden_settings_tonga_a11, 131 (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); 132 break; 133 case CHIP_CARRIZO: 134 amdgpu_program_register_sequence(adev, 135 cz_mgcg_cgcg_init, 136 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 137 amdgpu_program_register_sequence(adev, 138 cz_golden_settings_a11, 139 (const u32)ARRAY_SIZE(cz_golden_settings_a11)); 140 break; 141 default: 142 break; 143 } 144 } 145 146 /** 147 * sdma_v3_0_init_microcode - load ucode images from disk 148 * 149 * @adev: amdgpu_device pointer 150 * 151 * Use the firmware interface to load the ucode images into 152 * the driver (not loaded into hw). 153 * Returns 0 on success, error on failure. 154 */ 155 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) 156 { 157 const char *chip_name; 158 char fw_name[30]; 159 int err, i; 160 struct amdgpu_firmware_info *info = NULL; 161 const struct common_firmware_header *header = NULL; 162 163 DRM_DEBUG("\n"); 164 165 switch (adev->asic_type) { 166 case CHIP_TONGA: 167 chip_name = "tonga"; 168 break; 169 case CHIP_CARRIZO: 170 chip_name = "carrizo"; 171 break; 172 default: BUG(); 173 } 174 175 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 176 if (i == 0) 177 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 178 else 179 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 180 err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev); 181 if (err) 182 goto out; 183 err = amdgpu_ucode_validate(adev->sdma[i].fw); 184 if (err) 185 goto out; 186 187 if (adev->firmware.smu_load) { 188 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 189 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 190 info->fw = adev->sdma[i].fw; 191 header = (const struct common_firmware_header *)info->fw->data; 192 adev->firmware.fw_size += 193 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 194 } 195 } 196 out: 197 if (err) { 198 printk(KERN_ERR 199 "sdma_v3_0: Failed to load firmware \"%s\"\n", 200 fw_name); 201 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 202 release_firmware(adev->sdma[i].fw); 203 adev->sdma[i].fw = NULL; 204 } 205 } 206 return err; 207 } 208 209 /** 210 * sdma_v3_0_ring_get_rptr - get the current read pointer 211 * 212 * @ring: amdgpu ring pointer 213 * 214 * Get the current rptr from the hardware (VI+). 215 */ 216 static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring) 217 { 218 u32 rptr; 219 220 /* XXX check if swapping is necessary on BE */ 221 rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2; 222 223 return rptr; 224 } 225 226 /** 227 * sdma_v3_0_ring_get_wptr - get the current write pointer 228 * 229 * @ring: amdgpu ring pointer 230 * 231 * Get the current wptr from the hardware (VI+). 232 */ 233 static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring) 234 { 235 struct amdgpu_device *adev = ring->adev; 236 u32 wptr; 237 238 if (ring->use_doorbell) { 239 /* XXX check if swapping is necessary on BE */ 240 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; 241 } else { 242 int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1; 243 244 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2; 245 } 246 247 return wptr; 248 } 249 250 /** 251 * sdma_v3_0_ring_set_wptr - commit the write pointer 252 * 253 * @ring: amdgpu ring pointer 254 * 255 * Write the wptr back to the hardware (VI+). 256 */ 257 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) 258 { 259 struct amdgpu_device *adev = ring->adev; 260 261 if (ring->use_doorbell) { 262 /* XXX check if swapping is necessary on BE */ 263 adev->wb.wb[ring->wptr_offs] = ring->wptr << 2; 264 WDOORBELL32(ring->doorbell_index, ring->wptr << 2); 265 } else { 266 int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1; 267 268 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2); 269 } 270 } 271 272 /** 273 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine 274 * 275 * @ring: amdgpu ring pointer 276 * @ib: IB object to schedule 277 * 278 * Schedule an IB in the DMA ring (VI). 279 */ 280 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, 281 struct amdgpu_ib *ib) 282 { 283 u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf; 284 u32 next_rptr = ring->wptr + 5; 285 286 while ((next_rptr & 7) != 2) 287 next_rptr++; 288 next_rptr += 6; 289 290 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 291 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 292 amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc); 293 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); 294 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 295 amdgpu_ring_write(ring, next_rptr); 296 297 /* IB packet must end on a 8 DW boundary */ 298 while ((ring->wptr & 7) != 2) 299 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_NOP)); 300 301 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 302 SDMA_PKT_INDIRECT_HEADER_VMID(vmid)); 303 /* base must be 32 byte aligned */ 304 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 305 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 306 amdgpu_ring_write(ring, ib->length_dw); 307 amdgpu_ring_write(ring, 0); 308 amdgpu_ring_write(ring, 0); 309 310 } 311 312 /** 313 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 314 * 315 * @ring: amdgpu ring pointer 316 * 317 * Emit an hdp flush packet on the requested DMA ring. 318 */ 319 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 320 { 321 u32 ref_and_mask = 0; 322 323 if (ring == &ring->adev->sdma[0].ring) 324 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); 325 else 326 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); 327 328 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 329 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 330 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 331 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 332 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 333 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 334 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 335 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 336 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 337 } 338 339 /** 340 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring 341 * 342 * @ring: amdgpu ring pointer 343 * @fence: amdgpu fence object 344 * 345 * Add a DMA fence packet to the ring to write 346 * the fence seq number and DMA trap packet to generate 347 * an interrupt if needed (VI). 348 */ 349 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 350 unsigned flags) 351 { 352 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 353 /* write the fence */ 354 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 355 amdgpu_ring_write(ring, lower_32_bits(addr)); 356 amdgpu_ring_write(ring, upper_32_bits(addr)); 357 amdgpu_ring_write(ring, lower_32_bits(seq)); 358 359 /* optionally write high bits as well */ 360 if (write64bit) { 361 addr += 4; 362 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 363 amdgpu_ring_write(ring, lower_32_bits(addr)); 364 amdgpu_ring_write(ring, upper_32_bits(addr)); 365 amdgpu_ring_write(ring, upper_32_bits(seq)); 366 } 367 368 /* generate an interrupt */ 369 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 370 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 371 } 372 373 374 /** 375 * sdma_v3_0_ring_emit_semaphore - emit a semaphore on the dma ring 376 * 377 * @ring: amdgpu_ring structure holding ring information 378 * @semaphore: amdgpu semaphore object 379 * @emit_wait: wait or signal semaphore 380 * 381 * Add a DMA semaphore packet to the ring wait on or signal 382 * other rings (VI). 383 */ 384 static bool sdma_v3_0_ring_emit_semaphore(struct amdgpu_ring *ring, 385 struct amdgpu_semaphore *semaphore, 386 bool emit_wait) 387 { 388 u64 addr = semaphore->gpu_addr; 389 u32 sig = emit_wait ? 0 : 1; 390 391 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) | 392 SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig)); 393 amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8); 394 amdgpu_ring_write(ring, upper_32_bits(addr)); 395 396 return true; 397 } 398 399 /** 400 * sdma_v3_0_gfx_stop - stop the gfx async dma engines 401 * 402 * @adev: amdgpu_device pointer 403 * 404 * Stop the gfx async dma ring buffers (VI). 405 */ 406 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev) 407 { 408 struct amdgpu_ring *sdma0 = &adev->sdma[0].ring; 409 struct amdgpu_ring *sdma1 = &adev->sdma[1].ring; 410 u32 rb_cntl, ib_cntl; 411 int i; 412 413 if ((adev->mman.buffer_funcs_ring == sdma0) || 414 (adev->mman.buffer_funcs_ring == sdma1)) 415 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); 416 417 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 418 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 419 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 420 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 421 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 422 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 423 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 424 } 425 sdma0->ready = false; 426 sdma1->ready = false; 427 } 428 429 /** 430 * sdma_v3_0_rlc_stop - stop the compute async dma engines 431 * 432 * @adev: amdgpu_device pointer 433 * 434 * Stop the compute async dma queues (VI). 435 */ 436 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev) 437 { 438 /* XXX todo */ 439 } 440 441 /** 442 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch 443 * 444 * @adev: amdgpu_device pointer 445 * @enable: enable/disable the DMA MEs context switch. 446 * 447 * Halt or unhalt the async dma engines context switch (VI). 448 */ 449 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 450 { 451 u32 f32_cntl; 452 int i; 453 454 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 455 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); 456 if (enable) 457 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 458 AUTO_CTXSW_ENABLE, 1); 459 else 460 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 461 AUTO_CTXSW_ENABLE, 0); 462 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); 463 } 464 } 465 466 /** 467 * sdma_v3_0_enable - stop the async dma engines 468 * 469 * @adev: amdgpu_device pointer 470 * @enable: enable/disable the DMA MEs. 471 * 472 * Halt or unhalt the async dma engines (VI). 473 */ 474 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable) 475 { 476 u32 f32_cntl; 477 int i; 478 479 if (enable == false) { 480 sdma_v3_0_gfx_stop(adev); 481 sdma_v3_0_rlc_stop(adev); 482 } 483 484 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 485 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 486 if (enable) 487 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); 488 else 489 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 490 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); 491 } 492 } 493 494 /** 495 * sdma_v3_0_gfx_resume - setup and start the async dma engines 496 * 497 * @adev: amdgpu_device pointer 498 * 499 * Set up the gfx DMA ring buffers and enable them (VI). 500 * Returns 0 for success, error for failure. 501 */ 502 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) 503 { 504 struct amdgpu_ring *ring; 505 u32 rb_cntl, ib_cntl; 506 u32 rb_bufsz; 507 u32 wb_offset; 508 u32 doorbell; 509 int i, j, r; 510 511 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 512 ring = &adev->sdma[i].ring; 513 wb_offset = (ring->rptr_offs * 4); 514 515 mutex_lock(&adev->srbm_mutex); 516 for (j = 0; j < 16; j++) { 517 vi_srbm_select(adev, 0, 0, 0, j); 518 /* SDMA GFX */ 519 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 520 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 521 } 522 vi_srbm_select(adev, 0, 0, 0, 0); 523 mutex_unlock(&adev->srbm_mutex); 524 525 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 526 527 /* Set ring buffer size in dwords */ 528 rb_bufsz = order_base_2(ring->ring_size / 4); 529 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 530 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 531 #ifdef __BIG_ENDIAN 532 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 533 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 534 RPTR_WRITEBACK_SWAP_ENABLE, 1); 535 #endif 536 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 537 538 /* Initialize the ring buffer's read and write pointers */ 539 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 540 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 541 542 /* set the wb address whether it's enabled or not */ 543 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 544 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 545 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 546 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 547 548 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 549 550 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 551 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 552 553 ring->wptr = 0; 554 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); 555 556 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); 557 558 if (ring->use_doorbell) { 559 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, 560 OFFSET, ring->doorbell_index); 561 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 562 } else { 563 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 564 } 565 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell); 566 567 /* enable DMA RB */ 568 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 569 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 570 571 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 572 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 573 #ifdef __BIG_ENDIAN 574 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 575 #endif 576 /* enable DMA IBs */ 577 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 578 579 ring->ready = true; 580 581 r = amdgpu_ring_test_ring(ring); 582 if (r) { 583 ring->ready = false; 584 return r; 585 } 586 587 if (adev->mman.buffer_funcs_ring == ring) 588 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); 589 } 590 591 return 0; 592 } 593 594 /** 595 * sdma_v3_0_rlc_resume - setup and start the async dma engines 596 * 597 * @adev: amdgpu_device pointer 598 * 599 * Set up the compute DMA queues and enable them (VI). 600 * Returns 0 for success, error for failure. 601 */ 602 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev) 603 { 604 /* XXX todo */ 605 return 0; 606 } 607 608 /** 609 * sdma_v3_0_load_microcode - load the sDMA ME ucode 610 * 611 * @adev: amdgpu_device pointer 612 * 613 * Loads the sDMA0/1 ucode. 614 * Returns 0 for success, -EINVAL if the ucode is not available. 615 */ 616 static int sdma_v3_0_load_microcode(struct amdgpu_device *adev) 617 { 618 const struct sdma_firmware_header_v1_0 *hdr; 619 const __le32 *fw_data; 620 u32 fw_size; 621 int i, j; 622 623 if (!adev->sdma[0].fw || !adev->sdma[1].fw) 624 return -EINVAL; 625 626 /* halt the MEs */ 627 sdma_v3_0_enable(adev, false); 628 629 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 630 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data; 631 amdgpu_ucode_print_sdma_hdr(&hdr->header); 632 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 633 adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 634 635 fw_data = (const __le32 *) 636 (adev->sdma[i].fw->data + 637 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 638 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); 639 for (j = 0; j < fw_size; j++) 640 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); 641 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version); 642 } 643 644 return 0; 645 } 646 647 /** 648 * sdma_v3_0_start - setup and start the async dma engines 649 * 650 * @adev: amdgpu_device pointer 651 * 652 * Set up the DMA engines and enable them (VI). 653 * Returns 0 for success, error for failure. 654 */ 655 static int sdma_v3_0_start(struct amdgpu_device *adev) 656 { 657 int r; 658 659 if (!adev->firmware.smu_load) { 660 r = sdma_v3_0_load_microcode(adev); 661 if (r) 662 return r; 663 } else { 664 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 665 AMDGPU_UCODE_ID_SDMA0); 666 if (r) 667 return -EINVAL; 668 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 669 AMDGPU_UCODE_ID_SDMA1); 670 if (r) 671 return -EINVAL; 672 } 673 674 /* unhalt the MEs */ 675 sdma_v3_0_enable(adev, true); 676 /* enable sdma ring preemption */ 677 sdma_v3_0_ctx_switch_enable(adev, true); 678 679 /* start the gfx rings and rlc compute queues */ 680 r = sdma_v3_0_gfx_resume(adev); 681 if (r) 682 return r; 683 r = sdma_v3_0_rlc_resume(adev); 684 if (r) 685 return r; 686 687 return 0; 688 } 689 690 /** 691 * sdma_v3_0_ring_test_ring - simple async dma engine test 692 * 693 * @ring: amdgpu_ring structure holding ring information 694 * 695 * Test the DMA engine by writing using it to write an 696 * value to memory. (VI). 697 * Returns 0 for success, error for failure. 698 */ 699 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) 700 { 701 struct amdgpu_device *adev = ring->adev; 702 unsigned i; 703 unsigned index; 704 int r; 705 u32 tmp; 706 u64 gpu_addr; 707 708 r = amdgpu_wb_get(adev, &index); 709 if (r) { 710 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 711 return r; 712 } 713 714 gpu_addr = adev->wb.gpu_addr + (index * 4); 715 tmp = 0xCAFEDEAD; 716 adev->wb.wb[index] = cpu_to_le32(tmp); 717 718 r = amdgpu_ring_lock(ring, 5); 719 if (r) { 720 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 721 amdgpu_wb_free(adev, index); 722 return r; 723 } 724 725 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 726 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 727 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 728 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 729 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 730 amdgpu_ring_write(ring, 0xDEADBEEF); 731 amdgpu_ring_unlock_commit(ring); 732 733 for (i = 0; i < adev->usec_timeout; i++) { 734 tmp = le32_to_cpu(adev->wb.wb[index]); 735 if (tmp == 0xDEADBEEF) 736 break; 737 DRM_UDELAY(1); 738 } 739 740 if (i < adev->usec_timeout) { 741 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 742 } else { 743 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 744 ring->idx, tmp); 745 r = -EINVAL; 746 } 747 amdgpu_wb_free(adev, index); 748 749 return r; 750 } 751 752 /** 753 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine 754 * 755 * @ring: amdgpu_ring structure holding ring information 756 * 757 * Test a simple IB in the DMA ring (VI). 758 * Returns 0 on success, error on failure. 759 */ 760 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring) 761 { 762 struct amdgpu_device *adev = ring->adev; 763 struct amdgpu_ib ib; 764 unsigned i; 765 unsigned index; 766 int r; 767 u32 tmp = 0; 768 u64 gpu_addr; 769 770 r = amdgpu_wb_get(adev, &index); 771 if (r) { 772 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 773 return r; 774 } 775 776 gpu_addr = adev->wb.gpu_addr + (index * 4); 777 tmp = 0xCAFEDEAD; 778 adev->wb.wb[index] = cpu_to_le32(tmp); 779 780 r = amdgpu_ib_get(ring, NULL, 256, &ib); 781 if (r) { 782 amdgpu_wb_free(adev, index); 783 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); 784 return r; 785 } 786 787 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 788 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 789 ib.ptr[1] = lower_32_bits(gpu_addr); 790 ib.ptr[2] = upper_32_bits(gpu_addr); 791 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); 792 ib.ptr[4] = 0xDEADBEEF; 793 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 794 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 795 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 796 ib.length_dw = 8; 797 798 r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED); 799 if (r) { 800 amdgpu_ib_free(adev, &ib); 801 amdgpu_wb_free(adev, index); 802 DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r); 803 return r; 804 } 805 r = amdgpu_fence_wait(ib.fence, false); 806 if (r) { 807 amdgpu_ib_free(adev, &ib); 808 amdgpu_wb_free(adev, index); 809 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 810 return r; 811 } 812 for (i = 0; i < adev->usec_timeout; i++) { 813 tmp = le32_to_cpu(adev->wb.wb[index]); 814 if (tmp == 0xDEADBEEF) 815 break; 816 DRM_UDELAY(1); 817 } 818 if (i < adev->usec_timeout) { 819 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", 820 ib.fence->ring->idx, i); 821 } else { 822 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 823 r = -EINVAL; 824 } 825 amdgpu_ib_free(adev, &ib); 826 amdgpu_wb_free(adev, index); 827 return r; 828 } 829 830 /** 831 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART 832 * 833 * @ib: indirect buffer to fill with commands 834 * @pe: addr of the page entry 835 * @src: src addr to copy from 836 * @count: number of page entries to update 837 * 838 * Update PTEs by copying them from the GART using sDMA (CIK). 839 */ 840 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib, 841 uint64_t pe, uint64_t src, 842 unsigned count) 843 { 844 while (count) { 845 unsigned bytes = count * 8; 846 if (bytes > 0x1FFFF8) 847 bytes = 0x1FFFF8; 848 849 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 850 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 851 ib->ptr[ib->length_dw++] = bytes; 852 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 853 ib->ptr[ib->length_dw++] = lower_32_bits(src); 854 ib->ptr[ib->length_dw++] = upper_32_bits(src); 855 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 856 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 857 858 pe += bytes; 859 src += bytes; 860 count -= bytes / 8; 861 } 862 } 863 864 /** 865 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually 866 * 867 * @ib: indirect buffer to fill with commands 868 * @pe: addr of the page entry 869 * @addr: dst addr to write into pe 870 * @count: number of page entries to update 871 * @incr: increase next addr by incr bytes 872 * @flags: access flags 873 * 874 * Update PTEs by writing them manually using sDMA (CIK). 875 */ 876 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, 877 uint64_t pe, 878 uint64_t addr, unsigned count, 879 uint32_t incr, uint32_t flags) 880 { 881 uint64_t value; 882 unsigned ndw; 883 884 while (count) { 885 ndw = count * 2; 886 if (ndw > 0xFFFFE) 887 ndw = 0xFFFFE; 888 889 /* for non-physically contiguous pages (system) */ 890 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 891 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 892 ib->ptr[ib->length_dw++] = pe; 893 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 894 ib->ptr[ib->length_dw++] = ndw; 895 for (; ndw > 0; ndw -= 2, --count, pe += 8) { 896 if (flags & AMDGPU_PTE_SYSTEM) { 897 value = amdgpu_vm_map_gart(ib->ring->adev, addr); 898 value &= 0xFFFFFFFFFFFFF000ULL; 899 } else if (flags & AMDGPU_PTE_VALID) { 900 value = addr; 901 } else { 902 value = 0; 903 } 904 addr += incr; 905 value |= flags; 906 ib->ptr[ib->length_dw++] = value; 907 ib->ptr[ib->length_dw++] = upper_32_bits(value); 908 } 909 } 910 } 911 912 /** 913 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA 914 * 915 * @ib: indirect buffer to fill with commands 916 * @pe: addr of the page entry 917 * @addr: dst addr to write into pe 918 * @count: number of page entries to update 919 * @incr: increase next addr by incr bytes 920 * @flags: access flags 921 * 922 * Update the page tables using sDMA (CIK). 923 */ 924 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, 925 uint64_t pe, 926 uint64_t addr, unsigned count, 927 uint32_t incr, uint32_t flags) 928 { 929 uint64_t value; 930 unsigned ndw; 931 932 while (count) { 933 ndw = count; 934 if (ndw > 0x7FFFF) 935 ndw = 0x7FFFF; 936 937 if (flags & AMDGPU_PTE_VALID) 938 value = addr; 939 else 940 value = 0; 941 942 /* for physically contiguous pages (vram) */ 943 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); 944 ib->ptr[ib->length_dw++] = pe; /* dst addr */ 945 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 946 ib->ptr[ib->length_dw++] = flags; /* mask */ 947 ib->ptr[ib->length_dw++] = 0; 948 ib->ptr[ib->length_dw++] = value; /* value */ 949 ib->ptr[ib->length_dw++] = upper_32_bits(value); 950 ib->ptr[ib->length_dw++] = incr; /* increment size */ 951 ib->ptr[ib->length_dw++] = 0; 952 ib->ptr[ib->length_dw++] = ndw; /* number of entries */ 953 954 pe += ndw * 8; 955 addr += ndw * incr; 956 count -= ndw; 957 } 958 } 959 960 /** 961 * sdma_v3_0_vm_pad_ib - pad the IB to the required number of dw 962 * 963 * @ib: indirect buffer to fill with padding 964 * 965 */ 966 static void sdma_v3_0_vm_pad_ib(struct amdgpu_ib *ib) 967 { 968 while (ib->length_dw & 0x7) 969 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 970 } 971 972 /** 973 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA 974 * 975 * @ring: amdgpu_ring pointer 976 * @vm: amdgpu_vm pointer 977 * 978 * Update the page table base and flush the VM TLB 979 * using sDMA (VI). 980 */ 981 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 982 unsigned vm_id, uint64_t pd_addr) 983 { 984 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 985 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 986 if (vm_id < 8) { 987 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); 988 } else { 989 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); 990 } 991 amdgpu_ring_write(ring, pd_addr >> 12); 992 993 /* flush TLB */ 994 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 995 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 996 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 997 amdgpu_ring_write(ring, 1 << vm_id); 998 999 /* wait for flush */ 1000 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1001 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1002 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ 1003 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 1004 amdgpu_ring_write(ring, 0); 1005 amdgpu_ring_write(ring, 0); /* reference */ 1006 amdgpu_ring_write(ring, 0); /* mask */ 1007 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1008 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 1009 } 1010 1011 static int sdma_v3_0_early_init(void *handle) 1012 { 1013 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1014 1015 sdma_v3_0_set_ring_funcs(adev); 1016 sdma_v3_0_set_buffer_funcs(adev); 1017 sdma_v3_0_set_vm_pte_funcs(adev); 1018 sdma_v3_0_set_irq_funcs(adev); 1019 1020 return 0; 1021 } 1022 1023 static int sdma_v3_0_sw_init(void *handle) 1024 { 1025 struct amdgpu_ring *ring; 1026 int r; 1027 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1028 1029 /* SDMA trap event */ 1030 r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq); 1031 if (r) 1032 return r; 1033 1034 /* SDMA Privileged inst */ 1035 r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq); 1036 if (r) 1037 return r; 1038 1039 /* SDMA Privileged inst */ 1040 r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq); 1041 if (r) 1042 return r; 1043 1044 r = sdma_v3_0_init_microcode(adev); 1045 if (r) { 1046 DRM_ERROR("Failed to load sdma firmware!\n"); 1047 return r; 1048 } 1049 1050 ring = &adev->sdma[0].ring; 1051 ring->ring_obj = NULL; 1052 ring->use_doorbell = true; 1053 ring->doorbell_index = AMDGPU_DOORBELL_sDMA_ENGINE0; 1054 1055 ring = &adev->sdma[1].ring; 1056 ring->ring_obj = NULL; 1057 ring->use_doorbell = true; 1058 ring->doorbell_index = AMDGPU_DOORBELL_sDMA_ENGINE1; 1059 1060 ring = &adev->sdma[0].ring; 1061 sprintf(ring->name, "sdma0"); 1062 r = amdgpu_ring_init(adev, ring, 256 * 1024, 1063 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, 1064 &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0, 1065 AMDGPU_RING_TYPE_SDMA); 1066 if (r) 1067 return r; 1068 1069 ring = &adev->sdma[1].ring; 1070 sprintf(ring->name, "sdma1"); 1071 r = amdgpu_ring_init(adev, ring, 256 * 1024, 1072 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, 1073 &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1, 1074 AMDGPU_RING_TYPE_SDMA); 1075 if (r) 1076 return r; 1077 1078 return r; 1079 } 1080 1081 static int sdma_v3_0_sw_fini(void *handle) 1082 { 1083 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1084 1085 amdgpu_ring_fini(&adev->sdma[0].ring); 1086 amdgpu_ring_fini(&adev->sdma[1].ring); 1087 1088 return 0; 1089 } 1090 1091 static int sdma_v3_0_hw_init(void *handle) 1092 { 1093 int r; 1094 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1095 1096 sdma_v3_0_init_golden_registers(adev); 1097 1098 r = sdma_v3_0_start(adev); 1099 if (r) 1100 return r; 1101 1102 return r; 1103 } 1104 1105 static int sdma_v3_0_hw_fini(void *handle) 1106 { 1107 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1108 1109 sdma_v3_0_ctx_switch_enable(adev, false); 1110 sdma_v3_0_enable(adev, false); 1111 1112 return 0; 1113 } 1114 1115 static int sdma_v3_0_suspend(void *handle) 1116 { 1117 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1118 1119 return sdma_v3_0_hw_fini(adev); 1120 } 1121 1122 static int sdma_v3_0_resume(void *handle) 1123 { 1124 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1125 1126 return sdma_v3_0_hw_init(adev); 1127 } 1128 1129 static bool sdma_v3_0_is_idle(void *handle) 1130 { 1131 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1132 u32 tmp = RREG32(mmSRBM_STATUS2); 1133 1134 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1135 SRBM_STATUS2__SDMA1_BUSY_MASK)) 1136 return false; 1137 1138 return true; 1139 } 1140 1141 static int sdma_v3_0_wait_for_idle(void *handle) 1142 { 1143 unsigned i; 1144 u32 tmp; 1145 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1146 1147 for (i = 0; i < adev->usec_timeout; i++) { 1148 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1149 SRBM_STATUS2__SDMA1_BUSY_MASK); 1150 1151 if (!tmp) 1152 return 0; 1153 udelay(1); 1154 } 1155 return -ETIMEDOUT; 1156 } 1157 1158 static void sdma_v3_0_print_status(void *handle) 1159 { 1160 int i, j; 1161 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1162 1163 dev_info(adev->dev, "VI SDMA registers\n"); 1164 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", 1165 RREG32(mmSRBM_STATUS2)); 1166 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 1167 dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n", 1168 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i])); 1169 dev_info(adev->dev, " SDMA%d_F32_CNTL=0x%08X\n", 1170 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i])); 1171 dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n", 1172 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i])); 1173 dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n", 1174 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i])); 1175 dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n", 1176 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i])); 1177 dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n", 1178 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i])); 1179 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n", 1180 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i])); 1181 dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n", 1182 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i])); 1183 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n", 1184 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i])); 1185 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n", 1186 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i])); 1187 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n", 1188 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i])); 1189 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n", 1190 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i])); 1191 dev_info(adev->dev, " SDMA%d_GFX_DOORBELL=0x%08X\n", 1192 i, RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i])); 1193 mutex_lock(&adev->srbm_mutex); 1194 for (j = 0; j < 16; j++) { 1195 vi_srbm_select(adev, 0, 0, 0, j); 1196 dev_info(adev->dev, " VM %d:\n", j); 1197 dev_info(adev->dev, " SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n", 1198 i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i])); 1199 dev_info(adev->dev, " SDMA%d_GFX_APE1_CNTL=0x%08X\n", 1200 i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i])); 1201 } 1202 vi_srbm_select(adev, 0, 0, 0, 0); 1203 mutex_unlock(&adev->srbm_mutex); 1204 } 1205 } 1206 1207 static int sdma_v3_0_soft_reset(void *handle) 1208 { 1209 u32 srbm_soft_reset = 0; 1210 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1211 u32 tmp = RREG32(mmSRBM_STATUS2); 1212 1213 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { 1214 /* sdma0 */ 1215 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); 1216 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); 1217 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); 1218 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1219 } 1220 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) { 1221 /* sdma1 */ 1222 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); 1223 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); 1224 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); 1225 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1226 } 1227 1228 if (srbm_soft_reset) { 1229 sdma_v3_0_print_status((void *)adev); 1230 1231 tmp = RREG32(mmSRBM_SOFT_RESET); 1232 tmp |= srbm_soft_reset; 1233 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1234 WREG32(mmSRBM_SOFT_RESET, tmp); 1235 tmp = RREG32(mmSRBM_SOFT_RESET); 1236 1237 udelay(50); 1238 1239 tmp &= ~srbm_soft_reset; 1240 WREG32(mmSRBM_SOFT_RESET, tmp); 1241 tmp = RREG32(mmSRBM_SOFT_RESET); 1242 1243 /* Wait a little for things to settle down */ 1244 udelay(50); 1245 1246 sdma_v3_0_print_status((void *)adev); 1247 } 1248 1249 return 0; 1250 } 1251 1252 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev, 1253 struct amdgpu_irq_src *source, 1254 unsigned type, 1255 enum amdgpu_interrupt_state state) 1256 { 1257 u32 sdma_cntl; 1258 1259 switch (type) { 1260 case AMDGPU_SDMA_IRQ_TRAP0: 1261 switch (state) { 1262 case AMDGPU_IRQ_STATE_DISABLE: 1263 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1264 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1265 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1266 break; 1267 case AMDGPU_IRQ_STATE_ENABLE: 1268 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1269 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1270 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1271 break; 1272 default: 1273 break; 1274 } 1275 break; 1276 case AMDGPU_SDMA_IRQ_TRAP1: 1277 switch (state) { 1278 case AMDGPU_IRQ_STATE_DISABLE: 1279 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1280 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1281 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1282 break; 1283 case AMDGPU_IRQ_STATE_ENABLE: 1284 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1285 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1286 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1287 break; 1288 default: 1289 break; 1290 } 1291 break; 1292 default: 1293 break; 1294 } 1295 return 0; 1296 } 1297 1298 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev, 1299 struct amdgpu_irq_src *source, 1300 struct amdgpu_iv_entry *entry) 1301 { 1302 u8 instance_id, queue_id; 1303 1304 instance_id = (entry->ring_id & 0x3) >> 0; 1305 queue_id = (entry->ring_id & 0xc) >> 2; 1306 DRM_DEBUG("IH: SDMA trap\n"); 1307 switch (instance_id) { 1308 case 0: 1309 switch (queue_id) { 1310 case 0: 1311 amdgpu_fence_process(&adev->sdma[0].ring); 1312 break; 1313 case 1: 1314 /* XXX compute */ 1315 break; 1316 case 2: 1317 /* XXX compute */ 1318 break; 1319 } 1320 break; 1321 case 1: 1322 switch (queue_id) { 1323 case 0: 1324 amdgpu_fence_process(&adev->sdma[1].ring); 1325 break; 1326 case 1: 1327 /* XXX compute */ 1328 break; 1329 case 2: 1330 /* XXX compute */ 1331 break; 1332 } 1333 break; 1334 } 1335 return 0; 1336 } 1337 1338 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1339 struct amdgpu_irq_src *source, 1340 struct amdgpu_iv_entry *entry) 1341 { 1342 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1343 schedule_work(&adev->reset_work); 1344 return 0; 1345 } 1346 1347 static int sdma_v3_0_set_clockgating_state(void *handle, 1348 enum amd_clockgating_state state) 1349 { 1350 return 0; 1351 } 1352 1353 static int sdma_v3_0_set_powergating_state(void *handle, 1354 enum amd_powergating_state state) 1355 { 1356 return 0; 1357 } 1358 1359 const struct amd_ip_funcs sdma_v3_0_ip_funcs = { 1360 .early_init = sdma_v3_0_early_init, 1361 .late_init = NULL, 1362 .sw_init = sdma_v3_0_sw_init, 1363 .sw_fini = sdma_v3_0_sw_fini, 1364 .hw_init = sdma_v3_0_hw_init, 1365 .hw_fini = sdma_v3_0_hw_fini, 1366 .suspend = sdma_v3_0_suspend, 1367 .resume = sdma_v3_0_resume, 1368 .is_idle = sdma_v3_0_is_idle, 1369 .wait_for_idle = sdma_v3_0_wait_for_idle, 1370 .soft_reset = sdma_v3_0_soft_reset, 1371 .print_status = sdma_v3_0_print_status, 1372 .set_clockgating_state = sdma_v3_0_set_clockgating_state, 1373 .set_powergating_state = sdma_v3_0_set_powergating_state, 1374 }; 1375 1376 /** 1377 * sdma_v3_0_ring_is_lockup - Check if the DMA engine is locked up 1378 * 1379 * @ring: amdgpu_ring structure holding ring information 1380 * 1381 * Check if the async DMA engine is locked up (VI). 1382 * Returns true if the engine appears to be locked up, false if not. 1383 */ 1384 static bool sdma_v3_0_ring_is_lockup(struct amdgpu_ring *ring) 1385 { 1386 1387 if (sdma_v3_0_is_idle(ring->adev)) { 1388 amdgpu_ring_lockup_update(ring); 1389 return false; 1390 } 1391 return amdgpu_ring_test_lockup(ring); 1392 } 1393 1394 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { 1395 .get_rptr = sdma_v3_0_ring_get_rptr, 1396 .get_wptr = sdma_v3_0_ring_get_wptr, 1397 .set_wptr = sdma_v3_0_ring_set_wptr, 1398 .parse_cs = NULL, 1399 .emit_ib = sdma_v3_0_ring_emit_ib, 1400 .emit_fence = sdma_v3_0_ring_emit_fence, 1401 .emit_semaphore = sdma_v3_0_ring_emit_semaphore, 1402 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, 1403 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, 1404 .test_ring = sdma_v3_0_ring_test_ring, 1405 .test_ib = sdma_v3_0_ring_test_ib, 1406 .is_lockup = sdma_v3_0_ring_is_lockup, 1407 }; 1408 1409 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev) 1410 { 1411 adev->sdma[0].ring.funcs = &sdma_v3_0_ring_funcs; 1412 adev->sdma[1].ring.funcs = &sdma_v3_0_ring_funcs; 1413 } 1414 1415 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = { 1416 .set = sdma_v3_0_set_trap_irq_state, 1417 .process = sdma_v3_0_process_trap_irq, 1418 }; 1419 1420 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = { 1421 .process = sdma_v3_0_process_illegal_inst_irq, 1422 }; 1423 1424 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev) 1425 { 1426 adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1427 adev->sdma_trap_irq.funcs = &sdma_v3_0_trap_irq_funcs; 1428 adev->sdma_illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs; 1429 } 1430 1431 /** 1432 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine 1433 * 1434 * @ring: amdgpu_ring structure holding ring information 1435 * @src_offset: src GPU address 1436 * @dst_offset: dst GPU address 1437 * @byte_count: number of bytes to xfer 1438 * 1439 * Copy GPU buffers using the DMA engine (VI). 1440 * Used by the amdgpu ttm implementation to move pages if 1441 * registered as the asic copy callback. 1442 */ 1443 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ring *ring, 1444 uint64_t src_offset, 1445 uint64_t dst_offset, 1446 uint32_t byte_count) 1447 { 1448 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1449 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR)); 1450 amdgpu_ring_write(ring, byte_count); 1451 amdgpu_ring_write(ring, 0); /* src/dst endian swap */ 1452 amdgpu_ring_write(ring, lower_32_bits(src_offset)); 1453 amdgpu_ring_write(ring, upper_32_bits(src_offset)); 1454 amdgpu_ring_write(ring, lower_32_bits(dst_offset)); 1455 amdgpu_ring_write(ring, upper_32_bits(dst_offset)); 1456 } 1457 1458 /** 1459 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine 1460 * 1461 * @ring: amdgpu_ring structure holding ring information 1462 * @src_data: value to write to buffer 1463 * @dst_offset: dst GPU address 1464 * @byte_count: number of bytes to xfer 1465 * 1466 * Fill GPU buffers using the DMA engine (VI). 1467 */ 1468 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ring *ring, 1469 uint32_t src_data, 1470 uint64_t dst_offset, 1471 uint32_t byte_count) 1472 { 1473 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL)); 1474 amdgpu_ring_write(ring, lower_32_bits(dst_offset)); 1475 amdgpu_ring_write(ring, upper_32_bits(dst_offset)); 1476 amdgpu_ring_write(ring, src_data); 1477 amdgpu_ring_write(ring, byte_count); 1478 } 1479 1480 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = { 1481 .copy_max_bytes = 0x1fffff, 1482 .copy_num_dw = 7, 1483 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer, 1484 1485 .fill_max_bytes = 0x1fffff, 1486 .fill_num_dw = 5, 1487 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer, 1488 }; 1489 1490 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) 1491 { 1492 if (adev->mman.buffer_funcs == NULL) { 1493 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs; 1494 adev->mman.buffer_funcs_ring = &adev->sdma[0].ring; 1495 } 1496 } 1497 1498 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { 1499 .copy_pte = sdma_v3_0_vm_copy_pte, 1500 .write_pte = sdma_v3_0_vm_write_pte, 1501 .set_pte_pde = sdma_v3_0_vm_set_pte_pde, 1502 .pad_ib = sdma_v3_0_vm_pad_ib, 1503 }; 1504 1505 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1506 { 1507 if (adev->vm_manager.vm_pte_funcs == NULL) { 1508 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; 1509 adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring; 1510 } 1511 } 1512