1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 #include "vi.h" 30 #include "vid.h" 31 32 #include "oss/oss_2_4_d.h" 33 #include "oss/oss_2_4_sh_mask.h" 34 35 #include "gmc/gmc_8_1_d.h" 36 #include "gmc/gmc_8_1_sh_mask.h" 37 38 #include "gca/gfx_8_0_d.h" 39 #include "gca/gfx_8_0_enum.h" 40 #include "gca/gfx_8_0_sh_mask.h" 41 42 #include "bif/bif_5_0_d.h" 43 #include "bif/bif_5_0_sh_mask.h" 44 45 #include "iceland_sdma_pkt_open.h" 46 47 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev); 48 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev); 49 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev); 50 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev); 51 52 MODULE_FIRMWARE("amdgpu/topaz_sdma.bin"); 53 MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin"); 54 55 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 56 { 57 SDMA0_REGISTER_OFFSET, 58 SDMA1_REGISTER_OFFSET 59 }; 60 61 static const u32 golden_settings_iceland_a11[] = 62 { 63 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 64 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 65 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 66 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 67 }; 68 69 static const u32 iceland_mgcg_cgcg_init[] = 70 { 71 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 72 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 73 }; 74 75 /* 76 * sDMA - System DMA 77 * Starting with CIK, the GPU has new asynchronous 78 * DMA engines. These engines are used for compute 79 * and gfx. There are two DMA engines (SDMA0, SDMA1) 80 * and each one supports 1 ring buffer used for gfx 81 * and 2 queues used for compute. 82 * 83 * The programming model is very similar to the CP 84 * (ring buffer, IBs, etc.), but sDMA has it's own 85 * packet format that is different from the PM4 format 86 * used by the CP. sDMA supports copying data, writing 87 * embedded data, solid fills, and a number of other 88 * things. It also has support for tiling/detiling of 89 * buffers. 90 */ 91 92 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev) 93 { 94 switch (adev->asic_type) { 95 case CHIP_TOPAZ: 96 amdgpu_program_register_sequence(adev, 97 iceland_mgcg_cgcg_init, 98 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); 99 amdgpu_program_register_sequence(adev, 100 golden_settings_iceland_a11, 101 (const u32)ARRAY_SIZE(golden_settings_iceland_a11)); 102 break; 103 default: 104 break; 105 } 106 } 107 108 /** 109 * sdma_v2_4_init_microcode - load ucode images from disk 110 * 111 * @adev: amdgpu_device pointer 112 * 113 * Use the firmware interface to load the ucode images into 114 * the driver (not loaded into hw). 115 * Returns 0 on success, error on failure. 116 */ 117 static int sdma_v2_4_init_microcode(struct amdgpu_device *adev) 118 { 119 const char *chip_name; 120 char fw_name[30]; 121 int err, i; 122 struct amdgpu_firmware_info *info = NULL; 123 const struct common_firmware_header *header = NULL; 124 const struct sdma_firmware_header_v1_0 *hdr; 125 126 DRM_DEBUG("\n"); 127 128 switch (adev->asic_type) { 129 case CHIP_TOPAZ: 130 chip_name = "topaz"; 131 break; 132 default: BUG(); 133 } 134 135 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 136 if (i == 0) 137 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 138 else 139 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 140 err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev); 141 if (err) 142 goto out; 143 err = amdgpu_ucode_validate(adev->sdma[i].fw); 144 if (err) 145 goto out; 146 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data; 147 adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 148 adev->sdma[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 149 150 if (adev->firmware.smu_load) { 151 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 152 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 153 info->fw = adev->sdma[i].fw; 154 header = (const struct common_firmware_header *)info->fw->data; 155 adev->firmware.fw_size += 156 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 157 } 158 } 159 160 out: 161 if (err) { 162 printk(KERN_ERR 163 "sdma_v2_4: Failed to load firmware \"%s\"\n", 164 fw_name); 165 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 166 release_firmware(adev->sdma[i].fw); 167 adev->sdma[i].fw = NULL; 168 } 169 } 170 return err; 171 } 172 173 /** 174 * sdma_v2_4_ring_get_rptr - get the current read pointer 175 * 176 * @ring: amdgpu ring pointer 177 * 178 * Get the current rptr from the hardware (VI+). 179 */ 180 static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring) 181 { 182 u32 rptr; 183 184 /* XXX check if swapping is necessary on BE */ 185 rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2; 186 187 return rptr; 188 } 189 190 /** 191 * sdma_v2_4_ring_get_wptr - get the current write pointer 192 * 193 * @ring: amdgpu ring pointer 194 * 195 * Get the current wptr from the hardware (VI+). 196 */ 197 static uint32_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring) 198 { 199 struct amdgpu_device *adev = ring->adev; 200 int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1; 201 u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2; 202 203 return wptr; 204 } 205 206 /** 207 * sdma_v2_4_ring_set_wptr - commit the write pointer 208 * 209 * @ring: amdgpu ring pointer 210 * 211 * Write the wptr back to the hardware (VI+). 212 */ 213 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring) 214 { 215 struct amdgpu_device *adev = ring->adev; 216 int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1; 217 218 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2); 219 } 220 221 /** 222 * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine 223 * 224 * @ring: amdgpu ring pointer 225 * @ib: IB object to schedule 226 * 227 * Schedule an IB in the DMA ring (VI). 228 */ 229 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring, 230 struct amdgpu_ib *ib) 231 { 232 u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf; 233 u32 next_rptr = ring->wptr + 5; 234 235 while ((next_rptr & 7) != 2) 236 next_rptr++; 237 238 next_rptr += 6; 239 240 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 241 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 242 amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc); 243 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); 244 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 245 amdgpu_ring_write(ring, next_rptr); 246 247 /* IB packet must end on a 8 DW boundary */ 248 while ((ring->wptr & 7) != 2) 249 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_NOP)); 250 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 251 SDMA_PKT_INDIRECT_HEADER_VMID(vmid)); 252 /* base must be 32 byte aligned */ 253 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 254 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 255 amdgpu_ring_write(ring, ib->length_dw); 256 amdgpu_ring_write(ring, 0); 257 amdgpu_ring_write(ring, 0); 258 259 } 260 261 /** 262 * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring 263 * 264 * @ring: amdgpu ring pointer 265 * 266 * Emit an hdp flush packet on the requested DMA ring. 267 */ 268 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring) 269 { 270 u32 ref_and_mask = 0; 271 272 if (ring == &ring->adev->sdma[0].ring) 273 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); 274 else 275 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); 276 277 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 278 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 279 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 280 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 281 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 282 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 283 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 284 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 285 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 286 } 287 288 /** 289 * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring 290 * 291 * @ring: amdgpu ring pointer 292 * @fence: amdgpu fence object 293 * 294 * Add a DMA fence packet to the ring to write 295 * the fence seq number and DMA trap packet to generate 296 * an interrupt if needed (VI). 297 */ 298 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 299 unsigned flags) 300 { 301 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 302 /* write the fence */ 303 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 304 amdgpu_ring_write(ring, lower_32_bits(addr)); 305 amdgpu_ring_write(ring, upper_32_bits(addr)); 306 amdgpu_ring_write(ring, lower_32_bits(seq)); 307 308 /* optionally write high bits as well */ 309 if (write64bit) { 310 addr += 4; 311 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 312 amdgpu_ring_write(ring, lower_32_bits(addr)); 313 amdgpu_ring_write(ring, upper_32_bits(addr)); 314 amdgpu_ring_write(ring, upper_32_bits(seq)); 315 } 316 317 /* generate an interrupt */ 318 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 319 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 320 } 321 322 /** 323 * sdma_v2_4_ring_emit_semaphore - emit a semaphore on the dma ring 324 * 325 * @ring: amdgpu_ring structure holding ring information 326 * @semaphore: amdgpu semaphore object 327 * @emit_wait: wait or signal semaphore 328 * 329 * Add a DMA semaphore packet to the ring wait on or signal 330 * other rings (VI). 331 */ 332 static bool sdma_v2_4_ring_emit_semaphore(struct amdgpu_ring *ring, 333 struct amdgpu_semaphore *semaphore, 334 bool emit_wait) 335 { 336 u64 addr = semaphore->gpu_addr; 337 u32 sig = emit_wait ? 0 : 1; 338 339 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) | 340 SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig)); 341 amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8); 342 amdgpu_ring_write(ring, upper_32_bits(addr)); 343 344 return true; 345 } 346 347 /** 348 * sdma_v2_4_gfx_stop - stop the gfx async dma engines 349 * 350 * @adev: amdgpu_device pointer 351 * 352 * Stop the gfx async dma ring buffers (VI). 353 */ 354 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev) 355 { 356 struct amdgpu_ring *sdma0 = &adev->sdma[0].ring; 357 struct amdgpu_ring *sdma1 = &adev->sdma[1].ring; 358 u32 rb_cntl, ib_cntl; 359 int i; 360 361 if ((adev->mman.buffer_funcs_ring == sdma0) || 362 (adev->mman.buffer_funcs_ring == sdma1)) 363 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); 364 365 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 366 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 367 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 368 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 369 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 370 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 371 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 372 } 373 sdma0->ready = false; 374 sdma1->ready = false; 375 } 376 377 /** 378 * sdma_v2_4_rlc_stop - stop the compute async dma engines 379 * 380 * @adev: amdgpu_device pointer 381 * 382 * Stop the compute async dma queues (VI). 383 */ 384 static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev) 385 { 386 /* XXX todo */ 387 } 388 389 /** 390 * sdma_v2_4_enable - stop the async dma engines 391 * 392 * @adev: amdgpu_device pointer 393 * @enable: enable/disable the DMA MEs. 394 * 395 * Halt or unhalt the async dma engines (VI). 396 */ 397 static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable) 398 { 399 u32 f32_cntl; 400 int i; 401 402 if (enable == false) { 403 sdma_v2_4_gfx_stop(adev); 404 sdma_v2_4_rlc_stop(adev); 405 } 406 407 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 408 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 409 if (enable) 410 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); 411 else 412 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 413 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); 414 } 415 } 416 417 /** 418 * sdma_v2_4_gfx_resume - setup and start the async dma engines 419 * 420 * @adev: amdgpu_device pointer 421 * 422 * Set up the gfx DMA ring buffers and enable them (VI). 423 * Returns 0 for success, error for failure. 424 */ 425 static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev) 426 { 427 struct amdgpu_ring *ring; 428 u32 rb_cntl, ib_cntl; 429 u32 rb_bufsz; 430 u32 wb_offset; 431 int i, j, r; 432 433 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 434 ring = &adev->sdma[i].ring; 435 wb_offset = (ring->rptr_offs * 4); 436 437 mutex_lock(&adev->srbm_mutex); 438 for (j = 0; j < 16; j++) { 439 vi_srbm_select(adev, 0, 0, 0, j); 440 /* SDMA GFX */ 441 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 442 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 443 } 444 vi_srbm_select(adev, 0, 0, 0, 0); 445 mutex_unlock(&adev->srbm_mutex); 446 447 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 448 449 /* Set ring buffer size in dwords */ 450 rb_bufsz = order_base_2(ring->ring_size / 4); 451 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 452 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 453 #ifdef __BIG_ENDIAN 454 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 455 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 456 RPTR_WRITEBACK_SWAP_ENABLE, 1); 457 #endif 458 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 459 460 /* Initialize the ring buffer's read and write pointers */ 461 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 462 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 463 464 /* set the wb address whether it's enabled or not */ 465 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 466 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 467 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 468 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 469 470 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 471 472 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 473 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 474 475 ring->wptr = 0; 476 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); 477 478 /* enable DMA RB */ 479 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 480 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 481 482 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 483 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 484 #ifdef __BIG_ENDIAN 485 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 486 #endif 487 /* enable DMA IBs */ 488 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 489 490 ring->ready = true; 491 492 r = amdgpu_ring_test_ring(ring); 493 if (r) { 494 ring->ready = false; 495 return r; 496 } 497 498 if (adev->mman.buffer_funcs_ring == ring) 499 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); 500 } 501 502 return 0; 503 } 504 505 /** 506 * sdma_v2_4_rlc_resume - setup and start the async dma engines 507 * 508 * @adev: amdgpu_device pointer 509 * 510 * Set up the compute DMA queues and enable them (VI). 511 * Returns 0 for success, error for failure. 512 */ 513 static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev) 514 { 515 /* XXX todo */ 516 return 0; 517 } 518 519 /** 520 * sdma_v2_4_load_microcode - load the sDMA ME ucode 521 * 522 * @adev: amdgpu_device pointer 523 * 524 * Loads the sDMA0/1 ucode. 525 * Returns 0 for success, -EINVAL if the ucode is not available. 526 */ 527 static int sdma_v2_4_load_microcode(struct amdgpu_device *adev) 528 { 529 const struct sdma_firmware_header_v1_0 *hdr; 530 const __le32 *fw_data; 531 u32 fw_size; 532 int i, j; 533 bool smc_loads_fw = false; /* XXX fix me */ 534 535 if (!adev->sdma[0].fw || !adev->sdma[1].fw) 536 return -EINVAL; 537 538 /* halt the MEs */ 539 sdma_v2_4_enable(adev, false); 540 541 if (smc_loads_fw) { 542 /* XXX query SMC for fw load complete */ 543 } else { 544 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 545 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data; 546 amdgpu_ucode_print_sdma_hdr(&hdr->header); 547 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 548 fw_data = (const __le32 *) 549 (adev->sdma[i].fw->data + 550 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 551 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); 552 for (j = 0; j < fw_size; j++) 553 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); 554 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version); 555 } 556 } 557 558 return 0; 559 } 560 561 /** 562 * sdma_v2_4_start - setup and start the async dma engines 563 * 564 * @adev: amdgpu_device pointer 565 * 566 * Set up the DMA engines and enable them (VI). 567 * Returns 0 for success, error for failure. 568 */ 569 static int sdma_v2_4_start(struct amdgpu_device *adev) 570 { 571 int r; 572 573 if (!adev->firmware.smu_load) { 574 r = sdma_v2_4_load_microcode(adev); 575 if (r) 576 return r; 577 } else { 578 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 579 AMDGPU_UCODE_ID_SDMA0); 580 if (r) 581 return -EINVAL; 582 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 583 AMDGPU_UCODE_ID_SDMA1); 584 if (r) 585 return -EINVAL; 586 } 587 588 /* unhalt the MEs */ 589 sdma_v2_4_enable(adev, true); 590 591 /* start the gfx rings and rlc compute queues */ 592 r = sdma_v2_4_gfx_resume(adev); 593 if (r) 594 return r; 595 r = sdma_v2_4_rlc_resume(adev); 596 if (r) 597 return r; 598 599 return 0; 600 } 601 602 /** 603 * sdma_v2_4_ring_test_ring - simple async dma engine test 604 * 605 * @ring: amdgpu_ring structure holding ring information 606 * 607 * Test the DMA engine by writing using it to write an 608 * value to memory. (VI). 609 * Returns 0 for success, error for failure. 610 */ 611 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring) 612 { 613 struct amdgpu_device *adev = ring->adev; 614 unsigned i; 615 unsigned index; 616 int r; 617 u32 tmp; 618 u64 gpu_addr; 619 620 r = amdgpu_wb_get(adev, &index); 621 if (r) { 622 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 623 return r; 624 } 625 626 gpu_addr = adev->wb.gpu_addr + (index * 4); 627 tmp = 0xCAFEDEAD; 628 adev->wb.wb[index] = cpu_to_le32(tmp); 629 630 r = amdgpu_ring_lock(ring, 5); 631 if (r) { 632 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 633 amdgpu_wb_free(adev, index); 634 return r; 635 } 636 637 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 638 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 639 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 640 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 641 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 642 amdgpu_ring_write(ring, 0xDEADBEEF); 643 amdgpu_ring_unlock_commit(ring); 644 645 for (i = 0; i < adev->usec_timeout; i++) { 646 tmp = le32_to_cpu(adev->wb.wb[index]); 647 if (tmp == 0xDEADBEEF) 648 break; 649 DRM_UDELAY(1); 650 } 651 652 if (i < adev->usec_timeout) { 653 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 654 } else { 655 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 656 ring->idx, tmp); 657 r = -EINVAL; 658 } 659 amdgpu_wb_free(adev, index); 660 661 return r; 662 } 663 664 /** 665 * sdma_v2_4_ring_test_ib - test an IB on the DMA engine 666 * 667 * @ring: amdgpu_ring structure holding ring information 668 * 669 * Test a simple IB in the DMA ring (VI). 670 * Returns 0 on success, error on failure. 671 */ 672 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring) 673 { 674 struct amdgpu_device *adev = ring->adev; 675 struct amdgpu_ib ib; 676 unsigned i; 677 unsigned index; 678 int r; 679 u32 tmp = 0; 680 u64 gpu_addr; 681 682 r = amdgpu_wb_get(adev, &index); 683 if (r) { 684 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 685 return r; 686 } 687 688 gpu_addr = adev->wb.gpu_addr + (index * 4); 689 tmp = 0xCAFEDEAD; 690 adev->wb.wb[index] = cpu_to_le32(tmp); 691 692 r = amdgpu_ib_get(ring, NULL, 256, &ib); 693 if (r) { 694 amdgpu_wb_free(adev, index); 695 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); 696 return r; 697 } 698 699 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 700 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 701 ib.ptr[1] = lower_32_bits(gpu_addr); 702 ib.ptr[2] = upper_32_bits(gpu_addr); 703 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); 704 ib.ptr[4] = 0xDEADBEEF; 705 ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 706 ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 707 ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 708 ib.length_dw = 8; 709 710 r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED); 711 if (r) { 712 amdgpu_ib_free(adev, &ib); 713 amdgpu_wb_free(adev, index); 714 DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r); 715 return r; 716 } 717 r = amdgpu_fence_wait(ib.fence, false); 718 if (r) { 719 amdgpu_ib_free(adev, &ib); 720 amdgpu_wb_free(adev, index); 721 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 722 return r; 723 } 724 for (i = 0; i < adev->usec_timeout; i++) { 725 tmp = le32_to_cpu(adev->wb.wb[index]); 726 if (tmp == 0xDEADBEEF) 727 break; 728 DRM_UDELAY(1); 729 } 730 if (i < adev->usec_timeout) { 731 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", 732 ib.fence->ring->idx, i); 733 } else { 734 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 735 r = -EINVAL; 736 } 737 amdgpu_ib_free(adev, &ib); 738 amdgpu_wb_free(adev, index); 739 return r; 740 } 741 742 /** 743 * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART 744 * 745 * @ib: indirect buffer to fill with commands 746 * @pe: addr of the page entry 747 * @src: src addr to copy from 748 * @count: number of page entries to update 749 * 750 * Update PTEs by copying them from the GART using sDMA (CIK). 751 */ 752 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib, 753 uint64_t pe, uint64_t src, 754 unsigned count) 755 { 756 while (count) { 757 unsigned bytes = count * 8; 758 if (bytes > 0x1FFFF8) 759 bytes = 0x1FFFF8; 760 761 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 762 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 763 ib->ptr[ib->length_dw++] = bytes; 764 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 765 ib->ptr[ib->length_dw++] = lower_32_bits(src); 766 ib->ptr[ib->length_dw++] = upper_32_bits(src); 767 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 768 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 769 770 pe += bytes; 771 src += bytes; 772 count -= bytes / 8; 773 } 774 } 775 776 /** 777 * sdma_v2_4_vm_write_pte - update PTEs by writing them manually 778 * 779 * @ib: indirect buffer to fill with commands 780 * @pe: addr of the page entry 781 * @addr: dst addr to write into pe 782 * @count: number of page entries to update 783 * @incr: increase next addr by incr bytes 784 * @flags: access flags 785 * 786 * Update PTEs by writing them manually using sDMA (CIK). 787 */ 788 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, 789 uint64_t pe, 790 uint64_t addr, unsigned count, 791 uint32_t incr, uint32_t flags) 792 { 793 uint64_t value; 794 unsigned ndw; 795 796 while (count) { 797 ndw = count * 2; 798 if (ndw > 0xFFFFE) 799 ndw = 0xFFFFE; 800 801 /* for non-physically contiguous pages (system) */ 802 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 803 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 804 ib->ptr[ib->length_dw++] = pe; 805 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 806 ib->ptr[ib->length_dw++] = ndw; 807 for (; ndw > 0; ndw -= 2, --count, pe += 8) { 808 if (flags & AMDGPU_PTE_SYSTEM) { 809 value = amdgpu_vm_map_gart(ib->ring->adev, addr); 810 value &= 0xFFFFFFFFFFFFF000ULL; 811 } else if (flags & AMDGPU_PTE_VALID) { 812 value = addr; 813 } else { 814 value = 0; 815 } 816 addr += incr; 817 value |= flags; 818 ib->ptr[ib->length_dw++] = value; 819 ib->ptr[ib->length_dw++] = upper_32_bits(value); 820 } 821 } 822 } 823 824 /** 825 * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA 826 * 827 * @ib: indirect buffer to fill with commands 828 * @pe: addr of the page entry 829 * @addr: dst addr to write into pe 830 * @count: number of page entries to update 831 * @incr: increase next addr by incr bytes 832 * @flags: access flags 833 * 834 * Update the page tables using sDMA (CIK). 835 */ 836 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, 837 uint64_t pe, 838 uint64_t addr, unsigned count, 839 uint32_t incr, uint32_t flags) 840 { 841 uint64_t value; 842 unsigned ndw; 843 844 while (count) { 845 ndw = count; 846 if (ndw > 0x7FFFF) 847 ndw = 0x7FFFF; 848 849 if (flags & AMDGPU_PTE_VALID) 850 value = addr; 851 else 852 value = 0; 853 854 /* for physically contiguous pages (vram) */ 855 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); 856 ib->ptr[ib->length_dw++] = pe; /* dst addr */ 857 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 858 ib->ptr[ib->length_dw++] = flags; /* mask */ 859 ib->ptr[ib->length_dw++] = 0; 860 ib->ptr[ib->length_dw++] = value; /* value */ 861 ib->ptr[ib->length_dw++] = upper_32_bits(value); 862 ib->ptr[ib->length_dw++] = incr; /* increment size */ 863 ib->ptr[ib->length_dw++] = 0; 864 ib->ptr[ib->length_dw++] = ndw; /* number of entries */ 865 866 pe += ndw * 8; 867 addr += ndw * incr; 868 count -= ndw; 869 } 870 } 871 872 /** 873 * sdma_v2_4_vm_pad_ib - pad the IB to the required number of dw 874 * 875 * @ib: indirect buffer to fill with padding 876 * 877 */ 878 static void sdma_v2_4_vm_pad_ib(struct amdgpu_ib *ib) 879 { 880 while (ib->length_dw & 0x7) 881 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 882 } 883 884 /** 885 * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA 886 * 887 * @ring: amdgpu_ring pointer 888 * @vm: amdgpu_vm pointer 889 * 890 * Update the page table base and flush the VM TLB 891 * using sDMA (VI). 892 */ 893 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring, 894 unsigned vm_id, uint64_t pd_addr) 895 { 896 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 897 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 898 if (vm_id < 8) { 899 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); 900 } else { 901 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); 902 } 903 amdgpu_ring_write(ring, pd_addr >> 12); 904 905 /* flush TLB */ 906 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 907 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 908 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 909 amdgpu_ring_write(ring, 1 << vm_id); 910 911 /* wait for flush */ 912 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 913 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 914 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ 915 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 916 amdgpu_ring_write(ring, 0); 917 amdgpu_ring_write(ring, 0); /* reference */ 918 amdgpu_ring_write(ring, 0); /* mask */ 919 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 920 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 921 } 922 923 static int sdma_v2_4_early_init(void *handle) 924 { 925 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 926 927 sdma_v2_4_set_ring_funcs(adev); 928 sdma_v2_4_set_buffer_funcs(adev); 929 sdma_v2_4_set_vm_pte_funcs(adev); 930 sdma_v2_4_set_irq_funcs(adev); 931 932 return 0; 933 } 934 935 static int sdma_v2_4_sw_init(void *handle) 936 { 937 struct amdgpu_ring *ring; 938 int r; 939 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 940 941 /* SDMA trap event */ 942 r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq); 943 if (r) 944 return r; 945 946 /* SDMA Privileged inst */ 947 r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq); 948 if (r) 949 return r; 950 951 /* SDMA Privileged inst */ 952 r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq); 953 if (r) 954 return r; 955 956 r = sdma_v2_4_init_microcode(adev); 957 if (r) { 958 DRM_ERROR("Failed to load sdma firmware!\n"); 959 return r; 960 } 961 962 ring = &adev->sdma[0].ring; 963 ring->ring_obj = NULL; 964 ring->use_doorbell = false; 965 966 ring = &adev->sdma[1].ring; 967 ring->ring_obj = NULL; 968 ring->use_doorbell = false; 969 970 ring = &adev->sdma[0].ring; 971 sprintf(ring->name, "sdma0"); 972 r = amdgpu_ring_init(adev, ring, 256 * 1024, 973 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, 974 &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0, 975 AMDGPU_RING_TYPE_SDMA); 976 if (r) 977 return r; 978 979 ring = &adev->sdma[1].ring; 980 sprintf(ring->name, "sdma1"); 981 r = amdgpu_ring_init(adev, ring, 256 * 1024, 982 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, 983 &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1, 984 AMDGPU_RING_TYPE_SDMA); 985 if (r) 986 return r; 987 988 return r; 989 } 990 991 static int sdma_v2_4_sw_fini(void *handle) 992 { 993 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 994 995 amdgpu_ring_fini(&adev->sdma[0].ring); 996 amdgpu_ring_fini(&adev->sdma[1].ring); 997 998 return 0; 999 } 1000 1001 static int sdma_v2_4_hw_init(void *handle) 1002 { 1003 int r; 1004 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1005 1006 sdma_v2_4_init_golden_registers(adev); 1007 1008 r = sdma_v2_4_start(adev); 1009 if (r) 1010 return r; 1011 1012 return r; 1013 } 1014 1015 static int sdma_v2_4_hw_fini(void *handle) 1016 { 1017 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1018 1019 sdma_v2_4_enable(adev, false); 1020 1021 return 0; 1022 } 1023 1024 static int sdma_v2_4_suspend(void *handle) 1025 { 1026 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1027 1028 return sdma_v2_4_hw_fini(adev); 1029 } 1030 1031 static int sdma_v2_4_resume(void *handle) 1032 { 1033 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1034 1035 return sdma_v2_4_hw_init(adev); 1036 } 1037 1038 static bool sdma_v2_4_is_idle(void *handle) 1039 { 1040 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1041 u32 tmp = RREG32(mmSRBM_STATUS2); 1042 1043 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1044 SRBM_STATUS2__SDMA1_BUSY_MASK)) 1045 return false; 1046 1047 return true; 1048 } 1049 1050 static int sdma_v2_4_wait_for_idle(void *handle) 1051 { 1052 unsigned i; 1053 u32 tmp; 1054 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1055 1056 for (i = 0; i < adev->usec_timeout; i++) { 1057 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1058 SRBM_STATUS2__SDMA1_BUSY_MASK); 1059 1060 if (!tmp) 1061 return 0; 1062 udelay(1); 1063 } 1064 return -ETIMEDOUT; 1065 } 1066 1067 static void sdma_v2_4_print_status(void *handle) 1068 { 1069 int i, j; 1070 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1071 1072 dev_info(adev->dev, "VI SDMA registers\n"); 1073 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", 1074 RREG32(mmSRBM_STATUS2)); 1075 for (i = 0; i < SDMA_MAX_INSTANCE; i++) { 1076 dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n", 1077 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i])); 1078 dev_info(adev->dev, " SDMA%d_F32_CNTL=0x%08X\n", 1079 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i])); 1080 dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n", 1081 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i])); 1082 dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n", 1083 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i])); 1084 dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n", 1085 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i])); 1086 dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n", 1087 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i])); 1088 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n", 1089 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i])); 1090 dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n", 1091 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i])); 1092 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n", 1093 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i])); 1094 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n", 1095 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i])); 1096 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n", 1097 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i])); 1098 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n", 1099 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i])); 1100 mutex_lock(&adev->srbm_mutex); 1101 for (j = 0; j < 16; j++) { 1102 vi_srbm_select(adev, 0, 0, 0, j); 1103 dev_info(adev->dev, " VM %d:\n", j); 1104 dev_info(adev->dev, " SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n", 1105 i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i])); 1106 dev_info(adev->dev, " SDMA%d_GFX_APE1_CNTL=0x%08X\n", 1107 i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i])); 1108 } 1109 vi_srbm_select(adev, 0, 0, 0, 0); 1110 mutex_unlock(&adev->srbm_mutex); 1111 } 1112 } 1113 1114 static int sdma_v2_4_soft_reset(void *handle) 1115 { 1116 u32 srbm_soft_reset = 0; 1117 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1118 u32 tmp = RREG32(mmSRBM_STATUS2); 1119 1120 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { 1121 /* sdma0 */ 1122 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); 1123 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); 1124 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); 1125 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1126 } 1127 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) { 1128 /* sdma1 */ 1129 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); 1130 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); 1131 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); 1132 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1133 } 1134 1135 if (srbm_soft_reset) { 1136 sdma_v2_4_print_status((void *)adev); 1137 1138 tmp = RREG32(mmSRBM_SOFT_RESET); 1139 tmp |= srbm_soft_reset; 1140 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1141 WREG32(mmSRBM_SOFT_RESET, tmp); 1142 tmp = RREG32(mmSRBM_SOFT_RESET); 1143 1144 udelay(50); 1145 1146 tmp &= ~srbm_soft_reset; 1147 WREG32(mmSRBM_SOFT_RESET, tmp); 1148 tmp = RREG32(mmSRBM_SOFT_RESET); 1149 1150 /* Wait a little for things to settle down */ 1151 udelay(50); 1152 1153 sdma_v2_4_print_status((void *)adev); 1154 } 1155 1156 return 0; 1157 } 1158 1159 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev, 1160 struct amdgpu_irq_src *src, 1161 unsigned type, 1162 enum amdgpu_interrupt_state state) 1163 { 1164 u32 sdma_cntl; 1165 1166 switch (type) { 1167 case AMDGPU_SDMA_IRQ_TRAP0: 1168 switch (state) { 1169 case AMDGPU_IRQ_STATE_DISABLE: 1170 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1171 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1172 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1173 break; 1174 case AMDGPU_IRQ_STATE_ENABLE: 1175 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1176 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1177 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1178 break; 1179 default: 1180 break; 1181 } 1182 break; 1183 case AMDGPU_SDMA_IRQ_TRAP1: 1184 switch (state) { 1185 case AMDGPU_IRQ_STATE_DISABLE: 1186 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1187 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1188 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1189 break; 1190 case AMDGPU_IRQ_STATE_ENABLE: 1191 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1192 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1193 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1194 break; 1195 default: 1196 break; 1197 } 1198 break; 1199 default: 1200 break; 1201 } 1202 return 0; 1203 } 1204 1205 static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev, 1206 struct amdgpu_irq_src *source, 1207 struct amdgpu_iv_entry *entry) 1208 { 1209 u8 instance_id, queue_id; 1210 1211 instance_id = (entry->ring_id & 0x3) >> 0; 1212 queue_id = (entry->ring_id & 0xc) >> 2; 1213 DRM_DEBUG("IH: SDMA trap\n"); 1214 switch (instance_id) { 1215 case 0: 1216 switch (queue_id) { 1217 case 0: 1218 amdgpu_fence_process(&adev->sdma[0].ring); 1219 break; 1220 case 1: 1221 /* XXX compute */ 1222 break; 1223 case 2: 1224 /* XXX compute */ 1225 break; 1226 } 1227 break; 1228 case 1: 1229 switch (queue_id) { 1230 case 0: 1231 amdgpu_fence_process(&adev->sdma[1].ring); 1232 break; 1233 case 1: 1234 /* XXX compute */ 1235 break; 1236 case 2: 1237 /* XXX compute */ 1238 break; 1239 } 1240 break; 1241 } 1242 return 0; 1243 } 1244 1245 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev, 1246 struct amdgpu_irq_src *source, 1247 struct amdgpu_iv_entry *entry) 1248 { 1249 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1250 schedule_work(&adev->reset_work); 1251 return 0; 1252 } 1253 1254 static int sdma_v2_4_set_clockgating_state(void *handle, 1255 enum amd_clockgating_state state) 1256 { 1257 /* XXX handled via the smc on VI */ 1258 return 0; 1259 } 1260 1261 static int sdma_v2_4_set_powergating_state(void *handle, 1262 enum amd_powergating_state state) 1263 { 1264 return 0; 1265 } 1266 1267 const struct amd_ip_funcs sdma_v2_4_ip_funcs = { 1268 .early_init = sdma_v2_4_early_init, 1269 .late_init = NULL, 1270 .sw_init = sdma_v2_4_sw_init, 1271 .sw_fini = sdma_v2_4_sw_fini, 1272 .hw_init = sdma_v2_4_hw_init, 1273 .hw_fini = sdma_v2_4_hw_fini, 1274 .suspend = sdma_v2_4_suspend, 1275 .resume = sdma_v2_4_resume, 1276 .is_idle = sdma_v2_4_is_idle, 1277 .wait_for_idle = sdma_v2_4_wait_for_idle, 1278 .soft_reset = sdma_v2_4_soft_reset, 1279 .print_status = sdma_v2_4_print_status, 1280 .set_clockgating_state = sdma_v2_4_set_clockgating_state, 1281 .set_powergating_state = sdma_v2_4_set_powergating_state, 1282 }; 1283 1284 /** 1285 * sdma_v2_4_ring_is_lockup - Check if the DMA engine is locked up 1286 * 1287 * @ring: amdgpu_ring structure holding ring information 1288 * 1289 * Check if the async DMA engine is locked up (VI). 1290 * Returns true if the engine appears to be locked up, false if not. 1291 */ 1292 static bool sdma_v2_4_ring_is_lockup(struct amdgpu_ring *ring) 1293 { 1294 1295 if (sdma_v2_4_is_idle(ring->adev)) { 1296 amdgpu_ring_lockup_update(ring); 1297 return false; 1298 } 1299 return amdgpu_ring_test_lockup(ring); 1300 } 1301 1302 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { 1303 .get_rptr = sdma_v2_4_ring_get_rptr, 1304 .get_wptr = sdma_v2_4_ring_get_wptr, 1305 .set_wptr = sdma_v2_4_ring_set_wptr, 1306 .parse_cs = NULL, 1307 .emit_ib = sdma_v2_4_ring_emit_ib, 1308 .emit_fence = sdma_v2_4_ring_emit_fence, 1309 .emit_semaphore = sdma_v2_4_ring_emit_semaphore, 1310 .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush, 1311 .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush, 1312 .test_ring = sdma_v2_4_ring_test_ring, 1313 .test_ib = sdma_v2_4_ring_test_ib, 1314 .is_lockup = sdma_v2_4_ring_is_lockup, 1315 }; 1316 1317 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev) 1318 { 1319 adev->sdma[0].ring.funcs = &sdma_v2_4_ring_funcs; 1320 adev->sdma[1].ring.funcs = &sdma_v2_4_ring_funcs; 1321 } 1322 1323 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = { 1324 .set = sdma_v2_4_set_trap_irq_state, 1325 .process = sdma_v2_4_process_trap_irq, 1326 }; 1327 1328 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = { 1329 .process = sdma_v2_4_process_illegal_inst_irq, 1330 }; 1331 1332 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev) 1333 { 1334 adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1335 adev->sdma_trap_irq.funcs = &sdma_v2_4_trap_irq_funcs; 1336 adev->sdma_illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs; 1337 } 1338 1339 /** 1340 * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine 1341 * 1342 * @ring: amdgpu_ring structure holding ring information 1343 * @src_offset: src GPU address 1344 * @dst_offset: dst GPU address 1345 * @byte_count: number of bytes to xfer 1346 * 1347 * Copy GPU buffers using the DMA engine (VI). 1348 * Used by the amdgpu ttm implementation to move pages if 1349 * registered as the asic copy callback. 1350 */ 1351 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ring *ring, 1352 uint64_t src_offset, 1353 uint64_t dst_offset, 1354 uint32_t byte_count) 1355 { 1356 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1357 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR)); 1358 amdgpu_ring_write(ring, byte_count); 1359 amdgpu_ring_write(ring, 0); /* src/dst endian swap */ 1360 amdgpu_ring_write(ring, lower_32_bits(src_offset)); 1361 amdgpu_ring_write(ring, upper_32_bits(src_offset)); 1362 amdgpu_ring_write(ring, lower_32_bits(dst_offset)); 1363 amdgpu_ring_write(ring, upper_32_bits(dst_offset)); 1364 } 1365 1366 /** 1367 * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine 1368 * 1369 * @ring: amdgpu_ring structure holding ring information 1370 * @src_data: value to write to buffer 1371 * @dst_offset: dst GPU address 1372 * @byte_count: number of bytes to xfer 1373 * 1374 * Fill GPU buffers using the DMA engine (VI). 1375 */ 1376 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ring *ring, 1377 uint32_t src_data, 1378 uint64_t dst_offset, 1379 uint32_t byte_count) 1380 { 1381 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL)); 1382 amdgpu_ring_write(ring, lower_32_bits(dst_offset)); 1383 amdgpu_ring_write(ring, upper_32_bits(dst_offset)); 1384 amdgpu_ring_write(ring, src_data); 1385 amdgpu_ring_write(ring, byte_count); 1386 } 1387 1388 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = { 1389 .copy_max_bytes = 0x1fffff, 1390 .copy_num_dw = 7, 1391 .emit_copy_buffer = sdma_v2_4_emit_copy_buffer, 1392 1393 .fill_max_bytes = 0x1fffff, 1394 .fill_num_dw = 7, 1395 .emit_fill_buffer = sdma_v2_4_emit_fill_buffer, 1396 }; 1397 1398 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev) 1399 { 1400 if (adev->mman.buffer_funcs == NULL) { 1401 adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs; 1402 adev->mman.buffer_funcs_ring = &adev->sdma[0].ring; 1403 } 1404 } 1405 1406 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = { 1407 .copy_pte = sdma_v2_4_vm_copy_pte, 1408 .write_pte = sdma_v2_4_vm_write_pte, 1409 .set_pte_pde = sdma_v2_4_vm_set_pte_pde, 1410 .pad_ib = sdma_v2_4_vm_pad_ib, 1411 }; 1412 1413 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev) 1414 { 1415 if (adev->vm_manager.vm_pte_funcs == NULL) { 1416 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs; 1417 adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring; 1418 } 1419 } 1420